Semiconductor element

Abstract

A semiconductor element is provided. The semiconductor device includes one or more conductor structures and a guard ring. The guard ring includes a first portion and a second portion higher than the first portion. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first areas of the protection ring, the first part of the protection ring does not vertically coincide with the second part of the protection ring.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor components are used in a wide variety of electronic devices, such as mobile phones, notebook computers, desktop computers, tablet computers, watches, gaming systems, and various other industrial, commercial, and consumer electronic products. Semiconductor components generally include a semiconductor portion and a wiring portion formed within the semiconductor portion. Utility Model Content

[0003] A semiconductor element comprises one or more dielectric layers, one or more conductor structures and a guard ring. The one or more conductor structures are in the one or more dielectric layers. The guard ring is arranged in the one or more dielectric layers. The guard ring comprises a first portion and a second portion. The first portion comprises one or more first through holes or one or more first metal layers. The second portion has a height higher than the first portion. The second portion comprises one or more second through holes or one or more second metal layers. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0004] A semiconductor element comprises one or more conductor structures and a guard ring. The guard ring comprises a first portion and a second portion. The second portion has a height higher than the first portion. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0005] A semiconductor element includes a protection ring. The protection ring includes a first portion and a second portion. The first portion laterally surrounds a first block. The second portion is above the first portion. The second portion laterally surrounds the first block. In one or more first regions, a first section of the second portion of the protection ring vertically overlaps with the first portion of the protection ring. In one or more first regions, a second section of the second portion of the protection ring does not vertically overlap with the first portion of the protection ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read together with the accompanying drawings, various aspects of the present disclosure can be best understood from the detailed description below. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1A A top view of a semiconductor device according to some embodiments is shown;

[0008] Figure 1B depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0009] Figure 1C depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0010] Figure 2A A top view of a semiconductor device according to some embodiments is shown;

[0011] Figure 2B depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0012] Figure 2C depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0013] Figure 3A A top view of a semiconductor device according to some embodiments is shown;

[0014] Figure 3B depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0015] Figure 3C depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0016] Figure 4A A top view of a semiconductor device according to some embodiments is shown;

[0017] Figure 4B depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0018] Figure 4C depicts a cross-sectional view of a semiconductor device according to some embodiments;

[0019] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments;

[0020] Figure 6 is a flow chart illustrating a method according to some embodiments.

[0021]

Explanation of symbols

[0022] BB,CC: Line segment

[0023] x1,x2,x3,x4,x5,x7: x-axis position

[0024] y1,y2,y3,y4: y-axis position

[0025] 100:Semiconductor components

[0026] 102: First Block

[0027] 104: First corner area

[0028] 106: Second corner area

[0029] 107: Arrow

[0030] 108: Protection ring

[0031] 109: Arrow

[0032] 110: First Wall

[0033] 111: Arrow

[0034] 113: Arrow

[0035] 114: The Third Wall

[0036] 115: Arrow

[0037] 116: The Fourth Wall

[0038] 117: Arrow

[0039] 118: Conductor structure

[0040] 119: Arrow

[0041] 121: Arrow

[0042] 122: Second Wall

[0043] 124: Fourth Corner Area

[0044] 126: Third Corner Area

[0045] 134: First semiconductor layer

[0046] 136: Etching stop layer

[0047] 138: Third semiconductor layer

[0048] 140: first passivation layer

[0049] 142: Fifth dielectric layer

[0050] 146: fourth dielectric layer

[0051] 150: third dielectric layer

[0052] 154: Second dielectric layer

[0053] 158: first dielectric layer

[0054] 162: Second semiconductor layer

[0055] 164: Base material

[0056] 166:Metal layer

[0057] 168:Through hole

[0058] 170:Metal layer

[0059] 172:Through hole

[0060] 174:Through hole

[0061] 176:Metal layer

[0062] 178:Through hole

[0063] 180:Metal layer

[0064] 182:Through hole

[0065] 184:Metal layer

[0066] 184a: First paragraph

[0067] 184b: Second paragraph

[0068] 186: Top

[0069] 188:Metal layer

[0070] 190: Top

[0071] 192: First Part

[0072] 194: Second part

[0073] 196,197,198,199:Distance

[0074] 200:Semiconductor components

[0075] 202: First Block

[0076] 204: First corner area

[0077] 206: Second corner area

[0078] 208: Protection ring

[0079] 210: First Wall

[0080] 214: The Third Wall

[0081] 216: The Fourth Wall

[0082] 218: Conductor structure

[0083] 222: Second Wall

[0084] 224: Fourth Corner Area

[0085] 226: Third Corner Area

[0086] 234: First semiconductor layer

[0087] 236: Etching stop layer

[0088] 238: Third semiconductor layer

[0089] 240: first passivation layer

[0090] 242: Fifth dielectric layer

[0091] 246: fourth dielectric layer

[0092] 250: third dielectric layer

[0093] 254: Second dielectric layer

[0094] 258: first dielectric layer

[0095] 262: Second semiconductor layer

[0096] 264: Base material

[0097] 266:Metal layer

[0098] 268:Through hole

[0099] 270:Metal layer

[0100] 272:Through hole

[0101] 274:Through hole

[0102] 276:Metal layer

[0103] 278:Through hole

[0104] 280:Metal layer

[0105] 282:Through hole

[0106] 284:Metal layer

[0107] 286: Top

[0108] 287: Top

[0109] 288:Metal layer

[0110] 290: Top

[0111] 291: Top

[0112] 292: First Part

[0113] 294: Second part

[0114] 300:Semiconductor components

[0115] 302: First block

[0116] 304: First corner area

[0117] 306: Second corner area

[0118] 308: Protection ring

[0119] 310: First Wall

[0120] 314: The Third Wall

[0121] 316: The Fourth Wall

[0122] 318: Conductor structure

[0123] 322: Second Wall

[0124] 324: Fourth Corner Area

[0125] 326: Third Corner Area

[0126] 334: first semiconductor layer

[0127] 336: Etching stop layer

[0128] 338: Third semiconductor layer

[0129] 340: first passivation layer

[0130] 342: Fifth dielectric layer

[0131] 346: fourth dielectric layer

[0132] 350: third dielectric layer

[0133] 354: Second dielectric layer

[0134] 358: first dielectric layer

[0135] 362: Second semiconductor layer

[0136] 364: Base material

[0137] 366:Metal layer

[0138] 368:Through hole

[0139] 370:Metal layer

[0140] 372:Through hole

[0141] 374:Through hole

[0142] 376:Metal layer

[0143] 378:Through hole

[0144] 380:Metal layer

[0145] 382:Through hole

[0146] 384:Metal layer

[0147] 388:Metal layer

[0148] 390: Top

[0149] 391: Top

[0150] 392: First Part

[0151] 400:Semiconductor components

[0152] 401:Through hole

[0153] 402: First block

[0154] 403:Metal layer

[0155] 404: First corner area

[0156] 405: fourth dielectric layer

[0157] 406: Second corner area

[0158] 407:Through hole

[0159] 408: Protection Ring

[0160] 409:Metal layer

[0161] 410: First Wall

[0162] 411: fifth dielectric layer

[0163] 413:Through hole

[0164] 414: The Third Wall

[0165] 415:Metal layer

[0166] 416: The Fourth Wall

[0167] 417: Seventh dielectric layer

[0168] 418: Conductor structure

[0169] 419:Through hole

[0170] 421:Metal layer

[0171] 422: Second Wall

[0172] 423: Eighth dielectric layer

[0173] 424: Fourth Corner Area

[0174] 423: Eighth dielectric layer

[0175] 426: Third Corner Area

[0176] 434: first semiconductor layer

[0177] 436: Etching stop layer

[0178] 438: Third semiconductor layer

[0179] 440: first passivation layer

[0180] 442: Ninth dielectric layer

[0181] 446: Sixth dielectric layer

[0182] 450: third dielectric layer

[0183] 454: Second dielectric layer

[0184] 458: first dielectric layer

[0185] 462: Second semiconductor layer

[0186] 464: Base material

[0187] 466:Metal layer

[0188] 468:Through hole

[0189] 470:Metal layer

[0190] 472:Through hole

[0191] 474:Through hole

[0192] 476:Metal layer

[0193] 478:Through hole

[0194] 480:Metal layer

[0195] 482:Through hole

[0196] 484:Metal layer

[0197] 487: Top

[0198] 488:Metal layer

[0199] 490: Top

[0200] 491: Top

[0201] 492: First Part

[0202] 494: Second part

[0203] 496: The third part

[0204] 500:Semiconductor components

[0205] 502: welding bump

[0206] 504: first gap filling structure

[0207] 505: Second gap filling structure

[0208] 506: dielectric layer

[0209] 508: First protection ring

[0210] 509: Second protection ring

[0211] 510: semiconductor layer 511:

[0213] 512: Layer

[0214] 514: First Part

[0215] 515: Second part

[0216] 518: first conductor structure

[0217] 519: Second conductor structure

[0218] 534: Semiconductor layer

[0219] 536: Etching stop layer

[0220] 538: Semiconductor layer

[0221] 540: first passivation layer

[0222] 562: Semiconductor layer

[0223] 564: First substrate

[0224] 565: Second substrate

[0225] 590: Third gap filling structure

[0226] 591: Fourth gap filling structure

[0227] 592: Fifth gap filling structure

[0228] 593:Semiconductor Structure

[0229] 599: Semiconductor layer

[0230] 600: Method

[0231] 602,604,606: Operation DETAILED DESCRIPTION

[0232] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. In order to simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not meant to be restrictive. For example, in the following description, a first feature formed on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, or may include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0233] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0234] The term "overlying" and / or similar terms may be used to describe an element or feature that is vertically coincident with and located at a higher elevation than another element or feature. For example, a first element overlies a second element if the first element is taller than the second element and at least some of the first element is vertically coincident with at least some of the second element.

[0235] The term "underlying" and / or similar terms may be used to describe an element or feature that is vertically overlapped with another element or feature and is located at a lower height. For example, if a first element is located at a lower height than a second element and at least some of the first element vertically overlaps with at least some of the second element, then the first element is located below the second element.

[0236] The term "above" may be used to describe that one element or feature is located at a higher elevation than another element or feature. For example, if a first element is located at a higher elevation than a second element, the first element is above the second element.

[0237] The term "below" may be used to describe that one element or feature is located at a lower height than another element or feature. For example, if a first element is at a lower height than a second element, the first element is below the second element.

[0238] A semiconductor device has a protection ring that laterally surrounds a block. The protection ring has at least one of a protection area, a mask area, and an electrically isolated area. In some embodiments, the protection ring protects the area from contamination by moisture, contaminants, etc. generated in one or more manufacturing processes performed in one or more manufacturing stages of the semiconductor device, such as at least one of wafer dicing and wafer sawing. In some embodiments, the protection ring includes a first portion and a second portion that is higher than the first portion. In one or more first regions of the protection ring, such as a corner region of the protection region, the first portion of the protection ring is laterally offset from the second portion of the protection ring, that is, the first portion and the second portion do not overlap in the vertical direction. In some embodiments, the offset between the first portion and the second portion reduces the amount of stress on one or more portions of the semiconductor device compared to an embodiment in which the protection ring extends vertically on a single vertical axis. In some embodiments, in a wafer including a protection ring extending vertically on a single vertical axis, the amount of stress caused by the protection ring may cause delamination, peeling, etc. of a film at a corner, thereby damaging the wafer. Therefore, according to some embodiments, reducing the amount of stress in one or more locations in a semiconductor device reduces at least one of damage to the semiconductor device, wafer defects, etc., and provides improvements in performance, stability, quality, etc. of the semiconductor device.

[0239] Figures 1A to 1C A semiconductor device 100 according to some embodiments is depicted. Figure 1A A top view of the semiconductor device 100 is shown. Figure 1B Draw along Figure 1A A cross-sectional view of the semiconductor device 100 observed along line segment BB. Figure 1C Draw along Figure 1A 1 is a cross-sectional view of the semiconductor device 100 observed along the line segment CC. In some embodiments, the semiconductor device 100 includes a system on integrated chips (SoIC) chip.

[0240] The semiconductor device 100 includes a guard ring 108, such as at least one of a seal ring, a guard ring, etc. In some embodiments, the guard ring 108 laterally surrounds the first block 102 or at least one of the one or more conductor structures 118 in the first block 102. In some embodiments, the guard ring 108 is continuous so as to laterally surround or surround all of the first block 102 and / or the one or more conductor structures 118. In some embodiments, the guard ring 108 is discontinuous or has breaks so as to laterally surround or surround some but not all of the first block 102 and / or the one or more conductor structures 118.

[0241] In some embodiments, the semiconductor device 100 includes a first semiconductor layer 134 overlying the guard ring 108. Figure 1A Layers, features, components, etc. overlying the guard ring 108 and / or the one or more conductor structures 118 are removed to draw a top view of the guard ring 108 and / or the one or more conductor structures 118. According to some embodiments, Figure 1A The top surface 186 of the metal layer 184 of the guard ring 108 is depicted in FIG. Figure 1B and Figure 1C ) and the top surface 190 of the metal layer 188 of the guard ring 108 (shown in Figure 1B and Figure 1C In some embodiments, the top surface 186 and the top surface 190 are located at different heights. In order to separate the top surface 186 and the top surface 190, Figure 1A A dotted pattern on top surface 186 and a diagonal line pattern on top surface 190 are depicted.

[0242] In some embodiments, the one or more conductor structures 118 include at least one of one or more contacts, one or more wiring elements, one or more interconnect structures, one or more vias, one or more metal layers, one or more metal lines, etc. In some embodiments, at least some of the one or more conductor structures 118 include at least one of aluminum, copper, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of the one or more conductor structures 118 have the same composition as at least some of the guard rings 108. In some embodiments, the composition of at least some of the one or more conductor structures 118 is different from the composition of at least some of the guard rings 108. In some embodiments, at least some of the one or more conductor structures 118 have different composition than other conductor structures 118.

[0243] According to some embodiments, the guard ring 108 includes a first wall 110, a second wall 122 opposite to the first wall 110, a third wall 114, and a fourth wall 116 opposite to the third wall 114. Some of the at least one or more conductor structures 118 are located between the first wall 110 and the second wall 122, and at least some of the one or more conductor structures 118 are between the third wall 114 and the fourth wall 116. In some embodiments, the guard ring 108 includes at least one of a first angular region 104 separating the first wall 110 from the third wall 114, a second angular region 106 separating the fourth wall 116 from the first wall 110, a third angular region 126 separating the second wall 122 from the fourth wall 116, or a fourth angular region 124 separating the third wall 114 from the second wall 122. Other structures and / or configurations of the walls and / or angular regions of the guard ring 108 relative to other elements, features, etc. are within the scope of the present disclosure.

[0244] According to some embodiments, the guard ring 108 at least protects, shields, electrically isolates at least one of the semiconductor device 100, the one or more conductor structures 118, or one or more other layers, features, etc. of the semiconductor device 100. In some embodiments, the guard ring 108 provides support, stability, structural integrity, etc. for at least one of the semiconductor device 100, the one or more conductor structures 118, or one or more other layers, features, etc. of the semiconductor device 100.

[0245] According to some embodiments, Figure 1B The cross-sectional view shown in FIG. 1 includes a cross-sectional view of a fourth corner region 124 of the guard ring 108. In some embodiments, the semiconductor device 100 includes at least one of a substrate 164, a second semiconductor layer 162 on the substrate 164, a first dielectric layer 158 on the second semiconductor layer 162, a second dielectric layer 154 on the first dielectric layer 158, a third dielectric layer 150 on the second dielectric layer 154, a fourth dielectric layer 146 on the third dielectric layer 150, a fifth dielectric layer 142 on the fourth dielectric layer 146, a first passivation layer 140 on the fifth dielectric layer 142, a third semiconductor layer 138 on the first passivation layer 140, or a first semiconductor layer 134 on the third semiconductor layer 138.

[0246] In some embodiments, the substrate 164 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. The substrate 164 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. According to some embodiments, the substrate 164 includes single crystal silicon, a <100> Crystalline silicon with a crystallographic orientation <110> Crystalline silicon or other suitable materials in a crystal direction. In some embodiments, substrate 164 includes at least one doped region. Other structures and / or configurations of substrate 164 are also within the scope of the present disclosure.

[0247] The second semiconductor layer 162 includes at least one of silicon, an oxide semiconductor material such as silicon oxide, a nitride semiconductor material such as silicon nitride, an oxidized nitride material, or other suitable materials. In some embodiments, the second semiconductor layer 162 is an interlayer dielectric (ILD) layer. In some embodiments, the second semiconductor layer 162 includes at least one of tetrachlorosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), a polymeric thermosetting material, or other suitable materials. Other structures and / or configurations of the second semiconductor layer 162 are within the scope of the present disclosure. The second semiconductor layer 162 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin on, growth or other suitable techniques.

[0248] In some embodiments, at least one of the dielectric layers 158, 154, 150, 146, or 142 includes at least one of an oxide semiconductor material such as silicon oxide, a nitride semiconductor material such as silicon nitride, an oxynitride material, a polymer, polybenzobisoxazole (PBO), polyimide (PI), a metal nitride, silicon, germanium, carbide, gallium, arsenide, arsenic, indium, sapphire, or other suitable materials. In some embodiments, at least one of the dielectric layers 158, 154, 150, 146, or 142 is electrically insulated from at least one of the guard ring 108 or other layers, features, etc. of the semiconductor device 100. In some embodiments, at least one of dielectric layers 158, 154, 150, 146, or 142 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, at least some of dielectric layers 158, 154, 150, 146, or 142 are formed in the same manner. In some embodiments, at least some of dielectric layers 158, 154, 150, 146, or 142 are formed in different manners.

[0249] In some embodiments, the first passivation layer 140 comprises at least one of silicon, oxide semiconductor material, nitride semiconductor material, oxidized nitride material, AlN, Al2O3, SiO2, Si3N4, or other suitable materials. In some embodiments, the first passivation layer 140 comprises a chemically inert, corrosion-resistant dielectric material. In some embodiments, the first passivation layer 140 comprises an organic compound having at least one of a molecular structure of an N-, P- or S-group. In some embodiments, the first passivation layer 140 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, passivation process or other suitable techniques. In some embodiments, a chemically stable material is used to produce the first passivation layer 140. In some embodiments, the passivation process is a process in which a thin film covers an underlying material. In some embodiments, the underlying material comprises at least one portion of the fifth dielectric layer 142. In some embodiments, the thin film inhibits the dissolution of the underlying material. In some embodiments, the thin film reduces the chemical reactivity with the underlying material. In some embodiments, the film reduces the electrical reactivity to the underlying material. In some embodiments, the passivation process includes at least one of oxidation of the surface of the underlying material or complexing of the surface of the underlying material with an organic compound. In some embodiments, the first passivation layer 140 inhibits at least one of charges, atoms, or ions from diffusing to the underlying material. In some embodiments, the first passivation layer 140 reduces oxidation of the underlying material. In some embodiments, the first passivation layer 140 protects the underlying material from environmental conditions. In some embodiments, the first passivation layer 140 may serve as a diffusion barrier associated with the underlying material.

[0250] In some embodiments, the third semiconductor layer 138 includes at least one of silicon, an oxide semiconductor material such as silicon oxide, a nitride semiconductor material such as silicon nitride, an oxidized nitride material, or other suitable materials. In some embodiments, the third semiconductor layer 138 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0251] In some embodiments, the first semiconductor layer 134 includes at least one of silicon, an oxide semiconductor material such as silicon oxide, a nitride semiconductor material such as silicon nitride, an oxidized nitride material, or other suitable materials. In some embodiments, the first semiconductor layer 134 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0252] In some embodiments, the semiconductor device 100 includes one or more etch stop layers 136, such as etch stop layers 136 located between adjacent layers of the semiconductor device 100. In some embodiments, the etch stop layers have different etch selectivities relative to the overlying layers or adjacent layers, so that when the etchant etches through the overlying layers, the etching process slows down or stops when the etchant encounters the underlying etch stop layer. According to some embodiments, the etch stop layer includes silicon, carbon, or other suitable materials. In some embodiments, at least some different etch stop layers have different compositions, such as different etchants are required to etch different materials. In some embodiments, the etch stop layer 136 between the third semiconductor layer 138 and the first semiconductor layer 134 has a different composition than at least one other etch stop layer 136, such as because the etchant used to etch the first semiconductor layer 134 is different than the etchant used to etch at least one dielectric layer 158, 154, 150, 146, or 142. In some embodiments, the etch stop layer 136 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0253] In some embodiments, the guard ring 108 is disposed within one or more first dielectric layers of the semiconductor element 100. For example, according to some embodiments, the guard ring 108 extends over at least some of the one or more first dielectric layers and / or through at least some of one or more other layers of the semiconductor element 100. In some embodiments, the guard ring 108 is disposed within the first passivation layer 140. For example, according to some embodiments, the guard ring 108 extends over at least some of the first passivation layer 140 and / or through at least some of the one or more other layers of the semiconductor element 100. In some embodiments, the one or more first dielectric layers include at least one of the dielectric layers 158, 154, 150, 146, or 142. According to some embodiments, the guard ring 108 includes alternating stacks of metal layers and vias (also referred to as vertical interconnect accesses (VIAs)). In some embodiments, guard ring 108 includes at least one of via 182, metal layer 180 overlying via 182, via 178 overlying metal layer 180, metal layer 176 overlying via 178, via 174 overlying metal layer 176, metal layer 184 overlying via 174, via 172 overlying metal layer 184, metal layer 170 overlying via 172, via 168 overlying metal layer 170, metal layer 166 overlying via 168, or metal layer 188 overlying metal layer 166. In some embodiments, a metal layer or via of guard ring 108 is in contact with, such as in direct contact with, an adjacent via or metal layer. In some embodiments, at least one of the following is included: metal layer 180 contacts via 182, via 178 contacts metal layer 180, metal layer 176 contacts via 178, via 174 contacts metal layer 176, metal layer 184 contacts via 174, via 172 contacts metal layer 184, metal layer 170 contacts via 172, via 168 contacts metal layer 170, metal layer 166 contacts via 168, or metal layer 188 contacts metal layer 166. Other structures and / or configurations of vias and / or metal layers of guard ring 108 relative to other components, features, etc. are within the scope of the present disclosure.

[0254] In some embodiments, at least one of vias 182, 178, 174, 172, or 168 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, at least one of metal layers 180, 176, 184, 170, 166, or 188 is formed by at least one of PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. According to some embodiments, at least some of metal layers 180, 176, 184, 170, 166, or 188 have the same width. In some embodiments, at least some of metal layers 180, 176, 184, 170, 166, or 188 have different widths. In some embodiments, at least some of the metal layers 180, 176, 184, 170, 166, or 188 have the same height. In some embodiments, at least some of the metal layers 180, 176, 184, 170, 166, or 188 have different heights. In some embodiments, at least some of the vias 182, 178, 174, 172, or 168 have the same width. In some embodiments, at least some of the vias 182, 178, 174, 172, or 168 have different widths. In some embodiments, at least some of the vias 182, 178, 174, 172, or 168 have the same height. In some embodiments, at least some of the vias 182, 178, 174, 172, or 168 have different heights.

[0255] According to some embodiments, the width of at least some of the metal layers 180, 176, 184, 170, 166, or 188 is different from the width of at least some of the vias 182, 178, 174, 172, or 168. In some embodiments, the width of at least some of the metal layers 180, 176, 184, 170, 166, or 188 is the same as the width of at least some of the vias 182, 178, 174, 172, or 168. In some embodiments, the height of at least some of the metal layers 180, 176, 184, 170, 166, or 188 is different from the height of at least some of the vias 182, 178, 174, 172, or 168. In some embodiments, the height of at least some of the metal layers 180, 176, 184, 170, 166, or 188 is the same as the height of at least some of the vias 182, 178, 174, 172, or 168.

[0256] In some embodiments, at least one of the metal layers or vias of the guard ring 108, such as at least one of the metal layers 180, 176, 184, 170, 166, or 188 or at least one of the vias 182, 178, 174, 172, or 168, is formed by at least one of lithography, PVD, sputtering, CVD, PECVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In lithography, a photosensitive material (e.g., photoresist) is formed on the layer to be patterned. The properties of the photoresist (e.g., solubility) are affected by light. The photoresist is either a negative photoresist or a positive photoresist. For negative photoresists, when illuminated by a light source, areas of the negative photoresist become insoluble, so applying a solvent to the negative photoresist in a subsequent development stage can remove the non-illuminated areas of the negative photoresist. Therefore, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque area of ​​the mask between the light source and the negative photoresist. In the positive photoresist, the illuminated area of ​​the positive photoresist becomes soluble and is removed by applying a solvent in the development process. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque area of ​​the mask between the light source and the positive photoresist. According to some embodiments, the etchant is selective so that the speed at which the etchant removes or etches away the layer under the photoresist is greater than the speed at which the etchant removes or etches away the photoresist. Therefore, the opening in the photoresist allows the etchant to form a corresponding opening in the layer below the photoresist, thereby transferring the pattern in the photoresist to the layer below the photoresist. The pattern in the layer below the photoresist is filled with one or more materials to form one or more elements, features, etc., and the patterned photoresist is removed or cleaned before or after the pattern in the layer below the photoresist is filled with one or more materials. In some embodiments, a damascene process, such as a single damascene process or a dual damascene process, is used to form at least one of the metal layers or vias of the guard ring 108, such as the metal layers 180, 176, 184, 170, 166, or 188, or at least one of the vias 182, 178, 174, 172, or 168.

[0257] In some embodiments, at least one of the following is included: (i) forming a via 182 in the second semiconductor layer 162, (ii) forming a first dielectric layer 158 and a metal layer 180 in the first dielectric layer 158, (iii) forming a second dielectric layer 154 and a metal layer 176 and a via 178 in the second dielectric layer 154, (iv) forming a third dielectric layer 150 and a metal layer 184 and a via 174 in the third dielectric layer 150. , (v) forming a fourth dielectric layer 146, and a metal layer 170 and a through hole 172 are formed in the fourth dielectric layer 146, (vi) forming a fifth dielectric layer 142, and a metal layer 166 and a through hole 168 are formed in the fifth dielectric layer 142, or (vii) forming at least one of the first passivation layer 140 or the third semiconductor layer 138, and a metal layer 188 is formed in at least one of the first passivation layer 140 or the third semiconductor layer 138.

[0258] In some embodiments, guard ring 108 is discontinuous, that is, one or more intervening dielectric layers do not include at least one of the metal layers or vias of guard ring 108. In some embodiments, guard ring 108 is continuous because the intervening dielectric layers include at least one of the metal layers or vias of guard ring 108. In some embodiments, at least one of the metal layers or vias is formed prior to forming at least some of the surrounding dielectric layers, such as at least some of first dielectric layer 158, at least some of second dielectric layer 154, at least some of third dielectric layer 150, at least some of fourth dielectric layer 146, or at least some of fifth dielectric layer 142.

[0259] In some embodiments, at least some of the layers are formed and patterned to form vias 182, and then at least some of the second semiconductor layer 162 is formed around the vias 182, such that at least some of the vias 182 are located in the second semiconductor layer 162. In some embodiments, at least some of the layers are formed and patterned to form metal layer 180, and then at least some of the first dielectric layer 158 is formed around the metal layer 180, such that at least some of the metal layer 180 is located in the first dielectric layer 158. In some embodiments, at least some of the layers are formed and patterned to form vias 178, and then at least some of the second dielectric layer 154 is formed around the vias 178, such that at least some of the vias 178 are located in the second dielectric layer 154. In some embodiments, at least some of the layers are formed and patterned to form metal layer 176, and then at least some of the second dielectric layer 154 is formed around the metal layer 176, such that at least some of the metal layer 176 is located in the second dielectric layer 154. In some embodiments, at least some of the layers are formed and patterned to form vias 174, and then at least some of the third dielectric layer 150 is formed around the vias 174, so that at least some of the vias 174 are located in the third dielectric layer 150. In some embodiments, at least some of the layers are formed and patterned to form metal layers 184, and then at least some of the third dielectric layer 150 is formed around the metal layer 184, so that at least some of the metal layer 184 is located in the third dielectric layer 150. In some embodiments, at least some of the layers are formed and patterned to form vias 172, and then at least some of the fourth dielectric layer 146 is formed around the vias 172, so that at least some of the vias 172 are located in the fourth dielectric layer 146. In some embodiments, at least some of the layers are formed and patterned to form metal layers 170, and then at least some of the fourth dielectric layer 146 is formed around the metal layer 170, so that at least some of the metal layer 170 is located in the fourth dielectric layer 146. In some embodiments, at least some layers are formed and patterned to form vias 168, and then at least some fifth dielectric layer 142 is formed around vias 168, such that at least some of vias 168 are located in fifth dielectric layer 142. In some embodiments, at least some layers are formed and patterned to form metal layer 166, and then at least some fifth dielectric layer 142 is formed around metal layer 166, such that at least some of metal layer 166 is located in fifth dielectric layer 142. In some embodiments, at least some layers are formed and patterned to form metal layer 188, and then at least some first passivation layer 140 and at least some third semiconductor layer 138 are formed around metal layer 188, such that at least some of metal layer 188 is located within first passivation layer 140 and third semiconductor layer 138.

[0260] In some embodiments, at least one of the metal layers 180, 176, 184, 170, 166, or 188 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of the metal layers 180, 176, 184, 170, 166, or 188 comprises at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of the metal layers 180, 176, 184, 170, 166, or 188 have a different composition than the other metal layers. In some embodiments, at least one of the vias 182, 178, 174, 172, or 168 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of vias 182, 178, 174, 172, or 168 comprises at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of vias 182, 178, 174, 172, or 168 have a different composition than other vias. In some embodiments, (i) via 182 comprises tungsten, (ii) at least one of metal layer 180, via 178, metal layer 176, via 174, metal layer 184, via 172, metal layer 170, via 168, or metal layer 166 comprises copper, or (iii) metal layer 188 comprises aluminum. In some embodiments, at least some of the one or more conductor structures 118 have the same composition as at least one of the metal layers 180 , 176 , 184 , 170 , 166 , or 188 or at least one of the vias 182 , 178 , 174 , 172 , or 168 .

[0261] In some embodiments, the guard ring 108 includes a first portion 192, a second portion 194 located at a higher height than the first portion 192, and a third portion located between the first portion 192 and the second portion 194. In some embodiments, the first portion 192 of the guard ring 108 laterally surrounds the first block 102 and / or one or more conductor structures 118 (e.g., Figure 1A 108 ), for example, the first portion 192 extends across the circumference of the guard ring 108. In some embodiments, the first portion 192 of the guard ring 108 is discontinuous or has breaks so as to laterally surround, encircle some but not all of the first block 102 and / or the one or more conductor structures 118. In some embodiments, the first portion 192 of the guard ring 108 is continuous so as to laterally surround, encircle, etc. all of the first block 102 and / or the one or more conductor structures 118. In some embodiments, the first portion 192 includes at least one of the via 182, the metal layer 180, the via 178, the metal layer 176, or the via 174.

[0262] In some embodiments, the second portion 194 of the guard ring 108 laterally surrounds the first block 102 (at Figure 1A 102 and / or one or more conductor structures 118, such as where the second portion 194 extends beyond the circumference of the guard ring 108. In some embodiments, the second portion 194 of the guard ring 108 is discontinuous or has breaks so as to laterally surround, encircle some but not all of the first block 102 and / or the one or more conductor structures 118. In some embodiments, the second portion 194 of the guard ring 108 is continuous so as to laterally surround, encircle all of the first block 102 and / or the one or more conductor structures 118. In some embodiments, the second portion 194 includes at least one of the via 172, the metal layer 170, the via 168, the metal layer 166, or the metal layer 188.

[0263] In some embodiments, the third portion of the guard ring 108 laterally surrounds the first block 102 (at Figure 1A 102 and / or one or more conductor structures 118, for example, extending beyond the circumference of the guard ring 108 at the third portion. In some embodiments, the third portion of the guard ring 108 is discontinuous or has breaks so as to laterally surround or encircle some but not all of the first block 102 and / or one or more conductor structures 118. In some embodiments, the third portion of the guard ring 108 is continuous so as to laterally surround or encircle all of the first block 102 and / or one or more conductor structures 118. In some embodiments, the third portion includes a metal layer 184.

[0264] In some embodiments, the first portion 192 of the guard ring 108 and the second portion 194 of the guard ring 108 do not vertically overlap in one or more first regions of the guard ring 108. For example, in one or more first regions of the guard ring 108, the first portion 192 and the second portion 194 are laterally offset such that a vertical line (e.g., a line orthogonal to a plane where the maximum extent of a layer of the semiconductor device 100 lies) does not intersect both of the first portion 192 and the second portion 194. In some embodiments, the vertical line is perpendicular to the first portion 192 and the second portion 194. Figure 1B The Y axis shown in FIG.

[0265] In some embodiments, the third portion (e.g., metal layer 184) vertically overlaps with the first portion 192 and the second portion 194 in one or more first regions of the guard ring 108. In some embodiments, the third portion vertically overlaps with the first portion 192 and the second portion 194 in the entire region of the guard ring 108. In some embodiments, the first segment 184a of the metal layer 184 vertically overlaps with the first portion 192 but does not vertically overlap with the second portion 194. In some embodiments, the first segment 184a of the metal layer 184 contacts the first portion 192. In some embodiments, the second segment 184b of the metal layer 184 vertically overlaps with the second portion 194 but does not vertically overlap with the first portion 192. In some embodiments, the second segment 184b of the metal layer 184 contacts the second portion 194.

[0266] In some embodiments, the one or more first regions include the entire guard ring 108 (including the entirety of the guard ring 108 ), and the first portion 192 of the guard ring 108 does not vertically overlap with the second portion 194 of the guard ring 108 in any region of the guard ring 108 .

[0267] In some embodiments, the one or more first regions do not include the entirety of the guard ring 108, and the first portion 192 of the guard ring 108 vertically overlaps with the second portion 194 in the one or more second regions of the guard ring 108. In some embodiments, the one or more first regions where the first portion 192 does not vertically overlap with the second portion 194 include at least some of the first corner region 104, at least some of the second corner region 106, at least some of the third corner region 126, and / or at least some of the fourth corner region 124. In some embodiments, the one or more second regions where the first portion 192 vertically overlaps with the second portion 194 include at least some of the first wall 110, at least some of the second wall 122, at least some of the third wall 114, and / or at least some of the fourth wall 116.

[0268] In some embodiments, a first portion 192 of the guard ring 108 extends from a y-axis position y1 corresponding to the lowest height on the y-axis to a y-axis position y2 corresponding to the highest height on the y-axis. In some embodiments, a second portion 194 of the guard ring 108 extends from a y-axis position y3 corresponding to the lowest height to a y-axis position y4 corresponding to the highest height. In some embodiments, the first portion 192 includes the entire segment of the guard ring 108 that exists between the y-axis position y1 and the y-axis position y2. In some embodiments, the second portion 194 includes the entire segment of the guard ring 108 that exists between the y-axis position y3 and the y-axis position y4. That is, according to some embodiments, in one or more first regions of the protection ring 108, the entire portion of the protection ring 108 between the y-axis position y1 and the y-axis position y2 does not overlap with the entire portion of the protection ring 108 between the y-axis position y3 and the y-axis position y4 in the vertical direction, and in one or more first regions, the vertical line does not intersect with two of the portions between the y-axis position y1 and the y-axis position y2 of the protection ring 108 and the portion between the y-axis position y3 and the y-axis position y4 of the protection ring 108.

[0269] In some embodiments, the first portion 192 of the guard ring 108 is Figure 1BThe x-axis position x1 on the x-axis shown extends to the x-axis position x2. In some embodiments, the second portion 194 of the guard ring 108 extends from the x-axis position x3 to the x-axis position x4. In some embodiments, the distance 196 between the x-axis position x1 and the x-axis position x3 corresponds to the width of the first portion 192, such as the width of the metal layer of the first portion 192, such as at least one of the metal layer 180 or the metal layer 176. In some embodiments, the distance 197 between the x-axis position x2 associated with the first portion 192 and the x-axis position x3 associated with the second portion 194 corresponds to the first lateral offset between the first portion 192 and the second portion 194 at least some of the fourth corner region 124. In some embodiments, the distance 198 between the x-axis position x3 and the x-axis position x4 corresponds to the width of the second portion 194, such as the width of the metal layer of the second portion 194, such as at least one of the metal layer 170, the metal layer 166, or the metal layer 188. In some embodiments, the distance 196 corresponding to the width of the first portion 192 is approximately equal to the distance 198 corresponding to the width of the second portion 194. In some embodiments, the distance 196 corresponding to the width of the first portion 192 is different from the distance 198 corresponding to the width of the second portion 194. In some embodiments, the distance 197 corresponding to the first lateral offset is approximately equal to at least one of the distance 196 corresponding to the width of the first portion 192 or the distance 198 corresponding to the width of the second portion 194. In some embodiments, the distance 197 corresponding to the first lateral offset is less than at least one of the distance 196 corresponding to the width of the first portion 192 or the distance 198 corresponding to the width of the second portion 194. In some embodiments, the distance 197 corresponding to the first lateral offset is greater than at least one of the distance 196 corresponding to the width of the first portion 192 or the distance 198 corresponding to the width of the second portion 194. Distance 197 is greater than 0.1 microns. Other values ​​for distance 197 are also within the scope of the present disclosure.

[0270] In some embodiments, because the guard ring 108 has the first lateral offset, the distance between the guard ring 108 and one or more other layers, features, etc. outside the guard ring 108 is different at different heights of the guard ring 108. In some embodiments, the x-axis position x2 (e.g., Figure 1B ) and the conductor structure 118 in the first block 102 (as shown Figure 1A ) is different from the x-axis position x4 (as shown) associated with the second portion 194 of the guard ring 108. Figure 1B ) and the distance between the conductor structures 118 (as above).

[0271] In some embodiments, at least one of dielectric layers 158, 154, 150, 146, or 142 has a thickness of about 0.5 microns to about 50 microns. In some embodiments, the height of guard ring 108 is between about 5 microns and about 50 microns. In some embodiments, the height of guard ring 108 corresponds to a distance between y-axis position y1 and y-axis position y4.

[0272] In some embodiments, implementing a first lateral offset between the first portion 192 of the guard ring 108 and the second portion 194 of the guard ring 108 reduces the amount of stress on one or more portions of the semiconductor device 100. In some embodiments, the stress includes at least one of stress caused by thermal expansion of the guard ring, stress caused by a difference in thermal properties between the guard ring and surrounding materials, stress caused by thermal stress associated with other materials in the wafer, or thermal stress caused by a gap fill material of a gap fill structure, e.g. Figure 5 At least one of the gap filling structures 504, 505, 590, 591 or 592. In some embodiments, the wafer includes a guard ring extending vertically on a single vertical axis, and the stress associated with the guard ring in the above wafer is concentrated in a single direction and / or along a single vertical axis, which may cause at least one of thin film delamination, peeling, etc. of the wafer. In some embodiments, a first lateral offset is implemented between the first portion 192 and the second portion 194 to make the stress distribution in the semiconductor device 100 more uniform. In some embodiments, the stress is not concentrated in a single direction and / or along a single vertical axis, but is released and / or dispersed in multiple directions and / or multiple regions, for example, along a direction corresponding to Figure 1A and Figure 1B 107, 109, 111, 113, 115, 117, 119, 121 in the figure, thereby reducing the amount of stress generated in a single area of ​​the semiconductor device 100. In some embodiments, reducing the amount of stress can protect the semiconductor device 100 from at least one of damage, wafer defects, film delamination, peeling, etc.

[0273] Figure 1C194. The cross-sectional view depicted in FIG. 195 includes a cross-section of a third wall 114 of the guard ring 108, wherein in at least some of the third wall 114 of the guard ring 108, a first portion 192 of the guard ring 108 is laterally offset from a second portion 194 of the guard ring 108 such that a vertical line does not intersect both of the first portion 192 and the second portion 194. In some embodiments, the distance by which the first portion 192 of the guard ring 108 is laterally offset from the second portion 194 of the guard ring 108 varies in different regions of the guard ring 108. In some embodiments, a distance 199 between an x-axis position x5 associated with the first portion 192 and an x-axis position x7 associated with the second portion 194 corresponds to a second lateral offset between the first portion 192 and the second portion 194 in at least some of the third wall 114. A distance 197 (at a distance corresponding to the first lateral offset in the fourth corner region 124) corresponds to a distance 198 (at a distance corresponding to the first lateral offset in the fourth corner region 124). Figure 1B ) is different from, for example, greater than, the distance 199 corresponding to the second lateral offset in the third wall 114 (shown in Figure 1C In some embodiments, the distance 197 corresponding to the first lateral offset is substantially equal to the distance 199 corresponding to the second lateral offset.

[0274] FIG. 2A to FIG. 2C A semiconductor device 200 according to some embodiments is depicted. Figure 2A A top view of the semiconductor device 200 is shown. Figure 2B Draw along Figure 2A A cross-sectional view of the semiconductor device 200 observed along line segment BB. Figure 2C Draw along Figure 2A A cross-sectional view of the semiconductor device 200 observed along line segment CC.

[0275] The semiconductor device 200 includes a guard ring 208, such as at least one of a seal ring, a guard ring, etc. In some embodiments, the guard ring 208 laterally surrounds the first block 202 or at least one of the one or more conductor structures 218 in the first block 202. In some embodiments, the guard ring 208 is discontinuous or has breaks so as to laterally surround or surround some but not all of the first block 202 and / or the one or more conductor structures 218. In some embodiments, the guard ring 208 is continuous so as to laterally surround or surround all of the first block 202 and / or the one or more conductor structures 218.

[0276] In some embodiments, the semiconductor device 200 includes a first semiconductor layer 234 overlying the guard ring 208. Figure 2A In the embodiment, layers, features, components, etc. overlying the guard ring 208 and / or the one or more conductor structures 218 are removed to draw a top view of the guard ring 208 and / or the one or more conductor structures 218. Figure 2A The top surface 286 of the metal layer 284 of the guard ring 208 is depicted in FIG. Figure 2B and Figure 2C ), the top surface 287 of the metal layer 270 (in Figure 2B and Figure 2C ), the top surface 290 of the metal layer 266 of the guard ring 208 (in Figure 2B and Figure 2C ) and the top surface 291 of the metal layer 288 (in Figure 2B and Figure 2C In some embodiments, top surface 286, top surface 287, top surface 290, and top surface 291 are located at different heights.

[0277] In some embodiments, one or more conductor structures 218 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more conductor structures 118.

[0278] In some embodiments, the guard ring 208 includes a first wall 210, a second wall 222 opposite the first wall 210, a third wall 214, and a fourth wall 216 opposite the third wall 214. At least some of the one or more conductor structures 218 are between the first wall 210 and the second wall 222, and at least some of the one or more conductor structures 218 are between the third wall 214 and the fourth wall 216. In some embodiments, the guard ring 208 includes at least one of a first corner region 204 separating the first wall 210 from the third wall 214, a second corner region 206 separating the fourth wall 216 from the first wall 210, a third corner region 226 separating the second wall 222 from the fourth wall 216, or a fourth corner region 224 separating the third wall 214 from the second wall 222. Other structures and / or configurations of the walls and / or corner regions of the guard ring 208 relative to other elements, features, etc. are within the scope of the present disclosure.

[0279] According to some embodiments, the guard ring 208 at least protects, shields, electrically isolates, or at least one of the semiconductor device 200, the one or more conductor structures 218, or one or more other layers, features, etc. of the semiconductor device 200. In some embodiments, the guard ring 208 provides support, reinforcement, structural integrity, etc. for at least one of the semiconductor device 200, the one or more conductor structures 218, or one or more other layers, features, etc. of the semiconductor device 200.

[0280] According to some embodiments, Figure 2BThe cross-sectional view shown in FIG. 2 includes a cross-sectional view of a fourth corner region 224 of the guard ring 208. In some embodiments, the semiconductor device 200 includes at least one of a substrate 264, a second semiconductor layer 262 on the substrate 264, a first dielectric layer 258 on the second semiconductor layer 262, a second dielectric layer 254 on the first dielectric layer 258, a third dielectric layer 250 on the second dielectric layer 254, a fourth dielectric layer 246 on the third dielectric layer 250, a fifth dielectric layer 242 on the fourth dielectric layer 246, a first passivation layer 240 on the fifth dielectric layer 242, a third semiconductor layer 238 on the first passivation layer 240, or a first semiconductor layer 234 on the third semiconductor layer 238. In some embodiments, at least one of the substrate 264, the second semiconductor layer 262, the first dielectric layer 258, the second dielectric layer 254, the third dielectric layer 250, the fourth dielectric layer 246, the fifth dielectric layer 242, the first passivation layer 240, the third semiconductor layer 238, or the first semiconductor layer 234 has a dielectric layer corresponding to Figures 1A to 1C The features, characteristics, relationships, etc. of at least one of the substrate 164, the second semiconductor layer 162, the first dielectric layer 158, the second dielectric layer 154, the third dielectric layer 150, the fourth dielectric layer 146, the fifth dielectric layer 142, the first passivation layer 140, the third semiconductor layer 138, or the first semiconductor layer 134 are provided herein. In some embodiments, one, some, and / or all layers of the semiconductor device 200 are formed using the semiconductor device 200 described herein. Figures 1A to 1C Formed by one or more techniques provided.

[0281] In some embodiments, the semiconductor device 200 includes one or more etch stop layers 236, for example, the etch stop layer 236 is located between adjacent layers of the semiconductor device 200. In some embodiments, the one or more etch stop layers 236 have Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more etch stop layers 136. In some embodiments, one or more etch stop layers 236 are formed using the method described herein. Figures 1A to 1C The one or more etch stop layers 136 are formed by one or more techniques provided by the present invention.

[0282] In some embodiments, guard ring 208 is disposed within one or more first dielectric layers of semiconductor component 200. For example, according to some embodiments, guard ring 208 extends through at least some of the one or more first dielectric layers and / or through at least some of one or more other layers of semiconductor component 200. In some embodiments, one or more first dielectric layers include at least some of dielectric layers 258, 254, 250, 246, or 242. According to some embodiments, guard ring 208 includes alternating stacks of metal layers and vias. In some embodiments, guard ring 208 includes via 282, metal layer 280 overlying via 282, via 278 overlying metal layer 280, metal layer 276 overlying via 278, via 274 overlying metal layer 276, metal layer 284 overlying via 274, via 272 overlying metal layer 284, metal layer 270 overlying via 272, via 268 overlying metal layer 270, metal layer 266 overlying via 268, or metal layer 288 overlying metal layer 266. In some embodiments, a metal layer or via of guard ring 208 is in contact with, such as in direct contact with, an adjacent via or metal layer. In some embodiments, at least one of the following is included: metal layer 280 contacts via 282, via 278 contacts metal layer 280, metal layer 276 contacts via 278, via 274 contacts metal layer 276, metal layer 284 contacts via 274, via 272 contacts metal layer 284, metal layer 270 contacts via 272, via 268 contacts metal layer 270, metal layer 266 contacts via 268, or metal layer 288 contacts metal layer 266. Other structures and / or configurations of vias and / or metal layers of guard ring 208 relative to other components, features, etc. are within the scope of the present disclosure.

[0283] In some embodiments, the vias and / or metal layer of the guard ring 208 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the vias and / or metal layers of the guard ring 108. In some embodiments, the vias and / or metal layers of the guard ring 208 use the vias and / or metal layers described herein to form Figures 1A to 1C The guard ring 108 is formed by providing one or more techniques for the vias and / or metal layers.

[0284] In some embodiments, guard ring 208 is discontinuous, i.e., one or more intervening dielectric layers do not include at least one of a metal layer or a via of guard ring 208. In some embodiments, guard ring 208 is continuous, in that the intervening dielectric layers include at least one of a metal layer or a via of guard ring 208.

[0285] In some embodiments, at least one of the metal layers 280, 276, 284, 270, 266, or 288 includes at least one of a metal, a metal alloy, or other suitable materials. In some embodiments, at least one of the metal layers 280, 276, 284, 270, 266, or 288 includes at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of the metal layers 280, 276, 284, 270, 266, or 288 have a different composition than other metal layers. In some embodiments, at least one of the vias 282, 278, 274, 272, or 268 includes at least one of a metal, a metal alloy, or other suitable materials. In some embodiments, at least one of vias 282, 278, 274, 272, or 268 comprises at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, Al2O3, ZrO2, or other suitable materials. In some embodiments, at least some of vias 282, 278, 274, 272, or 268 have a different composition than other vias. In some embodiments, at least one of (i) via 282 comprises tungsten, (ii) at least one of metal layer 280, via 278, metal layer 276, via 274, metal layer 284, via 272, metal layer 270, via 268, or metal layer 266 comprises copper, or (iii) metal layer 288 comprises aluminum. In some embodiments, at least some of the one or more conductor structures 218 have the same composition as at least some of the metal layers 280 , 276 , 284 , 270 , 266 , or 288 or at least some of the vias 282 , 278 , 274 , 272 , or 268 .

[0286] In some embodiments, the guard ring 208 includes a first portion 292, a second portion 294 located at a higher height than the first portion 292, and a third portion located between the first portion 292 and the second portion 294. In some embodiments, the first portion 292 of the guard ring 208 laterally surrounds the first block 202 and / or one or more conductor structures 218 (e.g., Figure 2A ). In some embodiments, the first portion 292 of the guard ring 208 is discontinuous or has breaks so as to laterally surround, wrap around, etc. some but not all of the first block 202 and / or one or more conductor structures 218. In some embodiments, the first portion 292 of the guard ring 208 is continuous so as to laterally surround, wrap around, etc. all of the first block 202 and / or one or more conductor structures 218. In some embodiments, the first portion 292 includes at least one of the via 282, the metal layer 280, the via 278, the metal layer 276, or the via 274.

[0287] In some embodiments, the second portion 294 of the guard ring 208 laterally surrounds the first block 202 (at Figure 2A 202 and / or one or more conductor structures 218. In some embodiments, second portion 294 of guard ring 208 is discontinuous or has breaks so as to laterally surround, wrap around some but not all of first section 202 and / or one or more conductor structures 218. In some embodiments, second portion 294 of guard ring 208 is continuous so as to laterally surround, wrap around, etc. all of first section 202 and / or one or more conductor structures 218. In some embodiments, second portion 294 includes at least one of via 272, metal layer 270, via 268, metal layer 266, or metal layer 288.

[0288] In some embodiments, the third portion of the guard ring 208 laterally surrounds the first block 202 (eg, Figure 2A 202 and / or one or more conductor structures 218. In some embodiments, the third portion of the guard ring 208 is discontinuous or has breaks so as to laterally surround or encircle some but not all of the first block 202 and / or one or more conductor structures 218. In some embodiments, the third portion of the guard ring 208 is continuous so as to laterally surround or encircle all of the first block 202 and / or one or more conductor structures 218. In some embodiments, the third portion includes a metal layer 284.

[0289] In some embodiments, the first portion 292 of the guard ring 208 does not vertically overlap with the second portion 294 of the guard ring 208 in one or more first regions of the guard ring 208. For example, in one or more first regions of the guard ring 208, the first portion 292 is laterally offset from the second portion 294 such that a vertical line (e.g., a line orthogonal to a plane in which the maximum extent of a layer of the semiconductor device 200 lies) does not intersect both of the first portion 292 and the second portion 294. In some embodiments, the one or more first regions include the entirety of the guard ring 208, and the first portion 292 of the guard ring 208 does not vertically overlap with the second portion 294 of the guard ring 208 in any region of the guard ring 208.

[0290] In some embodiments, the one or more first regions do not include the entirety of the guard ring 208, and the first portion 292 of the guard ring 208 vertically overlaps with the second portion 294 in the one or more second regions of the guard ring 208. In some embodiments, the one or more first regions where the first portion 292 does not vertically overlap with the second portion 294 include at least some of the first corner region 204, at least some of the second corner region 206, at least some of the third corner region 226, and / or at least some of the fourth corner region 224. In some embodiments, the one or more second regions where the first portion 292 vertically overlaps with the second portion 294 include at least some of the first wall 210, at least some of the second wall 222, at least some of the third wall 214, and / or at least some of the fourth wall 216.

[0291] Figure 2C The cross-sectional view shown in FIG. 1 includes a cross-section of a third wall 214 of a protective ring 208 according to some embodiments, wherein in at least some of the third wall 214 of the protective ring 208, a first portion 292 of the protective ring 208 is laterally offset from a second portion 294 of the protective ring 208 such that a vertical line does not intersect both of the first portion 292 and the second portion 294.

[0292] FIG. 3A to FIG. 3C A semiconductor device 300 according to some embodiments is depicted. Figure 3A A top view of the semiconductor device 300 is shown. Figure 3B Draw along Figure 3A A cross-sectional view of the semiconductor device 300 observed along line segment BB. Figure 3C Draw along Figure 3A A cross-sectional view of the semiconductor device 300 observed along line segment CC.

[0293] The semiconductor device 300 includes a guard ring 308, such as at least one of a seal ring, a guard ring, etc. In some embodiments, the guard ring 308 laterally surrounds the first block 302 or at least one of the one or more conductor structures 318 in the first block 302. In some embodiments, the guard ring 308 is discontinuous or has breaks so as to laterally surround, encircle, etc. some but not all of the first block 302 and / or the one or more conductor structures 318. In some embodiments, the guard ring 308 is continuous so as to laterally surround, encircle, etc. all of the first block 302 and / or the one or more conductor structures 318.

[0294] In some embodiments, the semiconductor device 300 includes a first semiconductor layer 334 overlying the guard ring 308. Figure 3A Layers, features, components, etc. overlying the guard ring 308 and / or the one or more conductor structures 318 are removed to draw a top view of the guard ring 308 and / or the one or more conductor structures 318. According to some embodiments, Figure 3A The top surface 390 of the metal layer 366 of the guard ring 308 is depicted in FIG. Figure 3B and Figure 3C ) and the top surface 391 of the metal layer 388 (shown in Figure 3B and Figure 3C In some embodiments, top surface 390 and top surface 391 are located at different heights.

[0295] In some embodiments, one or more conductor structures 318 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more conductor structures 118.

[0296] In some embodiments, the guard ring 308 includes a first wall 310, a second wall 322 opposite the first wall 310, a third wall 314, and a fourth wall 316 opposite the third wall 314. At least some of the one or more conductor structures 318 are located between the first wall 310 and the second wall 322, and at least some of the one or more conductor structures 318 are located between the third wall 314 and the fourth wall 316. In some embodiments, the guard ring 308 includes at least one of a first angular region 304 separating the first wall 310 from the third wall 314, a second angular region 306 separating the fourth wall 316 from the first wall 310, a third angular region 326 separating the second wall 322 from the fourth wall 316, or a fourth angular region 324 separating the third wall 314 from the second wall 322. Other structures and / or configurations of the walls and / or angular regions of the guard ring 308 relative to other elements, features, etc. are within the scope of the present disclosure.

[0297] According to some embodiments, the guard ring 308 at least protects, shields, electrically isolates, or at least one of the semiconductor device 300, the one or more conductor structures 318, or one or more other layers, features, etc. of the semiconductor device 300. In some embodiments, the guard ring 308 provides support, stability, structural integrity, etc. for at least one of the semiconductor device 300, the one or more conductor structures 318, or one or more other layers, features, etc. of the semiconductor device 300.

[0298] According to some embodiments, Figure 3BThe cross-sectional view shown in FIG. 3 includes a cross-sectional view of a fourth corner region 324 of the guard ring 308. In some embodiments, the semiconductor device 300 includes at least one of a substrate 364, a second semiconductor layer 362 over the substrate 364, a first dielectric layer 358 over the second semiconductor layer 362, a second dielectric layer 354 over the first dielectric layer 358, a third dielectric layer 350 over the second dielectric layer 354, a fourth dielectric layer 346 over the third dielectric layer 350, a fifth dielectric layer 342 over the fourth dielectric layer 346, a first passivation layer 340 over the fifth dielectric layer 342, a third semiconductor layer 338 over the first passivation layer 340, or a first semiconductor layer 334 over the third semiconductor layer 338. In some embodiments, at least one of the substrate 364, the second semiconductor layer 362, the first dielectric layer 358, the second dielectric layer 354, the third dielectric layer 350, the fourth dielectric layer 346, the fifth dielectric layer 342, the first passivation layer 340, the third semiconductor layer 338, or the first semiconductor layer 334 has a dielectric layer corresponding to Figures 1A to 1C The features, characteristics, relationships, etc. of at least one of the substrate 164, the second semiconductor layer 162, the first dielectric layer 158, the second dielectric layer 154, the third dielectric layer 150, the fourth dielectric layer 146, the fifth dielectric layer 142, the first passivation layer 140, the third semiconductor layer 138, or the first semiconductor layer 134 are provided herein. In some embodiments, one, some, and / or all layers of the semiconductor device 300 are formed using the Figures 1A to 1C Formed by one or more techniques provided.

[0299] In some embodiments, the semiconductor device 300 includes one or more etch stop layers 336, for example, the etch stop layers 336 are located between adjacent layers of the semiconductor device 300. In some embodiments, the one or more etch stop layers 336 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more etch stop layers 136. In some embodiments, one or more etch stop layers 336 are formed using the Figures 1A to 1C One or more techniques for forming the one or more etch stop layers 136 are formed.

[0300] In some embodiments, guard ring 308 is disposed within one or more first dielectric layers of semiconductor component 300. For example, according to some embodiments, guard ring 308 extends over at least some of the one or more first dielectric layers and / or through at least some of one or more other layers of semiconductor component 300. In some embodiments, one or more first dielectric layers include at least one of dielectric layers 358, 354, 350, 346, or 342. According to some embodiments, guard ring 308 includes alternating stacks of metal layers and vias. In some embodiments, guard ring 308 includes at least one of via 382, ​​metal layer 380 overlying via 382, ​​via 378 overlying metal layer 380, metal layer 376 overlying via 378, via 374 overlying metal layer 376, metal layer 384 overlying via 374, via 372 overlying metal layer 384, metal layer 370 overlying via 372, via 368 overlying metal layer 370, metal layer 366 overlying via 368, or metal layer 388 overlying metal layer 366. In some embodiments, a metal layer or via of guard ring 308 is in contact with, such as in direct contact with, an adjacent via or metal layer. In some embodiments, at least one of the following is included: metal layer 380 is in contact with via 382, ​​via 378 is in contact with metal layer 380, metal layer 376 is in contact with via 378, via 374 is in contact with metal layer 376, metal layer 384 is in contact with via 374, via 372 is in contact with metal layer 384, metal layer 370 is in contact with via 372, via 368 is in contact with metal layer 370, metal layer 366 is in contact with via 368, or metal layer 388 is in contact with metal layer 366. Other structures and / or configurations of vias and / or metal layers of guard ring 308 relative to other components, features, etc. are within the scope of the present disclosure.

[0301] In some embodiments, the vias and / or metal layer of the guard ring 308 have Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the vias and / or metal layers of the guard ring 108. In some embodiments, the vias and / or metal layers of the guard ring 308 use the Figures 1A to 1C The vias and / or metal layers used to form the guard ring 108 may be formed using one or more corresponding techniques provided herein.

[0302] In some embodiments, guard ring 308 is discontinuous, that is, one or more intermediate dielectric layers do not include at least one of the metal layer or the via of guard ring 308. In some embodiments, guard ring 308 is continuous, in that the intermediate dielectric layer includes at least one of the metal layer or the via of guard ring 308.

[0303] In some embodiments, at least one of metal layers 380, 376, 384, 370, 366, or 388 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of metal layers 380, 376, 384, 370, 366, or 388 comprises at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of metal layers 380, 376, 384, 370, 366, or 388 have a different composition than other metal layers. In some embodiments, at least one of vias 382, ​​378, 374, 372, or 368 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of vias 382, ​​378, 374, 372, or 368 comprises at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable materials. In some embodiments, at least some of vias 382, ​​378, 374, 372, or 368 have a different composition than other vias. In some embodiments, (i) via 382 comprises tungsten, (ii) at least one of metal layer 380, via 378, metal layer 376, via 374, metal layer 384, via 372, metal layer 370, via 368, or metal layer 366 comprises copper, or (iii) metal layer 388 comprises aluminum. In some embodiments, at least some of one or more conductor structures 318 have the same composition as at least some of metal layers 380 , 376 , 384 , 370 , 366 , or 388 or at least some of vias 382 , 378 , 374 , 372 , or 368 .

[0304] In some embodiments, the guard ring 308 includes a first portion 392, a second portion located at a higher height than the first portion 392, and a third portion located at a higher height than the second portion. In some embodiments, the first portion 392 of the guard ring 308 laterally surrounds the first block 302 and / or one or more conductor structures 318 (e.g., Figure 3A ). In some embodiments, the first portion 392 of the guard ring 308 is discontinuous or has breaks so as to laterally surround or encircle some but not all of the first block 302 and / or the one or more conductor structures 318. In some embodiments, the first portion 392 of the guard ring 308 is continuous so as to laterally surround or encircle all of the first block 302 and / or the one or more conductor structures 318. In some embodiments, the first portion 392 includes at least one of the via 382, ​​the metal layer 380, the via 378, the metal layer 376, or the via 374.

[0305] In some embodiments, the second portion of the guard ring 308 laterally surrounds the first block 302 (eg, Figure 3A 302 and / or one or more conductor structures 318. In some embodiments, the second portion of the guard ring 308 is discontinuous or has breaks so as to laterally surround, wrap around, etc. some but not all of the first block 302 and / or one or more conductor structures 318. In some embodiments, the second portion of the guard ring 308 is continuous so as to laterally surround, wrap around, etc. all of the first block 302 and / or one or more conductor structures 318. In some embodiments, the second portion includes a through hole 368.

[0306] In some embodiments, the third portion of the guard ring 308 laterally surrounds the first block 302 (eg, Figure 3A 302 and / or one or more conductor structures 318. In some embodiments, the third portion of the guard ring 308 is discontinuous or has breaks so as to laterally surround, wrap around, etc. some but not all of the first block 302 and / or one or more conductor structures 318. In some embodiments, the third portion of the guard ring 308 is continuous so as to laterally surround, wrap around, etc. all of the first block 302 and / or one or more conductor structures 318. In some embodiments, the third portion includes a metal layer 388.

[0307] In some embodiments, the first portion 392 of the guard ring 308 does not vertically overlap with the second portion of the guard ring 308 in one or more first regions of the guard ring 308. For example, in one or more first regions of the guard ring 308, the first portion 392 is laterally offset from the second portion such that a vertical line (e.g., a line orthogonal to a plane in which the maximum extent of a layer of the semiconductor device 300 lies) does not intersect both of the first portion 392 and the second portion. In some embodiments, the one or more first regions include all of the guard ring 308, and the first portion 392 of the guard ring 308 does not vertically overlap with the second portion of the guard ring 308 in any region of the guard ring 308.

[0308] In some embodiments, the first portion 392 of the guard ring 308 does not vertically coincide with the third portion of the guard ring 308 in one or more first regions of the guard ring 308. For example, in one or more first regions of the guard ring 308, the first portion 392 is laterally offset from the third portion such that a vertical line does not intersect both of the first portion 392 and the third portion.

[0309] In some embodiments, the second portion of the guard ring 308 does not vertically coincide with the third portion of the guard ring 308 in the one or more first regions of the guard ring 308. For example, in the one or more first regions of the guard ring 308, the second portion is laterally offset from the third portion such that a vertical line does not intersect both of the second portion and the third portion.

[0310] In some embodiments, the one or more first regions do not include all of the guard ring 308, and the first portion 392 of the guard ring 308 vertically overlaps with the second portion in the one or more second regions of the guard ring 308. In some embodiments, the one or more first regions where the first portion 392 does not vertically overlap with the second portion include at least some of the first corner region 304, at least some of the second corner region 306, at least some of the third corner region 326, and / or at least some of the fourth corner region 324. In some embodiments, the one or more second regions where the first portion 392 vertically overlaps with the second portion include at least some of the first wall 310, at least some of the second wall 322, at least some of the third wall 314, and / or at least some of the fourth wall 316.

[0311] Figure 3C 3 includes a cross-section of a third wall 314 of the guard ring 308 according to some embodiments. In some embodiments, in at least some of the third wall 314 of the guard ring 308, a first portion 392 of the guard ring 308 is laterally offset from a second portion of the guard ring 308 such that a vertical line does not intersect both of the first portion 392 and the second portion. In some embodiments, in at least some of the third wall 314 of the guard ring 308, a first portion 392 of the guard ring 308 is laterally offset from a third portion of the guard ring 308 such that a vertical line does not intersect both of the first portion 392 and the third portion.

[0312] FIG. 4A to FIG. 4C A semiconductor device 400 according to some embodiments is depicted. Figure 4A A top view of the semiconductor device 400 is shown. Figure 4B Draw along Figure 4A A cross-sectional view of the semiconductor device 400 observed along line segment BB. Figure 4C Draw along Figure 4A A cross-sectional view of the semiconductor device 400 observed along line segment CC.

[0313] The semiconductor device 400 includes a guard ring 408, such as at least one of a seal ring, a guard ring, etc. In some embodiments, the guard ring 408 laterally surrounds the first block 402 or at least one of the one or more conductor structures 418 in the first block 402. In some embodiments, the guard ring 408 is discontinuous or has breaks so as to laterally surround, encircle, etc. some but not all of the first block 402 and / or the one or more conductor structures 418. In some embodiments, the guard ring 408 is continuous so as to laterally surround, encircle, etc. all of the first block 402 and / or the one or more conductor structures 418.

[0314] In some embodiments, the semiconductor device 400 includes a first semiconductor layer 434 overlying the guard ring 408. Figure 4AIn the embodiment, layers, features, components, etc. overlying guard ring 408 and / or one or more conductor structures 418 are removed to show a top view of guard ring 408 and / or one or more conductor structures 418. Figure 4A The top surface 487 of the metal layer 470 of the guard ring 408 is depicted in FIG. Figure 4B and Figure 4C ), the top surface 490 of the metal layer 466 (in Figure 4B and Figure 4C ) and the top surface 491 of the metal layer 488 (in Figure 4B and Figure 4C In some embodiments, top surface 487, top surface 490, and top surface 491 are located at different heights.

[0315] In some embodiments, one or more conductor structures 418 have Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more conductor structures 118.

[0316] In some embodiments, the guard ring 408 includes a first wall 410, a second wall 422 opposite the first wall 410, a third wall 414, and a fourth wall 416 opposite the third wall 414. At least some of the one or more conductor structures 418 are located between the first wall 410 and the second wall 422, and at least some of the one or more conductor structures 418 are located between the third wall 414 and the fourth wall 416. In some embodiments, the guard ring 408 includes at least one of a first corner region 404 separating the first wall 410 from the third wall 414, a second corner region 406 separating the fourth wall 416 from the first wall 410, a third corner region 426 separating the second wall 422 from the fourth wall 416, or a fourth corner region 424 separating the third wall 414 from the second wall 422. Other structures and / or configurations of the walls and / or corner regions of the guard ring 408 relative to other elements, features, etc. are within the scope of the present disclosure.

[0317] According to some embodiments, the guard ring 408 at least protects, shields, electrically isolates, etc., at least one of the semiconductor device 400, the one or more conductor structures 418, or one or more other layers, features, etc. of the semiconductor device 400. In some embodiments, the guard ring 408 provides support, reinforcement, structural integrity, etc. for at least one of the semiconductor device 400, the one or more conductor structures 418, or one or more other layers, features, etc. of the semiconductor device 400.

[0318] According to some embodiments, Figure 4BThe cross-sectional view shown in FIG. 4 includes a cross-sectional view of a fourth corner region 424 of the guard ring 408. In some embodiments, the semiconductor device 400 includes a substrate 464, a second semiconductor layer 462 above the substrate 464, a first dielectric layer 458 above the second semiconductor layer 462, a second dielectric layer 454 above the first dielectric layer 458, a third dielectric layer 450 above the second dielectric layer 454, a fourth dielectric layer 405 above the third dielectric layer 450, a fifth dielectric layer 411 above the fourth dielectric layer 405, At least one of the sixth dielectric layer 446 over the fifth dielectric layer 411, the seventh dielectric layer 417 over the sixth dielectric layer 446, the eighth dielectric layer 423 over the seventh dielectric layer 417, the ninth dielectric layer 442 over the eighth dielectric layer 423, the first passivation layer 440 over the ninth dielectric layer 442, the third semiconductor layer 438 over the first passivation layer 440, or the first semiconductor layer 434 over the third semiconductor layer 438. In some embodiments, one or more layers of the semiconductor device 400 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the semiconductor device 100 of the present invention. In some embodiments, one, some, and / or all layers of the semiconductor device 400 are formed using the present invention. Figures 1A to 1C One or more techniques are provided.

[0319] In some embodiments, the semiconductor device 400 includes one or more etch stop layers 436, such as between adjacent layers of the semiconductor device 400. In some embodiments, the one or more etch stop layers 436 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more etch stop layers 136. In some embodiments, one or more etch stop layers 436 are formed using the method described herein. Figures 1A to 1C The one or more etch stop layers 136 may be formed by one or more techniques provided by the present invention.

[0320] In some embodiments, guard ring 408 is disposed within one or more first dielectric layers of semiconductor component 400. For example, according to some embodiments, guard ring 408 extends over at least some of the one or more first dielectric layers and / or through at least some of one or more other layers of semiconductor component 400. In some embodiments, one or more first dielectric layers include at least one of dielectric layers 458, 454, 450, 405, 411, 446, 417, 423, or 442. According to some embodiments, guard ring 408 includes alternating stacks of metal layers and vias. In some embodiments, guard ring 408 includes via 482, metal layer 480 overlying via 482, via 478 overlying metal layer 480, metal layer 476 overlying via 478, via 474 overlying metal layer 476, metal layer 484 overlying via 474, metal layer 403 overlying via 401, via 407 overlying metal layer 403, and metal layer 484 overlying via 474. 09, via 472 overlying metal layer 409, metal layer 470 overlying via 472, via 413 overlying metal layer 470, metal layer 415 overlying via 413, via 419 overlying metal layer 415, metal layer 421 overlying via 419, via 468 overlying metal layer 421, metal layer 466 overlying via 468, or metal layer 488 overlying metal layer 466. In some embodiments, a metal layer or via of guard ring 408 is in contact with, such as in direct contact with, an adjacent via or metal layer. In some embodiments, at least one of the following is included: metal layer 480 is in contact with via 482, via 478 is in contact with metal layer 480, metal layer 476 is in contact with via 478, via 474 is in contact with metal layer 476, metal layer 484 is in contact with via 474, via 401 is in contact with metal layer 484, metal layer 403 is in contact with via 401, via 407 is in contact with metal layer 403, metal layer 409 is in contact with Via 407 contacts metal layer 409, metal layer 470 contacts via 472, via 413 contacts metal layer 470, metal layer 415 contacts via 413, via 419 contacts metal layer 415, metal layer 421 contacts via 419, via 468 contacts metal layer 421, metal layer 466 contacts via 468, or metal layer 488 contacts metal layer 466. Other structures and / or configurations of vias and / or metal layers of guard ring 408 relative to other components, features, etc. are within the scope of the present disclosure.

[0321] In some embodiments, the vias and / or metal layer of the guard ring 408 have Figures 1A to 1COne or more features, characteristics, relationships, etc. provided by the vias and / or metal layers of the guard ring 108. In some embodiments, the vias and / or metal layers of the guard ring 408 are formed using the Figures 1A to 1C The guard ring 108 is formed by providing one or more techniques for the vias and / or metal layers.

[0322] In some embodiments, guard ring 408 is discontinuous, i.e., one or more intervening dielectric layers do not include at least one of a metal layer or a via of guard ring 408. In some embodiments, guard ring 408 is continuous, in that an intervening dielectric layer includes at least one of a metal layer or a via of guard ring 408.

[0323] In some embodiments, at least one of metal layers 480, 476, 484, 403, 409, 470, 415, 421, 466, or 488 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of metal layers 480, 476, 484, 403, 409, 470, 415, 421, 466, or 488 comprises copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, AL2O3, ZrO2, or other suitable material. In some embodiments, at least some of metal layers 480, 476, 484, 403, 409, 470, 415, 421, 466, or 488 have a different composition than other metal layers. In some embodiments, at least one of vias 482, 478, 474, 401, 407, 472, 413, 419, or 468 comprises at least one of a metal, a metal alloy, or other suitable material. In some embodiments, at least one of vias 482, 478, 474, 401, 407, 472, 413, 419, or 468 includes at least one of copper, aluminum, tin, nickel, gold, silver, tungsten, TaN, Al2O3, ZrO2, or other suitable materials. In some embodiments, at least some vias 482, 478, 474, 401, 407, 472, 413, 419, or 468 have a different composition than other vias. In some embodiments, (i) via 482 comprises tungsten, (ii) at least one of metal layer 480, via 478, metal layer 476, via 474, metal layer 484, via 401, metal layer 403, via 407, metal layer 409, via 472, metal layer 470, via 413, metal layer 415, via 419, metal layer 421, via 468, or metal layer 466 comprises copper, or (iii) metal layer 488 comprises aluminum. In some embodiments, at least some of the one or more conductor structures 418 have the same composition as at least one of metal layers 480, 476, 484, 403, 409, 470, 415, 421, 466, or 488 or at least one of vias 482, 478, 474, 401, 407, 472, 413, 419, or 468.

[0324] In some embodiments, the guard ring 408 includes a first portion 492, a second portion 494 located at a higher height than the first portion 492, and a third portion 496 located at a higher height than the second portion 494. In some embodiments, the first portion 492 of the guard ring 408 laterally surrounds the first block 402 and / or one or more conductor structures 418 (e.g., Figure 4A4. In some embodiments, the first portion 492 of the guard ring 408 is discontinuous or has breaks so as to laterally surround or wrap around some but not all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the first portion 492 of the guard ring 408 is continuous so as to laterally surround or wrap around all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the first portion 492 includes at least one of the via 482, the metal layer 480, the via 478, the metal layer 476, or the via 474.

[0325] In some embodiments, the second portion 494 of the guard ring 408 laterally surrounds the first block 402 (at Figure 4A 402 and / or one or more conductor structures 418. In some embodiments, the second portion 494 of the guard ring 408 is discontinuous or has breaks so as to laterally surround, wrap around, etc. some but not all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the second portion 494 of the guard ring 408 is continuous so as to laterally surround, wrap around, etc. all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the second portion 494 includes at least one of the via 401, the metal layer 403, the via 407, the metal layer 409, or the via 472.

[0326] In some embodiments, the third portion 496 of the guard ring 408 laterally surrounds the first block 402 (at Figure 4A 402 and / or one or more conductor structures 418. In some embodiments, the third portion 496 of the guard ring 408 is discontinuous or has breaks so as to laterally surround, wrap around some but not all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the third portion 496 of the guard ring 408 is continuous so as to laterally surround, wrap around, etc. all of the first block 402 and / or one or more conductor structures 418. In some embodiments, the third portion 496 includes at least one of the via 413, the metal layer 415, the via 419, the metal layer 421, or the via 468.

[0327] In some embodiments, the first portion 492 of the guard ring 408 does not vertically overlap with the second portion 494 of the guard ring 408 in one or more first regions of the guard ring 408. For example, in one or more first regions of the guard ring 408, the first portion 492 is laterally offset from the second portion 494 such that a vertical line (e.g., a line orthogonal to a plane in which the maximum extent of a layer of the semiconductor device 400 lies) does not intersect both of the first portion 492 and the second portion 494. In some embodiments, the one or more first regions include the entire guard ring 408, and the first portion 492 of the guard ring 408 does not vertically overlap with the second portion 494 of the guard ring 408 in any region of the guard ring 408.

[0328] In some embodiments, the first portion 492 of the guard ring 408 does not vertically coincide with the third portion 496 of the guard ring 408 in one or more first regions of the guard ring 408. For example, in one or more first regions of the guard ring 408, the first portion 492 is laterally offset from the third portion 496 such that a vertical line does not intersect both of the first portion 492 and the third portion 496.

[0329] In some embodiments, the second portion 494 of the guard ring 408 does not vertically coincide with the third portion 496 of the guard ring 408 in one or more first regions of the guard ring 408. For example, in one or more first regions of the guard ring 408, the second portion 494 is laterally offset from the third portion 496 such that a vertical line does not intersect both of the second portion 494 and the third portion 496.

[0330] In some embodiments, the one or more first regions do not include all of the guard ring 408, and the first portion 492 of the guard ring 408 vertically overlaps with the second portion 494 in the one or more second regions of the guard ring 408. In some embodiments, the one or more first regions where the first portion 492 does not vertically overlap with the second portion 494 include at least some of the first corner region 404, at least some of the second corner region 406, at least some of the third corner region 426, and / or at least some of the fourth corner region 424. In some embodiments, the one or more second regions where the first portion 492 vertically overlaps with the second portion 494 include at least some of the first wall 410, at least some of the second wall 422, at least some of the third wall 414, and / or at least some of the fourth wall 416.

[0331] Figure 4C4. The cross-sectional view depicted in FIG. 4 includes a cross-section of a third wall 414 of the guard ring 408 according to some embodiments. In some embodiments, in at least some of the third wall 414 of the guard ring 408, a first portion 492 of the guard ring 408 is laterally offset from a second portion 494 of the guard ring 408 such that a vertical line does not intersect both of the first portion 492 and the second portion 494. In some embodiments, in at least some of the third wall 414 of the guard ring 408, a first portion 492 of the guard ring 408 is laterally offset from a third portion 496 of the guard ring 408 such that a vertical line does not intersect both of the first portion 492 and the third portion 496.

[0332] Figure 5 A semiconductor device 500 according to some embodiments is shown. In some embodiments, the semiconductor device 500 includes a first portion 514 and a second portion 515. In some embodiments, the first portion 514 includes at least one of a first die, a first wafer, etc., and the second portion 515 includes at least one of a second die, a second wafer, etc. In some embodiments, the first portion 514 and the second portion 515 are separately manufactured and then disposed together.

[0333] In some embodiments, the first portion 514 of the semiconductor device 500 includes a first gap-filling structure 504, a second gap-filling structure 505, a first substrate 564, a semiconductor layer 562 over the first substrate 564, one or more dielectric layers 506 over the semiconductor layer 562, a first passivation layer 540 over the one or more dielectric layers 506, a semiconductor layer 538 over the first passivation layer 540, a semiconductor layer 534 over the semiconductor layer 538, a semiconductor layer 510 over the semiconductor layer 534, or a layer 512 over the semiconductor layer 510. In some embodiments, at least one of the first substrate 564, the semiconductor layer 562, the one or more dielectric layers 506, the first passivation layer 540, the semiconductor layer 538, or the semiconductor layer 534 is located between the first gap-filling structure 504 and the second gap-filling structure 505. In some embodiments, one, some, and / or all of the layers of the first portion 514 are formed using the techniques described herein. Figures 1A to 1C One or more techniques are provided.

[0334] In some embodiments, the first substrate 564 has Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the substrate 164. In some embodiments, the semiconductor layer 562 has the Figures 1A to 1C The semiconductor layer 562 is a middle-of-line (MOL) layer. In some embodiments, the one or more dielectric layers 506 have the characteristics, properties, relationships, etc. provided by the second semiconductor layer 162. Figures 1A to 1COne or more features, characteristics, relationships, etc. provided by dielectric layers 154, 150, 146, and 142. In some embodiments, one or more dielectric layers 506 are one or more back-end-of-line (BEOL) layers. In some embodiments, first passivation layer 540 has the characteristics described herein. Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the first passivation layer 140. In some embodiments, the semiconductor layer 538 has the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the third semiconductor layer 138. In some embodiments, the semiconductor layer 534 has the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the first semiconductor layer 134. In some embodiments, the semiconductor layer 510 is a second passivation layer having the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by the first passivation layer 140. In some embodiments, the semiconductor layer 510 has the same composition as the first passivation layer 540. In some embodiments, the semiconductor layer 510 has a different composition than the first passivation layer 540.

[0335] According to some embodiments, the first portion 514 of the semiconductor device 500 includes one or more first conductor structures 518. In some embodiments, the one or more first conductor structures 518 have Figures 1A to 1C In some embodiments, the solder bump 502 is in contact with the conductor structure of the one or more first conductor structures 518. In some embodiments, the solder bump 502 is used to connect the semiconductor device 500 to a second semiconductor device (not shown). In some embodiments, the one or more first conductor structures 518 include at least one of BEOL interconnects or MOL interconnects. In some embodiments, the one or more first conductor structures 518 include at least one of one or more BEOL interconnects in the one or more dielectric layers 506 or one or more MOL interconnects in the semiconductor layer 562.

[0336] According to some embodiments, the first portion 514 of the semiconductor device 500 includes a first guard ring 508. In some embodiments, the first guard ring 508 has Figures 1A to 1C Protection ring 108, FIG. 2A to FIG. 2C Protection ring 208, FIG. 3A to FIG. 3C Protection ring 308 or FIG. 4A to FIG. 4CIn some embodiments, the first guard ring 508 at least protects, shields, electrically isolates, etc., one or more first conductor structures 518, or one or more other layers, features, etc. of the semiconductor device 500. In some embodiments, the first guard ring 508 provides support, reinforcement, structural integrity, etc. for at least one of the semiconductor device 500, the one or more first conductor structures 518, or one or more other layers, features, etc. of the semiconductor device 500.

[0337] In some embodiments, the semiconductor device 500 includes one or more etch stop layers 536, for example, the etch stop layer 536 is located between adjacent layers of the semiconductor device 500. In some embodiments, the one or more etch stop layers 536 have the Figures 1A to 1C One or more features, characteristics, relationships, etc. provided by one or more etch stop layers 136. In some embodiments, one or more etch stop layers 536 are formed using the method described herein. Figures 1A to 1C The one or more etch stop layers 536 are formed by one or more techniques provided by the present invention.

[0338] In some embodiments, the semiconductor device 500 includes a semiconductor layer 599 between the first portion 514 and the second portion 515. In some embodiments, the semiconductor layer 599 promotes adhesion between the first portion 514 and the second portion 515. In some embodiments, the semiconductor layer 599 includes at least one of silicon, an oxide semiconductor material such as silicon oxide, a nitride semiconductor material such as silicon nitride, an oxynitride material, or other suitable materials.

[0339] In some embodiments, the second portion 515 of the semiconductor device 500 has one or more features, characteristics, relationships, etc. provided herein with respect to the first portion 514. In some embodiments, the second portion 515 includes at least one of a third gap filling structure 590, a fourth gap filling structure 591, a fifth gap filling structure 592, a semiconductor structure 593, a second substrate 565, one or more second conductor structures 519, or a second guard ring 509. In some embodiments, the second guard ring 509 at least protects, shields, electrically isolates, etc., one or more second conductor structures 519 of the semiconductor device 500, or at least one of one or more other layers, features, etc. of the semiconductor device 500. In some embodiments, at least one of the first gap filling structure 504, the second gap filling structure 505, the third gap filling structure 590, the fourth gap filling structure 591, or the fifth gap filling structure 592 includes an oxide semiconductor material, such as silicon oxide, or other suitable materials. In some embodiments, the semiconductor structure 593 separates the fourth gap filling structure 591 from the fifth gap filling structure 592. In some embodiments, the semiconductor structure 593 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. In some embodiments, the semiconductor structure 593 has the same composition as at least one of the first substrate 564 or the second substrate 565. In some embodiments, the semiconductor structure 593 has a different composition than at least one of the first substrate 564 or the second substrate 565. In some embodiments, the metal interconnect 520 provides electrical connection between the one or more first conductor structures 518 and the one or more second conductor structures 519.

[0340] According to some embodiments, Figure 6, a method 600 for forming a semiconductor device is depicted in FIG. 602. In operation 602, a first portion of a guard ring is formed, wherein the first portion of the guard ring laterally surrounds a first block. In operation 604, a second portion of the guard ring is formed above the first portion of the guard ring. The second portion of the guard ring laterally surrounds the first block. In one or more first regions, a first segment of the second portion of the guard ring vertically overlaps with the first portion of the guard ring. In one or more first regions, a second segment of the second portion of the guard ring does not overlap with the first portion of the guard ring in a vertical direction. In operation 606, a third portion of the guard ring is formed above the second portion of the guard ring. The third portion of the guard ring laterally surrounds the first block. In one or more first regions, a second segment of the second portion of the guard ring vertically overlaps with the third portion of the guard ring. In one or more first regions, a first segment of the second portion of the guard ring does not overlap with the third portion of the guard ring in a vertical direction. The one or more first regions include at least some of the first portion of the guard ring, at least some of the second portion of the guard ring, and at least some of the third portion of the guard ring.

[0341] In some embodiments, the guard ring comprises Figures 1A to 1C In some embodiments, the first portion of the guard ring corresponds to Figure 1B and Figure 1C The first portion 192 shown in FIG. 1 corresponds to the second portion of the guard ring. Figure 1B and Figure 1C The metal layer 184 shown in FIG. 1 and the third portion of the guard ring corresponds to Figure 1B and Figure 1C In some embodiments, the first portion of forming the guard ring includes forming a through hole 182 (eg, Figure 1B and Figure 1C ), metal layer 180, via 178, metal layer 176, or at least one of via 174. In some embodiments, forming the second portion of the guard ring includes forming metal layer 184 (as shown in FIG. Figure 1B and Figure 1C 184a of metal layer 184. In some embodiments, the second segment of the second portion of the guard ring corresponds to the second segment 184b of metal layer 184. In some embodiments, forming the third portion of the guard ring includes forming at least one of via 172, metal layer 170, via 168, metal layer 166, or metal layer 188.

[0342] In some embodiments, a semiconductor element is provided. The semiconductor element includes one or more conductor structures and a guard ring. The guard ring includes a first portion and a second portion located at a higher height than the first portion. The first portion of the guard ring laterally surrounds the one or more conductor structures. The second portion of the guard ring laterally surrounds the one or more conductor structures. In one or more first regions of the guard ring, the first portion of the guard ring is at least partially laterally offset from the second portion of the guard ring, so that at least a portion of the first portion does not overlap with the second portion in the vertical direction. In some embodiments, in one or more first regions of the guard ring, a first section of the first portion of the guard ring does not vertically overlap with the second portion of the guard ring, while the second section of the first portion of the guard ring vertically overlaps with the second portion of the guard ring.

[0343] In some embodiments, a semiconductor element is provided. The semiconductor element includes one or more dielectric layers. The semiconductor element includes one or more conductor structures in the one or more dielectric layers. The semiconductor element includes a guard ring provided in the one or more dielectric layers. The guard ring includes a first portion, the first portion includes one or more first through holes or at least one of one or more first metal layers. The guard ring includes a second portion, the second portion is located at a higher height than the first portion. The second portion includes one or more second through holes or at least one of one or more second metal layers. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0344] In some embodiments, a semiconductor element is provided. The semiconductor element includes one or more conductor structures and a guard ring. The guard ring includes a first portion and a second portion located at a higher height than the first portion. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0345] In some embodiments, a method for forming a semiconductor element is provided. The method includes forming a first portion of a guard ring, wherein the first portion of the guard ring laterally surrounds a first block. The method includes forming a second portion of the guard ring on the first portion of the guard ring. The second portion of the guard ring laterally surrounds the first block. In one or more first regions, a first segment of the second portion of the guard ring vertically overlaps with the first portion of the guard ring. In one or more first regions, a second segment of the second portion of the guard ring does not vertically overlap with the first portion of the guard ring. The method includes forming a third portion of the guard ring on the second portion of the guard ring. The third portion of the guard ring laterally surrounds the first block. In one or more first regions, the second segment of the second portion of the guard ring vertically overlaps with the third portion of the guard ring. In one or more first regions, the first segment of the second portion of the guard ring does not vertically overlap with the third portion of the guard ring. The one or more first regions include at least some of the first portion of the guard ring, at least some of the second portion of the guard ring, and at least some of the third portion of the guard ring.

[0346] A semiconductor element comprises one or more dielectric layers, one or more conductor structures and a guard ring. The one or more conductor structures are in the one or more dielectric layers. The guard ring is arranged in the one or more dielectric layers. The guard ring comprises a first portion and a second portion. The first portion comprises one or more first through holes or one or more first metal layers. The second portion has a height higher than the first portion. The second portion comprises one or more second through holes or one or more second metal layers. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0347] In some embodiments, the guard ring includes a first wall, a second wall, a third wall, and a fourth wall. The second wall is opposite to the first wall. One or more first conductor structures of the one or more conductor structures are located between the first wall and the second wall. The fourth wall is opposite to the third wall. One or more second conductor structures of the one or more conductor structures are located between the third wall and the fourth wall. The first region includes at least one of a first corner region, a second corner region, a third corner region, or a fourth corner region. The first corner region separates the first wall and the third wall. The second corner region separates the fourth wall and the first wall. The third corner region separates the second wall and the fourth wall. The fourth corner region separates the third wall and the second wall.

[0348] In some embodiments, the one or more first regions of the guard ring include an entirety of the guard ring.

[0349] In some embodiments, the guard ring includes a third portion, the third portion having a height higher than the first portion and a height lower than the second portion. One or more conductor structures are laterally surrounded by the third portion of the guard ring. In one or more first regions of the guard ring, the third portion of the guard ring vertically overlaps the first portion of the guard ring and the second portion of the guard ring.

[0350] In some embodiments, the third portion of the guard ring contacts at least one of the first portion of the guard ring or the second portion of the guard ring.

[0351] In some embodiments, the third location includes at least one of one or more third vias or one or more third metal layers.

[0352] In some embodiments, the semiconductor device includes a passivation layer overlying one or more dielectric layers.

[0353] In some embodiments, a guard ring is disposed in the passivation layer.

[0354] In some embodiments, a semiconductor device includes a substrate underlying one or more dielectric layers.

[0355] In some embodiments, the first portion of the guard ring is located in one or more first dielectric layers of the one or more dielectric layers. The second portion of the guard ring is located in one or more second dielectric layers of the one or more dielectric layers. The one or more second dielectric layers overlie the one or more first dielectric layers.

[0356] A semiconductor element comprises one or more conductor structures and a guard ring. The guard ring comprises a first portion and a second portion. The second portion has a height higher than the first portion. The one or more conductor structures are laterally surrounded by the first portion of the guard ring. The one or more conductor structures are laterally surrounded by the second portion of the guard ring. In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

[0357] In some embodiments, the guard ring includes a first wall, a second wall, a third wall, and a fourth wall. The second wall is opposite to the first wall. One or more first conductor structures of the one or more conductor structures are located between the first wall and the second wall. The fourth wall is opposite to the third wall. One or more second conductor structures of the one or more conductor structures are located between the third wall and the fourth wall. The first region includes at least one of a first corner region, a second corner region, a third corner region, or a fourth corner region. The first corner region separates the first wall and the third wall. The second corner region separates the fourth wall and the first wall. The third corner region separates the second wall and the fourth wall. The fourth corner region separates the third wall and the second wall.

[0358] In some embodiments, the guard ring includes a third portion, the third portion has a height higher than the first portion and a height lower than the second portion. One or more conductor structures are laterally surrounded by the third portion. In one or more first regions of the guard ring, the third portion of the guard ring vertically overlaps the first portion of the guard ring and the second portion of the guard ring.

[0359] In some embodiments, the third portion of the guard ring contacts at least one of the first portion of the guard ring or the second portion of the guard ring.

[0360] A method for forming a semiconductor element includes: forming a first portion of a guard ring, wherein the first portion of the guard ring laterally surrounds a first block; forming a second portion of the guard ring above the first portion of the guard ring, and forming a third portion of the guard ring above the second portion of the guard ring. The second portion of the guard ring laterally surrounds the first block. In one or more first regions, a first section of the second portion of the guard ring vertically overlaps with the first portion of the guard ring. In one or more first regions, a second section of the second portion of the guard ring does not vertically overlap with the first portion of the guard ring. The third portion of the guard ring laterally surrounds the first block. In one or more first regions, a second section of the second portion of the guard ring vertically overlaps with the third portion of the guard ring. In one or more first regions, the first section of the second portion of the guard ring does not vertically overlap with the third portion of the guard ring. The one or more first regions include at least some of the first portions of the guard ring, at least some of the second portions of the guard ring, and at least some of the third portions of the guard ring.

[0361] In some embodiments, forming the second portion of the guard ring includes forming a metal layer over the first portion of the guard ring.

[0362] In some embodiments, the method further includes forming a first dielectric layer, wherein forming a first portion of the guard ring includes forming at least one of a first metal layer or a first via in the first dielectric layer. The method also includes forming a second dielectric layer above the first dielectric layer, wherein forming a second portion of the guard ring includes forming at least one of a second metal layer or a second via in the second dielectric layer.

[0363] In some embodiments, the method includes forming a passivation layer over the second dielectric layer.

[0364] In some embodiments, forming at least one of the first metal layer or the first via in the first dielectric layer includes performing a damascene process.

[0365] In some embodiments, the method includes forming one or more conductor structures in a first block.

[0366] In some embodiments, a semiconductor device is provided. The semiconductor device includes a guard ring. The guard ring includes a first portion and a second portion. The first portion laterally surrounds a first block. The second portion is above the first portion. The second portion laterally surrounds the first block. In one or more first regions, a first section of the second portion of the guard ring vertically overlaps with the first portion of the guard ring. In one or more first regions, a second section of the second portion of the guard ring does not vertically overlap with the first portion of the guard ring.

[0367] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose or to achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

[0368] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described herein are disclosed as example forms of implementing at least some of the claims.

[0369] Various operations of the embodiments are provided herein. The order of some or all operations described should not be construed as implying that these operations must depend on the order. The alternative order will be understood to have the benefits described herein. In addition, it is understood that not all operations must exist in each embodiment provided herein. In addition, it is understood that in certain embodiments, not all operations are necessary.

[0370] It is understood that the layers, features, elements, etc. depicted herein are described with specific dimensions relative to each other, such as structural dimensions or orientations, for the purpose of simplicity and ease of understanding, and in some embodiments, the same actual dimensions are very different from the dimensions described herein. In addition, there are various techniques for forming the layers, regions, features, elements, etc. mentioned herein, such as etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques, such as at least one of chemical vapor deposition (CVD).

[0371] In addition, "example" and "example" are used here to refer to examples, instances, illustrations, etc., and are not necessarily advantageous. In the present application, "or" means an inclusive "or", not an exclusive "or". In addition, "the" used in the present application and the appended claims is generally understood to be "one or more", unless otherwise specified or clearly indicated from the context that it is for a singular form. In addition, when using "comprises", "includes", "has", "has" or their variations, these terms are intended to be inclusive in a manner similar to the term "comprising". In addition, unless otherwise defined, "first", "second" or similar words do not mean time, space, order, etc. On the contrary, these terms are used only as identification words, names, etc. of features, elements, projects, etc. For example, the first element and the second element generally correspond to element A and element B or two different or two identical elements or the same element.

[0372] In addition, although the disclosure has been shown and described for one or more embodiments, equivalent changes and modifications will occur to those skilled in the art based on reading and understanding this specification and the accompanying drawings. The disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned elements (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such elements are intended to correspond to any element (e.g., functionally equivalent) that performs the specified functions of the elements, even if they are not structurally equivalent to the disclosed structures. In addition, although the specific features of the disclosure may be disclosed only for one of several embodiments, such features may be combined with one or more other features in other embodiments, because this may be necessary and advantageous for any given or specific application.

Claims

1. A semiconductor element, characterized in that: Include: one or more dielectric layers; one or more conductor structures in the one or more dielectric layers; and A guard ring is disposed in the one or more dielectric layers, the guard ring comprising: A first part includes at least one of the following: one or more first through holes; or one or more first metal layers; and A second portion, having a height higher than that of the first portion, includes at least one of the following: one or more second through holes; or one or more second metal layers, in: The one or more conductor structures are laterally surrounded by the first portion of the guard ring; The one or more conductor structures are laterally surrounded by the second portion of the guard ring; and In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

2. The semiconductor device according to claim 1, wherein: in: The protection ring contains: a first wall; a second wall, opposite to the first wall, wherein one or more first conductor structures of the one or more conductor structures are located between the first wall and the second wall; a third wall; and a fourth wall, opposite to the third wall, wherein one or more second conductor structures of the one or more conductor structures are located between the third wall and the fourth wall; and The one or more first regions include at least one of the following: a first corner region separating the first wall and the third wall; a second corner region separating the fourth wall and the first wall; a third corner region separating the second wall and the fourth wall; or A fourth corner region separates the third wall and the second wall.

3. The semiconductor device according to claim 1, wherein: in: The one or more first regions of the guard ring include an entirety of the guard ring.

4. The semiconductor device according to claim 1, wherein: in: The protection ring includes a third portion, the third portion having a height higher than the first portion and a height lower than the second portion; The one or more conductor structures are laterally surrounded by the third portion of the guard ring; and In the one or more first regions of the guard ring, the third portion of the guard ring vertically overlaps with the first portion of the guard ring and the second portion of the guard ring.

5. The semiconductor device according to claim 1, wherein: in: The first portion of the guard ring is located in one or more first dielectric layers of the one or more dielectric layers; The second portion of the guard ring is located in one or more second dielectric layers of the one or more dielectric layers; and The one or more second dielectric layers overlie the one or more first dielectric layers.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: Include: A passivation layer is above the one or more dielectric layers.

7. A semiconductor element, characterized in that: Include: one or more conductor structures; and A protection ring, comprising: a first portion; and a second portion having a height greater than that of the first portion; in: The one or more conductor structures are laterally surrounded by the first portion of the guard ring; The one or more conductor structures are laterally surrounded by the second portion of the guard ring; and In one or more first regions of the guard ring, the first portion of the guard ring does not vertically overlap with the second portion of the guard ring.

8. The semiconductor device according to claim 7, wherein: in: The protection ring includes a third portion, the third portion having a height higher than the first portion and a height lower than the second portion; The one or more conductor structures are laterally surrounded by the third portion; and In the one or more first regions of the guard ring, the third portion of the guard ring vertically overlaps with the first portion of the guard ring and the second portion of the guard ring.

9. The semiconductor device according to claim 8, wherein: in: The third portion of the guard ring contacts at least one of the first portion of the guard ring or the second portion of the guard ring.

10. A semiconductor element, characterized in that: Include: A protection ring, comprising: A first portion laterally surrounds a first block; and a second portion, above the first portion; in: The second portion laterally surrounds the first block; In one or more first regions, a first section of the second portion of the protection ring vertically overlaps the first portion of the protection ring; and In the one or more first regions, a second section of the second portion of the protective ring does not vertically overlap with the first portion of the protective ring.

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