Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure, which comprises a first packaging assembly, the first packaging assembly comprises a first surface dielectric layer, and the first surface dielectric layer comprises a plurality of first parts and a plurality of second parts. A plurality of first portions extend from a surface of the first surface dielectric layer into the first surface dielectric layer, where the first portions have a first atomic percentage of oxygen, and a plurality of second portions separate the first portions from each other, where the second portions have a second atomic percentage of oxygen lower than the first atomic percentage of oxygen, by selectively treating portions of some of the surface dielectric layer to form a first portion and a second portion, the propagation of bonding waves at the time of bonding is discontinued, thereby mitigating or eliminating minute non-bonding issues.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure, and more particularly to a semiconductor structure including a bonded package assembly. Background Art

[0002] Fusion bonding is a common bonding method used to join two package components (such as chips and / or dies) together. During the bonding process, the packages are first bonded through a pre-bonding process at a lower temperature, followed by a bonding process at a higher temperature to bond the packages together. Utility Model Content

[0003] An embodiment of the present invention provides a semiconductor structure including a first package component, the first package component including a first surface dielectric layer, the first surface dielectric layer including a plurality of first portions and a plurality of second portions. The plurality of first portions extend from a surface of the first surface dielectric layer into the first surface dielectric layer, wherein the first portions have a first oxygen atomic percentage, and the plurality of second portions separate the first portions from each other, wherein the second portions have a second oxygen atomic percentage lower than the first oxygen atomic percentage.

[0004] An embodiment of the present invention provides a semiconductor structure including a device die, the device die including a silicon-containing dielectric layer, the silicon-containing dielectric layer including a plurality of first portions and a plurality of second portions. The plurality of first portions extend from a top surface of the silicon-containing dielectric layer to an intermediate stage between the top surface and a bottom surface of the silicon-containing dielectric layer, and the plurality of second portions extend from the top surface to the bottom surface, wherein the first portions have a higher oxygen atomic percentage than the second portions.

[0005] Based on the above, selected portions of the surface of one or both package components are treated by plasma treatment. By selectively treating some, but not all, portions of the surface dielectric layer to be fused and bonded to form a first portion (e.g., a treated portion) and a second portion (e.g., an untreated portion), during the bonding process of the two package components, a bonding wave travels at different speeds through the treated and untreated portions. Consequently, when the bonding wave enters the treated portion, its propagation is interrupted and discontinuous, thereby reducing the Joule-Thomson effect and at least alleviating or eliminating minor non-bonding issues.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 7A cross-sectional view is shown of an intermediate stage in package formation including a fusion bonding process, in accordance with some embodiments.

[0008] Figures 8 to 10A and Figure 10B Cross-sectional views of some packages according to some embodiments are shown.

[0009] Figure 11 A top view of a wafer, processed patterns, and bonding wave propagation is shown, according to some embodiments.

[0010] 12A to 12E A processed pattern in a device die is shown according to some embodiments.

[0011] Figure 13 Processed patterns in a wafer are shown according to some embodiments.

[0012] Figure 14 and 15 Some oxygen distribution patterns in a treated portion and an adjacent untreated portion are shown according to some embodiments.

[0013] Figure 16 A process flow for forming a package according to some embodiments is shown.

[0014] Description of Reference Numerals

[0015] 20, 120: Package; 22: Die / Device Die / Package / Chip; 24: Semiconductor Substrate; 26, 126: Integrated Circuit Device; 28, 128: Interlayer Dielectric / ILD; 30, 56, 130: Contact Plug; 32, 132: Interconnect Structure; 34, 134: Metal Line; 34A, 134A: Metal Pad; 36, 136: Via; 38, 58, 138: Dielectric Layer; 42: Bonding Film / Untreated Portion; 42A, 42B, 142A, 142B: Dielectric Layer; 42PT, 142 PT: processed portion; 43, 62: arrows; 44: patterned processing mask; 46: processing process; 50: cutting line; 54: encapsulation; 57: dielectric isolation ring; 60: reconstructed wafer; 60': package; 120": wafer; 122: package component / chip; 124: substrate / semiconductor substrate; 142: bonding film / surface dielectric layer / unprocessed portion; 200: process flow; 202, 204, 208, 210, 212, 214, 216: process; P1: pitch; RT1: thickness; W1: width. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clarifying the description of the present disclosure, and is not intended to limit the relationship between the various embodiments and / or configurations.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one component or feature to another component or feature as depicted in the figures. These spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used therein may be interpreted in a similar manner.

[0018] A package and a method for forming a package by fusion bonding are provided. According to some embodiments, fusion bonding is used to bond two package components. Selected portions of the surface of one or both package components are treated by plasma treatment. The treatment causes the treated portion to have properties different from those of the untreated portion. This changes the behavior of bond wave propagation. This avoids small non-bonded areas that may otherwise occur. The embodiments discussed herein are intended to provide examples for implementing or using the subject matter of the present disclosure, and a person of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0019] Figures 1 to 7 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments, including a handling process and a bonding process. The corresponding process is also schematically reflected in FIG. Figure 16 The process flow shown.

[0020] Figure 1A cross-sectional view of a package assembly 20 is shown. According to some embodiments, the package assembly 20 is or includes a device wafer including active devices, represented as integrated circuit devices 26, and possibly passive devices. The package assembly 20 may include a plurality of dies 22 therein, with details of one of the dies 22 shown. According to an alternative embodiment, the package assembly 20 is an interposer wafer, which does not contain active devices and may or may not include passive devices. According to another alternative embodiment, the package assembly 20 is or includes a package, such as an integrated fan-out (InFO) package. For example, the package assembly 20 may be a reconstituted wafer, which includes a plurality of device dies and / or one or more wafers bonded together and encapsulated in one or more encapsulation bodies, such as a molding compound. The package assembly 20 may also be a silicon carrier, which does not contain metal features and has active devices therein.

[0021] The package assembly 20 (instead of being wafer-level) may also be at the die-level and may be a device die, an interposer die, a discrete package (sawed from a reconstituted wafer), etc. In the subsequent discussion, a device wafer is used as an example of the package assembly 20, and the package assembly 20 may also be referred to as a wafer 20. These embodiments may also be applied to an interposer wafer, a reconstituted wafer, discrete packages, discrete device dies, discrete interposer dies, etc.

[0022] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed on a top surface of semiconductor substrate 24. Semiconductor substrate 24 may include or be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, a Group V III compound semiconductor, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0023] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. Details of integrated circuit devices 26 are not detailed herein.

[0024] An inter-layer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills the spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD 28 is made of phospho silicate glass (PSG), boro silicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, or the like. ILD 28 can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), or the like.

[0025] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to overlying metal lines and vias. According to some embodiments, contact plug 30 includes or is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0026] An interconnect structure 32 is formed over ILD 28 and contact plugs 30. Interconnect structure 32 may include metal lines 34 and vias 36 formed in a dielectric layer 38 (also referred to as an inter-metal dielectric (IMD)). Metal lines in the same layer are collectively referred to as a metal layer below. According to some embodiments, interconnect structure 32 includes multiple metal layers interconnected by vias 36. Metal lines 34 and vias 36 may be formed of copper, a copper alloy, and / or another metal. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the low-k dielectric material may have a dielectric constant (k value) less than approximately 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0027] The interconnect structure 32 may further include a passivation layer, which may be formed of a non-low-k dielectric material on top of the low-k dielectric layer. The passivation layer may include or be formed of undoped silicate glass (USG), silicon nitride, silicon oxide, or the like, or multiple layers thereof. It may also include a metal pad (e.g., an aluminum-copper pad), a post-passivation interconnect (PPI), a metal pad, or the like, collectively referred to as a conductive feature.

[0028] Further references Figure 1 , a bonding film 42 is deposited on top of the interconnect structure 32. The top surfaces of the bonding film 42 are coplanar. The bonding film 42 can be a blanket dielectric layer that does not contain conductive features (such as wires and conductive pads). According to some embodiments, the entire bonding film 42 is a homogeneous layer having a uniform composition. In this document, when two components (such as two layers) are referred to as having the same composition, it means that the two components have the same type of elements and the percentages of the corresponding elements in the two components are the same as each other. Conversely, when two components are referred to as having different compositions, it means that one of the two components has at least one element that is not in the other component, or the two components have the same element but the percentages of the elements in the two components are different from each other.

[0029] According to some embodiments, the bonding film 42 may be formed of a silicon-based dielectric material, which may include one or more of oxygen, carbon, and nitrogen. The bonding film 42 may be represented by SiO x N y C z , wherein x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, and z is in a range between about 0 and about 1, and x, y, and z are not all equal to 0. For example, the bonding film 42 may include or be formed of SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.

[0030] According to alternative embodiments, bonding film 42 is a composite layer comprising two or more sub-layers. For example, in the illustrated example, bonding film 42 comprises a dielectric (sub-)layer 42A and a dielectric (sub-)layer 42B disposed on top of dielectric (sub-)layer 42A. Dielectric layers 42A and 42B comprise different materials and compositions. A dashed line is drawn between dielectric layers 42A and 42B to indicate that bonding film 42 can be a homogenous layer or comprise more than one layer.

[0031] Reference Figure 2 , forming a patterned processing mask 44. The corresponding process is Figure 16202 in the process flow 200 is shown in FIG. According to some embodiments, the patterned processing mask 44 includes a photoresist. According to an alternative embodiment, the patterned processing mask 44 is a three-layer mask including a bottom layer, an intermediate layer above the bottom layer, and a photoresist above the intermediate layer. According to yet another embodiment, the patterned processing mask 44 includes a hard mask formed of a material different from that of the bonding film 42 and is patterned with the aid of the photoresist. For example, the patterned processing mask 44 may include titanium nitride, boron nitride, etc. The material of the patterned processing mask 44 is selected so that the bonding film 42 is not damaged when it is removed in a subsequent process.

[0032] The patterned process mask 44 covers some portions of the bonding film 42 while leaving some other portions exposed. According to an embodiment in which the patterned process mask 44 is three-layered, the middle layer and the bottom layer are etched using the patterned photoresist as an etch mask, thereby exposing some portions of the bonding film 42.

[0033] Further references Figure 2 , perform the selective treatment process 46. The corresponding process is Figure 16 2 is shown as process 204 in process flow 200. According to some embodiments, treatment process 46 includes plasma treatment. Process gases used to perform plasma selective treatment process 46 may include nitrogen (N2), oxygen (O2), argon, He, H2, NH3, or combinations thereof, such as N2 / H2, H2 / He, or N2 / He. The treatment time may be shorter than about 60 seconds and may be in a range between about 10 seconds and about 60 seconds.

[0034] According to some embodiments, treatment process 46 is performed using a plasma generated locally from the process gas. The treatment can be performed with an RF power of less than about 100 watts, and the power can be in a range between about 50 watts and about 100 watts. According to some embodiments, a small bias power is applied, the bias power being less than about 200 watts or about 75 watts, for example, between about 10 watts and about 200 watts. According to an alternative embodiment, treatment process 46 is performed without applying a bias power. According to yet another alternative embodiment, treatment process 46 is performed using a remote plasma, wherein the plasma is generated in a remote chamber separate from the process chamber in which selective treatment process 46 is performed, and the plasma is conducted to the process chamber.

[0035] The selective treatment process 46 produces light bombardment on the exposed surface portion of the bonding film 42. Some bonds in the bonding film 42 are thereby destroyed. The treated portion of the bonding film 42 is hereinafter referred to as the treated portion 42PT, and the untreated portion is referred to as the untreated portion 42. The treated portion 42PT may not be visually distinguishable from the untreated portion 42. Accordingly, the pattern of the treated portion 42PT is collectively referred to as a stealth pattern. However, the treated portion 42PT and the untreated portion 42 can be distinguished using tools such as X-ray photoelectron spectroscopy (XPS) and energy-dispersive X-ray spectroscopy (EDX).

[0036] Figure 11 A schematic top view of a wafer 20 is shown in accordance with some embodiments. The wafer 20 includes device dies 22 spaced apart from each other by scribe lines 50. In accordance with some embodiments, a selective processing process 46 is performed at the die level, wherein the pattern of the processed portions 42PT in each device die 22 is the same as the pattern of the processed portions 42PT in the other device dies 22. In accordance with some embodiments, the processed portions 42PT may be confined to the device die 22. Some or all of the processed portions 42PT may be formed in the scribe lines 50. For example, Figure 11 The processed portions 42PT in the dicing streets 50 are shown (using dashed lines). The processed portions 42PT in the dicing streets 50 can form straight strips whose length directions are parallel to the length directions of the corresponding dicing streets 50. Each dicing street 50 can include one or more processed portions 42PT that are parallel to each other. According to other embodiments, the processed portions 42PT are formed in both the device die 22 and the dicing streets 50.

[0037] Figure 12A 、 12B 12C, 12D, and 12E illustrate some example device dies 22 and treated portions 42PT therein according to some embodiments. It should be understood that the treated portions 42PT may have any suitable pattern, provided that, as discussed later, when a bonding wave propagates, the treated portions 42PT are in the path of the bonding wave and are capable of changing the propagation behavior of the bonding wave.

[0038] The treated portion 42PT may form a plurality of rings that may be equally spaced or unevenly spaced and may or may not have breaks therein. Figure 12AAs shown, the treated portion 42PT forms a pattern of multiple squares, with multiple outer squares surrounding corresponding inner squares. Figure 12B The processed portion 42PT is shown forming a pattern of multiple rectangles, with multiple outer rectangles surrounding corresponding inner rectangles. Figure 12C The rectangular (or square) processed portion 42PT is shown with breakpoints to divide each rectangle into a plurality of strips. Figure 12C In the , the processed part is aligned with multiple rectangles, Figure 12A Same as shown in Figure 12A The processed portion 42PT in the rectangle is interrupted (by the unprocessed portion) to form Figure 12C The pattern shown in . Figure 12D The processed portion 42PT is shown forming a plurality of circles. Figure 12E The circular processed portion 42PT is shown to have breakpoints to separate each circle into a plurality of curved strips. Figure 12E In the figure, the processed part is aligned with multiple circles, and Figure 12D Same as shown in Figure 12D The circular treated portion 42PT in FIG. 4 is interrupted (by the untreated portion) to form Figure 12E The treated portion 42PT may also have any other shape, including but not limited to a hexagon, an octagon, a triangle, etc.

[0039] Figure 13 An embodiment is shown in which the processed portion 42PT is formed at the wafer level, which is employed when performing bonding via wafer-on-wafer bonding or chip-on-wafer bonding. The processed portion 42PT may have any other shape, such as a ring, including but not limited to a rectangular, circular, hexagonal, octagonal, triangular, etc. One or more processed portions 42PT may extend into multiple device dies 22. The processed portion 42PT shown may include a circle, rectangle, hexagon, octagon, or the like, and the pattern of the processed portion 42PT may or may not have breaks therein. In addition, the breaks in the outer ring may not be aligned to the same radius as the adjacent inner ring.

[0040] After the selective treatment, the wafer 20 is removed from the corresponding chamber and the vacuum is broken. The patterned processing mask 44 is then removed, for example, by an etching process, wherein ammonia water can be used as an etching liquid. The resulting wafer 20 is as follows Figure 3As shown. Due to the previous treatment process, some bonds in the treated portion 42PT of the bonding film 42 are broken and form dangling bonds. These dangling bonds can react with oxygen or moisture in the air to form oxides. Therefore, the treated portion 42PT has an oxygen atomic percentage OAP greater than that of the untreated portion 42. 42 High oxygen atomic percentage OAP 42PT .

[0041] When wafer 20 is subsequently bonded to package assembly 120, the top surface of treated portion 42PT may be coplanar with the top surface of untreated portion 42. Alternatively, the top surface of treated portion 42PT may be substantially coplanar with the top surface of untreated portion 42. For example, the top surface of treated portion 42PT may be slightly higher than the top surface of untreated portion 42 by a small height difference, which may be less than about 2 angstroms or less than about 1 angstrom. Treated portion 42PT may be oxide-rich (having a higher atomic percentage of oxygen than the untreated portion) and have a thickness RT1 of less than about 100 angstroms, and may be in a range between about 40 angstroms and about 100 angstroms.

[0042] Reference Figure 4 , forming a package assembly 120 and aligning the package assembly 120 with and placing it on the device die 22 in the wafer 20. According to some embodiments, the package assembly 120 is a device die, an interposer die, a package, etc. Alternatively, the package assembly 120 can be a device wafer, an interposer wafer, a reconstituted wafer including bonded device dies, etc. Figure 4 An example of a device die is shown.

[0043] In some exemplary embodiments, package assembly 120 has a structure similar to package assembly 120. The structure and materials of features in package assembly 120 may refer to similar features in wafer 20. Similar features in package assembly 120 are indicated by adding the number "1" before the reference number of the corresponding feature in wafer 20. For example, the substrate in wafer 20 is labeled 24, while the substrate in package assembly 120 is correspondingly labeled 124. Package assembly 120 may include integrated circuit devices 126, ILDs 128, contact plugs 130, interconnect structures 132, dielectric layers 138, metal lines 134, and vias 136. The details of these features may be similar to those of the corresponding features in wafer 20 and are not further described here.

[0044] Package assembly 120 further includes a bonding film 142 on a surface. Bonding film 142 can be a single layer formed of a homogeneous dielectric material or a composite layer including multiple dielectric layers (e.g., 142A and 142B) formed of different dielectric materials and different compositions. The material of bonding film 142 can be selected from the same candidate materials used to form bonding film 42 (and dielectric layers 42A and 42B).

[0045] According to some embodiments, the bonding film 142 is not subjected to the selective treatment process. According to alternative embodiments, the bonding film 142 is also treated by the selective treatment process. The selective treatment process may be performed using a method selected from the same set of candidate methods as the selective treatment process 46. The selective treatment process may also be performed using a process gas selected from the same set of candidate process gases as the selective treatment process 46. The resulting structure is as shown in FIG. Figure 8 to 1 0, which will be discussed in the subsequent paragraphs.

[0046] According to some embodiments, the surface of the bonding film 42 is activated in an activation process, for example, by performing the treatment process in a forming gas including N 2 and H 2 . The selective treatment process 46 may be performed before or after the activation process. The selective treatment process 46 may also be performed using a forming gas including N 2 and H 2 .

[0047] Figure 4 The corresponding process is shown in Figure 16 200 . In some embodiments, during pre-bonding, package assembly 120 is brought into contact with wafer 20 and pressure is applied to press package assemblies 20 and 120 together. Pre-bonding can be performed at room temperature (between about 20° C. and about 25° C.), although higher temperatures may also be used.

[0048] Pre-bonding may begin with the center of package 120 contacting wafer 20. This contact propagates from the contact point to the edges of package 20 and 120, generating a bonding wave that propagates from the contact point to the edges. Figure 11 、 12A The arrow 43 in FIG3 shows the direction of the bonding wave propagation. As the bonding wave propagates from the contact point to the edge, the air between the packaging components (20 and 120) is gradually squeezed out, so that no bubbles or moisture are trapped between the packaging components (20 and 120).

[0049] During the propagation of the bonding wave, the Joule-Thomson effect may occur, in which the temperature of some parts of the packaging components (20 and 120) may drop, and moisture may condense on the low-temperature surface. This will cause some tiny non-bonding areas to appear. If the bonding surface of the bonding film (42 and 142) is isotropic, the Joule-Thomson effect is likely to occur. When the selective treatment process 46 is performed, the surface of the corresponding bonding film 42 (and / or bonding film 142) includes a treated portion 42PT and an untreated portion 42 having different compositions and different properties. The bonding wave travels through the treated portion 42PT and the untreated portion 42 at different speeds. Therefore, when entering the treated portion, the propagation of the bonding wave is interrupted and discontinuous. The Joule-Thomson effect is reduced, and the tiny non-bonding areas are at least reduced or may even be eliminated.

[0050] According to some embodiments, in order to effectively disrupt the coalescence wave, the size and spacing of the treated portions 42PT are selected to effectively disrupt the coalescence wave. Figure 12A 1 shows the width and pitch of processed portions 42PT according to some embodiments. The width W1 of the processed portions 42PT, which may be equal to or different from each other, may range from about 1 μm to about 20 μm. The pitch P1 of the processed portions 42PT, which may also be equal to or different from each other, may range from about 1 μm to about 100 μm. The total area of ​​the processed portions 42PT may be less than about 15% of the total area of ​​the corresponding chip or wafer, and may range from about 5% to about 10%.

[0051] A plurality of package components 120 may be pre-bonded to the wafer 20. After the pre-bonding, an annealing process is performed, such as forming a silicon-oxygen-silicon bond between the bonding films (42 and 142), thereby bonding the bonding films (42 and 142) to each other. Figure 16 2 is shown as process 210 in process flow 200. According to some embodiments, the annealing process is performed at a temperature in a range between about 250° C. and about 300° C. According to some embodiments, the annealing duration may be in a range between about 5 minutes and about 30 minutes.

[0052] Reference Figure 5 , the package component 120 is encapsulated in the encapsulation body 54 (dielectric gap filling area). The corresponding process is Figure 162 is shown as process 212 in process flow 200. According to some embodiments, encapsulation 54 may include a dielectric liner and a dielectric filler material on the dielectric liner. The dielectric liner may be formed of or include silicon nitride, and the dielectric filler material may include silicon oxide. Alternatively, encapsulation 54 may include a molding compound, an epoxy, a resin, and / or the like. A planarization process, such as a CMP process, is performed to make the top surface of encapsulation 54 flush with the top surface of package component 120.

[0053] According to some embodiments, some of the treated portions 42PT may be in areas not bonded to any packaged component 120. Thus, the encapsulant 54 may be in physical contact with the top surfaces of one or both of the treated portions 42PT and the untreated portions 42.

[0054] Figure 6 FIG. 1 shows an exemplary embodiment in which contact plugs 56 are formed to penetrate package component 120 and electrically connect metal pads 134A in package component 120 to metal pads 34A in wafer 20. The corresponding process is shown in FIG. Figure 16 2 is shown as process 214 in process flow 200. Contact plug 56 lands on metal pad 34A of wafer 20. Contact plug 56 penetrates bonding film (42 and 142) and can penetrate and contact both treated portion 42PT and untreated portion 42. A dielectric isolation ring 57 can be formed to electrically insulate contact plug 56 from semiconductor substrate 124.

[0055] Reference Figure 7 , a dielectric layer 58 may be formed to cover the contact plugs 56 and the substrate 124. This forms a reconstructed wafer 60. A singulation process may then be performed along the sawing streets 50 to saw the reconstructed wafer 60 and form packages 60'. Figure 16 , which is shown as process 216 in process flow 200. Each of packages 60' may include a package component 22 (eg, a device die) bonded to a package component 122 (eg, a device die).

[0056] Figure 8 The formation of a reconstituted wafer 60 and a package 60' according to alternative embodiments is shown. The formation processes, structures, and materials of these embodiments are similar to those of Figure 1-7 , except that the selective treatment process 46 is not performed on the wafer 20 but on the package component 120. Therefore, the surface dielectric layer 142 in the package component 120 has a treated portion 142PT and an untreated portion 142. The details of the selective treatment of the surface dielectric layer 142 can be substantially the same as those of the selective treatment process 46.

[0057] Figure 9The formation of a reconstituted wafer 60 and a package 60' according to alternative embodiments is shown. The formation processes, structures, and materials of these embodiments are similar to those of Figure 1-7 , except that both wafer 20 and package assembly 120 are selectively processed. According to these embodiments, each of processed portion 142PT and unprocessed portion 142 can be joined to either processed portion 42PT or unprocessed portion 42 in any combination, depending on the size and location of the processed and unprocessed portions.

[0058] Figure 10A The formation of a reconstituted wafer 60 and a package 60' according to alternative embodiments is shown. The formation processes, structures, and materials of these embodiments are similar to those of Figures 1 to 7 The embodiments are similar to those in the embodiments of the present invention, except that wafer-on-wafer bonding is performed instead of wafer-on-chip bonding, where wafer 120" is bonded to wafer 20. The selective processing process can be performed on one or both of the wafers (20 and 120"). When selective processing is performed on both wafers 20 and 120", each of the treated portion 142PT and the unprocessed portion 142 can be bonded to either of the processed portion 42PT and the unprocessed portion 42 in any combination, depending on the size and location of the processed and unprocessed portions. Figure 10B An embodiment is shown in which stacked die bonding is performed, wherein die 122 is bonded to die 22 .

[0059] As described above, the selective treatment results in the treated portion having a composition that is different from the composition of the untreated portion. Oxygen atomic percentage OAP of the treated portion 42PT 42PT The oxygen atomic percentage OAP may be higher than that of the untreated portion 42 42 Difference (OAP 42PT -OAP 42 ) may be greater than about 2%, and may be within a range between about 2% and about 4%.

[0060] According to embodiments where non-oxygen process gases (e.g., N2 and / or Ar) are used for the selective treatment process 46, the atomic percentage of non-oxygen elements in the process gas may not significantly increase, or may even decrease, in the treated portion 42PT compared to the untreated portion 42. For example, if N2 is used for the selective treatment process 46, the atomic percentage of nitrogen NAP in the treated portion 42PT may be less than 1%. 42PT The nitrogen atomic percentage NAP may be equal to or lower than that in the untreated portion 42. 42 .

[0061] Figure 14The percentage of oxygen atoms in the treated portion 42PT is shown schematically as a function of its position. The surface portion of the bonding film 42 is also Figure 14 The positions corresponding to the treated portion 42PT and the untreated portion 42 and their oxygen atomic percentages are shown in FIG. Figure 14 A line 90 representing the atomic percentage of oxygen is shown. Figure 14 It is shown that the oxygen atomic percentage in the treated portion 42PT is higher than that in the untreated portion 42 .

[0062] Figure 15 The oxygen atomic percentage in the treated portion 42PT is schematically shown as a function of its depth in the bonding film 42. Figure 14 In FIG. 4 , the X-axis represents the position in the direction of arrow 62. It also shows that the treated portion 42PT has a higher atomic percentage of oxygen, while the untreated portion 42 has a lower atomic percentage. The difference in composition can be seen using XPS, EDX, etc.

[0063] The disclosed embodiments have several advantageous features: By selectively processing some, but not all, portions of the surface dielectric layer to be bonded by fusion, the Joule-Thomson effect is reduced and minor non-bonding issues are at least mitigated or can be eliminated.

[0064] According to some embodiments, a method includes: forming a process mask over a first surface dielectric layer of a first package component; patterning the process mask to expose a first portion of the first surface dielectric layer; performing a selective plasma treatment on the first portion of the first surface dielectric layer exposed by the process mask to form a first treated portion; removing the process mask; and bonding a second surface dielectric layer in a second package component to the first surface dielectric layer. In one embodiment, the selective plasma treatment is performed using a process gas selected from nitrogen (N2), oxygen (O2), argon, and combinations thereof.

[0065] In one embodiment, a first package assembly includes a wafer including a plurality of dies, wherein a first processed portion of each of the plurality of dies has a pattern identical to a pattern of first processed portions of other dies in the plurality of dies. In one embodiment, a method further includes activating a first surface dielectric layer using a forming gas including nitrogen (N2) and hydrogen (H2), wherein a selective plasma treatment is performed prior to the activation. In one embodiment, the method further includes activating the first surface dielectric layer using a forming gas including nitrogen (N2) and hydrogen (H2), wherein the selective plasma treatment is performed after the activation.

[0066] In one embodiment, the selective plasma treatment is performed with a bias power. In one embodiment, the first treated portion has a width in a range between about 1 μm and about 20 μm and a pitch in a range between about 1 μm and about 100 μm. In one embodiment, the method further includes, after the selective plasma treatment, performing a vacuum break to expose the first package assembly to air, wherein the vacuum break causes the first treated portion of the first surface dielectric layer to have an increased oxygen atomic percentage.

[0067] In one embodiment, the method further comprises performing an additional selective plasma treatment on a second portion of the second surface dielectric layer to form a second treated portion. In one embodiment, after the bonding, one of the first treated portions is bonded to one of the second treated portions.

[0068] According to some embodiments, a structure includes: a first package component including a first surface dielectric layer, further including a plurality of first portions extending from a surface of the first surface dielectric layer into the first surface dielectric layer, wherein the first portions have a first atomic percentage of oxygen; and a plurality of second portions separating the first portions from each other, wherein the second portions have a second atomic percentage of oxygen lower than the first atomic percentage. In one embodiment, the first package component includes a die, wherein the first portion has a plurality of ring shapes, with outer rings surrounding corresponding inner rings.

[0069] In one embodiment, the first portion has a width in a range between about 1 μm and about 20 μm, and the first portion has a pitch in a range between about 1 μm and about 100 μm. In one embodiment, the structure further includes a second packaging component comprising a second surface dielectric layer, wherein the second surface dielectric layer is bonded to the first surface dielectric layer. In one embodiment, the first portion extends into the first surface dielectric layer to a depth of less than about 100 angstroms. In one embodiment, the first portion has a thickness of less than about 100 angstroms.

[0070] According to some embodiments, a structure includes: a device die including a silicon-containing dielectric layer, further including a first portion extending from a top surface of the silicon-containing dielectric layer to an intermediate stage between the top and bottom surfaces of the silicon-containing dielectric layer; and a second portion extending from the top surface to the bottom surface, wherein the first portion has a higher atomic percentage of oxygen than the second portion. In one embodiment, the first portion has a thickness of less than approximately 100 angstroms. In one embodiment, the first portion forms a plurality of rings.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: The first packaging component comprises: The first surface dielectric layer comprises: a plurality of first portions extending from a surface of the first surface dielectric layer into the first surface dielectric layer, wherein the first portions have a first oxygen atomic percentage; and a plurality of second portions separating the first portions from each other, wherein the second portions have a second oxygen atomic percentage lower than the first oxygen atomic percentage.

2. The semiconductor structure according to claim 1, characterized in that: The first oxygen atomic percentage is greater than the second oxygen atomic percentage by more than 2%.

3. The semiconductor structure according to claim 1, characterized in that: The first package assembly includes a die, and the first portion has a plurality of ring shapes, wherein an outer ring surrounds a corresponding inner ring.

4. The semiconductor structure according to claim 1, characterized in that Wherein the first portion has a width in the range between 1 micron and 20 microns, and the first portion has a pitch in the range between 1 micron and 100 microns.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: The second packaging component includes a second surface dielectric layer, wherein the second surface dielectric layer is bonded to the first surface dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that The first portion extends into the first surface dielectric layer to a depth less than 100 angstroms.

7. The semiconductor structure according to claim 1, characterized in that: The first portion has a thickness less than 100 angstroms.

8. A semiconductor structure, characterized in that: include: A device die, comprising: A silicon-containing dielectric layer comprising: a plurality of first portions extending from a top surface of the silicon-containing dielectric layer to an intermediate stage between the top surface and a bottom surface of the silicon-containing dielectric layer; and A plurality of second portions extend from the top surface to the bottom surface, wherein the first portion has a higher oxygen atomic percentage than the second portion.

9. The semiconductor structure according to claim 8, characterized in that: The first portion has a thickness less than 100 angstroms.

10. The semiconductor structure according to claim 8, characterized in that Wherein the first portion forms a plurality of rings.

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