Printed circuit board of multi-level circuit and power converter

Abstract

The utility model provides a printed circuit board of a multi-level circuit and a power converter, the multi-level circuit comprises a plurality of bus capacitors, a plurality of switching devices and at least one thin-film capacitor, the plurality of bus capacitors and the plurality of switching devices are connected to form the multi-level circuit, the thin-film capacitor is connected in parallel with one bus capacitor, and the thin-film capacitor is connected in parallel with the other bus capacitor. The printed circuit board comprises a core device area, the switching devices and the thin-film capacitors are arranged in the core device area, and the bus capacitors are located outside the core device area. The thin-film capacitor is introduced and located in the core device area, the current path between the thin-film capacitor and each switching device is shorter, and the commutation path in the commutation process can be shortened, so that the path stray inductance is reduced, the inverse peak is reduced, and the service life of the device is prolonged.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a printed circuit board and a power converter of a multi-level circuit. Background Art

[0002] A power converter is a converter that converts one form of electrical energy into another form of electrical energy by turning on and off semiconductor power switching devices. More specifically, it includes rectifiers, inverters, etc. Since multi-level circuits have the advantages of small voltage stress of switching devices and low harmonic content of output voltage, they are often used as rectifiers or inverters. During operation, if the multi-level conversion circuit reaches the current limit point, the current loop will switch. In this process, a large reverse peak may occur, which will damage the switching devices in the multi-level conversion circuit. This is an urgent problem to be solved. Summary of the invention

[0003] The present application provides a printed circuit board of a multi-level circuit and a power converter.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a printed circuit board of a multi-level circuit, wherein the multi-level circuit includes multiple bus capacitors, multiple switching devices and at least one thin film capacitor, wherein multiple bus capacitors and multiple switching devices are connected to form a multi-level circuit, wherein the thin film capacitor is connected in parallel with one of the bus capacitors, wherein the printed circuit board includes a core device area, wherein multiple switching devices and the thin film capacitors are all arranged within the core device area, and multiple bus capacitors are all located outside the core device area.

[0006] In this way, by introducing thin film capacitors and locating the thin film capacitors within the core device area, the current path between the thin film capacitors and each switching device is shorter, which can shorten the commutation path during the commutation process, thereby reducing the path stray inductance, thereby reducing the reverse peak and increasing the device life.

[0007] In some embodiments, the plurality of switching devices include positive half-cycle switching devices and negative half-cycle switching devices, the thin film capacitor includes a first thin film capacitor and a second thin film capacitor, and the corresponding core device area includes a first core device area and a second core device area arranged adjacent to each other, wherein the positive half-cycle switching device and the first thin film capacitor are arranged in the first core device area, and the negative half-cycle switching device and the second thin film capacitor are arranged in the second core device area.

[0008] In this way, the core device area is further divided into a first core device area and a second core device area, and the closely related positive half-cycle switching device and the first thin film capacitor are arranged in the first core device area, and the closely related negative half-cycle switching device and the second thin film capacitor are arranged in the second core device area, so that the connection path between the switching device and the thin film capacitor is shorter, which can further shorten the commutation path, reduce the noise inductance, and reduce the reverse peak.

[0009] In some embodiments, there are multiple three-level circuits, corresponding to which the printed circuit board includes multiple core device areas, and the multiple core device areas are arranged in an array in at least one direction. Multiple switching devices and thin film capacitors of each multi-level circuit are arranged in a core device area accordingly, and the bus capacitors include multiple first bus capacitor arrays and multiple second bus capacitor arrays, and each bus capacitor array includes multiple capacitors; the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each of the core device areas, and the first bus capacitor array and the second bus capacitor array are arranged alternately.

[0010] In this way, the bus capacitor can be divided into different parts and arranged on the circuit board. The commutation paths of each multi-level circuit are of equal length and the current sharing is relatively high. At the same time, the bus capacitor is realized in the form of multiple small-packaged capacitors connected in parallel, and the stray inductance of multiple small-packaged capacitors is smaller than that of large capacitors, leaving greater layout freedom for other devices.

[0011] In some embodiments, the capacitance of the film capacitor satisfies: the ripple value of the film capacitor for reverse peak current is greater than the current value of the film capacitor for industrial frequency ripple current, and the ripple value of the film capacitor for reverse peak current is greater than the current value of the film capacitor for switching frequency ripple.

[0012] In this way, the film capacitor has almost no current division for the industrial frequency ripple current, and a very small current division for the switching frequency ripple current, but a large current division for the reverse peak ripple current. It can efficiently absorb the reverse peak ripple current without affecting the normal working current, thereby reducing the reverse peak.

[0013] In some embodiments, the multi-level circuit output includes a first level, a middle level, and a second level; after the multi-level circuit triggers a current limiting point, at least one main switch device is turned off, so that the multi-level circuit switches from a current current loop to a middle freewheeling loop; and at least one freewheeling switch device is turned off, so that the multi-level circuit switches from a middle freewheeling loop to a reverse freewheeling loop through the thin film capacitor; wherein the switch device located on the middle level channel serves as the freewheeling switch device, and the switch device located on the first level channel or the second level channel serves as the main switch device, when the current current loop is the first level channel, the reverse freewheeling loop is a freewheeling loop passing through the main switch device on the second level channel, and when the current level path is the second level channel, the reverse freewheeling loop is a freewheeling loop passing through the main switch device on the first level channel.

[0014] In this way, since some switching devices are in the extreme withstand voltage condition during the process of switching the mid-position freewheeling circuit to the reverse freewheeling circuit in the multi-level circuit, the introduced thin film capacitor can provide an additional path to switch the mid-position freewheeling circuit to the reverse freewheeling circuit, thereby reducing the reverse peak in the extreme withstand voltage condition, thereby reducing the pressure on the switching devices and improving the device life.

[0015] In some embodiments, the commutation path from the neutral freewheeling loop to the reverse freewheeling loop of the multi-level circuit includes a first path passing through the film capacitor and a second path passing through the bus capacitor, and the length of the first path is shorter than that of the second path.

[0016] In this way, since the film capacitor can provide an additional shorter commutation path, the path stray inductance is reduced, thereby reducing the reverse peak and increasing the life of the device.

[0017] In some embodiments, the multi-level topology is specifically a T-type three-level topology; the plurality of switch devices include a first switch device, a second switch device, a third switch device and a fourth switch device, and the bus capacitor includes a first bus capacitor and a second bus capacitor; the first switch device and the fourth switch device are connected in series to form a vertical tube bridge arm, the second switch device and the third switch device are connected in series to form a horizontal tube bridge arm, and the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, wherein the common point of the first switch device and the fourth switch device is used as an output point, and the common point of the first bus capacitor and the second bus capacitor is used as a midpoint, The two free ends of the vertical tube bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal tube bridge arm is respectively connected to the neutral point, and the second end is connected to the output point; the thin film capacitor is bridged across the free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm; the first switch device and the fourth switch device are used as main switch devices, and the second switch device and the third switch device are used as freewheeling switch devices. The first level channel refers to the channel from the free end of the first bus capacitor and the first switch device to the output point, the second level channel is the channel from the free end of the second bus capacitor and the fourth switch device to the output point, and the mid-level channel is the channel from the midpoint and the horizontal tube bridge arm to the output point.

[0018] In some embodiments, the multi-level topology is specifically an I-type three-level topology; the plurality of switch devices include a first switch module, a second switch device, a third switch device, a fourth switch device, a first diode and a second diode, and the bus capacitor includes a first bus capacitor and a second bus capacitor; the first switch device, the second switch device, the third switch device, and the fourth switch device are sequentially connected in series to form an I-type bridge arm, the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, and the first diode and the second diode are connected in series to form a diode bridge arm, wherein the common point of the first switch device and the second switch device is used as the first connection point, the common point of the second switch device and the third switch device is used as the output point, the common point of the third switch device and the fourth switch device is used as the second connection point, and the first bus capacitor and the second The common point of the bus capacitor is used as the midpoint, the two free ends of the I-type bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the free ends of the diode bridge arm are respectively connected to the first connection point and the second connection point, and the common point of the diode bridge arm is connected to the midpoint; the thin film capacitor is connected between the free end of the I-type bridge arm and the common point of the diode bridge arm; the first switch device and the fourth switch device are used as main switch devices, the second switch device and the third switch device are used as freewheeling switch devices, the first level channel is the free end of the first bus capacitor, the first switch device, the second switch device to the output point, the second level channel is the free end of the second bus capacitor, the fourth switch device, the third switch device to the output point, and the mid-level channel is the midpoint, the first diode, the second switch device to the output point or the midpoint, the second diode, the third switch device to the output point.

[0019] In a second aspect, an embodiment of the present application provides a power converter, wherein the power converter comprises a printed circuit board as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a T-type three-level topology provided in an embodiment of the present application;

[0021] Figure 2 Schematic diagram of commutation of a T-type three-level topology provided in an embodiment of the present application Figure 1 ;

[0022] Figure 3 Schematic diagram of commutation of a T-type three-level topology provided in an embodiment of the present application Figure 2 ;

[0023] Figure 4 A schematic diagram of a type I three-level topology provided in an embodiment of the present application;

[0024] Figure 5 Schematic diagram of the location of the film capacitor of the I-type three-level topology provided in the embodiment of the present application Figure 1;

[0025] Figure 6 Schematic diagram of the location of the film capacitor of the I-type three-level topology provided in the embodiment of the present application Figure 2 ;

[0026] Figure 7 The commutation diagram of the I-type three-level topology provided in the embodiment of the present application is as follows: Figure 1 ;

[0027] Figure 8 The commutation diagram of the I-type three-level topology provided in the embodiment of the present application is as follows: Figure 2 ;

[0028] Fig. 9 A schematic diagram of the structure of a type I five-level topology provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of the structure of a printed circuit board provided in an embodiment of the present application;

[0030] Fig.11 A schematic diagram of the structure of a printed circuit board in a T-shaped layout provided in an embodiment of the present application;

[0031] Fig.12 A schematic diagram of the structure of a printed circuit board in a rectangular layout provided in an embodiment of the present application;

[0032] Fig.13 A schematic diagram of the structure of a printed circuit board in a diamond-shaped layout provided in an embodiment of the present application;

[0033] Fig.14 A schematic diagram of the structure of a printed circuit board of a multi-phase multi-level circuit provided in an embodiment of the present application;

[0034] Fig.15 A schematic diagram of the structure of a printed circuit board with an I-type three-level topology provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that shown or described.

[0036] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor;

[0037] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

[0038] BJT (Bipolar Junction Transistor): Bipolar junction transistor;

[0039] HBT (Hetero Junction Bipolar Transistor): Heterojunction bipolar transistor.

[0040] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0041] In one embodiment, a printed circuit board for a multi-level circuit is provided. Fig.10 , which is a schematic diagram of the structure of a printed circuit board 30 provided in an embodiment of the present application. Fig.10As shown, the printed circuit board is used to form a multi-level circuit 10. The multi-level circuit includes a plurality of bus capacitors, a plurality of switching devices and at least one thin film capacitor, a plurality of bus capacitors and a plurality of the switching devices are connected to form a multi-level circuit, the thin film capacitor is connected in parallel with one of the bus capacitors, the printed circuit board includes a core device area, a plurality of the switching devices and the thin film capacitors are all arranged in the core device area, and a plurality of the bus capacitors are all located outside the core device area.

[0042] It should be noted that a multi-level circuit refers to a circuit with multiple output levels, which can be used in inverters, rectifiers, converters, etc. Taking an inverter as an example, a multi-level circuit is specifically used to convert direct current into alternating current, and can include a three-level circuit, a five-level circuit, a seven-level circuit, etc., which are not listed here one by one.

[0043] Taking the application of multi-level circuits in inverters as an example, the bus capacitors in the multi-level circuits are mainly used to stabilize the DC power supply of the inverter and reduce the fluctuation of DC power to ensure the stability of the output AC power. Those skilled in the art understand that bus capacitors refer to capacitors installed on the bus for stabilizing voltage, reducing bus voltage fluctuations and reducing harmonics. They can adjust and balance voltage fluctuations in the power system and suppress and eliminate harmonics. Although the film capacitor is connected in parallel with the bus capacitor and is also connected to the bus, it is arranged together with multiple switching devices in the core device area of ​​the printed circuit board, which is different from the bus capacitor being arranged outside the core device area. Its function is to shorten the commutation path of the switching process from one current loop to another current loop, that is, the "film capacitor arranged in the core device area" in this case and the bus capacitor are two capacitors with different functions, and the "film capacitor" in this case cannot be regarded as a conventional bus capacitor.

[0044] When the multi-level circuit reaches the current limit point (i.e. the current is too large), the multi-level circuit can switch the current loop through the bus capacitor by controlling the on or off of the switching devices. In this process, the current passing through some switching devices is rapidly reduced to 0. The highly variable dI / dt (unit current change per unit time) will generate an induced voltage △V when flowing through the system stray inductance. The superposition of △V and the bus voltage produces an anti-peak, which makes the switching device bear a higher voltage stress than usual, which may cause permanent damage to the switching device.

[0045] In the embodiment of the present application, by introducing a thin film capacitor connected in parallel with the bus capacitor, since the volume of the thin film capacitor is smaller than the volume of the bus capacitor, the current path formed by the thin film capacitor itself will also be shorter due to the small volume of the thin film capacitor, thereby shortening the commutation path during the current loop switching process, thereby reducing the stray inductance of the commutation path, and reducing the value of the induced voltage △V, thereby reducing the reverse peak, avoiding damage to the switching device, and extending the life of the multi-level circuit. In addition, due to the small size, the physical space occupied is small, and in terms of physical layout, the thin film capacitor is allowed to be distributed nearby around the switching device, further shortening the commutation path during the current loop switching process.

[0046] It should be noted that for a three-level circuit, its output three levels can be represented by a positive level +V, a negative level -V and a zero level 0V. One of the positive level and the negative level is respectively called the first level or the second level, and the other of the positive level and the negative level is respectively called the other of the first level or the second level. The zero level is located in the middle of the positive level and the negative level, so the zero level can also be expressed as the middle level.

[0047] For a five-level circuit, the five levels of its output can be simply expressed by voltage as +2V, +V, 0V, -V, and -2V in sequence, where +V can be considered as the middle level of +2V and 0V, +2V and 0V are the first level and the second level respectively, and 0V can be the middle level of +2V and -2V or +V and -V, and the first level and the second level can also be determined correspondingly.

[0048] The same can be said for other types of multi-level circuits.

[0049] In this way, no matter what type of multi-level circuit, the first level, the middle level and the second level can be defined in the level of its output. After the multi-level circuit triggers the current limit point, at least one main switch device is turned off, so that the multi-level circuit switches from the current current loop to the middle freewheeling loop; and at least one freewheeling switch device is turned off, so that the multi-level circuit switches from the middle freewheeling loop to the reverse freewheeling loop through the film capacitor; wherein, the switch device located on the middle level channel is used as the freewheeling switch device, and the switch device located on the first level channel or the second level channel is used as the main switch device, when the current current loop is the first level channel, the reverse freewheeling loop is the freewheeling loop passing through the main switch device on the second level channel, and when the current level path is the second level channel, the reverse freewheeling loop is the freewheeling loop passing through the main switch device on the first level channel. It is known to those skilled in the art that the above-mentioned reverse freewheeling loop refers to the current loop formed by the parasitic diode flowing through the main switch device (in some embodiments, it can be an external diode reversely connected in parallel with the main switch device), and the current loop formed by the main switch part flowing through the main switch device is called the main current loop in this case. The multi-level circuit has multiple current loops, specifically including a selectively conducting neutral freewheeling loop, a reverse freewheeling loop and a main current loop.

[0050] In a specific embodiment, the first level and the middle level are connected via a first bus capacitor, the middle level and the second level are connected via a second bus capacitor, the film capacitor includes a first film capacitor and a second film capacitor, the first film capacitor is connected in parallel with the first bus capacitor, and the second film capacitor is connected in parallel with the second bus capacitor. The above is only an example, and the number of bus capacitors and the number of film capacitors can be selected according to actual use requirements.

[0051] The specific structure and working principle of the multi-level circuit 10 are described below by taking a multi-level topology that is specifically a T-type three-level topology as an example.

[0052] First, see Figure 1The multi-level circuit 10 is specifically a T-type three-level topology; the multiple switch devices in the multi-level circuit 10 include a first switch device 11, a second switch device 12, a third switch device 13 and a fourth switch device 14, and the bus capacitor includes a first bus capacitor 15 and a second bus capacitor 16; the first switch device 11 and the fourth switch device 14 are connected in series to form a vertical pipe bridge arm, the second switch device 12 and the third switch device 13 are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor 15 and the second bus capacitor 16 are connected in series to form a capacitor bridge arm, wherein the common point of the first switch device 11 and the fourth switch device 14 is used as the output point, the common point of the first bus capacitor 15 and the second bus capacitor 16 is used as the midpoint O, the two free ends of the vertical pipe bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal pipe bridge arm is respectively connected to the neutral point, and the second end is connected to the output point, the two free ends of the capacitor bridge arm are also respectively connected to the positive and negative ends of the power supply, and the film capacitor is connected across the free end of the vertical pipe bridge arm and the first end of the horizontal pipe bridge arm.

[0053] It should be noted that Figure 1 The first to fourth switch devices 11 to 14 are all IGBT devices. In other embodiments, the first to fourth switch devices 11 to 14 may also be formed by other types of switch devices or combinations of switch devices, such as MOS, BJT, HBT, diode, etc. At the same time, each switch device may include a single transistor or multiple transistors.

[0054] At the same time, Figure 1 In the embodiment, the film capacitors include a first film capacitor 17 and a second film capacitor 18. The first film capacitor 17 is connected in parallel with the first bus capacitor 15, and the second film capacitor 18 is connected in parallel with the second bus capacitor 16. However, this is only an example. The number of film capacitors may be more or less.

[0055] for Figure 1 In the structure shown, the first switch device 11 and the fourth switch device 14 are used as main switch devices, the second switch device 12 and the third switch device 13 are used as freewheeling switch devices, the first level channel refers to the free end of the first bus capacitor 15, the channel from the first switch device 11 to the output point, the second level channel is the free end of the second bus capacitor 16, the channel from the fourth switch device 14 to the output point, and the middle level channel is the channel from the midpoint O to the cross-tube bridge arm to the output point. The reverse freewheeling loop is a diode freewheeling channel flowing through the first switch device 11 or the fourth switch device 14.

[0056] Specifically, see Figure 2 (a)~ Figure 2 (c) shows the commutation operation of the multi-level circuit 10 after the current limiting point is triggered in the positive half cycle: Specifically:

[0057] Step 1: Before the current limiting point is triggered, the current loop of the multi-level circuit 10 is as follows: Figure 2 (a)

[0058] Step 2: After the current limiting point is triggered, the vertical tube, i.e., the first switch device 11, is closed first. Figure 2 (b), at this time, the current loop is switched to the middle level channel, the cross tube, that is, the second switch device 12 is turned on, and the parasitic diode of the third switch device 13 is turned on. At this time, the platform voltage borne by the first switch device 11 is half of the bus voltage (for example, 500V). If the withstand voltage of the first switch device 11 is 1200V, it is in a non-limit working condition at this time;

[0059] Step 3: After the second switch device 12 is stably turned on, continue to turn off the second switch device 12. Figure 2 (c) The parasitic diode of the fourth switch device 14 is turned on. At this time, the platform voltage borne by the first switch device 11 is the entire bus voltage (for example, 1000V). Similarly, when the withstand voltage of the first switch device 11 is 1200V, there is only a margin of 200V. Once the induced voltage exceeds 200V, the reverse peak voltage formed by the superimposed bus platform voltage exceeds 1200V, which exceeds the withstand voltage of the device and damages the switch device, which is an extreme operating condition.

[0060] Thus, in the switching process from step 2 to step 3, without setting the film capacitor, the commutation loop is: the current loop from the midpoint O, the cross-tube bridge arm, and the output point is switched to the path of the midpoint O, the second bus capacitor 16, the fourth switch device 14, and the output point. Since the bus capacitor has a large capacitance, a large volume, and a long path, there is a high stray inductance (illustrated by the inductance symbol in the figure), and a large voltage / current change acts on the stray inductance to generate a large reverse peak, which may break down the switch device; since the embodiment of the present application introduces a film capacitor connected in parallel with the bus capacitor, since the volume of the film capacitor is smaller than the volume value of the bus capacitor, it can be connected between the first end of the cross-tube bridge arm and the free end of the vertical bridge arm, so the commutation loop also includes the path of the second film capacitor and the fourth switch device 14, and the sum of the paths at both ends of the film capacitor is shorter than the sum of the paths at both ends of the bus capacitor, and the stray inductance is small, thereby reducing the reverse peak borne by the first switch device 11 and improving the life of the multi-level circuit 10.

[0061] See also Figure 3 (a)~ Figure 3 (c) shows the commutation operation of the multi-level circuit 10 after the current limit point is triggered in the negative half cycle: Specifically:

[0062] Step 1: Before the current limit point is triggered, the current loop of the multi-level inverter circuit is as follows: Figure 3 (a)

[0063] Step 2: After the current limiting point is triggered, the vertical tube, i.e., the fourth switch device 14, is closed first. Figure 3 (b), at this time, the current loop is switched to the middle level channel, the cross tube, that is, the third switch device 13 is turned on, the parasitic diode of the second switch device 12 is turned on, and the platform voltage borne by the fourth switch device 14 is half of the bus voltage (for example, 500V). If the withstand voltage of the fourth switch device 14 is 1200V, it is in a non-limit working condition at this time;

[0064] Step 3: After the third switch device 13 is stably turned on, continue to turn off the third switch device 13, see Figure 2 (c) The parasitic diode of the first switch device 11 is turned on. At this time, the platform voltage borne by the fourth switch device 14 is the entire bus voltage (for example, 1000V). Similarly, the withstand voltage of the fourth switch device 14 is 1200V, and there is only a margin of 200V. Once the induced voltage exceeds 200V, the reverse peak voltage formed by the superimposed bus platform voltage exceeds 1200V, which exceeds the withstand voltage of the device and damages the switch device, which is an extreme operating condition.

[0065] Thus, in the switching process from step 2 to step 3, without setting the film capacitor, the commutation loop is: the current loop from the midpoint O, the cross-tube bridge arm, and the output point is switched to the path of the midpoint O, the first bus capacitor 15, the first switch device 11, and the output point. Since the bus capacitor has a large capacitance, a large volume, and a long path, there is a high stray inductance, and a large voltage / current change acts on the stray inductance to generate a large reverse peak, which may break down the switch device; since the embodiment of the present application introduces a film capacitor connected in parallel with the bus capacitor, since the volume of the film capacitor is smaller than the volume value of the bus capacitor, it can be connected between the first end of the cross-tube bridge arm and the free end of the vertical bridge arm, and the path is short, so the commutation loop also includes a path through the film capacitor and the first switch device 11, and the commutation loop is significantly shortened, and the stray inductance is small, thereby reducing the reverse peak borne by the fourth switch device 14 and improving the life of the multi-level circuit 10.

[0066] Generally speaking, the positive half-cycle waveform and the negative half-cycle of a multi-level circuit are symmetrical, and the devices in the symmetrical position will also select devices of the same specification. For example, the first switch device of the positive half-cycle and the second switch device of the negative half-cycle are both selected as switch devices with a withstand voltage of 1200V. Both the positive half-cycle and the negative half-cycle may trigger the current limiting protection. Therefore, it is generally necessary to set the first film capacitor and the second film capacitor at the same time. In some special cases, if the positive half-cycle device and the negative half-cycle device are selected from devices of different specifications, for example, the first switch device selects a switch with a withstand voltage of 1200V, and the fourth switch device selects a switch device of 2000V. Since the withstand voltage margin of the fourth switch device is large and can withstand a larger reverse peak, only the second film capacitor can be set.

[0067] In another specific embodiment, see Figure 4 In some embodiments, the multi-level circuit 10 is specifically an I-type three-level topology; the plurality of switch devices include a first switch device 11, a second switch device 12, a third switch device 13, a fourth switch device 14, a first diode 21 and a second diode 22, and the bus capacitor includes a first bus capacitor 15 and a second bus capacitor 16;

[0068] The first switch device 11, the second switch device 12, the third switch device 13, and the fourth switch device 14 are sequentially connected in series to form an I-type bridge arm, the first bus capacitor 15 and the second bus capacitor 16 are connected in series to form a capacitor bridge arm, and the first diode 21 and the second diode 22 are connected in series to form a diode bridge arm, wherein the common point of the first switch device 11 and the second switch device 12 is used as the first connection point, the common point of the second switch device 12 and the third switch device 13 is used as the output point, the common point of the third switch device 13 and the fourth switch device 14 is used as the second connection point, the common point of the first bus capacitor 15 and the second bus capacitor 16 is used as the midpoint O, the two free ends of the I-type bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the two free ends of the diode bridge arm are respectively connected to the first connection point and the second connection point, and the common point of the diode bridge arm is connected to the midpoint O;

[0069] The film capacitor is connected between the free end of the I-type bridge arm and the common point of the diode bridge arm.

[0070] Exemplarily, the film capacitor includes a first film capacitor 17 and a second film capacitor 18. In a specific embodiment, see Figure 5 , the first film capacitor 17 is connected between the free end of the first switching device 11 and the anode of the first diode 21, and the second film capacitor 18 is connected between the free end of the fourth switching device 14 and the cathode of the first diode 22;

[0071] Or, in another specific embodiment, see Figure 6 , the first film capacitor 17 is connected between the free end of the first switching device 11 and the cathode of the second diode 22, and the second film capacitor 18 is connected between the free end of the fourth switching device 14 and the anode of the first diode 21. Figure 5 The connection method of the film capacitor shown in the figure is Figure 6 The connection method of the film capacitor shown can further shorten the commutation path and reduce the reverse peak.

[0072] Specifically, the first switch device 11 and the fourth switch device 14 are used as main switch devices, the second switch device 12 and the third switch device 13 are used as freewheeling switch devices, and the first level channel is the free end of the first bus capacitor 15, the first switch device 11, the second switch device 12 to the output point, see Figure 7 In (b), the second level channel is the free end of the second bus capacitor 16, the fourth switch device 14, the third switch device 13 to the output point, the middle level channel is the midpoint O, the first diode 21, the second switch device 12 to the output point, and the middle level channel also includes the midpoint O, the second diode 22, the third switch device 13 to the output point. The reverse freewheeling loop is a diode freewheeling loop that flows through the first switch device 11 or the fourth switch device 14.

[0073] by Figure 5 For example, see the coupling capacitor shown in Figure 7 (a) to (c) in FIG. 1 show the commutation process of the multi-level circuit 10 under the I-type three-level topology when the commutation point is triggered in the positive half cycle; see FIG. Figure 8 (a) to (c) in the figure show the commutation process of the multi-level circuit 10 under the I-type three-level topology when the commutation point is triggered in the negative half cycle. Similarly, since the embodiment of the present application introduces a thin film capacitor connected in parallel with the bus capacitor, since the volume of the thin film capacitor is smaller than the volume value of the bus capacitor, it can be connected between the first vertical pipe bridge arm and the second vertical pipe bridge arm nearby, and the path is shorter, thereby significantly shortening the commutation loop, and the stray inductance therein is smaller, thereby reducing the reverse peak borne by the fourth switch device 14 and improving the life of the multi-level circuit 10.

[0074] In yet another specific embodiment, see Fig. 9 , the multi-level circuit 10 is specifically a five-level topology. Fig. 9 The multi-level circuit 10 includes 8 switching devices and 4 bus capacitors. The first switching device 11 to the fourth switching device 14 are connected in series to form a vertical pipe bridge arm. The fifth switching device 21 and the sixth switching device 22 are connected in series to form a horizontal pipe bridge arm. The first bus capacitor 15a, the second bus capacitor 15b, the fourth bus capacitor 16a and the third bus capacitor 16a are connected in series to form a capacitor bridge arm. The two free ends of the capacitor bridge arm and the two free ends of the vertical pipe bridge arm are connected in parallel.

[0075] The common point of the second bus capacitor 15b and the fourth bus capacitor 16b is used as the midpoint O, one free end of the cross-tube bridge arm is connected to the midpoint O, the other free end of the cross-tube bridge arm is connected to the common point of the second switch device 12 and the third switch device 13, and the common point of the second switch device 12 and the third switch device 13 forms an AC end (i.e., an output point); one end of the seventh switch device 27 is connected to the common point of the first switch device 11 and the second switch device 12, the other end of the seventh switch device 27 is connected to the common point of the first bus capacitor 15a and the third bus capacitor 15b, one end of the eighth switch device 28 is connected to the common point of the third switch device 13 and the fourth switch device 14, and the other end of the eighth switch device 28 is connected to the common end of the fourth bus capacitor 16b and the third bus capacitor 16a. The first decoupling capacitor 17 is connected to one end of the cross-tube bridge arm (away from the vertical bridge arm) and the first free end of the vertical bridge arm, and the second decoupling capacitor 18 is connected to one end of the cross-tube bridge arm (away from the vertical bridge arm) and the second free end of the vertical bridge arm.

[0076] The second switch device 12 , the third switch device 13 , the fifth switch device 21 , and the sixth switch device 22 are all freewheeling switch devices, and the first switch device 11 , the fourth switch device 14 , the seventh switch device 27 , and the eighth switch device 28 are all main switch devices.

[0077] See also Figure 8 The neutral freewheeling loop refers to an electrical path in which the second bus capacitor 16b and the fourth bus capacitor 16b are connected to the second switching device 12 and the third switching device 13 via the fifth switching device 21 and the sixth switching device 22.

[0078] The current loop switching process of the multi-level circuit 10 after the current limiting point is triggered can be understood by referring to the three-level I-type topology switching process, which will not be elaborated here. In this way, the commutation loop of the neutral level channel to the reverse freewheeling level channel is: the current loop of the midpoint O, the cross-tube bridge arm, and the output point is switched to the path of the midpoint O, the third bus capacitor 16a, the fourth bus capacitor 16b, the fourth switch device 14 to the output point, or the current loop of the midpoint O, the cross-tube bridge arm, and the output point is switched to the path of the midpoint O, the first bus capacitor 15a, the second bus capacitor 15b, the first switch device 11 to the output point; since the bus capacitor has a large capacitance, a large volume, and a long path, there is a high stray inductance, and a large voltage / current change acts on the stray inductance to produce a large reverse peak, The switch device may be broken down; since the embodiment of the present application introduces a film capacitor connected in parallel with the bus capacitor, and since the volume of the film capacitor is smaller than the volume value of the bus capacitor, it can be connected between the first end of the horizontal bridge arm and the free end of the vertical bridge arm, and the path is shorter, so the commutation loop also includes the path of the midpoint O, the first film capacitor 17, and the first switch device 11, or the commutation loop also includes the path of the midpoint O, the second film capacitor 18, and the fourth switch device 4, the commutation loop is significantly shortened, and the stray inductance therein is smaller, thereby reducing the reverse peak borne by the first switch device 11 or the fourth switch device 14, and improving the life of the multi-level circuit 10. In other control timings, the commutation loop may be inconsistent with the above embodiment, so the mid-level channel and the reverse freewheeling level channel may be inconsistent, and therefore, the commutation process is not limited to the above embodiment.

[0079] In the above description, the capacitance of the film capacitor satisfies: the ripple value of the film capacitor for reverse peak current is greater than the current value of the film capacitor for power frequency ripple current, and the ripple value of the film capacitor for reverse peak current is greater than the current value of the film capacitor for switching frequency ripple.

[0080] It should be noted that there are mainly three types of ripple currents in the multi-level circuit 10: (1) power frequency ripple current; (2) switching frequency ripple current; (3) reverse peak ripple current (also known as commutation current). The frequencies of these three ripple currents are different, the power frequency ripple frequency is less than the switching frequency ripple frequency and less than the reverse peak ripple frequency (generally, the power frequency ripple frequency is 50Hz or 60Hz and its multiples, the switching frequency ripple frequency is 10kHz to 100kHz, and the reverse peak ripple frequency is 1MHz to 10MHz). Through experiments, it is found that capacitors of different types and different capacitances have different passing capacity for the three different frequency ripples, and capacitors with small capacitance have a larger passing capacity for high switching frequencies. The capacitance of the film capacitor needs to allow the reverse peak ripple current to pass well, while allowing less passing capacity for the power frequency ripple current and the switching frequency ripple current. Therefore, the capacitance of the film capacitor cannot be too large, otherwise it is easy to be allocated too much switching frequency current, resulting in overheating of the capacitor.

[0081] In a specific scenario, the capacitance of the thin film capacitor set in the core device area and used to shorten the switching path of the switching process from one current loop to another is 0.47 microfarads, while the bus capacitor corresponding to absorbing the industrial frequency ripple current can have a capacitance of 470 microfarads. Electrolytic capacitors are used, which are large in size and set in a more peripheral area. They can be composed of multiple capacitors in parallel. The bus capacitor corresponding to absorbing the switching frequency ripple current can have a capacitance of 12 microfarads, which is larger in size than the thin film capacitor, is also set in a more peripheral area, and can be composed of multiple capacitors in parallel. After experimental verification, the 0.47 microfarad film capacitor has almost no current division for the power frequency ripple current, the current division for the switching frequency ripple current is about 1%, and the current division for the reverse peak ripple current is about 99%. The 12 microfarad bus capacitor has about 95% division for the switching frequency ripple current, and the stratification for the reverse peak ripple current is about 1%. The 0.47 microfarad film capacitor has almost no current division for the reverse peak ripple current, and the current division for the power frequency ripple current is about 99%. It can be seen that the reverse peak ripple current (i.e., the commutation current) mainly passes through the film capacitor. The above capacitance values ​​and test data are only a set of values ​​​​taken by the inventor during the test process, and cannot limit the unique value range of the capacitance of this application, nor can it limit the division of different capacitors for different ripple currents as measured by the test. It should be understood based on the inventive concept of the present invention.

[0082] The multi-level circuit is specifically a T-type three-level topology (i.e. Figure 1 Taking the structure shown in FIG. 1 as an example, several specific layouts of the printed circuit board 30 are provided for reference and understanding.

[0083] In the first specific embodiment, see Fig.11 , the first switch device 11, the second switch device 12, the third switch device 13, and the fourth switch device 14 present a T-shaped layout; the first switch device 11 and the fourth switch device 14 constitute the short side of the T-shaped layout; the second switch device 12 and the third switch device 13 constitute the long side of the T-shaped layout; the third switch device 13 is close to the short side of the T-shaped layout, and the second switch device 12 is far away from the long side of the T-shaped layout.

[0084] It should be noted that, in the T-type layout, even the commutation path through the bus capacitor is relatively short and the reverse peak is relatively low.

[0085] In addition, for the T-type layout, the first film capacitor 17 and the second film capacitor 18 are located between the first switching device 11, the fourth switching device 14 and the third switching device 13; one of the first bus capacitor 15 and the second bus capacitor 16 is located on the side of the first switching device 11 away from the fourth switching device 14, and the other of the first bus capacitor 15 and the second bus capacitor 16 is located on the side of the fourth switching device 14 away from the first switching device 11.

[0086] In this way, a first film capacitor 17 is arranged between the first switching device 11 and the third switching device 13, and a second film capacitor 18 is arranged between the fourth switching device 14 and the third switching device 13, so that the commutation path through the first film capacitor 17 and the commutation path through the second film capacitor 18 are further shortened, thereby reducing the reverse peak.

[0087] As mentioned above, each switching device may include a single transistor or may include multiple transistors. In the case where each switching device includes multiple transistors, see Fig.11 The second switch device 12 includes four second transistors, and the four second transistors are distributed in a trapezoidal shape; the third switch device 13 includes four third transistors, and the four third transistors are distributed in a 2×2 array; the first switch device 11 includes three first transistors, and the three first transistors are distributed in a triangular shape; the fourth switch device 14 includes three fourth transistors, and the three fourth transistors are distributed in a triangular shape (the specific shape of the triangle is not limited, such as a right triangle or an isosceles triangle); the first thin film capacitor 17 and the second thin film capacitor 18 are placed in the area surrounded by the first transistor at the top of the triangle, the fourth transistor at the top of the triangle, and the four third transistors.

[0088] In this way, the film capacitor does not occupy additional area and can better reduce the reverse peak.

[0089] In a specific embodiment, the first transistor to the fourth transistor are all IGBT transistors, which have the advantages of high withstand voltage, high current, high switching frequency, low switching loss and acceptable conduction loss.

[0090] In the second specific embodiment, see Fig.12 The first switch device 11, the second switch device 12, the third switch device 13, and the fourth switch device 14 are arranged in a rectangular layout; the first switch device 11 and the fourth switch device 14 are arranged along the first direction, and the second switch device 12 and the third switch device 13 are arranged along the first direction; the first switch device 11 and the third switch device 13 are arranged along the second direction, and the second switch device 12 and the fourth switch device 14 are arranged along the second direction.

[0091] The first thin film capacitor 17 and the second thin film capacitor 18 are located between the first switching device 11 , the second switching device 12 , the third switching device 13 and the fourth switching device 14 .

[0092] It should be noted that the commutation path of the rectangular layout is shorter than that of the T-shaped layout, and the first film capacitor 17 and the second film capacitor 18 are also added, so the reverse peak is smaller.

[0093] In the third specific embodiment, see Fig.13 The first switch device 11, the second switch device 12, the third switch device 13, and the fourth switch device 14 are arranged in a diamond shape; the first switch device 11, the third switch device 13, and the fourth switch device 14 are arranged along the first direction; the third switch device 13 and the second switch device 12 are arranged along the second direction; the first thin film capacitor 17 is located between the second switch device 12 and the third switch device 13, and is placed close to the first switch device 11; the second thin film capacitor 18 is located between the second switch device 12 and the third switch device 13, and is placed close to the fourth switch device 14.

[0094] According to the second and third embodiments described above, the core device region can be divided into a first core device region and a second core device region arranged adjacent to each other, and the plurality of switch devices constituting the multi-level circuit can be divided into positive half-cycle devices (corresponding to Fig.12 and Fig.13 The first switching device 11 and the second switching device 12 in the negative half cycle device (corresponding to Fig.12 and Fig.13 The fourth switching device 14 and the third switching device 13 in the circuit are configured such that the positive half-cycle switching device and the first thin film capacitor are arranged in the first core device area, and the negative half-cycle switching device and the second thin film capacitor are arranged in the second core device area, so that the switching devices and thin film capacitors that are closely related to each other are more closely arranged, thereby making the connection path between the switching devices and the thin film capacitors shorter, which can further shorten the commutation path, reduce the inductance, and reduce the reverse peak.

[0095] In other embodiments, the busbar capacitor may be formed by connecting multiple small capacitors in parallel, and the distribution position may be flexibly selected. Fig.11, each small block in the bus capacitor can be regarded as a small capacitor, and multiple small capacitors are connected in parallel to form a bus capacitor with a preset capacitance. It should be noted that when the bus capacitor is a plurality of small capacitors connected in parallel, the volume of the film capacitor should be smaller than the volume of the bus capacitor. It should not be understood that the volume of the film capacitor must be smaller than the volume of each small capacitor connected in parallel to form the bus capacitor, but it should be understood that the volume of the capacitor used for decoupling (i.e., the film capacitor) is smaller than the volume of the capacitor used as a bus support (i.e., the bus capacitor).

[0096] In other embodiments, there are multiple multi-level circuits 10, each of which constitutes a core device area, and the bus capacitors include multiple first bus capacitor arrays and multiple second bus capacitor arrays, each bus capacitor array includes multiple capacitors (the number of capacitors included in each bus capacitor may be the same or different); the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each multi-level circuit 10 (i.e., each core device area), and the first bus capacitor array and the second bus capacitor array are alternately arranged.

[0097] For example, see Fig.14 , the number of multi-level circuits 10 is three, that is, a three-phase three-level inverter circuit is formed, and at this time, the three multi-level circuits 10 are arranged in sequence along the first direction (when there are more multi-level inverter circuits, other arrangement arrays can be formed, such as multiple rows and multiple columns, which are not limited here), and the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each multi-level circuit 10. In this embodiment, the number of capacitors included in each bus capacitor array is different, and in other embodiments, the number of capacitors included in each bus capacitor array can be the same.

[0098] In this way, the busbar capacitor can be divided into different parts and arranged on the circuit board, and the commutation path of each multi-level circuit 10 is equal in length, and the current sharing degree is relatively high; at the same time, the busbar capacitor is realized in the form of multiple small package capacitors in parallel, and the stray inductance of multiple small package capacitors is smaller than that of large capacitors, and at the same time, a greater layout freedom is left for other devices. Through simulation, the stray inductance of the capacitor under this layout only accounts for 7% of the total stray inductance of the circuit.

[0099] In summary, the embodiment of the present application provides a printed circuit board 30 for implementing the aforementioned multi-level circuit 10, and provides thin film capacitor positions under a variety of layouts. Generally speaking, the thin film capacitor is closer to the switching device than the bus capacitor, thereby reducing the length of the commutation path during the switching process from the mid-position freewheeling circuit to the reverse freewheeling circuit, reducing the reverse peak, and extending the life of the device.

[0100] The multi-level circuit is specifically a type I three-level topology (i.e. Figure 5As an example, a specific layout of the printed circuit board 30 is provided, such as Fig.15 As shown. The core device area is divided into a first core device area and a second core device area, wherein the first switch device 11, the second switch device 12 and the first diode 21 form an "I" type layout in the first core device area, and the first diode 21 is placed adjacent to the first switch device 11, and the first decoupling capacitor 17 is arranged between the first diode 21 and the first switch device 11, and the fourth switch device 14, the third switch device 13 and the second diode 22 form an "I" type layout in the second core device area, and the second diode 22 is placed adjacent to the fourth switch device 14, and the second decoupling capacitor 18 is arranged between the second diode 22 and the fourth switch device 14, and the first core device area and the second core device area are mirror-symmetrical, wherein the fourth switch device 14 corresponds to the first switch device 11, the third switch device 13 corresponds to the second switch device 12, the second diode 22 corresponds to the first diode 21, and the first decoupling capacitor 17 corresponds to the second decoupling capacitor 18.

[0101] At the same time, the first pin of the first decoupling capacitor 17 (i.e., the pin connected to the first diode 21) is toward the first diode 21, and the second pin of the first decoupling capacitor 17 (i.e., the pin connected to the first switching device 11) is toward the first switching device 11. Similarly, the second decoupling capacitor 18 and the first decoupling capacitor 17 are mirror-symmetrical. Then, the second pin of the second decoupling capacitor 18 (i.e., the pin connected to the second diode 22) is toward the second diode 22, and the second pin of the second decoupling capacitor 18 (i.e., the pin connected to the fourth switching device 14) is toward the fourth switching device 14.

[0102] In this layout embodiment, the advantages of shortening the commutation path and reducing the reverse peak are also met.

[0103] In this embodiment, outside the core device area, a first bus capacitor and a second bus capacitor are provided. The bus capacitor can be formed by connecting multiple small capacitors in parallel, and the distribution position can be flexibly selected. In this embodiment, the first bus capacitor and the second bus capacitor can both include multiple bus capacitors. Fig.15 In the figure, each small circle and each small square can be regarded as a small bus capacitor, and multiple small bus capacitors are connected in parallel to form a first bus capacitor or a second bus capacitor with a preset capacitance. The specific distribution of the first bus capacitor and the second bus capacitor is not limited here. The bus capacitor can be set as a whole on one side of the core device area, or some of its bus capacitors can be set into multiple arrays and set on multiple sides of the core device area.

[0104] See also Fig.15When the number of three-level circuits is multiple, part of the bus capacitors constituting the first bus capacitors include multiple first bus capacitor arrays, part of the bus capacitors constituting the second bus capacitors include multiple second bus capacitor arrays, and each bus capacitor array includes multiple capacitors (such as small squares in the figure). Fig.15 It can be seen that each three-level circuit is enclosed into a core device area, and the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each core device area, and the first bus capacitor array and the second bus capacitor array are alternately arranged.

[0105] Specifically, the number of three-level circuits 10 is three, that is, a three-phase three-level inverter circuit is formed. At this time, the three three-level circuits 10 are arranged in sequence along the first direction, and the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each three-level circuit 10. The two first bus capacitor arrays serve as the first bus capacitor in the circuit, and the two second bus capacitor arrays serve as the second bus capacitor in the circuit. In this way, the bus capacitor can be divided into different parts and arranged on the circuit board. The commutation path of each three-level circuit 10 is equal in length and the current sharing is relatively high; at the same time, the bus capacitor is realized in the form of multiple small packaged capacitors in parallel, and the stray inductance of the multiple small packaged capacitors is smaller than that of the large capacitor, and at the same time, a greater layout freedom is left for other devices. Through simulation, the stray inductance of the capacitor under this layout is greatly reduced.

[0106] In yet another embodiment of the present application, a power converter is provided. The power converter includes the aforementioned printed circuit board 30 .

[0107] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. It should be noted that in the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A printed circuit board for a multi-level circuit, characterized in that: The multi-level circuit includes multiple bus capacitors, multiple switching devices and at least one thin film capacitor. The multiple bus capacitors and the multiple switching devices are connected to form a multi-level circuit. The thin film capacitor is connected in parallel with one of the bus capacitors. The printed circuit board includes a core device area. The multiple switching devices and the thin film capacitors are all arranged in the core device area, and the multiple bus capacitors are all located outside the core device area.

2. The printed circuit board according to claim 1, characterized in that: The multiple switching devices include positive half-cycle switching devices and negative half-cycle switching devices, the thin film capacitor includes a first thin film capacitor and a second thin film capacitor, and the corresponding core device area includes a first core device area and a second core device area arranged adjacent to each other, wherein the positive half-cycle switching device and the first thin film capacitor are arranged in the first core device area, and the negative half-cycle switching device and the second thin film capacitor are arranged in the second core device area.

3. The printed circuit board according to any one of claims 1 to 2, characterized in that: There are multiple multi-level circuits, corresponding to which the printed circuit board includes multiple core device areas, the multiple core device areas are arranged in an array in at least one direction, and multiple switching devices and thin film capacitors of each multi-level circuit are correspondingly arranged in a core device area. The bus capacitors include multiple first bus capacitor arrays and multiple second bus capacitor arrays, and each bus capacitor array includes multiple capacitors; the first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each core device area, and the first bus capacitor array and the second bus capacitor array are arranged alternately.

4. The printed circuit board according to claim 1, characterized in that: The capacitance of the film capacitor satisfies: The ripple current of the film capacitor for reverse peak current is greater than the current of the film capacitor for power frequency ripple current, and the ripple current of the film capacitor for reverse peak current is greater than the current of the film capacitor for switching frequency ripple.

5. The printed circuit board according to claim 1, characterized in that: The multi-level circuit output includes a first level, a middle level, and a second level; After the multi-level circuit triggers the current limiting point, at least one main switch device is turned off to switch the multi-level circuit from the current current loop to the middle freewheeling loop; and at least one freewheeling switch device is turned off to switch the multi-level circuit from the middle freewheeling loop to the reverse freewheeling loop through the film capacitor; Among them, the switching device located on the middle level channel serves as the freewheeling switching device, and the switching device located on the first level channel or the second level channel serves as the main switching device. When the current current loop is the first level channel, the reverse freewheeling loop is the freewheeling loop passing through the main switching device on the second level channel; when the current level path is the second level channel, the reverse freewheeling loop is the freewheeling loop passing through the main switching device on the first level channel.

6. The printed circuit board according to claim 5, characterized in that: The commutation path from the neutral freewheeling loop to the reverse freewheeling loop of the multi-level circuit includes a first path passing through the film capacitor and a second path passing through the bus capacitor, and the length of the first path is shorter than that of the second path.

7. The printed circuit board according to claim 6, characterized in that: The multi-level topology is specifically a T-type three-level topology; the plurality of switch devices include a first switch device, a second switch device, a third switch device and a fourth switch device, and the bus capacitor includes a first bus capacitor and a second bus capacitor; The first switch device and the fourth switch device are connected in series to form a vertical pipe bridge arm, the second switch device and the third switch device are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, wherein the common point of the first switch device and the fourth switch device is used as the output point, the common point of the first bus capacitor and the second bus capacitor is used as the midpoint, the two free ends of the vertical pipe bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal pipe bridge arm is respectively connected to the neutral point, and the second end is connected to the output point; The film capacitor is connected across the free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm; The first switch device and the fourth switch device serve as main switch devices, the second switch device and the third switch device serve as freewheeling switch devices, the first level channel refers to the channel from the free end of the first bus capacitor and the first switch device to the output point, the second level channel is the channel from the free end of the second bus capacitor and the fourth switch device to the output point, and the mid-level channel is the channel from the midpoint and the cross-tube bridge arm to the output point.

8. The printed circuit board according to claim 6, characterized in that: The multi-level topology is specifically an I-type three-level topology; the plurality of switch devices include a first switch device, a second switch device, a third switch device, a fourth switch device, a first diode and a second diode; the bus capacitor includes a first bus capacitor and a second bus capacitor; The first switch device, the second switch device, the third switch device, and the fourth switch device are sequentially connected in series to form an I-type bridge arm, the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, and the first diode and the second diode are connected in series to form a diode bridge arm, wherein a common point of the first switch device and the second switch device is used as a first connection point, a common point of the second switch device and the third switch device is used as an output point, a common point of the third switch device and the fourth switch device is used as a second connection point, a common point of the first bus capacitor and the second bus capacitor is used as a midpoint, two free ends of the I-type bridge arm are respectively connected in parallel with two free ends of the capacitor bridge arm, a free end of the diode bridge arm is respectively connected to the first connection point and the second connection point, and a common point of the diode bridge arm is connected to the midpoint; The film capacitor is connected between the free end of the I-shaped bridge arm and the common point of the diode bridge arm; The first switch device and the fourth switch device serve as main switch devices, the second switch device and the third switch device serve as freewheeling switch devices, the first level channel is the free end of the first bus capacitor, the first switch device, the second switch device to the output point, the second level channel is the free end of the second bus capacitor, the fourth switch device, the third switch device to the output point, and the mid-level channel is the midpoint, the first diode, the second switch device to the output point or the midpoint, the second diode, the third switch device to the output point.

9. A power converter, characterized in that: The power converter comprises a printed circuit board as claimed in any one of claims 1 to 7.

Images