Semiconductor structure

Abstract

A semiconductor structure including an active region and a conductor gate is provided. The conductor gate covers the active region, wherein the conductor gate includes a plug and a pad. The plug has an upper surface having a W-shaped profile and defining a lowest point. The pad covers the upper surface, where the pad contacts the plug along a gate interface having a gate interface region, where the plug has a plug cross-sectional region at a horizontal cross-section of a lowest point of the upper surface, and where the gate interface region is larger than the plug cross-sectional region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The electronics industry is experiencing an increasing demand for smaller and faster electronic components that can support increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking the size of semiconductor integrated circuits (such as the minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this expansion has also brought greater complexity to the semiconductor manufacturing process. Therefore, to achieve continued advancements in semiconductor integrated circuits and components, similar advances in semiconductor manufacturing processes and technologies are needed. Utility Model Content

[0003] In an exemplary embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region, wherein the conductive gate comprises a plug and a liner. The plug has an upper surface, the upper surface has a W-shaped profile and defines a lowest point. The liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area, and wherein the gate interface region is larger than the plug cross-sectional area.

[0004] In another embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region, wherein the conductive gate comprises a plug and a liner. The plug comprises a first horn, a first valley, a middle peak, a second valley, and a second horn, and has an upper surface, wherein the upper surface defines a lowest point. The liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area, and wherein the gate interface region is larger than the plug cross-sectional area.

[0005] In another embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region, wherein the conductive gate comprises a plug and a liner. The plug has an upper surface, the upper surface having a first negative slope extending from a first end to a first valley, a first positive slope extending from the first valley to a peak, a second negative slope extending from the peak to a second valley, and a second positive slope extending from the second valley to a second end, the upper surface defining a lowest point. The liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area, and wherein the gate interface region is larger than the plug cross-sectional area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, each aspect of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 is a flow chart of a method according to some embodiments;

[0008] Figure 2 is a plan layout diagram of a semiconductor device according to some embodiments;

[0009] Figures 3 to 8 is a cross-sectional view of a structure of a semiconductor device at successive manufacturing stages according to some embodiments;

[0010] Fig. 9 According to some embodiments Figure 8 A partial enlarged cross-sectional view of the interconnection of the structure and the interface between the inclined surfaces;

[0011] Fig.10 According to some embodiments Figure 7 A partial enlarged cross-sectional view of the interface between the gate material and the pad;

[0012] Fig.11 According to some embodiments, Fig.10 A similar enlarged cross-sectional view of the interface between the gate material and the liner, but with a larger gate critical dimension;

[0013] Figure 12 to Figure 14 According to some embodiments Figure 5 Cross-sectional view of alternative processing of a structure.

[0014]

Explanation of symbols

[0015] X,Y,Z: Direction

[0016] S102,S104,S106,S108,S110,S112,S114,S116,S118: Blocks

[0017] 100: Method

[0018] 200:Semiconductor components

[0019] 202: Base material

[0020] 204: Source / Drain Characteristics

[0021] 206: Gate structure

[0022] 210: Active area

[0023] 211,212: Area

[0024] 220: Shallow Trench Isolation Features

[0025] 230: Spacer layer

[0026] 240: Gate structure

[0027] 241: Layer

[0028] 242:Metal layer

[0029] 243: Flat upper surface

[0030] 248: Horizontal section

[0031] 249: Length

[0032] 250: Concave surface

[0033] 251:Central valley

[0034] 2511: Middle valley

[0035] 2512: First valley-shaped part

[0036] 2513: Second valley

[0037] 252,253: Horn

[0038] 262: First Edge

[0039] 263: The Second Edge

[0040] T1: Maximum vertical thickness

[0041] 500: Etching delay layer

[0042] 501: Central Area

[0043] 502,503: Edge area

[0044] 510: Upper surface

[0045] 511,515: end

[0046] 512,514: Valley

[0047] 513: Peak

[0048] 521,523: Negative slope

[0049] 522,524: Positive slope

[0050] W1,W2: distance

[0051] D1,D2,D3,D4: Height

[0052] 600: Upper surface

[0053] 611,615: End

[0054] 612,614: Valley

[0055] 613: Peak

[0056] 619: Height

[0057] 621: First negative slope area

[0058] 622: First positive slope area

[0059] 623: Second negative slope area

[0060] 624: Second positive slope area

[0061] 629: Surface length

[0062] 700:Padding

[0063] 710: Top surface

[0064] 711: first negative slope area

[0065] 712: First positive slope area

[0066] 713: Second negative slope area

[0067] 714: Second positive slope area

[0068] A1:Angle

[0069] 810: Dielectric material

[0070] 820: Interconnection

[0071] 822: Horizontal section

[0072] 825: Distance

[0073] 900: Interface

[0074] 901: Top

[0075] 902: Lower end

[0076] 905: Length

[0077] 921: Location

[0078] 950: Interface

[0079] 951: Interface length DETAILED DESCRIPTION

[0080] The following disclosure provides many different embodiments, or examples, for implementing different features of the present subject matter. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not meant to be restrictive. For example, in the following description, the formation of a first feature on a second feature may include an embodiment in which the first and second features are in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. As used herein, "directly covering" refers to the vertical arrangement of features so that when the upper features directly cover the underlying features, the vertical axis passes through the two features. In addition, the present disclosure may repeat reference digits and / or letters in various instances. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0081] As used herein, "positive slope" and "negative slope" refer to a typical reference system where a positive slope is defined by an increase in the vertical or direction Z and an increase in the lateral or direction Y, and a negative slope is defined by a decrease in the vertical or direction Z and an increase in the lateral or direction Y.

[0082] In addition, spatially relative terms, such as "vertically above," "above," "upper layer," "on," "up," "below," "below," "lower layer," "under," "bottom," "bottom," "side," "positive slope," and "negative slope," etc., may be used herein to describe the relationship of one element or feature to another element or feature for ease of description, as shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation, in addition to the orientations depicted in the figures. The elements may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0083] In some embodiments herein, a "material layer" is a layer containing at least 50% by weight of a known material, such as at least 60% by weight of a known material, or at least 75% by weight of a known material, or at least 90% by weight of a known material; and a layer being a "material" contains at least 50% by weight of a known material, such as at least 60% by weight of a known material, at least 75% by weight of a known material, or at least 90% by weight of a known material. For example, in some embodiments, each of the titanium nitride layer and the layer being titanium nitride is at least 50% by weight, at least 60% by weight, at least 75% by weight, titanium nitride, or at least 90% by weight of titanium nitride.

[0084] For the sake of brevity, conventional techniques related to the manufacture of conventional semiconductor components may not be described in detail herein. In addition, the various operations and processes described herein may be incorporated into a more comprehensive manufacturing sequence or process with additional functions not described in detail herein. In particular, the various processes for the manufacture of semiconductor components are well known, and therefore, for the sake of brevity, many conventional processes will only be briefly mentioned here, or omitted entirely, without providing well-known process details. It will be apparent to those skilled in the art, after a complete reading of this disclosure, that the structures disclosed herein may employ various techniques and may be incorporated into various semiconductor components and products. In addition, it should be noted that semiconductor component structures may include different numbers of components, and that a single component shown in the diagram may represent multiple components.

[0085] As described herein, an etching process is used to form a conductive gate having a desired profile. For example, in some embodiments, it may be desirable to increase the interface contact area between two layers, that is, the area of ​​surface contact. By providing a first layer with a non-horizontal planar profile, i.e., an inclined profile that increases and / or decreases in the vertical Z dimension, and then conformally depositing a second layer on the first layer, the contact area of ​​the interface can be increased without increasing the footprint area defined by the lateral X dimension and the longitudinal Y dimension.

[0086] In addition, in some embodiments, it may be desirable to increase the contact area between the interconnect and the conductive layer. Similarly, the contact area may be increased without increasing the footprint of the interconnect defined by the lateral Y dimension and the longitudinal X dimension by providing a non-horizontal planar contact interface, i.e., an inclined contact interface with an increase and / or decrease in the vertical Z dimension.

[0087] Embodiments of the present disclosure provide advantages over the prior art, although it is understood that other embodiments may provide different advantages, not all advantages are necessarily discussed herein, and no particular advantages need to apply to all embodiments. For example, embodiments discussed herein include conductive gate structures and related methods for processing metal gate structures to provide conductive interconnects. In some embodiments, a metal gate reflow in-situ etch-deposition-etch process is performed to provide an adjustable line end horn profile to improve WAT.

[0088] In various embodiments, a first etching process is performed to recess the metal gate structure into a non-planar recessed surface. More specifically, in some embodiments, the recessed surface has a central valley, and the recessed surface extends outward (in direction Y) and upward (in direction Z) from the central valley to the terminal horn. In order to adjust the threshold voltage of the gate material, an etching process is further performed in an exemplary embodiment. For example, an etching delay layer is deposited on the recessed surface. In an exemplary embodiment, the etching delay layer forms a larger thickness on the central valley and a smaller thickness on the terminal horn. Next, a second etching process is performed. The second etching process can be controlled to remove the thin portion of the etching delay layer, and then selectively etch the terminal horn, while the central valley is still covered by the etching delay layer. Therefore, the second etching process can be controlled to adjust the terminal horn so that the terminal horn forms a desired profile. Therefore, the process provides adjustment of the threshold voltage by the thickness of the line end horn. In addition, due to the different thicknesses of the etching delay layer, the central valley can be selectively etched to different depths. Therefore, the surface of the gate structure can form a W-shaped profile, having a first raised line end angle, a first valley, an intermediate peak, a second valley, and a second raised line end angle. At the same time, due to the W-shaped profile, the effective gate length is increased, and more contact area is provided between the metal gate and the cover layer to reduce the channel resistance (Rg). In addition, as the height difference of the surface features increases, the contact area with the later formed favorable interconnection increases, and the contact resistance (Rc) is reduced.

[0089] For the following discussion, Figure 1 A flow chart of method 100 according to various embodiments is provided. Method 100 will be discussed below with reference to a gate that is a metal gate formed, for example, in a replacement gate process. However, it will be appreciated that various aspects of method 100 may be equally applicable to other types of structures without departing from the scope of the present disclosure. It will be appreciated that method 100 includes steps that are characteristic of a complementary metal oxide semiconductor (CMOS) technology process flow and, therefore, are only briefly described herein. Additionally, other steps may be performed before, after, and / or during method 100.

[0090] The following describes method 100. First, please refer to Figure 2 , Figure 2 The plan layout diagram of the semiconductor device 200 is shown in FIG. Figures 3 to 8 , Figures 3 to 8 A semiconductor device 200 is shown at various stages of fabrication according to the method 100 . Figures 3 to 8 A cross-sectional view of one embodiment of a semiconductor device 200 is provided.

[0091] like Figure 2As shown, semiconductor element 200 includes substrate 202. In some embodiments, substrate 202 can be a semiconductor substrate, such as a silicon substrate. Substrate 202 can include various layers, including a conductive layer or an insulating layer formed on a semiconductor substrate. Substrate 202 can include various doping configurations, depending on design requirements known in the art. Substrate 202 can also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 can include a compound semiconductor and / or an alloy semiconductor. In addition, substrate 202 can selectively include an epitaxial layer, can be strained to enhance performance, can include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0092] In an exemplary embodiment, the source / drain region or active region 204 is formed in or above the substrate 202. Exemplarily, the active region 204 is parallel and extends in the direction Y in the orientation of the figure. In different examples, the source / drain feature 204 includes a semiconductor epitaxial layer, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP or other suitable materials, and the semiconductor epitaxial layer can be formed by one or more epitaxial processes. In some embodiments, the source / drain feature 204 can be in-situ doped in the epitaxial process. For example, in some embodiments, the epitaxially grown silicon germanium source / drain feature can be doped with boron. In some cases, the epitaxially grown silicon source / drain feature can be doped with carbon to form a Si:C source / drain feature, doped with phosphorus to form a Si:P source / drain feature, or doped with carbon and phosphorus to form a SiCP source / drain feature. In some embodiments, the source / drain features 204 are not doped in situ, but rather are doped by implantation. In some embodiments, the formation of the source / drain features 204 can be performed in separate processing steps for each of the N-type and P-type source / drain features.

[0093] like Figure 2 As shown, the device 200 further includes a gate structure 206. In an exemplary embodiment, the gate structure 206 is parallel and extends in the direction X in the direction of the figure. Figure 2 As shown, component 200 includes various component regions, such as region 211 and region 212 .

[0094] It is contemplated that the gate structure may be a portion of a fin field effect transistor (FinFET), a wrap-around gate (GAA) transistor, or other types of multi-gate components. In addition, the semiconductor component 200 may include various other components and features, such as other types of components, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and / or other logic circuits, etc., but are simplified for a better understanding of the concepts disclosed herein. In some embodiments, the semiconductor component 200 includes a plurality of semiconductor components (e.g., transistors), including PMOS components, NMOS components, etc., which may be interconnected. In addition, it should be noted that the process steps of method 100, including any description given with reference to the figures, are exemplary only and are not intended to be limited beyond the content specifically described in the claims that follow.

[0095] It is understood that the method 100 includes steps characteristic of a complementary metal oxide semiconductor (CMOS) technology process flow, and therefore, is only briefly described herein. In addition, other steps may be performed before, after, and / or during the method 100 .

[0096] The method 100 begins at block S102 by providing a partially fabricated gate structure. Figure 3 For example, in one embodiment of block S102, the partially fabricated device 200 includes an active region 210. The active region 210 may be composed of Figure 1 The substrate 202 forms the upper end of the three-dimensional fin of semiconductor material.

[0097] Shallow trench isolation (STI) features 220 may also be formed to separate the active regions 210. In some embodiments, the shallow trench isolation features 220 include silicon dioxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layer used to form the shallow trench isolation features may be deposited by a chemical vapor deposition process, a sub-atmospheric layer chemical vapor deposition (SACVD) process, a flow chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, and / or other suitable processes.

[0098] A gate structure 240 is formed on the active region 210. In the illustrated embodiment, the gate structure 240 includes a layer 241 and a conductive metal 242 in a high-k / metal gate stack or plug.

[0099] An exemplary layer 241 is a high-k gate dielectric. As used and described herein, a high-k gate dielectric comprises a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally treated silicon oxide (about 3.9). An exemplary high-k gate dielectric layer 241 may comprise a high-k dielectric material, such as hafnium oxide (HfO 2 Alternatively, the high-k gate dielectric layer 241 may include other high-k dielectric materials, such as TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 、ZrSiO 2 、LaO、AlO、ZrO、TiO、Ta 2 O 5 , Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO 3 (BST), Al 2 O 3 , Si 3 N 4 , oxynitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 241 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, and / or other suitable methods.

[0100] The gate structure 240 may further include a metal gate material 242 formed on the gate dielectric layer 241. The metal layer 242 may include a metal, a metal alloy, or a metal silicide. The metal layer 242 may include a single layer or an alternative multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance the performance of the device, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the metal layer 242 may include Al, Ti, Ag, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, W, WN, Cu, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In different embodiments, the metal layer 242 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, the metal layer 242 may be formed separately for N-type and P-type transistors, which may use different metal layers. Additionally, metal layer 242 may provide an N-type or P-type work function material, may serve as a transistor gate electrode, and in at least some embodiments, metal layer 242 may include a polysilicon layer.

[0101] As further shown, a spacer 230 may be formed on the sidewalls of the gate structure 240. The spacer 230 may be formed before forming a high-k / metal gate stack of the gate structure. For example, in some cases, the spacer 230 may be formed on the sidewalls of a previously formed dummy (sacrificial) gate stack, which is removed as part of a gate-last process and replaced by a high-k / metal gate stack. In some cases, the thickness of the spacer 230 may be 2 to 10 nanometers (nm). In some examples, the spacer 230 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxide, SiCN, silicon carbide, SiOCN, SiOHCN, a low-k material (e.g., a dielectric constant k<7), and / or a combination thereof. In some embodiments, the spacer 230 includes multiple layers, such as a main spacer layer, a liner layer, etc.

[0102] Therefore, block S102 may include performing a replacement gate process, including removing the sacrificial gate structure to form a cavity, depositing a gate material in the cavity, and planarizing the metal gate material to define a flat upper surface 243 of the gate structure 240 .

[0103] The method 100 further includes, at block S104, determining a desired threshold voltage of the gate material. This determination can be based on the intended use of the gate, the location in the NMOS device or the PMOS device, the size and material of the gate structure, and the size and material of the layer to be formed on the gate and / or interconnected with the gate. Based on the determination of the desired threshold voltage, the desired profile of the gate material is selected.

[0104] The method 100 may continue at block S106 by performing a first etching process to differentially etch the gate material. Figure 4 As shown, the etching process recesses the gate structure 240 to the recessed surface 250. As shown, the recessed surface 250 includes a central valley 251 and extends outwardly and upwardly to a first terminal horn 252 at a first edge 262 of the gate structure 240 and a second terminal horn 253 at a second edge 263 of the gate structure 240. More specifically, the central valley 251 of the recessed surface includes a first valley portion 2512 adjacent to the first terminal horn 252, a second valley portion 2513 adjacent to the second terminal horn 253, and an intermediate valley portion 2511 located between the first valley portion 2512 and the second valley portion 2513.

[0105] In an exemplary embodiment, the etching is dry etching and may be performed with BCl 3 / Cl 2 / O 2 gases, at pressures from 1mTorr to 200mTorr, at powers from 400W to 1200W, and at biases from 0W to 100W.

[0106] The method 100 may continue at block S108 by depositing an etch retardation layer 500 on the recessed surface 250. Figure 5 As shown, the etching retardation layer 500 is formed with a central region 501 located between edge regions 502 and 503. Specifically, the central region 501 is directly located above the central valley 251, the edge region 502 is directly located above the horn 252, and the edge region 503 is directly located above the horn 253. More specifically, the first edge region 502 is located above the first horn 252 and above the first valley 2512; the second edge region 503 is located above the second horn and above the second valley 2513; and the central region 501 is located above the middle valley 2511.

[0107] The exemplary etch retardation layer 500 is formed with a non-uniform thickness, including a minimum thickness in a thin region and a maximum thickness in a thick region. For example, as shown in the figure, the central region 501 of the etch retardation layer is thicker than the edge regions 502 and 503 of the etch retardation layer 500, so that the central region 501 is a thick region 501, and the edge regions 502 and 503 are thin regions 502 and 503. As shown in the figure, the etch holding layer 500 has a maximum vertical thickness T1 in the central region 501. In exemplary embodiments, the maximum vertical thickness T1 can be at least 1.1, at least 1.25, at least 1.5, at least 1.75, at least 2.0, at least 2.25, at least 2.5, at least 2.75, at least 3.0, at least 3.25, at least 3.5, at least 3.75, at least 4.0, at least 4.25, at least 4.5, at least 4.75, at least 5.0, at least 5.25, at least 5.5, at least 5.75, at least 6.0, at least 6.25, at least 6.5, at least 6.75, at least 7.0, at least 7.25, at least 7.5, at least 7.75, or at least 8.0 times the vertical thickness of the edge regions 502 and 503 measured at the interface of the dielectric 241 and the gate material 242.

[0108] The etch retardation layer 500 has an upper surface 510, which extends from an end 511 to a valley 512, from the valley 512 to a peak 513, from the peak to the valley 514, and from the valley 514 to an end 515. Therefore, the upper surface 510 includes a portion having a negative slope 521, a portion having a positive slope 522, a portion having a negative slope 523, and a portion having a positive slope 524.

[0109] It can be seen that the etch retardation layer 500 has a maximum vertical thickness T1 at the peak 513. Generally speaking, in the positive slope portion 522, the vertical thickness of the etch retardation layer increases from the valley 512 to the peak 513, and decreases from the peak 513 to the valley 514. In some embodiments, the first edge region 502 of the etch retardation layer 500 includes a negative slope portion 521 of the upper surface 510; the central region 501 of the etch retardation layer 500 includes a positive slope portion 522 and a negative slope portion 523 of the upper surface 510; and the second edge region 503 of the etch retardation layer 500 includes a positive slope portion 524 of the upper surface 510.

[0110] In an exemplary embodiment, the etch retardation layer includes carbon, boron, or carbon and boron.

[0111] By using BCl 3 / CH 4 / HB r Gas or SiCl 4 / O 2The exemplary etch retardation layer 500 is formed by a process performed using HBr gas, a pressure of 10 mTorr to 200 mTorr, a power of 400 W to 1200 W, and a bias of 0 W to 20 W.

[0112] It should be noted that the desired profile of the upper surface 510 of the etch retardation layer 500 can be obtained by controlling the duration of the deposition process. Similarly, the desired maximum vertical thickness T1 of the etch retardation layer 500 can be obtained by controlling the duration of the deposition process. For example, a shorter deposition time can result in a smaller maximum vertical thickness T1, while a longer deposition time can result in a larger maximum vertical thickness T1, and so on.

[0113] Please check Figure 4 as well as Figure 5 , it can be seen that the end 511 of the upper surface 510 is located at the first edge 262 of the gate structure 240, and the end 515 of the upper surface 510 is located at the second edge 263 of the gate structure 240. Further, the valley 512 is located directly above the boundary between the first valley-shaped portion 2512 and the middle valley-shaped portion 2511, i.e. vertically above; the peak 513 is located directly above the middle valley-shaped portion 2511, i.e. vertically above; and the valley 514 is located directly above the boundary between the second valley-shaped portion 2513 and the middle valley-shaped portion 2511, i.e. vertically above.

[0114] At action block S110 , the method 100 includes performing a second etching process to create a gate structure 240 having a top surface 600 with a desired profile, such as Figure 6 In an exemplary embodiment, the second etching process recesses or adjusts the corner portions 252 and 253. In an exemplary embodiment, the second etching process is controlled to selectively recess the portion of the central valley portion 251 of the recessed surface 250 to form the upper surface 600 having the desired W-shaped profile. For example, the first valley portion 2512 and the second valley portion 2513 may be etched to have a greater depth than the middle valley portion 2511, so that the middle valley portion 2511 is maintained at a height greater than the first valley portion 2512 and the second valley portion 2513.

[0115] like Figure 6As shown, the second etching process forms an upper surface 600 having a first end 611 adjacent to the spacer layer 230, a first valley-shaped portion or valley 612, a peak 613, a second valley-shaped portion or valley 614, and a second end 615 adjacent to the spacer layer 230. As shown, the first end 611 is formed at a vertical distance or angular height D1 from the top of the active region 210. In addition, the second end 615 is formed at a vertical distance or angular height D2 from the top of the active region 210. The angular heights D1 and D2 can be the same or different. In the illustrated embodiment, the first valley 612 and the second valley 614 are both formed at the same vertical distance or valley height D3 above the top of the active region 210. However, it is not necessary to etch the valleys 612 and 614 to the same height at the top of the active region 210. As further shown, the peak 613 is formed at a vertical distance or peak height D4 above the top of the active region 210. In the illustrated embodiment, peak height D4 is less than corner heights D1 and D2 ; however, it is contemplated that peak height D4 may be greater than one or both of corner heights D1 and D2 .

[0116] A vertical height difference ΔD14, equal to the difference between D1 and D4, is established between the end 611 and the peak 613. A vertical height difference ΔD24, equal to the difference between D2 and D4, is established between the end 615 and the peak 613. A vertical height difference ΔD43, equal to the difference between D4 and D3, is established between the peak 613 and the valley 612 and the valley 614. A vertical height difference ΔD13, equal to the difference between D1 and D3, is established between the end 611 and the valley 612. A vertical height difference ΔD23, equal to the difference between D2 and D3, is established between the end 615 and the valley 614.

[0117] In an exemplary embodiment of the upper surface 600 having a W-shaped profile, heights D1 and D2 are independently between 10 nanometers and 30 nanometers. In an exemplary embodiment, height D3 is independently between 5 nanometers and 15 nanometers. In an exemplary embodiment, height D4 is between 20 nanometers and 25 nanometers. In the middle of the raised valley, the height of the upper surface 600 increases from valley height D3 to peak height D4, so that the height of the active region at each position on the upper surface 600 in the middle of the valley is between 5 nanometers and 25 nanometers. In an exemplary embodiment, height differences ΔD14 and ΔD24 are independently between -10 nanometers and 15 nanometers, height difference ΔD43 is between 10 nanometers and 20 nanometers, and height differences ΔD13 and ΔD23 are independently between -5 nanometers and 25 nanometers.

[0118] like Figure 6As shown, gate structure 240 is formed with a lateral width or distance W1 from first end 611 to peak 613 and a lateral width or distance W2 from second end 615 to peak 613. In an exemplary embodiment, lateral width W1 and lateral width W2 are independently between 40 nanometers and 60 nanometers.

[0119] In some embodiments, the second etch is a dry etch. In some embodiments, the second etch is a CF 4 / O 2 / N 2 NF 3 / O 2 / N 2 or BCl 3 / Cl 2 / O 2 Gas, dry etching performed at a pressure of 1mTorr to 200mTorr, a power of 400W to 1200W, and a bias of 0W to 20W.

[0120] To achieve the ideal W-shaped profile of the gate, the duration and conditions of the second etch can be controlled. Figure 6 In the embodiment, the duration of the second etching is relatively short, thereby producing a substantially larger horn, the ends 611 and 615 of the horn protrude with a relatively larger maximum height, and the middle peak 613 protrudes with a relatively larger maximum height D4. Such an embodiment has less gate metal loss and has a lower threshold voltage for NMOS elements, but has a higher threshold voltage for PMOS elements.

[0121] In the illustrated embodiment, after the second etching is performed, the upper surface 600 extends from the end 611 to the valley 612, from the valley 612 to the peak 613, from the peak 613 to the valley 614, and from the valley 614 to the end 615. Therefore, the upper surface 600 includes a portion having a negative slope 621, a portion having a positive slope 622, a portion having a negative slope 623, and a portion having a positive slope 624. In the exemplary embodiment, the steepest inclination angle of the negative slope portion 621 is -45°, the steepest inclination angle of the positive slope portion 622 is 45°, the steepest inclination angle of the negative slope portion 623 is -45°, and the steepest inclination angle of the positive slope portion 624 is 45°. Each portion 621, 622, 623, and 624 has a flattest slope of 0° at its respective valley or peak. In an exemplary embodiment, the slope of the negative slope portion 621 is -5° to -45°, and the slope of the positive slope portion 624 is 5° to 45°. In an exemplary embodiment, the absolute value difference in slope between the negative slope portion 621 and the positive slope portion 624 is 0 to 20°. In an exemplary embodiment, the slope of the negative slope portion 623 is -5° to -45°, and the slope of the positive slope portion 622 is 5° to 45°. In an exemplary embodiment, the absolute value difference in slope between the negative slope portion 623 and the positive slope portion 622 is 0 to 20°.

[0122] It should be noted that the desired profile of the upper surface 600 can be obtained by controlling the duration of the process for depositing the etch retardation layer 500 and for performing the second etching of the etch retardation layer 500 and the gate structure 240. For example, the etching process can be performed for a relatively long time to form an upper surface 600 having a profile with equal heights D1, D2, D3, and D4 and a height difference ΔD14, ΔD24, ΔD43, ΔD13, and / or ΔD23 that is equal to zero, that is, a flat and horizontal upper surface 600. On the other hand, the etching process can be performed in a relatively short time to form an upper surface 600 having a profile with desired heights D1, D2, D3, and D4 and an increased or maximized height difference ΔD14, ΔD24, ΔD43, ΔD13, and / or ΔD23, that is, an upper surface 600 having a W-shaped profile. In an exemplary embodiment, the method forms a gate structure having a flat upper surface 600 in some device regions, while in other device regions, the method forms a gate structure having a surface with a W-shaped profile.

[0123] After establishing the desired profile of the upper surface 600 , the method 100 may continue at action block S112 by forming a liner 700 on the upper surface 600 of the gate structure 240 , such as Figure 7As shown. An exemplary liner 700 is conductive, such as a metal. In an exemplary embodiment, the liner 700 is tungsten. The liner 700 can be formed using ionized physical vapor deposition (ionizedPVD), however, other suitable deposition processes and thicknesses can be used. As shown, the exemplary liner 700 is conformal and is formed to a substantially uniform thickness. In an exemplary embodiment, the gate structure 240 can be considered to include a gate dielectric 241, a gate metal 242, and a liner 700.

[0124] The method 100 continues at block S114 by forming a dielectric material 810 on the liner 700, such as Figure 8 . An exemplary dielectric material 810 is SiN, although any suitable dielectric may be used. The dielectric material 810 may be deposited by a re-fill process.

[0125] The method 100 further includes, at block S116, forming an interconnect 820 in electrical contact with the pad 700, such as Figure 8 An exemplary interconnect 820 is a conductive material, such as a metal, such as cobalt, aluminum, copper, or other suitable material.

[0126] Method 100 may continue to further process component 200 at block S118. In general, further processing may form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / channels / lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect various features to form functional circuits that may include one or more multi-gate components. In a further example, the multilayer interconnect may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. Various interconnect features may be made of various conductive materials, including cobalt, aluminum, copper, tungsten, and / or silicide. In addition, additional process steps may be implemented before, during, and after method 100, and some of the process steps described above may be replaced or eliminated according to various embodiments of method 100.

[0127] like Figure 8 As shown, the pad 700 has an inclined top surface 710. More specifically, the top surface 710 includes a first negative slope region 711, a first positive slope region 712, a second negative slope region 713, and a second positive slope region 714.

[0128] Fig. 9 is a partial enlarged view of the interface 900 between the interconnect 820 and the pad 700. Figure 8 and Fig. 9, an angle A1 of the first negative slope portion 711 and the interface 900 relative to a horizontal plane (eg, a horizontal plane of the underlying substrate) can be determined. In an exemplary embodiment, the angle A1 is 5 to 45 degrees.

[0129] In an exemplary embodiment, the angle of each slope portion 712, 713, and 714 may have a corresponding absolute value of 5 to 45 degrees. In an exemplary embodiment, the difference in angle between the portions 711, 712, 713, and 714 is 0 to 20 degrees.

[0130] It should be further noted that the dimensions and dimension ratios disclosed herein may vary depending on the cross-sectional width of the gate. For a small gate having a critical dimension or width in the Y direction of about 50 nanometers, the angle A1 may be increased compared to a large gate having a critical dimension or width in the Y direction of about 600 nanometers. For example, the angle A1 (and other slopes) in the small gate may be about 10 to 30 degrees higher than the angle A1 (and other slopes) in the large gate.

[0131] In an exemplary embodiment, the interconnect 820 is formed in contact with the slope region 711 of the top surface 710 of the liner 700. Therefore, the contact interface 900 between the interconnect 820 and the liner 700 (and of the gate structure 240) extends from the upper end 901 to the lower end 902. Therefore, the contact interface 900 has an interface length 905, which is greater than or equal to the distance between the upper end 901 and the lower end 902. Further, the contact interface 900 has an interface area, which is the product of the interface length 905.

[0132] Furthermore, interconnect 820 has a horizontal profile 822 defined at upper end 901 of contact interface 900. Horizontal profile 822 extends a profile distance 825 from upper end 901 to position 921 at the same height and on the opposite edge of interconnect 820 and has an interconnect cross-sectional area that is the product of profile distance 825.

[0133] In an exemplary embodiment, the interface length 905 is greater than the cross-sectional distance 825, and the contact interface area is greater than the interconnect cross-sectional area. In such an embodiment, the contact interface area is about 1.05 to about 1.4 times the interconnect cross-sectional area. Due to the expansion of the contact interface area, the contact resistance (Rc) can be reduced. In addition, the reduction in contact resistance (Rc) can even be obtained in the cross-sectional distance 825 as the component size is reduced.

[0134] Comparison Figure 8 and Fig.10, provides a partial enlarged view of the interface 950 between the liner 700 and the upper surface 600 of the gate structure 240 (including the gate material 242 and the layer 241). As shown, the upper surface 600 is sloped and includes a first negative slope region 621, a first positive slope region 622, a second negative slope region 623, and a second positive slope region 624. In more detail, the upper surface 600 extends from the first highest point of the end 611 at the left edge to the first lowest point of the valley 612, to the next highest point of the peak 613, to the next lowest point of the valley 614, to the next highest point of the end 615 at the right edge, such that a surface length 629 from the end 611 to the end 615 is defined. In an exemplary embodiment, the liner 700 covers the entire upper surface 600 of the gate structure 240. Therefore, the interface 950 has an interface length 951 equal to the surface length 629, and has an interface area that is the product of the length 951.

[0135] The gate structure 240 includes a horizontal cross section 248 at the valley 612 and / or 614 of the inclined upper surface 600. The horizontal cross section 248 has a length 249. In an exemplary embodiment, the length 249 is 80 nanometers to 120 nanometers (nm). The cross-sectional area of ​​the gate is defined as the product of the length 249.

[0136] In an exemplary embodiment, gate interface length 951 is greater than cross-sectional length 249, and gate interface area is greater than cross-sectional area. In an exemplary embodiment, gate interface area is about 1.05 to about 1.4 times the cross-sectional area.

[0137] exist Fig.10 In the embodiment, the ends 611 and / or 615 of the upper surface 600 are formed at a maximum vertical distance or height 619 (equal to the above-mentioned ΔD23) above the valley 612 and / or the valley 614. The height 619 can be -5 to 25 nanometers. Therefore, in some embodiments, the maximum ratio of the height 619 to the length 249 is 25:80 to 25:120.

[0138] Fig.11 is a partial enlarged cross-sectional view of an interface 950 between the liner 700 and the upper surface 600 of the gate structure 240 (including the gate material 242 and the layer 241), similar to Fig.10 , but in embodiments with a larger gate critical dimension, such as 600 nanometers (nm). Fig.12As shown, the upper surface 600 is inclined and includes a first negative slope region 621, a first positive slope region 622, a second negative slope region 623, and a second positive slope region 624. In more detail, the upper surface 600 extends from a first highest point of the end 611 of the left edge to a first lowest point of the valley 612, to a next highest point of the peak 613, to a next lowest point of the valley 614, to a next highest point of the end 615 of the right edge, such that a surface length 629 from the end 611 to the end 615 is defined. In an exemplary embodiment, the liner 700 covers the entire upper surface 600 of the gate structure 240. Therefore, the interface 950 has an interface length 951 equal to the surface length 629, and has an interface area that is the product of the length 951.

[0139] The gate structure 240 includes a horizontal cross section 248 at the valley 612 and / or 614 of the inclined upper surface 600. The horizontal cross section 248 has a length 249. In an exemplary embodiment, the length 249 is 600 nanometers (nm). The cross-sectional area of ​​the gate is defined as the product of the length 249.

[0140] In an exemplary embodiment, gate interface length 951 is greater than cross-sectional length 249, and gate interface area is greater than cross-sectional area. In an exemplary embodiment, gate interface area is about 1.05 to about 1.4 times greater than cross-sectional area.

[0141] exist Fig.11 In the embodiment, the ends 611 and / or 615 of the upper surface 600 are formed at a maximum vertical distance or height 619 (equal to the above-mentioned ΔD23) above the valley 612 and / or the valley 614. The height 619 can be -5 to 25 nanometers. Therefore, in some embodiments, the maximum ratio of the height 619 to the length 249 is 25:600.

[0142] Please refer to Figure 12 to Figure 14 , depicts another embodiment of the second etching process. Specifically, Figure 5 Initially, the second etching process is performed for a relatively long time, resulting in elimination of the corners 252 and 253 and recessing the surface into a flat surface, such as Fig.12 Specifically, the upper surface 600 is formed as a substantially flat surface, ie, a non-inclined surface. With the elimination of the corners 252 and 253, there is more gate metal loss, and a lower threshold voltage for the PMOS element, but a higher threshold voltage for the NMOS element.

[0143] From comparison Figure 4 and Fig.12 It will be appreciated that the second etch process can be controlled to provide any desired recessed surface profile, depending on the duration of the second etch and the composition and dimensions of the etch retardation layer.

[0144] exist Fig.13 In the embodiment, the pad 700 is formed on the non-inclined upper surface 600. Fig.14 In the embodiment, a dielectric material 810 is formed on the liner 700, and an interconnect 820 is formed in electrical contact with the liner 700. An exemplary interconnect 820 is a conductive material, such as a metal, such as cobalt, aluminum, copper, or other suitable material.

[0145] because Figure 12 to Figure 14 The upper surface is planar and non-inclined, and the interface area between gate structure 240 and pad 700 is substantially equal to the cross-sectional area of ​​gate structure 240. Similarly, the area of ​​contact interface 900 between interconnect 820 and pad 700 is substantially equal to the cross-sectional area of ​​interconnect 820 near interface 900.

[0146] Comparison Figure 6 and Fig.12 It can be understood that for the exemplary embodiment of the upper surface 600 having a planar profile, the heights D1, D2, D3, D4 and D5 are the same and are 5 to 30 nanometers, and the height differences ΔD14, ΔD24, ΔD43, ΔD13 and ΔD23 are zero.

[0147] In some embodiments, the method 100 may include depositing the etching retardation layer 500 in different regions of the substrate or component with different process parameters at S108, so that an etching retardation layer having a first maximum thickness is formed in the first region, and an etching retardation layer having a second maximum thickness different from the first maximum thickness is formed in the second region. For example, the deposition process may be performed for a first deposition time or duration in the first region and for a second deposition time or duration in the second region. When the second deposition time is greater than the first deposition time, the second maximum thickness is greater than the first maximum thickness.

[0148] Further, method 100 may include performing a second etching process with different parameters in different regions of the substrate or component. For example, the second etching process may be performed for a first process time or duration in a first region and for a second process time or duration in a second region. Generally, the longer the process time, the more gate material is removed in the second etching process. For example, the second etching process may form a gate having Figure 6 A region of an element of a structure, and having Fig.12 another area of ​​the structure element, and / or having a Figure 6 and Fig.12 Any other region of an element of any desired profile of a combination of structures. Thus, the method 100 provides a controllable mechanism for forming a structure having desired properties.

[0149] In an exemplary embodiment, a method is provided, comprising performing a first etching process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first corner, a second corner, and a valley between the first corner and the second corner, and wherein the valley includes a first region proximate to the first corner, a second region proximate to the second corner, and an intermediate region between the first region and the second region; depositing an etch retardation layer above the recessed surface, wherein the etch retardation layer includes a first etch region, a second etch region, and a central region between the first etch region and the second etch region, wherein the first etch region is above the first corner and the first region, wherein the second etch region is above the second corner and the second region, wherein the central region is above the intermediate region, and wherein the central region is thicker than the first etch region and the second etch region; and performing a second etching process to recess the gate material to establish a gate material having a W-shaped profile.

[0150] In an exemplary embodiment, the etch retardation layer is formed to have a first negative slope extending from a first end to a first valley, a first positive slope extending from the first valley to a peak, a second positive slope extending from the peak to a second valley, and a second negative slope extending from the second valley to the second end.

[0151] In an exemplary embodiment, the method further includes forming a liner over the W-shaped profile of the gate material, wherein the gate material and the liner form a gate; forming a dielectric material over the gate; and forming an interconnect contacting the gate.

[0152] In exemplary embodiments, the etch retardation layer includes carbon, boron, or carbon and boron.

[0153] In an exemplary embodiment, the method further includes determining a desired threshold voltage for the gate material, wherein the W-shaped profile of the gate material is selected based on the desired threshold voltage, and wherein the second etching process is performed for a selected time to create the gate material having the W-shaped profile.

[0154] In an exemplary embodiment, the method further includes forming a liner over a W-shaped profile of a gate material, wherein the gate material and the liner form a gate; wherein the W-shaped profile of the gate material includes a sloped upper surface having a lowest point; wherein the liner contacts the sloped upper surface along a gate interface having a gate interface region; wherein a horizontal cross-section of the gate material at the lowest point of the sloped upper surface has a cross-sectional area; and wherein the gate interface region is larger than the cross-sectional area.

[0155] In an exemplary embodiment, the gate interface area is about 1.05 times to about 1.4 times the cross-sectional area.

[0156] In an exemplary embodiment, the method further includes forming a pad above the W-shaped profile of the gate material, wherein the pad has a sloped upper surface; and forming the sloped upper surface of the interconnect contact pad on a contact interface extending from an upper end to a lower end, and defining a contact interface area, wherein a horizontal cross-section of the interconnect at the upper end of the contact interface has an interconnect cross-sectional area, and wherein the contact interface area is larger than the interconnect cross-sectional area.

[0157] In an exemplary embodiment, the contact interface area is about 1.05 times to about 1.4 times the interconnect cross-sectional area.

[0158] In another embodiment, a method is provided, comprising: providing a semiconductor structure having a first region and a second region; performing a deposition process to deposit an etch stop layer over a metal gate material in the first region and the second region, wherein: the deposition process performs a first deposition time in the first region to form an etch stop layer having a first maximum thickness; the deposition process performs a second deposition time in the second region to form an etch stop layer having a second maximum thickness, wherein the second deposition time is greater than the first deposition time and the second maximum thickness is greater than the first maximum thickness; and performing an etching process to remove the etch stop layer and recess the metal gate material, wherein the etching process performs a first etching time in the first region to form a metal gate material having a W-shaped profile in the first region.

[0159] In an exemplary embodiment, the etching process is performed in the second region for a second etching time greater than the first etching time to form a metal gate material having a substantially flat profile in the second region.

[0160] In certain example embodiments, the etch stop layer includes carbon, boron, or carbon and boron.

[0161] In an exemplary embodiment, the etching process is a second etching process, and the method further includes performing the first etching process to differentially etch the metal gate material to a recessed surface, wherein the recessed surface includes a first corner, a second corner, and a valley between the first corner and the second corner.

[0162] In an exemplary embodiment, the valley portion includes a first region close to the first horn portion, a second region close to the second horn portion, and a middle region between the first region and the second region, and the first maximum thickness and the second maximum thickness are each located above the middle region.

[0163] In an exemplary embodiment, the method further includes forming a metal liner above the metal gate material in each region, wherein the metal gate material and the metal liner form a metal gate in each region, wherein the metal liner contacts a W-shaped profile of the metal gate material along a gate interface having a gate interface region, wherein a horizontal cross-section of the metal gate material at a lowest point of the W-shaped profile has a cross-sectional area and wherein the gate interface region is larger than the cross-sectional area.

[0164] In an exemplary embodiment, after the etching process, the metal gate material in the first region includes a first angular portion, a first valley portion, a middle peak, a second valley portion, and a second angular portion, wherein the middle peak has a maximum height that is less than the maximum heights of the first angular portion and the second angular portion.

[0165] In another embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region, wherein the conductive gate comprises a plug and a liner. The plug has an upper surface, the upper surface has a W-shaped profile and defines a lowest point. The liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area, and wherein the gate interface region is larger than the plug cross-sectional area.

[0166] In an exemplary embodiment, the gate interface area is about 1.05 times to about 1.4 times the plug cross-sectional area.

[0167] In an exemplary embodiment, the pad has a top surface with a W-shaped profile, and wherein the semiconductor structure further includes a conductor interconnect, the conductor interconnect directly contacts the top surface at a contact interface, the contact interface extends from an upper end to a lower end, and defines a contact interface area, wherein a horizontal cross-section of the conductor interconnect at the upper end of the contact interface has an interconnect cross-sectional area, and wherein the contact interface area is larger than the interconnect cross-sectional area.

[0168] In an exemplary embodiment, the contact interface area is about 1.05 times to about 1.4 times the interconnect cross-sectional area.

[0169] In another embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region. The conductive gate comprises a plug and a liner. The plug comprises a first horn, a first valley, a middle peak, a second valley, and a second horn, and has an upper surface. The upper surface defines a lowest point. The liner covers the upper surface. The liner contacts the plug along a gate interface having a gate interface region. A horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area. The gate interface region is larger than the plug cross-sectional area.

[0170] In an exemplary embodiment, the upper surface has a W-shaped profile.

[0171] In an exemplary embodiment, the middle peak has a maximum height that is smaller than the maximum heights of the first angular portion and the second angular portion.

[0172] In another embodiment, a semiconductor structure is provided, comprising an active region and a conductive gate. The conductive gate covers the active region. The conductive gate comprises a plug and a liner. The plug has an upper surface. The upper surface has a first negative slope extending from a first end to a first valley, a first positive slope extending from the first valley to a peak, a second negative slope extending from the peak to a second valley, and a second positive slope extending from the second valley to a second end. The upper surface defines a lowest point. The liner covers the upper surface. The liner contacts the plug along a gate interface having a gate interface region. A horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional area. The gate interface region is larger than the plug cross-sectional area.

[0173] In an exemplary embodiment, the steepest inclination angle of the first negative slope and the second negative slope is -45°. The steepest inclination angle of the first positive slope and the second positive slope is 45°.

[0174] In an exemplary embodiment, the first negative ramp has a slope of -5° to -45°. The second positive ramp has a slope of 5° to 45°.

[0175] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: an active region; and A conductive gate covering the active region, wherein the conductive gate comprises: a plug having an upper surface having a W-shaped profile and defining a lowest point; and A liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional region, and wherein the gate interface region is larger than the plug cross-sectional region.

2. The semiconductor structure according to claim 1, wherein: The gate interface area is 1.05 to 1.4 times the plug cross-sectional area.

3. The semiconductor structure according to claim 1, wherein: wherein the pad has a top surface with a W-shaped profile, and wherein the semiconductor structure further comprises: A conductor interconnect directly contacts the top surface at a contact interface, the contact interface extends from an upper end to a lower end and defines a contact interface area, wherein the conductor interconnect has an interconnect cross-sectional area at a horizontal section at the upper end of the contact interface, and wherein the contact interface area is larger than the interconnect cross-sectional area.

4. The semiconductor structure according to claim 3, characterized in that The contact interface area is 1.05 to 1.4 times the interconnection cross-sectional area.

5. A semiconductor structure, characterized in that: Include: an active region; and A conductive gate covering the active region, wherein the conductive gate comprises: A plug including a first angular portion, a first valley portion, a middle peak, a second valley portion, and a second angular portion, and having an upper surface defining a lowest point; and A liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional region, and wherein the gate interface region is larger than the plug cross-sectional region.

6. The semiconductor structure according to claim 5, characterized in that The upper surface has a W-shaped profile.

7. The semiconductor structure according to claim 5, characterized in that The middle peak has a maximum height, which is smaller than a maximum height of the first angular portion and a maximum height of the second angular portion.

8. A semiconductor structure, characterized in that: Include: an active region; and A conductive gate covering the active region, wherein the conductive gate comprises: a plug having an upper surface, wherein the upper surface has a first negative slope extending from a first end to a first valley, a first positive slope extending from the first valley to a peak, a second negative slope extending from the peak to a second valley, and a second positive slope extending from the second valley to a second end, the upper surface defining a lowest point; and A liner covers the upper surface, wherein the liner contacts the plug along a gate interface having a gate interface region, wherein a horizontal cross-section of the plug at the lowest point of the upper surface has a plug cross-sectional region, and wherein the gate interface region is larger than the plug cross-sectional region.

9. The semiconductor structure according to claim 8, characterized in that The steepest inclination angle between the first negative slope and the second negative slope is -45°, and the steepest inclination angle between the first positive slope and the second positive slope is 45°.

10. The semiconductor structure according to claim 8, wherein: The slope of the first negative slope is between -5° and -45°, and the slope of the second positive slope is between 5° and 45°.

Images