Semiconductor device

Abstract

A semiconductor device includes a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and a secondary structure. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. A first plurality of conductors is formed over the first active region. The second active region is on a second side of the isolation structure opposite the first active region. A second plurality of conductors is formed over the second active region. A secondary structure is formed over the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device by forming a plurality of polysilicon structures on a semiconductor substrate and the formed semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a substrate, and patterning the various material layers using lithography to form multiple circuit components and multiple components thereon. As the semiconductor industry has evolved to nanotechnology process nodes pursuing higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of many three-dimensional designs, including, for example, Metal-Oxide-Silicon Field Effect Transistors (MOS-FET), Field Effect Transistors (FET), Fin Field Effect Transistors (FinFET), Nanosheet Field Effect Transistors, Nanowire Field Effect Transistors, and Gate-All-Around (GAA) devices.

[0003] Integrated circuit (IC) manufacturing is generally divided into the front-end-of-line (FEOL) process and the back-end-of-line (BEOL) process. The front-end process of the production line generally covers those processes related to the manufacture of functional elements (such as transistors and resistors) in or on a semiconductor substrate. For example, the front-end process of the production line generally includes the formation of isolation features, gate structures, and source and drain features (also known as source / drain, S / D, or SD features). The back-end process of the production line generally covers those processes related to the manufacture of multilayer interconnect (MLI) features, which interconnect multiple functional integrated circuit elements and multiple structures manufactured during the back-end process of the production line to provide connections to the resulting integrated circuit device and enable the integrated circuit device to operate. Reducing process and structural modifications associated with process complexity and / or feature size (such as gate structures and multilayer interconnect structures) tend to reduce the overall size of the integrated circuit device, improve cycle time, and / or increase yield and reliability. Utility Model Content

[0004] Some embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and a secondary structure. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite to the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors.

[0005] Other embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and a secondary structure. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite to the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors. A length of the isolation structure between the first active region and the second active region is greater than 1.5 times a spacing between any two of the first plurality of conductors or a spacing between any two of the second plurality of conductors.

[0006] Still other embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and at least two secondary structures. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the at least two secondary structures are between the first plurality of conductors and the second plurality of conductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be better understood by the following detailed description and reading together with the accompanying drawings. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of each feature can be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A , Figure 1C , Figure 1E , Figure 1G , Fig. 1I , Figure 1K ,and Figure 1M to Figure 1Qis a cross-sectional view of a semiconductor device during various operations of a semiconductor device fabrication process according to some embodiments;

[0009] Figure 1B , Figure 1D , Figure 1F , Figure 1H , Figure 1J ,and Figure 1L According to some embodiments, in the case corresponding to Figure 1A , Figure 1C , Figure 1E , Figure 1G , Fig. 1I ,and Figure 1K a plan view of a semiconductor device during various operations of a semiconductor device manufacturing process;

[0010] FIG. 2A to FIG. 2E is a plan view of each semiconductor device manufactured according to a plurality of manufacturing processes of some embodiments, wherein one or more functional elements are formed above an isolation structure on a surface of a semiconductor substrate;

[0011] FIG. 3A to FIG. 3N is a cross-sectional view of a semiconductor device during various operations of a semiconductor device fabrication process according to some embodiments;

[0012] 4A to 4F is a cross-sectional view of a semiconductor device during various operations of a semiconductor device fabrication process according to some embodiments;

[0013] FIG. 5A to FIG. 5L is a cross-sectional view of a semiconductor device during various operations of a semiconductor device fabrication process according to some embodiments;

[0014] 6A to 6F is a flow chart of a manufacturing process for production of an integrated circuit device according to some embodiments;

[0015] Figure 7 is a schematic diagram of a system for manufacturing a field effect transistor device according to some embodiments;

[0016] Figure 8 is a flow chart of integrated circuit device design, fabrication, and programming of an integrated circuit device according to some embodiments;

[0017] Fig. 9 is a schematic diagram of a processing system for fabrication of integrated circuit devices according to some embodiments.

[0018]

Explanation of symbols

[0019] 100A: Integrated Circuit Devices

[0020] 100C: Integrated Circuit Devices

[0021] 100E: Integrated Circuit Devices

[0022] 100G: Integrated Circuit Devices

[0023] 100Q: Integrated Circuit Devices

[0024] 100I: Integrated Circuit Device

[0025] 100K: Integrated Circuit Devices

[0026] 100M: Integrated Circuit Devices

[0027] 100N: Integrated Circuit Devices

[0028] 100O: Integrated Circuit Devices

[0029] 100P: Integrated Circuit Device

[0030] 100Q: Integrated Circuit Devices

[0031] 101:Semiconductor substrate

[0032] 102: Active area

[0033] 104: Isolation Structure

[0034] 106: Primary polysilicon structure

[0035] 106′: Primary polysilicon structure

[0036] 108: Hard mask pattern

[0037] 110: Secondary polysilicon structure

[0038] 110′: Secondary polysilicon structure

[0039] 110A: Secondary polysilicon structure

[0040] 110B: Secondary polysilicon structure

[0041] 110R: Secondary polysilicon structure

[0042] 111: Secondary opening

[0043] 112: Photoresist pattern

[0044] 113: Conductive material

[0045] 114: Dielectric region

[0046] 114′: Dielectric material

[0047] 115: Flat surface

[0048] 116: contact etching stop layer

[0049] 116′: Etching stop pattern (remaining portion of the contact etching stop layer)

[0050] 118: Photoresist pattern

[0051] 120: Primary contact opening

[0052] 120′: Reduced contact opening

[0053] 121: Conductive material (conductive layer)

[0054] 121′: layered conductive structure

[0055] 122: Conductive composite structure (conductive composite layer)

[0056] 122′: Start gate structure

[0057] 122″: Final gate structure

[0058] 123: Flattened surface

[0059] 125: Flat surface

[0060] 126: Interlayer dielectric layer

[0061] 126′: interlayer dielectric layer (interlayer dielectric pattern)

[0062] 128: Opening (contact opening, starting contact opening)

[0063] 128′: Secondary contact opening

[0064] 130: Barrier metal layer

[0065] 132: Conductive material

[0066] 134: Contact etching stop layer

[0067] 134′: contact etching stop layer

[0068] 136: Etching pattern

[0069] 138: Opening

[0070] 138′: Reduced opening

[0071] 140: Conformal layer

[0072] 142: Insulating materials (dielectric materials)

[0073] 143: Flat surface

[0074] 144: Interlayer dielectric layer

[0075] 144′: interlayer dielectric pattern

[0076] 144″: Interlayer dielectric pattern

[0077] 145: Conductive element

[0078] 150: Opening (starting contact opening)

[0079] 150′: Secondary contact opening

[0080] 202: Active area

[0081] 202′: Active area

[0082] 206: Primary polysilicon structure

[0083] 206′: offset primary polysilicon structure

[0084] 206A: Primary polysilicon structure

[0085] 206A′: Primary polysilicon structure

[0086] 206B: Primary polysilicon structure

[0087] 206B′: Primary polysilicon structure

[0088] 210: Secondary polysilicon structure

[0089] 210′: Secondary polysilicon structure

[0090] 210A: Secondary polysilicon structure

[0091] 210B: Secondary polysilicon structure

[0092] 211: Conductor

[0093] 212: Conductive material (resistor cap)

[0094] 214:Semiconductor board

[0095] 216: Conductive material (conductive element)

[0096] 218: Resistors

[0097] 218A: Resistors

[0098] 218B: Resistors

[0099] 218C: Resistors

[0100] 218D: Resistors

[0101] 218E: Resistors

[0102] 219: Barrier layer

[0103] 220: Conductive material

[0104] 221: Power rail (composite conductor structure)

[0105] 222: Heat dissipation structure

[0106] 223:Variable and controllable resistor (resistor)

[0107] 224: Heat dissipation structure

[0108] 230: Interval

[0109] 230′: Second interval

[0110] 300A: Integrated Circuit Devices

[0111] 300B: Integrated Circuit Devices

[0112] 300C: Integrated Circuit Devices

[0113] 300D: Integrated Circuit Devices

[0114] 300E: Integrated Circuit Devices

[0115] 300F: Integrated Circuit Devices

[0116] 300G: Integrated Circuit Devices

[0117] 300H: Integrated Circuit Devices

[0118] 300I: Integrated Circuit Device

[0119] 300J: Integrated Circuit Devices

[0120] 300K: Integrated Circuit Devices

[0121] 300L: Integrated Circuit Devices

[0122] 300M: Integrated Circuit Devices

[0123] 300N: Integrated Circuit Devices

[0124] 400A: Integrated Circuit Devices

[0125] 400B: Integrated Circuit Devices

[0126] 400C: Integrated Circuit Devices

[0127] 400D: Integrated Circuit Devices

[0128] 400E: Integrated Circuit Devices

[0129] 400F: Integrated Circuit Devices

[0130] 500A: Integrated Circuit Devices

[0131] 500B: Integrated Circuit Devices

[0132] 500C: Integrated Circuit Devices

[0133] 500D: Integrated Circuit Devices

[0134] 500E: Integrated Circuit Devices

[0135] 500F: Integrated Circuit Devices

[0136] 500G: Integrated Circuit Devices

[0137] 500H: Integrated Circuit Devices

[0138] 500I: Integrated Circuit Device

[0139] 500J: Integrated Circuit Devices

[0140] 500K: Integrated Circuit Devices

[0141] 500L: Integrated Circuit Devices

[0142] 600A: Manufacturing Process

[0143] 600B: Manufacturing Process

[0144] 600C: Manufacturing Process

[0145] 600D: Manufacturing process

[0146] 600E: Manufacturing Process

[0147] 602a: Operation

[0148] 602b: Operation

[0149] 602c: Operation

[0150] 602d: Operation

[0151] 602e: Operation

[0152] 604a: Operation

[0153] 604b: Operation

[0154] 604c: Operation

[0155] 604d: Operation

[0156] 604e1: Operation

[0157] 604e2: Operation

[0158] 604e3: Operation

[0159] 604e4: Operation

[0160] 606a: Operation

[0161] 606b: Operation

[0162] 606c: Operation

[0163] 606d: Operation

[0164] 606e1: Operation

[0165] 606e3: Operation

[0166] 606e4: Operation

[0167] 608a: Operation

[0168] 608b: Operation

[0169] 608c: Operation

[0170] 608d: Operation

[0171] 608e1: Operation

[0172] 608e2: Operation

[0173] 608e3: Operation

[0174] 608e4: Operation

[0175] 610a: Operation

[0176] 610b: Operation

[0177] 610c: Operation

[0178] 610d: Operation

[0179] 610e1: Operation

[0180] 610e2: Operation

[0181] 610e3: Operation

[0182] 612a: Operation

[0183] 612b: Operation

[0184] 612c: Operation

[0185] 612d: Operation

[0186] 612e1: Operation

[0187] 614a: Operation

[0188] 614b: Operation

[0189] 614c: Operation

[0190] 614d: Operation

[0191] 614e1: Operation

[0192] 614e2: Operation

[0193] 614e3: Operation

[0194] 614e4: Operation

[0195] 616a: Operation

[0196] 616b: Operation

[0197] 616c: Operation

[0198] 616d: Operation

[0199] 616e1: Operation

[0200] 618a: Operation

[0201] 618b: Operation

[0202] 618d: Operation

[0203] 618e1: Operation

[0204] 620a: Operation

[0205] 620b: Operation

[0206] 620d: Operation

[0207] 622a: Operation

[0208] 622b: Operation

[0209] 622d: Operation

[0210] 624a: Operation

[0211] 624b: Operation

[0212] 624d: Operation

[0213] 626b: Operation

[0214] 626d: Operation

[0215] 628b: Operation

[0216] 628d: Operation

[0217] 650: Operation Group

[0218] 652: Operation Group

[0219] 654: Operation Group

[0220] 656: Operation Group

[0221] 700: Electronic process control system

[0222] 702: Hardware processor

[0223] 704: Computer readable storage medium

[0224] 706: Computer program code

[0225] 708: Process Control Data

[0226] 710: User interface

[0227] 712: Input / output interface

[0228] 714: Network interface

[0229] 716: Network

[0230] 718: Bus

[0231] 720: Manufacturing Tools

[0232] 800: Manufacturing System

[0233] 820: Design Company

[0234] 822: Integrated Circuit Design Layout

[0235] 830: Photomask Company

[0236] 832: Mask Data Preparation

[0237] 844:Mask Manufacturing

[0238] 845: Photomask

[0239] 850: Integrated Circuit Manufacturing Plant

[0240] 852: Wafer Manufacturing

[0241] 853:Semiconductor Wafer

[0242] 855: Integrated Circuit Manufacturing Plant

[0243] 857: Wafer Manufacturing

[0244] 859: Wafer

[0245] 860: Integrated Circuit Device

[0246] 880: The back end of the production line

[0247] 902: Wafer transfer operation

[0248] 904: Photolithography

[0249] 906: Etching operation

[0250] 908: Ion implantation operation

[0251] 910: Clearing / stripping operation

[0252] 912: Chemical Mechanical Polishing Operation

[0253] 914: Epitaxial Growth Operation

[0254] 916: Deposition operation

[0255] 918: Heat treatment

[0256] AA′: plane

[0257] CC′: plane

[0258] EE′: plane

[0259] GG′: plane

[0260] II′: Plane

[0261] KK′: plane DETAILED DESCRIPTION

[0262] The disclosure that follows provides many different implementations or embodiments to implement the different features of the subject matter provided. In order to simplify the disclosure, multiple specific embodiments of components, values, operations, materials, arrangements, or the like are described below. These are of course only embodiments and are not intended to be restrictive. Other components, values, operations, materials, arrangements, or the like are also contemplated. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an implementation in which additional features may be formed between the first feature and the second feature, so the first feature and the second feature may not be in direct contact may be included. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and repetition itself does not mean the relationship between the various embodiments discussed and / or the relationship between the configurations.

[0263] Additionally, to facilitate describing the relationship of one element or feature to another element or feature as depicted in the figures, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0264] The structures and methods described in detail below generally relate to structures, designs and manufacturing methods for integrated circuit devices, including a series of multiple active regions or multiple active areas separated by isolation structures (e.g., shallow trench isolation (STI) structures), wherein one or more supplementary structures are provided above the isolation structures to improve multiple process operations, such as by improving uniformity among multiple structures in multiple active regions, and / or providing additional functional elements, and thereby improving the utilization of the surface area of ​​the semiconductor device and providing the desired functionality. Although these structures and methods will be discussed based on fin field effect transistor (FIN FET) devices, these structures and methods are not limited to this, but are applicable to the manufacturing processes of integrated circuit devices of other classifications and configurations, including but not limited to bulk semiconductor devices and silicon-on-insulator (SOI) devices, metal oxide silicon field effect transistors (MOSFET or simply FET), fin field effect transistors (FIN FET), nanosheet field effect transistors, nanowire field effect transistors, gate-all-around (GAA) devices, gate-first devices, gate-last devices, high-κMetal Gate (HKMG) devices, planar devices, and back end of line (BEOL) devices.

[0265] As feature areas continue to shrink, physical alignment and sizing of successive layers and elements, as well as maintaining electrical isolation of separated elements, present significant challenges. In some embodiments, repositioning and / or sizing of one or more features provides sufficient space to accommodate additional conductive features, such as vias, power rails, resistors, and heat sinks, which in turn reduces the need for additional conductive elements in one or more associated conductive patterns, and / or can increase device density. In some embodiments, the formation of multiple functional elements above an isolation structure retains multiple active areas for a predetermined circuit, and / or reduces the height of an integrated circuit device by providing multiple functional elements in a configuration corresponding to, for example, the height of a gate structure. In some embodiments, modifying the composition used to form certain features provides increased etch selectivity, and an increased likelihood of complete removal of residual material from even high aspect ratio features can be achieved without undue over-etching or non-uniformity.

[0266] Figure 1A is a cross-sectional view of an integrated circuit device 100A during an operation used in integrated circuit device fabrication according to some embodiments. Figure 1AThe integrated circuit device 100A in the embodiment includes a semiconductor substrate 101, and the semiconductor substrate 101 has a plurality of active regions 102 separated by isolation structures 104 (or isolation regions). In some embodiments, two or more dielectric materials are used to form the isolation structure. In some embodiments, the semiconductor substrate 101 is patterned and etched to form a plurality of recessed regions (not shown), and dielectric materials are deposited or grown into these recessed regions to form the isolation structure 104. In some embodiments, the isolation structure 104 is selected from a shallow trench isolation (STI) structure, a local oxidation of silicon (LOCOS) structure, a deep trench isolation (DTI) structure, a trench isolation, and a pn junction isolation (PN) / pin isolation (PIN) structure. In some embodiments, the isolation structure 104 is formed using a material having a high dielectric constant (k value), such as a material with κ>3.9. In some embodiments, the high-k dielectric material includes HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, SiO x N y , and one or more of a combination thereof, or another suitable material. The insulating / dielectric material forming the isolation structure 104 may be deposited via atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM), and / or one or more other suitable methods.

[0267] exist Figure 1AThe integrated circuit device 100A in the embodiment includes a series of a plurality of preliminary polysilicon structures 106 above a plurality of active regions 102, which in some embodiments have been etched from a first polysilicon layer (not shown) by removing a plurality of portions of the first polysilicon layer not covered by a hard mask pattern 108. In some embodiments, the plurality of preliminary polysilicon structures 106 are arranged above the plurality of active regions 102 (or, in some embodiments, directly on the plurality of active regions 102) with a spacing referred to as a contacted polysilicon pitch (CPP), the distance being determined by design rules applicable to a particular manufacturing method used in manufacturing the integrated circuit device.

[0268] Figure 1A The integrated circuit device 100A in the embodiment also includes one or more secondary polysilicon structures 110 formed above the isolation structure 104. In some embodiments, the primary polysilicon structures 106 and the secondary polysilicon structures 110 are both formed from the first polysilicon layer during an etching operation. In some embodiments, the secondary polysilicon structures 110 are formed after the primary polysilicon structures 106 by growing or depositing polysilicon on predetermined portions of the upper surface of the isolation structure 104 exposed by the photoresist pattern 112. The number and spacing of the secondary polysilicon structures 110 used in a particular semiconductor device layout is at least partially a function of the number and width of the open space above the isolation structure 104. In some embodiments, if the width of the open space between two active regions 102 is greater than 1.5 times the applicable contact polysilicon pitch (CPP), there is room for placing one or more secondary polysilicon structures 110 above the isolation structure 104.

[0269] exist Figure 1B The integrated circuit device 100A is in Figure 1A (Along Figure 1B The plan view of the structure in the cross-sectional view (taken by plane AA′ of FIG. 1 ) shows multiple upper surfaces of the hard mask pattern 108 , the secondary polysilicon structure 110 , and the photoresist pattern 112 .

[0270] exist Figure 1C The integrated circuit device 100C is according to some embodiments in Figure 1A A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1CThe integrated circuit device 100C in FIG. 1 has been processed by a cleaning operation to remove the photoresist pattern 112, and by a deposition operation to fill the plurality of spaces left by the removal of the photoresist pattern 112 with an interlayer dielectric (ILD) layer (not shown). A planarization process is then applied to remove the hard mask pattern 108, as well as an upper portion of the first interlayer dielectric layer (not shown), an upper portion of the plurality of secondary polysilicon structures 110, and an upper portion of the plurality of primary polysilicon structures 106 to form a flat surface 115.

[0271] In some embodiments, the addition of secondary polysilicon structures 110 can improve the uniformity of subsequent processing operations (including, for example, etching and / or planarization operations) by improving the uniformity of polysilicon density across the surface of the wafer. In some embodiments, this improved uniformity will be evident in post-process inspection of those structures in multiple active regions adjacent to isolation structures. The improved uniformity achieved across the surface of the wafer will tend to be reflected in improved processing yields and increased performance, and / or reliability of the resulting semiconductor devices.

[0272] In some embodiments, the planarization process utilizes a chemical-mechanical polishing (CMP) process or a back etch process to provide a flatter surface for subsequent processing. The chemical-mechanical polishing process utilizes a polishing pad in combination with a polishing slurry, and a polishing machine is used to apply the polishing slurry to the surface of the integrated circuit device for removing multiple upper portions of different material layers. In some embodiments, the specific combination of the chemical-mechanical polishing pad and the slurry is selected based on multiple factors including the material to be removed (e.g., silicon dioxide, polycrystalline silicon, or monocrystalline silicon), technical performance requirements, process optimization, and / or cost of ownership considerations. In the back etch process, the surface of the integrated circuit device is exposed to one or more dry etching processes to remove a portion of the upper layer of the material, thereby improving the flatness of the surface of the integrated circuit device. In some embodiments, the etchant gas used in the back etch process includes a combination of CF4, CHF3, Ar, and O2, and is applied at different levels of gas flow and RF power according to the material to be etched and the stage of the back etch process.

[0273] Figure 1D The integrated circuit device 100C is in Figure 1C (Along Figure 1D A plan view of the structure in a cross-sectional view (taken by plane CC′) shows the upper surface of the flat surface 115.

[0274] exist Figure 1E The integrated circuit device 100E is according to some embodiments in Figure 1CA cross-sectional view of an integrated circuit device as a result of an operation after an operation. Figure 1E The integrated circuit device 100E in FIG. 1 has been processed to apply a contact etch stop layer 116 (CESL) to the planar surface 115 using a deposition operation.

[0275] exist Figure 1F The integrated circuit device 100E is in Figure 1E (Along Figure 1F A plan view of the structure in a cross-sectional view (taken along plane EE′) shows the upper surface of the contact etch stop layer 116.

[0276] exist Figure 1G The integrated circuit device 100G is according to some embodiments in Figure 1E A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1G The integrated circuit device 100G in FIG. 1 has been processed using both a patterning operation and an etching operation. The patterning operation exposes and develops a photoresist layer (not shown), and a plurality of remaining portions of the photoresist layer form a photoresist pattern 118, which is used as an etching mask to remove the exposed portion of the contact etch stop layer 116 and leave a remaining portion 116′ of the contact etch stop layer to protect the secondary polysilicon structure 110 (sometimes referred to as “dummy” polysilicon), while simultaneously exposing the upper surface of the primary polysilicon structure 106 and the remaining dielectric region 114 surrounding the primary polysilicon structure 106.

[0277] exist Figure 1H The integrated circuit device 100G is in Figure 1G (Along Figure 1H A plan view of the structure in a cross-sectional view (taken by plane GG′ of FIG. 1 ) shows multiple upper surfaces of the photoresist pattern 118, the preliminary polysilicon structure 106, and the remaining dielectric region 114 surrounding the preliminary polysilicon structure.

[0278] exist Fig. 1I The integrated circuit device 100I is according to some embodiments in Figure 1G A cross-sectional view of an integrated circuit device during operation after an operation of Fig. 1I The integrated circuit device 100I in FIG. 1 has been processed to remove the photoresist pattern 118 using a cleaning operation and to remove the primary polysilicon structure 106 using an etching operation, thereby forming a series of multiple primary contact openings 120 corresponding to multiple locations of the primary polysilicon structure 106 .

[0279] exist Figure 1J The integrated circuit device 100I is in Fig. 1I (Along Figure 1J The plan view of the structure in the cross-sectional view (taken by plane II′ of FIG. 1 ) shows the upper surface of the remaining portion 116′ of the contact etch stop layer, the multiple primary contact openings 120 formed by removing the multiple primary polysilicon structures 106, and the remaining dielectric region 114 surrounding the multiple primary contact openings 120.

[0280] In some embodiments, the etching process is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etching solution. In some embodiments, the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), thylenediamine pyrocatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof, for removing the plurality of preliminary polysilicon structures 106.

[0281] In some embodiments, the etching process is performed using a dry etching or plasma etching process using a halogen-containing reactive gas that is excited by an electromagnetic field to dissociate into a plurality of ions that are then accelerated toward the material being etched and used to remove the target material or materials including, for example, a plurality of preliminary polysilicon structures 106. Reactive gases or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, and combinations thereof, although other semiconductor material etchant gases are also contemplated within the scope of the present disclosure.

[0282] exist Figure 1K The integrated circuit device 100K is according to some embodiments in Fig. 1I A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1KThe integrated circuit device 100K in FIG. 1 has been processed using a series of deposition operations, growth operations, and / or planarization operations to fill the plurality of primary contact openings 120 with a conductive material. In some embodiments, the conductive material is a conductive composite structure 122 including a plurality of conductive materials. In some embodiments, the conductive composite structure 122 includes a work function metal element, and the work function metal element includes TiN, TiAl, W, Ti, La, Hf, TaN, Al, or a combination thereof.

[0283] exist Figure 1L The integrated circuit device 100K is in Figure 1K (Along Figure 1L A plan view of the structure in a cross-sectional view (taken by plane KK′ of FIG. 1 ), showing the upper surface of the etch stop pattern 116′ and the upper surface of the uppermost layer of the conductive composite structure 122, which fills the multiple primary contact openings 120 and extends over the remaining dielectric region 114 surrounding the primary contact openings 120.

[0284] exist Figure 1M The integrated circuit device 100M is according to some embodiments in Figure 1L A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1M The integrated circuit device 100M in FIG. 1 has been processed using a planarization operation to remove upper portions of the conductive composite structure 122 and leave a start gate structure 122′ (or contact structure) filling the plurality of primary contact openings 120, while also removing portions of the conductive composite structure 122 extending over the remaining dielectric region 114. In some embodiments, the planarization operation also removes the etch stop pattern 116′, upper portions of the remaining dielectric region 114, and upper portions of the plurality of secondary polysilicon structures 110 to leave a remaining portion of the plurality of secondary polysilicon structures 110′ and form a planar surface 125. In some embodiments, the integrated circuit device is processed using a first chemical mechanical polishing process that uses operating conditions selected for improved metal removal other than the material used to form the etch stop pattern 116′, such as atomic layer deposition (ALD) silicon nitride (SiN). x N y ). Accordingly, a second chemical mechanical polishing process is then used to complete the removal of the etch stop pattern 116' to form a flat surface 125 for additional processing, the second chemical mechanical polishing process using operating conditions selected for improved removal of the material used in forming the etch stop pattern 116'.

[0285] exist Figure 1NThe integrated circuit device 100N is according to some embodiments in Figure 1M A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1N The integrated circuit device 100N has been processed, using a deposition or growth process, to form an interlayer dielectric layer 126 on the flat surface 125 .

[0286] exist Fig.1O The integrated circuit device 100O is according to some embodiments in Figure 1N A cross-sectional view of an integrated circuit device during operation after an operation of Fig.1O The integrated circuit device 100O in FIG. 1 has been processed using patterning and etching operations to form a contact etch pattern (not shown) on an upper surface of an interlayer dielectric layer 126, and then etching the wafer to remove multiple exposed portions of the interlayer dielectric layer 126 to form a plurality of starting contact openings 128 separated by multiple remaining portions of the interlayer dielectric layer 126′. In some embodiments, the etching operation also removes an upper portion of the starting gate structure 122′ to form a final gate structure 122″ that is recessed relative to the upper surface of the remaining dielectric region 114.

[0287] exist Figure 1P The integrated circuit device 100P is according to some embodiments in Fig.1O A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1P The integrated circuit device 100P in FIG. 1 has been processed, using growth and / or deposition operations and planarization operations, to form a barrier metal layer 130 on the sidewalls and bottom surface of the starting contact openings 128 and the final gate structure 122″. The barrier metal layer 130 reduces the size of the multiple starting contact openings 128 by approximately twice the thickness of the barrier metal layer to form a plurality of secondary contact openings 128′, and the plurality of secondary contact openings 128′ have a reduced diameter relative to the starting contact openings 128.

[0288] Figure 1Q The integrated circuit device 100Q is according to some embodiments in Figure 1P A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1QThe integrated circuit device 100Q in has been processed, using growth and / or deposition operations and planarization operations, to fill the plurality of secondary contact openings 128′ with a conductive material 132. In some embodiments, the first and second conductive materials are selected from the group including metals, metal alloys, and / or metal silicides. In some embodiments, the conductive material will include various combinations of multiple materials to enhance device performance and / or device life, including, for example, barrier layers, liner layers, wetting layers, adhesion layers, metal fill layers, and / or one or more other suitable layers. In some embodiments, the conductive material will be selected from Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, and other conductive materials suitable for use in combination with polysilicon, as well as combinations and alloys thereof.

[0289] Figure 2A is based on Figure 1A to Figure 1P , wherein a plurality of secondary polysilicon structures 210 are located above the isolation structure 104 between the first plurality of primary polysilicon structures 206A and the second plurality of primary polysilicon structures 206B. In one embodiment, Figure 1M After the operations reflected in and before the addition of the interlayer dielectric layer 126, additional operations are performed to electrically connect the secondary polysilicon structure 210 with the conductor 211 to form a resistor 218. In some embodiments, the secondary polysilicon structure 210 is removed and replaced with another conductor (not shown) to obtain the resistor 218, which has a resistance within a predetermined resistance range. In some embodiments, multiple ends of the conductor 211 are covered or terminated by different conductive materials 212, and in some embodiments, the conductive material 212 includes a metal, a metal compound, or a metal alloy.

[0290] Figure 2B is based on FIG. 5A to FIG. 5L, wherein a first group of multiple secondary polysilicon structures 210 are located in a space 230 between a first plurality of primary polysilicon structures 206A and a second group of multiple primary polysilicon structures 206B. In some embodiments, at least one of the first group of multiple secondary polysilicon structures 210 is removed and replaced by a composite conductor structure 221, which includes a barrier layer 219 (e.g., titanium nitride (TiN)) and a major portion of a conductive material 220, which in some embodiments includes tungsten (W) or a tungsten alloy. In some embodiments, these secondary polysilicon structures extend through at least two groups of the first and second pluralities of primary polysilicon structures 206, and the composite conductor structures 221 serve as power rails for the distribution of Vdd throughout the integrated circuit device.

[0291] Figure 2B Also included is a plan view of an integrated circuit device having a plurality of structures, the structures being based on the 4A to 4F and / or FIG. 5A to FIG. 5E In some embodiments, a portion of the dielectric material 114' adjacent to one or more of the plurality of secondary polysilicon structures 110 is removed to form an opening corresponding to the dielectric material 114' formed around the plurality of secondary polysilicon structures 110. Figure 4E The secondary openings 111 are then filled with a barrier layer 219 (e.g., titanium nitride (TiN)) and a major portion of a conductive material 220 (including tungsten (W) in some embodiments) to form a heat sink structure 222. In some embodiments, a portion of the secondary polysilicon structure 110 is removed to form a heat sink structure 222. Figure 4E The secondary opening 111 in the gate structure 222 is then filled with a barrier layer 219, such as titanium nitride (TiN), and a major portion of a conductive material 220, which in some embodiments comprises tungsten (W), to form a heat sink structure 222. In some embodiments, the composite conductor structure 221 is used as a power rail to which a Vdd voltage is applied during testing and operation of semiconductor devices fabricated according to the methods and structures disclosed above. In some embodiments, the power rail structure will include a structure that includes less work function metal than that used in the corresponding gate structure.

[0292] In some embodiments, the disclosed method is produced and used in combination with Figure 2BA semiconductor device configured in a consistent manner includes a substrate, an isolation structure on the substrate, and an active region on the substrate. In some embodiments, the active region includes a device including a source, a drain, a channel region, and a gate electrode, wherein the gate electrode includes at least one work function metal element. Multiple structures formed above the isolation structure can be configured to utilize available space between multiple active regions and provide desired functionality.

[0293] In some embodiments, the original secondary polysilicon structure remains in place during the remainder of the semiconductor device processing. In other embodiments, one or more of the plurality of secondary polysilicon structures are removed and replaced by one or more other materials, including, for example, oxides, metals, and polysilicon, and may be configured into any shape consistent with the available spacing and applicable design rules. If the spacing between adjacent plurality of active regions is greater than 1.5 times the contact polysilicon pitch (CPP) (sometimes referred to as the gate pitch), a secondary polysilicon structure may be inserted above the isolation structure. In some embodiments, the secondary polysilicon structure reduces the impact of loading effects during subsequent processing and thereby improves the uniformity of the plurality of primary polysilicon structures 106 and those functional elements that will be fabricated to replace the plurality of primary polysilicon structures.

[0294] In embodiments where the spacing between adjacent active regions is greater than 2 times the contact poly pitch (CPP) or gate pitch, at least two secondary polysilicon structures may be formed above the isolation structure. In some embodiments, at least one of the secondary polysilicon structures is removed and replaced with a conductor (having sidewalls or adhesion / boundary layers such as TiN), and the remainder of the opening is filled with another conductive material, such as tungsten, or another metal, or a metal with sufficient conductivity to provide a power rail line that does not present excessive resistance. In some embodiments, multiple conductors formed above a single isolation structure may be connected to multiple conductors formed above other isolation structures to form a power rail structure that can be utilized during back-end-of-line (BEOL) processing. In some embodiments, the secondary polysilicon structures 110 may be treated or their materials replaced using an ion implantation process to adjust the electrical impedance of the structure.

[0295] As in Figure 2BAs shown in , in some embodiments, the composite conductor structure 221 extends beyond the space 230 and extends through the second space 230'. In some embodiments, the second space 230' is defined between the third plurality of primary polysilicon structures 206A' and the fourth plurality of primary polysilicon structures 206B'. In some embodiments, the composite conductor structure 221 includes at least one of the plurality of secondary polysilicon structures 210 formed in the second space 230'. In some embodiments, the composite conductor structure 221 utilizes less than all of the plurality of secondary polysilicon structures 210 formed in the space above the isolation structure (not shown), and the remaining plurality of secondary polysilicon structures 210 can be used to construct other components. In some embodiments, one or more of the plurality of secondary polysilicon structures 210 can be surrounded by a composite conductor structure to form a heat dissipation structure 222, which includes the barrier layer 219 and a major portion of the conductive material 220. In such an embodiment, even without electrical connection to another feature, the heat dissipation structure, identified as heat dissipation structure 222, can function as a heat sink for adjacent circuitry during operation of the final semiconductor device. In some embodiments, one or more of the plurality of secondary polysilicon structures 210 can be removed and replaced with a composite conductor structure that does not retain the secondary polysilicon structure 210 therein.

[0296] Figure 2C is a plan view of an embodiment of an integrated circuit device, wherein a first group of multiple secondary polysilicon structures 210 are located in a spacer 230 between a first plurality of primary polysilicon structures 206A and a second group of multiple primary polysilicon structures 206B. In some embodiments, an inner one of the first group of multiple secondary polysilicon structures 210 is removed and replaced by a conductive material 216, which includes, for example, a metal, a metal compound, a metal alloy, and / or polysilicon. In some embodiments, the conductive element 216 is covered or terminated with a different conductive material to cover the conductive element, a resistor cap, which is selected from a material selected from a metal, a metal compound, or a metal alloy. As shown in Figure 2C As shown in FIG. 2 , in some embodiments, multiple semiconductor plates 214 are located between conductive element 216 and adjacent secondary polysilicon structures 210A and 210B to form a variable controllable resistor 223. In some embodiments, only a single semiconductor plate is used.

[0297] Figure 2D is a plan view of an embodiment of an integrated circuit device, the integrated circuit device includes a plurality of functional structures, the functional structures including Figure 2A and Figure 2C, resistor 218E, and resistor 223 are multiple resistors corresponding to the multiple resistor implementations discussed above. Figure 2D Resistors configured according to other embodiments are also included, including c-shaped resistor 218A, larger resistor 218B, smaller resistor 218C, and extended resistor 218D. In some embodiments, resistors 218A-218D include a main conductive element 216 formed of, for example, polysilicon and a resistor cap 212 formed using a different material than the conductive element 216. Figure 2D A controllable variable resistor 223 is also incorporated, the controllable variable resistor 223 comprising a conductive element 216, a semiconductor plate 214, and adjacent secondary polysilicon structures 210A, 210B on both sides of the conductive element 216, such as in the case of a combination of Figure 2C In some embodiments, one or more of the plurality of active regions 202' are vertically offset from the other plurality of active regions 202, and the plurality of secondary polysilicon structures 210' can be offset accordingly to provide the benefits of the plurality of secondary polysilicon structures 210' to the plurality of structures in the plurality of offset primary polysilicon structures 206'.

[0298] Figure 2E is a plan view of an embodiment of an integrated circuit device, the integrated circuit device including a plurality of functional structures including power rails 221 (V dd ) and heat dissipation structures 222 (including secondary polysilicon structure 210), heat dissipation structures 224 (excluding secondary polysilicon structure 210). In some embodiments, the conductive functional structure includes a barrier layer 219 formed of a first conductive material and a major portion of a second conductive material 220. In some embodiments, one or more of the multiple active regions 202′ are vertically offset from the other multiple active regions 202, and the associated secondary polysilicon structures 210′, 210″ are correspondingly offset or extended to provide the benefits of the multiple secondary polysilicon structures 210′, 210″ to the multiple primary polysilicon structures 206″ above the offset multiple active regions 202′.

[0299] Figure 3A is a cross-sectional view of an integrated circuit device during an operation used in the fabrication of the integrated circuit device according to some embodiments. Figure 3A The integrated circuit device 300A in the embodiment includes a semiconductor substrate 101 having a plurality of active regions 102 separated by isolation structures 104 using one or more dielectric materials.

[0300] exist Figure 3AThe integrated circuit device 300A includes a series of multiple primary polysilicon structures 106 above multiple active regions 102. In some embodiments, these primary polysilicon structures 106 have been etched out from a first polysilicon layer (not shown) by removing multiple portions of the first polysilicon layer that are not covered by a hard mask pattern 108. Figure 3A The integrated circuit device 300A in the embodiment also includes one or more secondary polysilicon structures 110 formed above the isolation structure 104. In some embodiments, both the primary polysilicon structure 106 and the secondary polysilicon structure 110 are formed from the first polysilicon layer during the etching operation. In some embodiments, the plurality of secondary polysilicon structures 110 are formed after the plurality of primary polysilicon structures 106 by growing or depositing polysilicon on a plurality of predetermined portions of the upper surface of the isolation structure 104 exposed by the photoresist pattern 112. Figure 3A In some embodiments, the size and spacing of the plurality of secondary polysilicon structures 110 are configured to match the size and spacing of the plurality of primary polysilicon structures.

[0301] exist Figure 3B The integrated circuit device 300B is according to some embodiments in Figure 3A A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3B The integrated circuit device 300B in FIG. 1 has been processed by a cleaning operation to remove the photoresist pattern 112, and by a deposition operation to fill the plurality of spaces left by the removal of the photoresist pattern 112 with an interlayer dielectric (ILD) layer (not shown). A planarization process is then applied to remove the hard mask pattern 108, as well as an upper portion of the first interlayer dielectric layer, an upper portion of the plurality of secondary polysilicon structures 110, and an upper portion of the plurality of primary polysilicon structures 106. After the planarization process is completed, the primary polysilicon structure 106′, the secondary polysilicon structure 110′, and the plurality of remaining portions of the remaining dielectric region 114 form a planar surface 115, which will be subjected to additional processing.

[0302] According to some embodiments, Figure 3C The integrated circuit device 300C is in Figure 3B A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3C The integrated circuit device 300C in FIG. 1 has been processed to remove the remaining portions of the plurality of primary polysilicon structures 106′ and the remaining portions of the plurality of secondary polysilicon structures 110′ using one or more etching operations, thereby forming a plurality of primary contact openings 120 in the remaining dielectric region 114. By removing both the plurality of primary polysilicon structures 106 and the plurality of secondary polysilicon structures 110 in the same operation, the primary contact openings 120 are formed according to the present invention. FIG. 3A to FIG. 3MEmbodiments of the method of avoid the need to protect the plurality of secondary polysilicon structures 110 during removal of the plurality of primary polysilicon structures 106. Thus, in this manner, the method according to some embodiments can avoid the need to protect the plurality of secondary polysilicon structures 110 during removal of the plurality of primary polysilicon structures 106. Figure 1E to Figure 1L The deposition, patterning, etching, and removal operations associated with the use of the contact etch stop layer 116 and the etch stop pattern 116 ′ are reflected in FIG.

[0303] exist Figure 3D The integrated circuit device 300D is according to some embodiments in Figure 3C A cross-sectional view of an integrated circuit device during operation after an operation of Figure 1D The integrated circuit device 300D in FIG. 1 has been processed using one or more deposition or growth operations to deposit multiple initial layers (or, in some embodiments, one initial layer) of conductive material 121 in the plurality of preliminary contact openings 120. The deposition of the multiple initial layers of conductive material 121 effectively reduces the size of the preliminary contact openings 120 and forms reduced contact openings 120′.

[0304] exist Figure 3E The integrated circuit device 300E in some embodiments is Figure 3D A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3E The integrated circuit device 300E has been processed using one or more deposition or growth operations to deposit multiple additional layers (or, in some embodiments, a single layer) of conductive material to fill the remaining space in the reduced contact opening 120′ and form a layered conductive structure 121′.

[0305] According to some embodiments, Figure 3F The integrated circuit device 300F is in Figure 3E A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3F The integrated circuit device 300F in FIG. 1 has been subjected to a planarization process to remove multiple upper portions of the layered conductive structure 121′, an etching process to remove a second upper portion of the multiple remaining portions of the layered conductive structure 121′, and a deposition or growth operation to deposit additional material on the remaining portions of the layered conductive structure 121′. In some embodiments utilizing a deposition process, a layer of deposited additional material (not shown) is subjected to a planarization process to remove the upper portion of the additional material and form a planarized surface 123, wherein the additional material forms an upper portion of the conductive composite structure 122.

[0306] exist Figure 3G The integrated circuit device 300G is according to some embodiments in Figure 3FA cross-sectional view of an integrated circuit device during operation after an operation of Figure 3G The integrated circuit device 300G in the embodiment has been subjected to a deposition or growth process to Figure 3F A contact etch stop layer 134 (CESL) is formed over the planarized surface 123 produced during the operation.

[0307] exist Figure 3H The integrated circuit device 300H is according to some embodiments in Figure 3G A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3H The integrated circuit device 300H in FIG. 1 has been subjected to a patterning process for forming an etch pattern 136 over the surface of the contact etch stop layer 134. The etch pattern 136 is then used as an etch mask during a subsequent etching process for removing exposed portions of the contact etch stop layer 134. Depending on the material and etching chemistry utilized, one or more etching processes may be utilized to remove exposed portions of the contact etch stop layer 134 to expose upper surfaces of the conductive composite structure 122 and remove the conductive composite structure 122 to form a plurality of openings 138 over the isolation structure 104.

[0308] exist Fig. 3I The integrated circuit device 300I in some embodiments is Figure 3H A cross-sectional view of an integrated circuit device during operation after an operation of Fig. 3I The integrated circuit device 300I in FIG. 1 has been subjected to a deposition or growth process for forming a conformal layer 140 on the side surfaces and the bottom surface of the opening 138 and on the exposed upper surfaces of the exposed portions of the remaining dielectric region 114 surrounding the opening 138. The formation of the conformal layer 140 reduces the size of the opening 138, resulting in a reduced opening 138′.

[0309] exist Figure 3J The integrated circuit device 300J in some embodiments is Fig. 3I A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3J The integrated circuit device 300J in FIG. 1 has been subjected to a deposition or growth process to form an insulating layer (not shown) that fills the reduced opening 138′ with an insulating material. The insulating layer is then subjected to a planarization process to remove the upper portion of the insulating material and leave the remaining portion of the insulating material 142 that fills the reduced opening and forms a flat surface 143 together with the upper surface of the conductive composite structure 122.

[0310] exist Figure 3K The integrated circuit device 300K is according to some embodiments in Figure 3JA cross-sectional view of an integrated circuit device during operation after an operation of Figure 3K The integrated circuit device 300K in FIG. 1 has been subjected to a deposition or growth process for forming an interlayer dielectric layer 144 on the flat surface 143 .

[0311] exist Figure 3L The integrated circuit device 300L is according to some embodiments in Figure 3K A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3L The integrated circuit device 300L in FIG. 1 has been subjected to a patterning process to form an etching mask (not shown) that exposes a plurality of predetermined regions of the interlayer dielectric layer 144 above the conductive composite structure 122 while protecting a plurality of structures formed above the isolation structure 104. The patterning process is followed by an etching process that uses an etching mask (not shown) to remove a plurality of predetermined regions of the interlayer dielectric layer 144 and form an interlayer dielectric pattern 144′ having a plurality of start contact openings 128. The etching process also removes an upper portion of the conductive composite structure 122 to form a modified version of the start gate structure 122′.

[0312] exist Figure 3M The integrated circuit device 300M is according to some embodiments in Figure 3L A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3M The integrated circuit device 300M in FIG. 1 has been processed, using growth and / or deposition operations and planarization operations, to form a barrier metal layer 130 on the sidewalls and bottom surface of the starting contact opening 128 and the final gate structure 122″. The barrier metal layer 130 reduces the size of the starting contact opening 128 by approximately two times the thickness of the barrier metal layer to form a secondary contact opening 128′ having a reduced diameter relative to the starting contact opening 128.

[0313] exist Figure 3N The integrated circuit device 300N is according to some embodiments in Figure 3M A cross-sectional view of an integrated circuit device during operation after an operation of Figure 3N The integrated circuit device 300N in has been processed using growth and / or deposition operations and planarization operations to fill the secondary contact opening 128' with a conductive material 132. In some embodiments, the first and second conductive materials are selected from the group consisting of metals, metal alloys, and / or metal silicides.

[0314] In some embodiments, the conductive material will include various combinations of materials to promote device performance and / or device life, including, for example, barrier layers, liner layers, wetting layers, adhesion layers, metal fill layers, and / or one or more other suitable layers. In some embodiments, the conductive material will be selected from Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, and other conductive materials suitable for use in combination with polysilicon, as well as combinations and alloys thereof.

[0315] exist Figure 4A The integrated circuit device 400A in FIG. 4 includes a series of multiple preliminary polysilicon structures 106 above the active region, which in some embodiments have been etched out of a first polysilicon layer (not shown) by removing multiple portions of the first polysilicon layer not covered by the hard mask pattern 108. Figure 4A The integrated circuit device 400A in the embodiment also includes a secondary polysilicon structure 110 formed over the isolation structure 104. In some embodiments, both the primary polysilicon structure 106 and the secondary polysilicon structure 110 are formed from the first polysilicon layer during an etching operation. In some embodiments, the secondary polysilicon structure 110 is formed after the plurality of primary polysilicon structures 106 by growing or depositing polysilicon over a plurality of predetermined portions of the upper surface of the isolation structure 104 exposed by the photoresist pattern 112.

[0316] exist Figure 4B The integrated circuit device 400B is in accordance with some embodiments. Figure 4A A cross-sectional view of an integrated circuit device during operation after operation. Figure 4B The integrated circuit device 400B in FIG. 4 has been processed via a cleaning operation using a chemical solution (wet), plasma (dry), and / or ash (dry) process to remove the photoresist pattern 112 from between the plurality of primary polysilicon structures 106 and the secondary polysilicon structures 110. The photoresist removal operation is followed by a deposition operation to fill the plurality of spaces left by the removal of the photoresist pattern 112 with an interlayer dielectric (ILD) layer (not shown). A planarization process is then applied to remove the hard mask pattern 108 and the plurality of upper portions of the first interlayer dielectric layer (not shown) to leave the plurality of remaining dielectric regions 114 separating the primary polysilicon structures and the secondary polysilicon structures, the plurality of secondary polysilicon structures 110, and the plurality of primary polysilicon structures 106 to form a flat surface 115.

[0317] exist Figure 4C The integrated circuit device 400C is according to some embodiments in Figure 4BA cross-sectional view of an integrated circuit device during operation after an operation of Figure 4C The integrated circuit device 400C in FIG. 1 has been processed to apply a contact etch stop layer 116 (CESL) to the planar surface 115 using a deposition operation.

[0318] exist Figure 4D The integrated circuit device 400D is in accordance with some embodiments. Figure 4C A cross-sectional view of an integrated circuit device during operation after an operation of Figure 4D The integrated circuit device 400D in FIG. 4 has been processed using both a patterning operation and an etching operation. The patterning operation exposes and develops the photoresist layer (not shown), and the plurality of remaining portions of the photoresist layer form a photoresist pattern 118, and the photoresist pattern 118 is used as an etching mask (not shown) for removing the plurality of exposed portions of the contact etch stop layer 116 and leaving the remaining portion of the contact etch stop layer to form an etching stop pattern 116′ to protect the plurality of predetermined portions of the secondary polysilicon structure 110, while simultaneously exposing the plurality of upper surfaces of the plurality of primary polysilicon structures 106 and the upper surface of the remaining dielectric region 114 surrounding the plurality of primary polysilicon structures 106.

[0319] exist Figure 4E The integrated circuit device 400E is according to some embodiments in Figure 4D A cross-sectional view of an integrated circuit device during operation after an operation of Figure 4E The integrated circuit device 400E in FIG. 4 has been processed to remove the photoresist pattern 118 using a cleaning operation and to remove portions of the primary polysilicon structure 106 and the secondary polysilicon structure 110 using an etching operation, thereby forming a series of a plurality of primary contact openings 120 corresponding to a plurality of locations of the primary polysilicon structure 106, and a series of a plurality of secondary openings 111 above the isolation structure 104 corresponding to a plurality of exposed portions of the secondary polysilicon structure 110. In some embodiments, the plurality of protected portions of the plurality of secondary polysilicon structures 110 form a plurality of secondary polysilicon structures 110′ having a width that is a predetermined fraction of the original width of the plurality of secondary polysilicon structures 110.

[0320] In some embodiments, a larger secondary polysilicon structure 110 is formed, and then the larger secondary polysilicon structure 110 is patterned and etched to form a plurality of smaller secondary polysilicon structures 110′, thereby constructing a corresponding plurality of secondary openings 111 adjacent to the plurality of secondary polysilicon structures 110′. In some embodiments, these additional secondary openings 111 provide a recess (or a plurality of recesses) within which other materials (e.g., metals and metal alloys) are deposited. In some embodiments, the material deposited or formed in the secondary openings 111 forms a heat sink, or forms other structures (in conjunction with the secondary polysilicon structure 110′). Further, the formation of the plurality of secondary openings 111 by etching the larger secondary polysilicon structure 110 does not require the removal of the dielectric region 114 adjacent to the secondary polysilicon structure 110, as in, for example Figure 1M By avoiding the need for additional patterning and etching operations for removing the dielectric region 114, the manufacturing method according to some embodiments is simplified.

[0321] exist Figure 4F The integrated circuit device 400F is in accordance with some embodiments. Figure 4E A cross-sectional view of an integrated circuit device during operation after an operation of Figure 4F The integrated circuit device 400F in FIG. 4 has been processed to fill the plurality of primary contact openings 120 and the plurality of secondary openings 111 with one or more conductive materials using a deposition operation, a growth operation, and / or a planarization operation. In some embodiments, the conductive material is a conductive composite structure 122 including a plurality of conductive materials. In some embodiments, the conductive composite structure 122 includes a work function metal element, and the work function metal element includes TiN, TiAl, W, Ti, La, Hf, TaN, Al, or a combination thereof. In some embodiments, the plurality of secondary openings 111 are primarily filled with the conductive material 113 to form a conductive structure that does not exhibit a multi-layer (layered) structure found in the conductive composite structure 122 formed in the primary contact openings 120 (in some embodiments, the conductive material 113 forms an upper portion of the conductive composite structure 122).

[0322] Figure 5A is a cross-sectional view of an integrated circuit device 500A during an operation used in the fabrication of an integrated circuit device according to some embodiments. The integrated circuit device 500A includes a semiconductor substrate 101 having a plurality of active regions 102 separated by isolation structures 104, the isolation structures 104 utilizing one or more formed dielectric materials. In some embodiments, the semiconductor substrate 101 is patterned and etched to form a recessed region (not shown), and a dielectric material is deposited into the recessed region to form the isolation structure 104.

[0323] The integrated circuit device 500A includes a series of a plurality of primary polysilicon structures 106 above the plurality of active regions 102, which in some embodiments have been etched from a first polysilicon layer (not shown) by removing portions of the first polysilicon layer not covered by a hard mask pattern 108. The integrated circuit device 500A also includes one or more secondary polysilicon structures 110 formed above the isolation structures 104. In some embodiments, both the primary polysilicon structures 106 and the secondary polysilicon structures 110 are formed from the first polysilicon layer during an etching operation. In some embodiments, the secondary polysilicon structures 110 are formed after the plurality of primary polysilicon structures 106 by growing or depositing polysilicon on predetermined portions of the upper surfaces of the isolation structures 104 exposed by the photoresist patterns 112.

[0324] exist Figure 5B The integrated circuit device 500B is according to some embodiments in Figure 5A 1. The integrated circuit device 500B is a cross-sectional view of an integrated circuit device in operation after the operation of FIG. The integrated circuit device 500B has been processed by a cleaning operation to remove the photoresist pattern 112 and by a deposition operation to fill the plurality of spaces left by the removal of the photoresist pattern 112 with an interlayer dielectric (ILD) layer (not shown). A planarization process is then applied to remove the hard mask pattern 108 and the plurality of upper portions of the interlayer dielectric layer to leave the plurality of remaining dielectric regions 114, the plurality of secondary polysilicon structures 110, and the plurality of primary polysilicon structures 106, thereby forming a flat surface 115.

[0325] exist Figure 5C The integrated circuit device 500C is according to some embodiments Figure 5B The integrated circuit device 500C has been processed to apply a contact etch stop layer 116 (CESL) to the planar surface 115 using a deposition operation.

[0326] exist Figure 5D The integrated circuit device 500D is according to some embodiments in Figure 5C1. A cross-sectional view of an integrated circuit device during operation after an operation of . The integrated circuit device 500D has been processed using both a patterning operation and an etching operation. The patterning operation exposes and develops a photoresist layer (not shown), and multiple remaining portions of the photoresist layer form a photoresist pattern 118. The photoresist pattern 118 is then used as an etching mask to remove multiple exposed portions of the contact etch stop layer 116 and leave remaining portions of the contact etch stop layer to form an etch stop pattern 116′. In some embodiments, the etch stop pattern 116′ protects some of the multiple secondary polysilicon structures 110A, 110B while simultaneously exposing the upper surfaces of the multiple primary polysilicon structures 106, the upper surfaces of some of the multiple secondary polysilicon structures 110R, and the upper surfaces of the multiple remaining dielectric regions 114 surrounding the multiple primary polysilicon structures 106.

[0327] According to, for example, FIG. 5A to FIG. 5E In the method of some embodiments illustrated in , a functional component is arranged above the isolation structure 104, thereby preserving valuable active region 102 surface area for the arrangement of functional circuits used by the final integrated circuit device when in operation. In addition to being located above the isolation structure 104, the functional component is also generally parallel to the specific functional circuit, thereby limiting the height of the final integrated circuit device while simultaneously providing some additional functionality. Some embodiments of the functional component will improve the operation and / or life of the resulting device by reducing resistive heating in adjacent circuits during operation of the final integrated circuit device.

[0328] exist Figure 5E The integrated circuit device 500E is according to some embodiments in Figure 5D 1. The integrated circuit device 500E is a cross-sectional view of an integrated circuit device during operation after an operation of . The integrated circuit device 500E has been processed using a cleaning operation to remove the photoresist pattern 118 and using an etching operation to remove the plurality of primary polysilicon structures 106 and some of the plurality of secondary polysilicon structures 110B to form a series of a plurality of primary contact openings 120 corresponding to a plurality of locations of the plurality of primary polysilicon structures 106 and the plurality of exposed secondary polysilicon structures 110B. The openings (not shown) resulting from the removal of the plurality of exposed secondary polysilicon structures 110B have been processed using a deposition or growth process to replace the plurality of exposed secondary polysilicon structures 110B with conductive elements 145.

[0329] In some embodiments, one of the plurality of secondary polysilicon structures 110R is selectively replaced with a conductive structure, a coupled board or a control board (see Figure 2C) and the retained multiple secondary polysilicon structures 110A, 110B result in the formation of a controllable variable resistor above the isolation structure 104.

[0330] exist Fig. 5F The integrated circuit device 500F is according to some embodiments in Figure 5E The integrated circuit device 500F has been processed to fill the plurality of primary contact openings 120 with a conductive material, or in some embodiments, to fill the primary contact openings 120 with a layered structure including a series of different materials, to form a conductive composite structure 122, using a series of growth and / or deposition processes.

[0331] exist Figure 5G The integrated circuit device 500G is according to some embodiments in Fig. 5F The integrated circuit device 500G has been processed using a planarization operation to remove upper portions of the conductive composite structure 122, upper portions of the etch stop pattern 116′, upper portions of the protected plurality of secondary polysilicon structures 110A, upper portions of the conductive element 145, and upper portions of the plurality of remaining dielectric regions 114 to form a planar surface 125 for additional processing.

[0332] exist Figure 5H The integrated circuit device 500H is according to some embodiments in Figure 5G A cross-sectional view of an integrated circuit device during operation after an operation of Figure 5H The integrated circuit device 500H in FIG. 1 has been subjected to a deposition or growth process for forming an interlayer dielectric layer 144 on the flat surface 143 .

[0333] exist Fig.5I The integrated circuit device 500I is according to some embodiments in Figure 5H The integrated circuit device 500I has been subjected to a patterning process to form an etch mask (not shown) that exposes a plurality of predetermined regions of the interlayer dielectric layer 144 adjacent to the conductive elements 145 above the remaining dielectric region 114 while protecting a plurality of structures formed above the active region 102. The patterning process is followed by an etching process that uses the etch mask (not shown) to remove a plurality of predetermined regions of the interlayer dielectric layer 144 and form an interlayer dielectric pattern 144′ having a plurality of openings 150.

[0334] exist Figure 5J The integrated circuit device 500J is according to some embodiments in Fig.5I 500J is a cross-sectional view of an integrated circuit device during operation after an operation of . The integrated circuit device 500J has been subjected to a patterning process to form an etching mask (not shown) that exposes multiple predetermined areas of the interlayer dielectric pattern 144′ above the conductive composite structure 122 and the conductive element 145. The patterning process is followed by an etching process that uses the etching mask (not shown) to remove multiple predetermined areas of the interlayer dielectric pattern 144′ and form a modified interlayer dielectric pattern 144″ having multiple openings 150 and 128. In some embodiments, a single pattern and etching is used to open the multiple openings 150 and 128.

[0335] exist Figure 5K The integrated circuit device 500K is according to some embodiments in Figure 5J A cross-sectional view of an integrated circuit device during operation after an operation of . According to some embodiments, the integrated circuit device 500K has been processed using growth and / or deposition operations and planarization operations to form a barrier metal layer 130 on the sidewalls and bottom surfaces of multiple starting contact openings 128 (leading to the final gate structure 122″) and multiple openings 150 (leading to multiple secondary polysilicon structures 110A adjacent to the conductive element 145). The barrier metal layer 130 reduces the size of the starting contact opening 128 by approximately two times the thickness of the barrier metal layer to form a secondary contact opening 128′ having a reduced diameter relative to the starting contact opening 128. Similarly, in some embodiments, the barrier metal layer 130 reduces the size of the starting contact opening 150 by approximately two times the thickness of the barrier metal layer to form a secondary contact opening 150′ having a reduced diameter relative to the starting contact opening 150.

[0336] exist Figure 5L The integrated circuit device 500L is according to some embodiments in Figure 5K 1. A cross-sectional view of an integrated circuit device during operation after an operation of. According to some embodiments, the integrated circuit device 500L has been processed to fill the plurality of secondary contact openings 128' with a conductive material 132 using a growth and / or deposition operation and a planarization operation. In some embodiments, the first and second conductive materials are selected from the group consisting of metals, metal alloys, and / or metal silicides.

[0337] Fig. 6A FIG. 6 is a flow chart of a manufacturing process 600A for producing an integrated circuit semiconductor device according to some embodiments. In some embodiments, the manufacturing process 600A is used to manufacture an integrated circuit semiconductor device according to Figure 1A to Figure 1P The integrated circuit device will be introduced below. Figure 1A to Figure 1P References to the multiple structures identified above are associated to aid understanding Fig. 6A 600A is not intended to limit the application of the manufacturing process 600A.

[0338] according to Fig. 6A Various embodiments include operation 602a, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end-of-line (FEOL) operations are completed to fabricate, for example, isolation structures 104, such as shallow trench isolation (STI) structures. In some embodiments, an etch-back and / or chemical mechanical polishing process is used to planarize the final layer or layers of material applied to the substrate surface to remove upper portions of at least some of the material layers present on semiconductor substrate 101 to prepare the surface for subsequent processing.

[0339] according to Fig. 6A The embodiment includes operation 604a, during which a substrate (e.g., semiconductor substrate 101) is prepared and certain front-end process operations are completed to manufacture, for example, a plurality of active regions 102, and then certain functional elements are formed over the plurality of active regions 102 to provide the desired functionality and performance of the resulting semiconductor device. In some embodiments, the order of operations 602a and 604a is reversed.

[0340] according to Fig. 6A Various embodiments include operation 606a during which a plurality of preliminary polysilicon structures 106 are formed over a plurality of active regions 102 of a substrate to establish spacing and dimensions of functional elements that will subsequently replace the plurality of preliminary polysilicon structures.

[0341] according to Fig. 6A Various embodiments of the present invention include operation 608a, during which a plurality of secondary polysilicon structures 110 are formed over the isolation structure 104 of the substrate to at least partially establish the spacing and size of functional elements that will subsequently replace the plurality of secondary polysilicon structures. In some embodiments, the order of operations 606a and 608a is reversed, while in other embodiments, operations 606a and 608a are performed simultaneously.

[0342] according to Fig. 6A Various embodiments of the present invention include operation 610a, during which a contact etch stop layer 116 is formed over the device surface and then patterned and etched to form an etch stop pattern 116' that selectively exposes or protects certain primary polysilicon structures 106 and / or secondary polysilicon structures 110. However, in operation 610a, the etch stop pattern 116' is used to protect the plurality of secondary polysilicon structures 110 formed over the isolation structure 104 of the substrate.

[0343] according to Fig. 6AEmbodiments of the present invention include operation 612a, during which the etch stop pattern 116' is used as an etch mask to expose the plurality of preliminary polysilicon structures 106 to the etching process. Removing polysilicon from the plurality of preliminary polysilicon structures 106 forms a corresponding plurality of series of preliminary contact openings 120 above the active region 102.

[0344] according to Fig. 6A Multiple embodiments include operations 614a and 616a, during which multiple primary contact openings 120 are filled with a plurality of conductive layers, which in some embodiments include a series of multiple conductive layers 121 above the active region 102, and are planarized to form a series of multiple conductive plugs or multiple starting gate structures 121', such as gate structures, and prepare a flat surface 125 for additional processing.

[0345] according to Fig. 6A Multiple embodiments include operation 618a, during which an interlayer dielectric layer 126 is formed to separate and insulate the conductive structure from a higher level metallization (not shown), and the plurality of primary contact openings 120 are filled with a plurality of conductive composite layers 122. In some embodiments, the conductive composite layers 122 include gate structures for a plurality of transistors arranged above the active region 102.

[0346] according to Fig. 6A The various embodiments of the present invention include, in some embodiments, an optional operation 620a, during which a contact pattern is formed on the interlayer dielectric layer 126. Then, multiple exposed portions of the interlayer dielectric layer 126 are etched to form multiple contact openings 128, which expose (and in some embodiments, partially remove) portions of the multiple starting gate structures 122' and form multiple final gate structures 122".

[0347] according to Fig. 6A Various embodiments include operation 622a, during which the plurality of contact openings 128 are filled with one or more conductive materials to provide electrical contacts between the final gate structure 122" and a subsequent metal layer (not shown) subsequently formed on the interlayer dielectric pattern 126'.

[0348] according to Fig. 6AMultiple embodiments of the present invention include, in some embodiments, an optional operation 624a, during which all subsequent processing operations are performed to test, package, and, in some embodiments, retest the semiconductor device to obtain a completed semiconductor integrated circuit device for sale to a customer.

[0349] Figure 6B FIG. 6 is a flow chart of a manufacturing process 600B for producing an integrated circuit semiconductor device according to some embodiments. In some embodiments, the manufacturing process 600B is used to manufacture an integrated circuit semiconductor device according to FIG. 3A to FIG. 3N The integrated circuit device will be introduced below. FIG. 3A to FIG. 3N References to the multiple structures identified above are associated to aid understanding Figure 6B 600B is not intended to limit the application of the manufacturing process 600B.

[0350] according to Figure 6B Various embodiments include operation 602b, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end process operations are completed to fabricate, for example, isolation structures 104, such as shallow trench isolation (STI) structures. In some embodiments, an etch-back and / or chemical mechanical polishing process is used to planarize the final layer or layers of material applied to the surface of the substrate to remove upper portions of at least some of the material layers present on semiconductor substrate 101 to prepare the surface for subsequent processing.

[0351] according to Figure 6B Many embodiments of the present invention include operation 604b, during which a substrate (e.g., semiconductor substrate 101) is prepared and certain front-end process operations are completed to manufacture, for example, a plurality of active regions 102, and then certain functional elements are formed over the plurality of active regions 102 to provide the desired functionality and performance of the resulting semiconductor device. In some embodiments, the order of operations 602b and 604b is reversed.

[0352] according to Figure 6B Various embodiments include operation 606b during which a plurality of preliminary polysilicon structures 106 are formed over the active region 102 of the substrate to establish spacing and dimensions of functional elements that will subsequently replace the plurality of preliminary polysilicon structures.

[0353] according to Figure 6BVarious embodiments of the present invention include operation 608b, during which a plurality of secondary polysilicon structures 110 are formed over the isolation structure 104 of the substrate to at least partially establish the spacing and size of the functional elements that will subsequently replace the plurality of secondary polysilicon structures. In some embodiments, the order of operations 606a and 608a is reversed, while in other embodiments, operations 606a and 608a are performed simultaneously.

[0354] according to Figure 6B Various embodiments include operation 610b during which both the plurality of primary polysilicon structures 106 and the plurality of secondary polysilicon structures 110 are removed using one or more wet and / or dry etching processes.

[0355] according to Figure 6B Various embodiments include operation 612b during which each of the plurality of openings is filled with a conductive composite structure 122 (eg, a gate electrode structure).

[0356] according to Figure 6B Embodiments of the present invention include operation 614b during which a conductive layer deposited on the device surface is planarized to remove upper portions of the conductive material and leave each of the plurality of openings filled with layered conductive structures 121', such as gate electrode structures.

[0357] according to Figure 6B Various embodiments include operation 616 b , during which an etch stop pattern 116 ′ is formed to protect a plurality of layered conductive structures 121 ′ formed over the active region 102 .

[0358] according to Figure 6B Various embodiments include operation 618 b , during which the exposed layered conductive structure 121 ′ formed over the isolation structure 104 is removed to form a plurality of openings 138 .

[0359] according to Figure 6B Various embodiments include operation 620 b , during which the opening 138 is filled with a dielectric material 142 .

[0360] according to Figure 6B Various embodiments include operation 622b during which an interlayer dielectric 144 layer is formed to separate and insulate the conductive structure from higher level metallization (not shown).

[0361] according to Figure 6BThe various embodiments include an optional operation 624b in some embodiments, during which a contact pattern is formed on the interlayer dielectric layer 144. Then, the plurality of exposed portions of the interlayer dielectric layer 144 are etched to form a plurality of contact openings 128 that expose (and in some embodiments, partially remove) a portion of the plurality of start gate structures 122′.

[0362] according to Figure 6B Various embodiments include operation 626b, during which the plurality of contact openings 128 are filled with one or more conductive materials to provide electrical contacts between the final gate structure 122" and a subsequent metal layer (not shown) subsequently formed on the interlayer dielectric pattern 144'.

[0363] according to Figure 6B Multiple embodiments of the present invention include, in some embodiments, an optional operation 628b, during which all subsequent processing operations are performed to test, package, and, in some embodiments, retest the semiconductor device to obtain a completed semiconductor integrated circuit device for sale to a customer.

[0364] Figure 6C is a flow chart of a manufacturing process 600C for producing an integrated circuit semiconductor device according to some embodiments. In some embodiments, the manufacturing process 600C is used to manufacture a semiconductor device according to 4A to 4F The integrated circuit device will be introduced below. 4A to 4F References to the multiple structures identified above are associated to aid understanding Figure 6C Flowchart is not intended to limit the application of manufacturing process 600C.

[0365] according to Figure 6C Various embodiments include operation 602c, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end process operations are completed to fabricate, for example, isolation structures 104, such as shallow trench isolation (STI) structures. In some embodiments, an etch-back and / or chemical mechanical polishing process is used to planarize the final layer or layers of material applied to the substrate surface to remove upper portions of at least some of the material layers present on semiconductor substrate 101 to prepare the surface for subsequent processing.

[0366] according to Figure 6CVarious embodiments of the present invention include operation 604c, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end process operations are performed to produce, for example, a plurality of active regions 102, and then certain functional elements are formed over the plurality of active regions 102 to provide the desired functionality and performance of the resulting semiconductor device. In some embodiments, the order of operations 602c and 604c is reversed.

[0367] according to Figure 6C Various embodiments include an operation 606c during which a plurality of preliminary polysilicon structures 106 are formed over the active region 102 of the substrate to establish spacing and dimensions of functional elements that will subsequently replace the plurality of preliminary polysilicon structures.

[0368] according to Figure 6C Various embodiments of the present invention include operation 608c, during which a single secondary polysilicon structure 110 is formed over the isolation structure 104 of the substrate to at least partially establish the spacing and size of the functional elements that will subsequently replace the secondary polysilicon structure. In some embodiments, the order of operations 606c and 608c is reversed, while in other embodiments, the operations of operations 606c and 608c are performed simultaneously.

[0369] according to Figure 6C Various embodiments include operation 610 c during which an etch stop pattern 116 ′ is formed to protect portions of the single secondary polysilicon structure 110 formed over the isolation structure 104 .

[0370] according to Figure 6C Various embodiments include operation 612 c , during which the plurality of secondary polysilicon structures 110 are etched to form a plurality of secondary polysilicon structures 110 ′ surrounded by a plurality of secondary openings 111 .

[0371] according to Figure 6C Various embodiments include operation 614 c , during which the plurality of secondary openings 111 are filled with a conductive material 113 .

[0372] according to Figure 6C Multiple embodiments of the present invention include, in some embodiments, an optional operation 616c, during which all subsequent processing operations are performed to test, package, and, in some embodiments, retest the semiconductor device to obtain a completed semiconductor integrated circuit device for sale to a customer.

[0373] Fig.6DFIG. 6 is a flow chart of a manufacturing process 600D for producing an integrated circuit semiconductor device according to some embodiments. In some embodiments, the manufacturing process 600D is used to manufacture an integrated circuit semiconductor device according to FIG. 5A to FIG. 5L The integrated circuit device will be introduced below. FIG. 5A to FIG. 5L References to the multiple structures identified above are associated to aid understanding Fig.6D Flowchart is not intended to limit the application of manufacturing process 600D.

[0374] according to Fig.6D Various embodiments include operation 602d, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end process operations are performed to fabricate, for example, isolation structures 104, such as shallow trench isolation (STI) structures. In some embodiments, an etch-back and / or chemical mechanical polishing process is used to planarize the final layer or layers of material applied to the substrate surface to remove upper portions of at least some of the material layers present on semiconductor substrate 101 to prepare the surface for subsequent processing.

[0375] according to Fig.6D Various embodiments include operation 604d, during which a substrate, such as semiconductor substrate 101, is prepared and certain front-end process operations are performed to produce, for example, a plurality of active regions 102, and then certain functional elements are formed over the plurality of active regions 102 to provide the desired functionality and performance of the resulting semiconductor device. In some embodiments, the order of operations 602d and 604d is reversed.

[0376] according to Fig.6D Various embodiments include an operation 606d during which a plurality of preliminary polysilicon structures 106 are formed over the active region 102 of the substrate to establish spacing and dimensions of functional elements that will subsequently replace the plurality of preliminary polysilicon structures.

[0377] according to Fig.6D Various embodiments of the present invention include operation 608d, during which a plurality of secondary polysilicon structures 110 are formed over the isolation structure 104 of the substrate to at least partially establish the spacing and size of the functional elements that will subsequently replace the plurality of secondary polysilicon structures. In some embodiments, the order of operations 606d and 608d is reversed, while in other embodiments, operations 606d and 608d are performed simultaneously.

[0378] according to Fig.6D Various embodiments include operation 610d during which an etch stop pattern 116' is formed to protect a group of the plurality of secondary polysilicon structures 110 during a subsequent etch.

[0379] according to Fig.6D Various embodiments include operation 612d during which the plurality of exposed secondary polysilicon structures 110 are removed to form one or more openings.

[0380] according to Fig.6D Various embodiments include operation 614d during which each of the plurality of openings is filled with one or more conductive materials to form conductive elements 145.

[0381] according to Fig.6D Various embodiments include operation 616 d during which the plurality of preliminary polysilicon structures 106 are removed to form a plurality of preliminary contact openings 120 .

[0382] according to Fig.6D Multiple embodiments include operation 618d, during which a conductive material 121 is deposited on the device surface to fill the primary contact opening 120, and then planarized to remove an upper portion of the conductive material and leave each of the multiple openings filled with a plurality of conductive composite structures 122 (e.g., a starting gate electrode structure 121′).

[0383] according to Fig.6D Various embodiments include operation 620d during which an interlayer dielectric 144 layer is formed to separate and insulate the conductive structure from higher level metallization (not shown).

[0384] according to Fig.6D In some embodiments, an optional operation 622d is included during which a contact pattern (not shown) is formed on the interlayer dielectric layer 144. The exposed portions of the interlayer dielectric layer 144 are then etched to form a first set of openings 150 on opposite sides of the conductive element 145.

[0385] according to Fig.6D In some embodiments, an optional operation 624d is included, during which a second contact pattern (not shown) is formed on the interlayer dielectric pattern 144' formed by the first contact etch. Then, multiple exposed portions of the interlayer dielectric pattern 144' layer are etched to form a second group of multiple contact openings 128.

[0386] according to Fig.6DVarious embodiments include operation 626d, during which the first and second contact openings 150, 128 are filled with one or more conductive materials to provide an electrical contact between the final gate structure 122", the conductive element 145, and the secondary polysilicon structures 110A, 110B adjacent to the conductive element 145, and a subsequent metal layer (not shown) subsequently formed on the interlayer dielectric pattern 144".

[0387] according to Fig.6D Multiple embodiments of the present invention include, in some embodiments, an optional operation 628d, during which all subsequent processing operations are performed to test, package, and, in some embodiments, retest the semiconductor device to obtain a completed semiconductor integrated circuit device for sale to a customer.

[0388] As reflected in the above discussion, the manner and order of forming, removing, replacing, and / or maintaining multiple primary polysilicon structures and secondary polysilicon structures can be applicable to most embodiments of the method of manufacturing a semiconductor device. In addition, the multiple operations at each stage of the process are at least to some extent independent of the previous multiple operations. Fig. 6E and Fig. 6F is a flow chart of various embodiments of a fabrication process 600E for fabricating an integrated circuit device using a secondary polysilicon structure 110 , 110 ′ over one or more isolation structures 104 .

[0389] As in Fig. 6E As reflected in FIG. 6 , the initial operation 602e involves generally forming an isolation structure 104 and an active region 102 on a semiconductor substrate 101. The next step in the fabrication process includes forming a plurality of primary polysilicon structures 106 and a plurality of secondary polysilicon structures 110, 110′ according to any one of operations 604e1 / 606e1, 604e2, 604e3 / 606e3, or 604e4 / 606e4, depending on the operation selected from the group of operations 650.

[0390] Once the plurality of primary polysilicon structures 106 and the plurality of secondary polysilicon structures 110 , 110 ′ are formed, the polysilicon structures are then maintained, operation 608e1 , selectively removed, operations 608e2 , 608e4 , or completely removed, operation 608e3 , depending on the operation selected from the group of operations 652 .

[0391] In various embodiments where some or all of the primary polysilicon structure 106 and the plurality of secondary polysilicon structures 110, 110' are removed, one or more openings are formed on the surface of the integrated circuit device. These openings are then filled with a dielectric material, operation 610e1, a conductive material / structure, operation 610e2, or a metal or metal gate structure, operation 610e3. In some embodiments, the metal / metal gate material is then removed to form a plurality of secondary openings, operation 612e1, which are selectively or completely removed (bridged) according to any of the operations in operation group 654. Fig. 6E and Fig. 6F ).

[0392] As in Fig. 6F As reflected in the continuation of the manufacturing process 600E in FIG. 6 , in some embodiments, once a plurality of openings have been formed on the surface of the integrated circuit device, the openings are then filled with one or more materials to form a plurality of functional elements located above the isolation structure 104 and thereby increase the device density without increasing the device height. In some embodiments, according to any of the operations in the group of operations 656, the plurality of openings formed by removing (or retaining) the plurality of secondary polysilicon structures 110, 110' are retained, operation 614e1, converted to form a resistor or a controllably variable resistor, operation 614e2, a heat sink, operations 614e1 / 616e1, 614e3, and / or a power rail, operation 614e4.

[0393] In some embodiments, the contemplated manufacturing method ends with optional operation 618e1, and in some embodiments, the semiconductor device is tested, packaged, and in some embodiments, retested during all subsequent process operations to obtain a completed semiconductor integrated circuit device for sale to a customer.

[0394] Figure 7 is a block diagram of an electronic process control system 700 (EPC system) according to some embodiments. Methods for generating cell layouts corresponding to some embodiments of field effect transistor device structures detailed above, particularly with respect to the addition and placement of electrical contacts, thermal contacts, active metal patterns, dummy metal patterns, and other heat dissipation structures, according to some embodiments of such a system, may be implemented, for example, using the electronic process control system 700.

[0395] In some embodiments, the electronic process control system 700 is a general purpose computing device including a hardware processor 702 and a non-transitory computer readable storage medium 704. The computer readable storage medium 704 is encoded with (i.e., stores) computer program code 706, i.e., a set of multiple computer executable instructions. The execution of the computer program code 706 by the hardware processor 702 represents (at least in part) an electronic process control tool that implements, for example, a portion or all of one or more (hereinafter referred to as processes and / or methods) described herein.

[0396] The hardware processor 702 is electrically coupled to the computer-readable storage medium 704 via a bus 718. The hardware processor 702 is also electrically coupled to an input / output (I / O) interface 712 via the bus 718. A network interface 714 is also electrically connected to the hardware processor 702 via the bus 718. The network interface 714 is connected to a network 716 so that the hardware processor 702 and the computer-readable storage medium 704 can be connected to external components via the network 716. The hardware processor 702 is configured to execute computer program code 706 encoded in the computer-readable storage medium 704 so that the electronic process control system 700 can be used to perform a portion or all of the described processes and / or methods. In one or more embodiments, the hardware processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0397] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk read-only memory (CD ROM), a compact disk read / write (CD R / W,) and / or a digital video disk (DVD).

[0398] In one or more embodiments, the computer-readable storage medium 704 stores computer program code 706 configured to enable the electronic process control system 700 (where such execution represents (at least in part) an electronic process control tool) to perform a portion or all of the described processes and / or methods. In one or more embodiments, the computer-readable storage medium 704 also stores information that facilitates the execution of a portion or all of the described processes and / or methods. In one or more embodiments, the computer-readable storage medium 704 stores process control data 708, which in some embodiments includes control algorithms, process variables and constants, target ranges, set points, programmed control data, and program code for implementing statistical process control (SPC), and / or model predictive control (MPC) based control of various processes.

[0399] The electronic process control system 700 includes an input / output interface 712. The input / output interface 712 is coupled to external circuits. In one or more embodiments, the input / output interface 712 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for communicating messages and commands to the hardware processor 702.

[0400] The electronic process control system 700 also includes a network interface 714 coupled to the hardware processor 702. The network interface 714 allows the electronic process control system 700 to communicate with a network 716 to which one or more other computer systems are connected. The network interface 714 includes a wireless network interface, such as Bluetooth, Wireless Fidelity (WIFI), World Wide Web of Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA), or includes a wired network interface, such as Ethernet (ETHERNET), Universal Serial Bus (USB), or High-Performance Serial Bus 1364 (IEEE-1364). In one or more embodiments, a portion or all of the processes and / or methods described are implemented in two or more electronic process control systems 700.

[0401] The electronic process control system 700 is configured to send and receive information to and from a manufacturing tool 720, which includes one or more of an ion implantation tool, an etching tool, a deposition tool, a coating tool, a rinse tool, a cleaning tool, a chemical mechanical planarization (CMP) tool, a test tool, an inspection tool, a transport system tool, and a thermal processing tool, which will perform a predetermined series of multiple manufacturing operations to produce the desired integrated circuit devices. The information includes one or more of operational data, parameter data, test data, and functional data used to control, monitor, and / or evaluate the execution, progress, and / or completion of a particular manufacturing process. The process tool information is stored in and / or retrieved from a computer-readable storage medium 704.

[0402] The electronic process control system 700 is configured to receive messages through the input / output interface 712. The messages received through the input / output interface 712 include one or more of instructions, data, programming data that specify design rules such as layer thickness, spacing, structure, and layer resistivity, feature dimensions, process performance history, target ranges, set points, and / or other parameters for processing by the hardware processor 702. The messages are transmitted to the hardware processor 702 via the bus 718. The electronic process control system 700 is configured to receive messages related to a user interface (UI) through the input / output interface 712. The messages are stored in the computer-readable storage medium 704 as the user interface (UI) 710.

[0403] In some embodiments, at least a portion of the processes and / or methods are implemented as a standalone software application executed via a processor. In some embodiments, a portion or all of the processes and / or methods are implemented as a software application that is at least a portion of an additional software application. In some embodiments, at least a portion of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an electronic process control tool. In some embodiments, a portion or all of the processes and / or methods are implemented as a software application used by an electronic process control system 700.

[0404] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., read-only memory, random access memory), memory cards, and the like. One or more.

[0405] Figure 8 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and its associated integrated circuit manufacturing flow, which is used to manufacture an integrated circuit device including improved control of SSD (solid state drive) and EPI (epi) profiles according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 800 is used to manufacture at least one of (A) "one or more semiconductor masks" or (B) "at least one component in a layer of a semiconductor integrated circuit".

[0406] exist Figure 8 8, an integrated circuit manufacturing system 800 includes multiple entities that interact in the design, development, and manufacturing cycles, and / or services associated with manufacturing an integrated circuit device 860, such as a design company 820, a mask company 830, and an integrated circuit manufacturer / fab ("fab") 850. Once the manufacturing process of forming multiple integrated circuit devices on a wafer is completed, the wafer is optionally sent to the back end or back end of the line (BEOL) 880 for programming, electrical testing, and packaging of the devices to obtain the final integrated circuit device product. Multiple entities in the manufacturing system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet.

[0407] The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design company 820, the mask company 830, and the integrated circuit manufacturing plant 850 are owned by a single larger company. In some embodiments, two or more of the design company 820, the mask company 830, and the integrated circuit manufacturing plant 850 coexist in a common facility and use common resources.

[0408] The design company 820 (or design team) generates an integrated circuit design layout 822. The integrated circuit design layout 822 includes various geometric patterns designed for the integrated circuit device 860. The geometric patterns correspond to multiple patterns of metal, oxide, or semiconductor layers that make up the various components of the integrated circuit device 860 to be manufactured. The various layers are combined to form various integrated circuit features.

[0409] For example, a portion of the integrated circuit design layout diagram 822 includes various integrated circuit features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for metal-to-metal interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design company 820 implements an appropriate design program to form the integrated circuit design layout diagram 822. The design program includes one or more of a logic design, a physical design, or placement and routing. The integrated circuit design layout diagram 822 is presented in one or more data files having information of multiple geometric patterns. For example, the integrated circuit design layout diagram 822 will be expressed in a GDSII file format or a DFII file format.

[0410] The pattern of the modified integrated circuit design layout diagram is adjusted by appropriate methods so as to reduce the parasitic capacitance of the integrated circuit, for example, compared with the unmodified integrated circuit design layout diagram. The modified integrated circuit design layout diagram reflects the result of the position change of the wire in the layout diagram, and in some embodiments, features associated with the capacitor isolation structure are inserted into the integrated circuit design layout diagram to further reduce the parasitic capacitance relative to the integrated circuit structure having the modified integrated circuit design layout diagram but without the features for forming the capacitor isolation structure therein.

[0411] The mask company 830 includes mask data preparation 832 and mask manufacturing 844. The mask company 830 uses the integrated circuit design layout 822 to manufacture one or more masks 845, which are used to manufacture various layers of the integrated circuit device 860 according to the integrated circuit design layout 822. The mask company 830 performs mask data preparation 832, in which the integrated circuit design layout 822 is translated into a representative data file ("RDF"). The mask data preparation 832 provides the representative data file (RDF) to the mask manufacturing 844. The mask manufacturing 844 includes a mask writer. The mask writer converts the representative data file into an image on a substrate, such as a mask 845 (reduced mask) or a semiconductor wafer 853. The integrated circuit design layout 822 is manipulated by the mask data preparation 832 to conform to the specific characteristics of the mask writer and / or the requirements of the integrated circuit manufacturing plant 850. In Figure 8In the embodiment, mask data preparation 832 and mask manufacturing 844 are illustrated as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 are collectively referred to as mask data preparation.

[0412] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those known to be caused by diffraction, interference, other process effects, and the like. Optical proximity correction adjusts the integrated circuit design layout 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats optical proximity correction as an inverse imaging problem.

[0413] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks an integrated circuit design layout 822 that has been processed in optical proximity correction using a set of multiple mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the mask rule checker modifies the integrated circuit design layout 822 to compensate for the constraints during mask fabrication 844, which can undo some of the modifications performed by the optical proximity correction to satisfy the multiple mask creation rules.

[0414] In some embodiments, the mask data preparation 832 includes a lithography process checking (LPC), which simulates the process to be performed by the integrated circuit manufacturing plant 850 to manufacture the integrated circuit device 860. The lithography process checking simulates this process based on the integrated circuit design layout 822 to create a simulated manufactured device, such as the integrated circuit device 860. In some embodiments, the plurality of process parameters in the lithography process checking simulation will include a plurality of parameters associated with various processes of the integrated circuit manufacturing cycle, a plurality of parameters associated with the tools used to manufacture the integrated circuit, and / or other aspects of the manufacturing process. The lithography process checking takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated manufactured device has been created by the lithography process checking, if the simulated device is not close enough in shape to meet the design rules, the optical proximity correction and / or the mask rule checker are repeated to further refine the integrated circuit design layout 822.

[0415] It should be understood that the above description of mask data preparation 832 has been simplified for the purpose of clarity. In some embodiments, mask data preparation 832 includes additional features, such as logic operations (LOPs), to modify the integrated circuit design layout 822 according to manufacturing rules. In addition, the multiple processes applied to the integrated circuit design layout 822 during mask data preparation 832 can be performed in a variety of different orders.

[0416] After the mask data preparation 832 and during the mask manufacturing 844, a mask 845 or a group of multiple masks 845 are manufactured based on the modified integrated circuit design layout 822. In some embodiments, the mask manufacturing 844 includes performing one or more lithography exposures based on the integrated circuit design layout 822. In some embodiments, based on the modified integrated circuit design layout 822, a pattern is formed on the mask 845 (mask or shrink mask) using an electron beam (e-beam) or multiple electron beam mechanisms. The mask 845 will be formed using a process selected from a variety of available technologies. In some embodiments, the mask 845 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., ultraviolet (UV)) is used to expose an image sensitive material layer (e.g., photoresist) that has been coated on a wafer, and the radiation beam is blocked by the opaque areas and transmitted through the transparent areas. In one embodiment, a binary reticle version of reticle 845 includes a transparent substrate (eg, fused quartz) and an opaque material (eg, chrome) coated in the opaque regions of the binary reticle.

[0417] In another embodiment, the mask 845 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 845, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various embodiments, the phase shift mask will be an attenuated phase shift mask (attenuated PSM) or an alternating phase shift mask (alternating PSM). In various processes, the mask produced by the mask manufacturing 844 is used. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 853, in an etching process to form various etched regions in the semiconductor wafer 853, and / or in other suitable processes.

[0418] Integrated circuit manufacturing plant 850 includes wafer manufacturing 852. Integrated circuit manufacturing plant 850 is an integrated circuit manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, integrated circuit manufacturing plant 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing) of multiple integrated circuit products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line, BEOL) manufacturing) of interconnects and packaging for integrated circuit products, and a third manufacturing facility can provide other services for the foundry business.

[0419] Wafer fabrication 852 includes forming a patterned layer of mask material on a semiconductor substrate made of a mask material including one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or a combination thereof. In some embodiments, the mask 845 includes a single layer of mask material. In some embodiments, the mask 845 includes multiple layers of mask material.

[0420] In some embodiments, the integrated circuit manufacturing plant 855 includes wafer manufacturing 857. The integrated circuit manufacturing plant 855 is an integrated circuit manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, the integrated circuit manufacturing plant 855 is a manufacturing facility that provides back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of integrated circuit products to add one or more metallization layers to the wafer 859, and a third manufacturing facility (not shown) may provide other services to the foundry enterprise, such as packaging and labeling.

[0421] In some embodiments, the mask material is patterned via exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a light that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (ultraviolet, visible, and / or infrared) lights.

[0422] In some embodiments, the etching process includes exposing a plurality of exposed structures in the functional area to an oxygen-containing atmosphere to oxidize portions outside the plurality of exposed structures, followed by a chemical trimming process, such as the plasma etching or liquid chemical etching described above, to remove the oxidized material and leave the modified structure. In some embodiments, oxidation is performed and then chemical trimming is performed to provide greater size selectivity for the exposed material and reduce the possibility of accidental material removal during the manufacturing process. In some embodiments, the plurality of exposed structures may include a plurality of fin structures of a fin field effect transistor (FinFET), wherein the plurality of fins are embedded in a dielectric support medium covering the plurality of sides of the plurality of fins. In some embodiments, the plurality of exposed portions of the plurality of fins in the functional area are the top surfaces and sides of the fins, which are above the top surface of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level below the top surface of the fins, but still covers the lower portion of the plurality of sides of the plurality of fins.

[0423] After the mask patterning operation, multiple areas not covered by the mask are etched to modify the size of one or more structures within the exposed areas. According to some embodiments, in some embodiments, the etching is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etching solution. The chemical substances of the liquid chemical etching solution include one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (buffered hydrofluoric acid, BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), ethylenediaminecatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof.

[0424] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of substrate materials is performed using a halogen-containing reactive gas excited by an electromagnetic field to dissociate into a plurality of ions. Reactive gases or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or a combination thereof, although other semiconductor material etchant gases are also foreseen within the scope of the present disclosure. According to plasma etching methods known in the art, ions are accelerated to impact the exposed material via an alternating electromagnetic field or a fixed bias.

[0425] In some embodiments, molecular-scale processing techniques that share the self-limiting surface reaction characteristics utilized in atomic layer deposition (ALD) include, for example, molecular layer deposition (MLD) and self-assembled monolayers (SAM). Molecular layer deposition utilizes a continuous precursor-surface reaction in which the precursor is introduced into a reaction zone above the wafer surface. The precursor is adsorbed to the wafer surface where it is limited by physical adsorption. The precursor then undergoes rapid chemical adsorption reactions with a plurality of active surface sites, resulting in the formation of self-limited molecular attachments in specific components or regularly repeating structures. These molecular layer deposition (MLD) structures will be successfully formed using lower process temperatures than some conventional deposition techniques.

[0426] Self-assembled monolayer (SAM) is a deposition technique involving the spontaneous adhesion of organized organic structures on the surface of a wafer. This adhesion involves the adsorption of organic structures from a gas phase or a liquid phase using relatively weak interactions with the wafer surface. Initially, these structures are adsorbed on the surface via physical adsorption, such as via van der Waals forces or polar interactions. The self-assembled monolayer will then be confined to this surface via a chemical adsorption process. In some embodiments, the ability of the self-assembled monolayer to grow a layer as thin as a single molecule via chemical adsorption-driven interactions with the wafer surface is particularly useful in forming films including, for example, "near-zero thickness" activation layers or barrier layers. Self-assembled monolayers are also particularly useful in area-selective deposition (ASD) (or area-specific deposition), which uses molecules that show preferential reactions with specific portions of the wafer surface below in order to promote or hinder subsequent material growth in the target area. In some embodiments, the self-assembled monolayer is used to form a base region or a blueprint region for subsequent area-selective atomic layer deposition (AS-ALD) or area-selective chemical vapor deposition (AS-CVD).

[0427] Atomic layer deposition (ALD), molecular layer deposition (MLD), and self-assembled monolayer (SAM) processes represent a number of viable options for fabricating thin layers (in some embodiments, the fabricated layers are only a few atoms thick) that exhibit sufficient uniformity, conformality, and / or purity for intended integrated circuit device applications. These processes and precise control of the resulting surface chemistry allow for excellent control over processing parameters and target composition and properties of the resulting films by individually and sequentially delivering the components of the material system being fabricated to the processing environment.

[0428] Fig. 9 9 is a schematic diagram of various processing departments defined within a fabrication plant / front end of line / foundry for manufacturing integrated circuit devices according to some embodiments. The processing departments utilized in the fabrication of integrated circuit devices in the front end of line (FEOL) and back end of line (BEOL) generally include a wafer transfer operation 902 for moving wafers between the various processing departments. In some embodiments, the wafer transfer operation will be associated with the wafer transfer operation according to Figure 7The electronic process control (EPC) system of the wafer transfer operation 902 is integrated and used to provide process control operations to ensure that the wafers are processed in a timely manner and transferred to the appropriate processing department in the order determined by the process flow. In some embodiments, the electronic process control system will also provide control and / or quality assurance and parameter data for the proper operation of the defined processing equipment. Interconnected via the wafer transfer operation 902 will be various processing departments, such as providing photolithography operations 904, etching operations 906, ion implantation operations 908, cleaning / stripping operations 910, chemical mechanical polishing (CMP) operations 912, epitaxial growth operations 914, deposition operations 916, and thermal treatment 918.

[0429] In some embodiments, a method for manufacturing a semiconductor device includes multiple operations: forming an isolation structure in a substrate, forming a first active region on a first side of the isolation structure, forming a first plurality of primary polysilicon structures above the first active region, the first plurality of primary polysilicon structures having a first contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure above the isolation structure.

[0430] In some additional embodiments, the method of manufacturing a semiconductor device includes one or more additional operations, including, for example, the operation of forming secondary polysilicon structures, including forming a second plurality of secondary polysilicon structures, the second plurality of secondary polysilicon structures having a polysilicon pitch of a second contact; spacing the second plurality of secondary polysilicon structures so that the polysilicon pitch of the first contact and the polysilicon pitch of the second contact are different; spacing the second plurality of secondary polysilicon structures so that the polysilicon pitch of the first contact and the polysilicon pitch of the second contact are equal; removing one of the second plurality of secondary polysilicon structures to form an opening, and filling the opening with a conductive material; removing one of the second plurality of secondary polysilicon structures to form an opening, and filling the opening with a polysilicon / silicon oxide / metal layered structure. to fill this opening; remove the second plurality of secondary polysilicon structures to form a plurality of openings, and fill the plurality of openings with insulating material; remove one of the second plurality of secondary polysilicon structures to form an opening so that the opening is located between and adjacent to two of the remaining second plurality of secondary polysilicon structures, fill the opening with a conductive material, and establish an electrical contact, which is connected to the conductive material in the opening and the two secondary polysilicon structures adjacent to the filled opening; patterning and etching the plurality of secondary polysilicon structures to form a second plurality of secondary polysilicon structures; and / or removing the first plurality of primary polysilicon structures to form a plurality of primary openings, removing the second plurality of secondary polysilicon structures to form a plurality of secondary openings, and filling the plurality of primary openings and the plurality of secondary openings with conductive structures.

[0431] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: forming an isolation structure in a substrate; forming a first active region on a first side of the isolation structure; forming a first plurality of primary polysilicon structures above the first active region, each of the first plurality of primary polysilicon structures having a first contact polysilicon pitch (CPP); and forming a secondary polysilicon structure above the isolation structure, the secondary polysilicon structure being parallel to the first plurality of primary polysilicon structures.

[0432] In some embodiments, in a method of manufacturing a semiconductor device, forming a secondary polysilicon structure further includes forming a second plurality of secondary polysilicon structures, wherein the second plurality of secondary polysilicon structures have a second contacted polysilicon pitch.

[0433] In some embodiments, in the method of manufacturing a semiconductor device, forming the second plurality of secondary polysilicon structures further includes spacing the second plurality of secondary polysilicon structures apart so that a polysilicon pitch of the first contact and a polysilicon pitch of the second contact are different.

[0434] In some embodiments, in the method of manufacturing a semiconductor device, forming the second plurality of secondary polysilicon structures further includes spacing the second plurality of secondary polysilicon structures apart so that a polysilicon pitch of the first contacts is equal to a polysilicon pitch of the second contacts.

[0435] In some embodiments, the method of manufacturing a semiconductor device further includes: removing one of the second plurality of secondary polysilicon structures to form an opening; and filling the opening with a conductive material.

[0436] In some embodiments, the method of manufacturing a semiconductor device further includes: removing one of the second plurality of secondary polysilicon structures to form an opening; and filling the opening with a polysilicon / silicon oxide / metal layered structure.

[0437] In some embodiments, the method of manufacturing a semiconductor device further includes: removing the second plurality of secondary polysilicon structures to form a third plurality of openings; and filling the third plurality of openings with an insulating material.

[0438] In some embodiments, the method of manufacturing a semiconductor device further includes: removing a first-level polysilicon structure to form an opening, wherein the opening is formed between a second-level polysilicon structure and a third-level polysilicon structure, and the second-level polysilicon structure and the third-level polysilicon structure are adjacent to the opening; filling the opening with a conductive material; and establishing an electrical contact connected to the conductive material and the second-level polysilicon structure and the third-level polysilicon structure.

[0439] In some embodiments, in the method of manufacturing a semiconductor device, forming the second plurality of secondary polysilicon structures further includes patterning and etching the secondary polysilicon structures to form the second plurality of secondary polysilicon structures.

[0440] In some embodiments, the method of manufacturing a semiconductor device further includes: removing the first plurality of primary polysilicon structures to form a plurality of primary openings; removing the second plurality of secondary polysilicon structures to form a plurality of secondary openings; and filling the plurality of primary openings and the plurality of secondary openings with a conductive structure.

[0441] In some embodiments, a method of manufacturing a semiconductor device includes multiple operations: forming an isolation structure in a substrate, forming a first active region on a first side of the isolation structure, forming a first plurality of primary polysilicon structures above the first active region, forming a second plurality of secondary polysilicon structures above the isolation structure, removing the first plurality of primary polysilicon structures to form a first plurality of openings, removing the second plurality of secondary polysilicon structures to form a second plurality of openings, filling the first plurality of openings and the second plurality of openings with a conductive material, removing the conductive material from the second plurality of openings to form a third plurality of openings, and filling the third plurality of openings with a dielectric material.

[0442] In some additional embodiments, the method of manufacturing a semiconductor device includes one or more additional operations, including, for example, forming a barrier layer on exposed surfaces of the third plurality of openings before filling the third plurality of openings with a dielectric material; forming a first plurality of contacts extending to the conductive material in the first plurality of openings; and / or forming a conductive structure comprising a plurality of different conductive materials.

[0443] In some embodiments, the method of manufacturing a semiconductor device further includes: before filling the third plurality of openings with a dielectric material, forming a barrier layer on exposed surfaces of the third plurality of openings.

[0444] In some embodiments, the method of fabricating a semiconductor device further includes forming a first plurality of contacts to the conductive material in the first plurality of openings.

[0445] In some embodiments, in a method of manufacturing a semiconductor device, filling the first plurality of openings and the second plurality of openings with a conductive material further includes: forming a conductive structure including a plurality of different conductive materials.

[0446] In some embodiments, features of a semiconductor device include: a substrate, an isolation structure in the substrate, a first active region on a first side of the isolation structure, a first plurality of conductors formed above the first active region, a second active region on a second side of the isolation structure opposite the first active region, a second plurality of conductors formed above the second active region, and a secondary structure formed above the isolation structure, the secondary structure being between the first plurality of conductors and the second plurality of conductors.

[0447] In some additional embodiments, the semiconductor device includes one or more additional features, including, for example, a conductor structure, a first polysilicon structure on a first side of the conductor structure, a second polysilicon structure on a second side of the conductor structure, a dielectric layer over the conductor structure and the first and second polysilicon structures, and a contact extending through the dielectric layer and providing direct electrical contact to the conductor structure and the first and second polysilicon structures; a first plurality of polysilicon structures; a first plurality of dielectric structures; a conductor structure having a first conductive material forming a barrier film on a dielectric surface and a second conductive material contained within a recess defined by the first conductive material and / or a secondary structure, the secondary structure being configured to provide a functional structure arranged between the first and second plurality of conductors, the functional structure comprising at least one of a resistor, a power supply, a heat sink, and / or a variable resistor.

[0448] The semiconductor devices fabricated according to the embodiments of the methods detailed above each include at least one functional element arranged above one or more isolation structures 104 and at the same level as vertical device structures including, for example, device gate structures and / or contact metal structures including conductive composite structures 122 to provide additional functionality without increasing device height or reducing device density. In some embodiments where the functional element is a power rail 221, the conductive material of most, if not all, of the power rail 221 includes one or more of W, Mo, Co, Nb, Al, Cu, Au, Ag, Ca, Zn, or Ir, and mixtures and alloys thereof.

[0449] Still other embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and a secondary structure. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors.

[0450] In some embodiments, in the semiconductor device, the secondary structure further comprises: a conductor structure, a first polysilicon structure, a second polysilicon structure, a dielectric layer, and a plurality of contacts. The first polysilicon structure is on a first side of the conductor structure. The second polysilicon structure is on a second side of the conductor structure. The dielectric layer is above the conductor structure and the first polysilicon structure and the second polysilicon structure. The plurality of contacts extend through the dielectric layer and provide direct electrical contact to the conductor structure and the first polysilicon structure and the second polysilicon structure.

[0451] In some embodiments, in the semiconductor device, the secondary structure further includes: a first plurality of polysilicon structures.

[0452] In some embodiments, in the semiconductor device, the secondary structure further includes: a first plurality of dielectric structures.

[0453] In some embodiments, in the semiconductor device, the secondary structure further comprises: a conductor structure having a film of a first conductive material on a dielectric surface and a second conductive material contained within a channel defined by the film of the first conductive material, wherein the first conductive material and the second conductive material are different.

[0454] In some embodiments, in the semiconductor device, the secondary structure further includes a functional structure selected from the group consisting of a resistor, a power supply, a heat sink, a variable resistor, and a combination thereof.

[0455] Some embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and a secondary structure. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite to the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors. A length of the isolation structure between the first active region and the second active region is greater than 1.5 times a spacing between any two of the first plurality of conductors or a spacing between any two of the second plurality of conductors.

[0456] In some embodiments, in a semiconductor device, a secondary structure includes a barrier layer and a conductive material.

[0457] Some embodiments of the present disclosure provide a semiconductor device comprising: a substrate, an isolation structure, a first active region, a first plurality of conductors, a second active region, a second plurality of conductors, and at least two secondary structures. The isolation structure is in the substrate. The first active region is on a first side of the isolation structure. The first plurality of conductors are formed above the first active region. The second active region is on a second side of the isolation structure opposite the first active region. The second plurality of conductors are formed above the second active region. The secondary structure is formed above the isolation structure, wherein the at least two secondary structures are between the first plurality of conductors and the second plurality of conductors.

[0458] In some embodiments, in a semiconductor device, one of the at least two sub-structures includes polysilicon, and another of the at least two sub-structures includes a conductive material.

[0459] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a substrate; an isolation structure in the substrate; a first active region on a first side of the isolation structure; a first plurality of conductors formed over the first active region; a second active region on a second side of the isolation structure opposite the first active region; a second plurality of conductors formed over the second active region; as well as A secondary structure is formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors.

2. The semiconductor device according to claim 1, wherein The substructure also includes: a conductor structure; a first polysilicon structure on a first side of the conductor structure; a second polysilicon structure on a second side of the conductor structure; a dielectric layer over the conductor structure and the first polysilicon structure and the second polysilicon structure; as well as A plurality of contacts extend through the dielectric layer and provide direct electrical contact to the conductor structure and the first polysilicon structure and the second polysilicon structure.

3. The semiconductor device according to claim 1, wherein: The substructure also includes: A first plurality of polysilicon structures.

4. The semiconductor device according to claim 1, wherein: The substructure also includes: A first plurality of dielectric structures.

5. The semiconductor device according to claim 1, wherein The substructure also includes: A conductor structure having a film of a first conductive material on a dielectric surface and a second conductive material contained within a channel defined by the film of the first conductive material, wherein the first conductive material and the second conductive material are different.

6. The semiconductor device according to claim 1, wherein: The secondary structure also includes a functional structure selected from the group consisting of a resistor, a power supply, a heat sink, a variable resistor, and combinations thereof.

7. A semiconductor device, characterized in that: Include: a substrate; an isolation structure in the substrate; a first active region on a first side of the isolation structure; a first plurality of conductors formed over the first active region; a second active region on a second side of the isolation structure opposite the first active region; a second plurality of conductors formed over the second active region; as well as a secondary structure formed above the isolation structure, wherein the secondary structure is between the first plurality of conductors and the second plurality of conductors; A length of the isolation structure between the first active region and the second active region is greater than 1.5 times a pitch between any two of the first conductors or a pitch between any two of the second conductors.

8. The semiconductor device according to claim 7, wherein: The secondary structure comprises a barrier layer and a conductive material.

9. A semiconductor device, characterized in that: Include: a substrate; an isolation structure in the substrate; a first active region on a first side of the isolation structure; a first plurality of conductors formed over the first active region; a second active region on a second side of the isolation structure opposite the first active region; a second plurality of conductors formed over the second active region; as well as At least two secondary structures are formed above the isolation structure, wherein the at least two secondary structures are between the first plurality of conductors and the second plurality of conductors.

10. The semiconductor device according to claim 9, wherein: One of the at least two sub-structures includes polysilicon, and another of the at least two sub-structures includes a conductive material.

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