Solar cell, cell assembly and photovoltaic system
By adopting a three-layer conductive layer design in the solar cell, including the first ITO film, the IFO:H film and the second ITO film, the problem of conductivity and light transmittance is solved, and the efficiency of the solar cell is improved .
Patent Information
- Application Number
- CN202323087855.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-15
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2033-11-15
AI Technical Summary
The existing solar cell conductive layer is difficult to take into account both good conductivity and light transmittance, resulting in low battery efficiency.
The conductive layer design adopts a three-layer structure, including stacking the first ITO film, the IFO:H film and the second ITO film on the battery substrate, and improving the carrier transmission capability of the conductive layer by adjusting the thickness and process parameters of each layer. and light transmittance.
The short-circuit current density and filling factor of solar cells are increased, the photoelectric conversion efficiency is improved, and the conductivity and light transmittance are taken into account.
Smart Images
Figure CN222366560U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of solar cells, and in particular to a solar cell, a battery assembly and a photovoltaic system. Background Art
[0002] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductor pn junction to convert sunlight into electrical energy.
[0003] In the related art, indium tin oxide (ITO) in transparent conductive oxide (TCO) is usually used as the conductive layer. However, the electron mobility of the ITO conductive layer is low, and the carrier concentration is high. The carriers cause the scattering of the incident light, resulting in a loss of transmittance, and it is impossible to achieve both good conductivity and light transmittance.
[0004] Based on this, how to design the conductive layer of solar cells to take into account both conductivity and light transmittance has become an urgent problem to be solved. Utility Model Content
[0005] The present application provides a solar cell, a cell assembly and a photovoltaic system, aiming to solve the problem of how to design a conductive layer of a solar cell to take into account both conductivity and light transmittance.
[0006] The solar cell provided in the present application comprises a cell substrate and a conductive layer, wherein the conductive layer comprises a first ITO film, an IFO:H film and a second ITO film sequentially stacked on the cell substrate.
[0007] Optionally, the first ITO film has a thickness of 10 nm-20 nm.
[0008] Optionally, the IFO:H film has a thickness of 70nm-80nm.
[0009] Optionally, the second ITO film has a thickness of 10 nm-20 nm.
[0010] Optionally, the battery substrate includes a silicon substrate, a first interface passivation layer, a first doping layer, a second interface passivation layer and a second doping layer, the first interface passivation layer and the first doping layer are stacked in sequence on one side of the silicon substrate, and the second interface passivation layer and the second doping layer are stacked in sequence on the other side of the silicon substrate; the conductive layer is located on the side of the first doping layer away from the first interface passivation layer, and / or the conductive layer is located on the side of the second doping layer away from the second interface passivation layer.
[0011] Optionally, the thickness of the first interface passivation layer is 5nm-10nm;
[0012] And / or, the thickness of the second interface passivation layer is 5nm-10nm.
[0013] Optionally, the thickness of the first doping layer is 5nm-10nm;
[0014] And / or, the thickness of the second doping layer is 5nm-10nm.
[0015] Optionally, the solar cell comprises a first electrode and a second electrode, and the thickness of the first electrode is 30 μm-40 μm;
[0016] And / or, the thickness of the second electrode is 30 μm-40 μm.
[0017] The battery assembly provided in the present application includes any of the above-mentioned solar cells.
[0018] The photovoltaic system provided in the present application includes the above-mentioned battery assembly.
[0019] The solar cell, battery assembly and photovoltaic system of the embodiment of the present application include a first ITO film, an IFO:H film and a second ITO film sequentially stacked on the battery substrate, so the ability of the conductive layer to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate can be increased, thereby increasing the short-circuit current density of the solar cell. Moreover, the first ITO film and the second ITO film can form good contact with the battery substrate and the electrode respectively, thereby improving the short-circuit current density and fill factor of the solar cell. In this way, the conductive layer can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;
[0021] Figure 2 It is a schematic flow chart of a method for manufacturing a conductive layer of a solar cell according to an embodiment of the present application;
[0022] Description of main component symbols:
[0023] Solar cell 100, cell substrate 10, silicon substrate 101, first interface passivation layer 11, first doping layer 12, second interface passivation layer 14, second doping layer 15; conductive layer 20, first ITO film 21, IFO:H film 22, second ITO film 23; first electrode 31, second electrode 32. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.
[0025] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0028] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0029] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.
[0030] In the present application, since the conductive layer includes a first ITO film, an IFO:H film, and a second ITO film sequentially stacked on the battery substrate, the ability of the conductive layer to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate can be increased, thereby increasing the short-circuit current density of the solar cell. Moreover, the first ITO film and the second ITO film can form good contact with the battery substrate and the electrode respectively, thereby improving the short-circuit current density and fill factor of the solar cell. In this way, the conductive layer can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell.
[0031] Embodiment 1
[0032] See also Figure 1 The solar cell 100 of the embodiment of the present application includes a cell substrate 10 and a conductive layer 20 , wherein the conductive layer 20 includes a first ITO film 21 , an IFO:H film 22 , and a second ITO film 23 sequentially stacked on the cell substrate 10 .
[0033] In the solar cell 100 of the embodiment of the present application, since the conductive layer 20 includes the first ITO film 21, the IFO:H film 22 and the second ITO film 23 sequentially stacked on the cell substrate 10, the ability of the conductive layer 20 to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate 101 can be increased, thereby increasing the short-circuit current density of the solar cell 100. Moreover, the first ITO film 21 and the second ITO film 23 can form good contact with the cell substrate 10 and the electrode respectively, thereby increasing the short-circuit current density and fill factor of the solar cell 100. In this way, the conductive layer 20 can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell 100.
[0034] In this embodiment, the cell substrate 10 includes a silicon substrate 101, a first interface passivation layer 11, a first doping layer 12, a second interface passivation layer 14, and a second doping layer 15. The first interface passivation layer 11 and the first doping layer 12 are sequentially stacked on one side of the silicon substrate 101, and the second interface passivation layer 14 and the second doping layer 15 are sequentially stacked on the other side of the silicon substrate 101. In this way, the solar cell 100 is a heterojunction cell.
[0035] It is understood that in other embodiments, the solar cell 100 may also be a PERC cell, a TopCon cell, or other types of cells. The specific form of the solar cell 100 is not limited herein.
[0036] In this embodiment, the solar cell 100 may further include a first electrode 31 and a second electrode 32, the number of the conductive layers 20 is two, one conductive layer 20 is disposed between the first doping layer 12 and the first electrode 31, and the other conductive layer 20 is disposed between the second doping layer 15 and the second electrode 32. Further, the first electrode 31 and the second electrode 32 may be metal grid electrodes.
[0037] It can be understood that in other embodiments, the conductive layer 20 may be disposed between the first doping layer 12 and the first electrode 31, and no conductive layer 20 may be disposed between the second doping layer 15 and the second electrode 32; or the conductive layer 20 may not be disposed between the first doping layer 12 and the first electrode 31, and the conductive layer 20 may be disposed between the second doping layer 15 and the second electrode 32.
[0038] In this embodiment, the conductive layer 20 covers the entire surface of the battery substrate 10. It is understood that in other embodiments, the conductive layer 20 may cover only a portion of the battery substrate 10.
[0039] The specific number of the conductive layers 20 and the specific positions on the battery substrate 10 are not limited here.
[0040] Specifically, the first ITO film 21 and the second ITO film 23 are both tin-doped indium oxide (ITO) films, and the IFO:H film 22 is an indium oxide film doped with hydrogen and fluorine.
[0041] It can be understood that the electron mobility of the first ITO film 21 and the second ITO film 23 is low and the carrier concentration is high, so the conductivity of the conductive layer 20 is good. In addition, the first ITO film 21 has good contact with amorphous silicon, and the second ITO film 23 has good contact with the electrode, so that the conductive layer 20 has good contact with the battery substrate 10.
[0042] Furthermore, the IFO:H film 22 has a high electron mobility and a low carrier concentration, so it can take into account the conductivity and light transmittance of the conductive layer 20, so that the light transmittance of the conductive layer 20 is better, thereby making the solar cell 100 have a higher short-circuit current and fill factor. In addition, since the light transmittance of the IFO:H film 22 is good, the IFO:H film 22 can better match the refractive index with the first ITO film 21 and the second ITO film 23, so that the anti-reflection effect of the conductive layer 20 is better.
[0043] In addition, in the first ITO film 21 and the second ITO film 23, In 3+ The ionic radius is Sn 4+ The ionic radius is IFO:H film 22, F - The ionic radius is O 2- The ionic radius is Because F - With O 2- The ionic radius of In 3+ With Sn 4+ Therefore, the IFO:H film 22 has smaller crystalline silicon distortion and fewer defect states than the ITO film used in the related art, which is beneficial to the collection of electrons.
[0044] In summary, the conductive layer 20 in the present application includes a first ITO film 21, an IFO:H film 22 and a second ITO film 23, which is a three-layer structure, which can increase the ability of the conductive layer 20 to transmit carriers, and increase the absorption and utilization rate of light by the solar cell 100, thereby increasing the short-circuit current density of the solar cell 100. While ensuring good transmittance, it also takes into account electrical properties, so that the solar cell 100 has a higher short-circuit current density and fill factor.
[0045] Embodiment 2
[0046] In some optional embodiments, the thickness of the first ITO film 21 is 10 nm-20 nm, for example, 10 nm, 11 nm, 15 nm, 18 nm, or 20 nm.
[0047] In this way, the thickness of the first ITO film 21 is within an appropriate range, which can avoid poor conductivity due to too small thickness of the first ITO film 21 and poor light transmittance due to too large thickness of the first ITO film 21 .
[0048] Preferably, the thickness of the first ITO film 21 is 14 nm-16 nm, for example, 14 nm, 14.2 nm, 15 nm, 15.5 nm, 16 nm. In this way, the thickness of the first ITO film 21 is in a more suitable range, which is conducive to further taking into account the conductivity and transmittance, and the overall effect is better.
[0049] Embodiment 3
[0050] In some optional embodiments, the thickness of the IFO:H film 22 is 70 nm-80 nm, for example, 70 nm, 71 nm, 75 nm, 78 nm, or 80 nm.
[0051] In this way, the thickness of the IFO:H film 22 is within an appropriate range, which can avoid poor conductivity due to too small thickness of the IFO:H film 22 and can also avoid waste of materials and increased costs due to too large thickness of the IFO:H film 22.
[0052] Preferably, the thickness of the IFO:H film 22 is 74 nm-76 nm, for example, 74 nm, 74.2 nm, 75 nm, 75.5 nm, 76 nm. In this way, the thickness of the IFO:H film 22 is in a more suitable range, which is conducive to further taking into account the conductivity and cost, and the overall effect is better.
[0053] Embodiment 4
[0054] In some optional embodiments, the thickness of the second ITO film 23 is 10 nm-20 nm, for example, 10 nm, 11 nm, 15 nm, 18 nm, or 20 nm.
[0055] In this way, the thickness of the second ITO film 23 is within an appropriate range, which can avoid poor conductivity due to too small thickness of the second ITO film 23 and poor light transmittance due to too large thickness of the second ITO film 23 .
[0056] Preferably, the thickness of the second ITO film 23 is 14 nm-16 nm, for example, 14 nm, 14.2 nm, 15 nm, 15.5 nm, 16 nm. In this way, the thickness of the second ITO film 23 is in a more suitable range, which is conducive to further taking into account the conductivity and transmittance, and the overall effect is better.
[0057] Embodiment 5
[0058] See also Figure 1In some optional embodiments, the battery substrate 10 includes a silicon substrate 101, a first interface passivation layer 11, a first doping layer 12, a second interface passivation layer 14 and a second doping layer 15, the first interface passivation layer 11 and the first doping layer 12 are sequentially stacked on one side of the silicon substrate 101, and the second interface passivation layer 14 and the second doping layer 15 are sequentially stacked on the other side of the silicon substrate 101; the conductive layer 20 is located on the side of the first doping layer 12 away from the first interface passivation layer 11, and / or the conductive layer 20 is located on the side of the second doping layer 15 away from the second interface passivation layer 14.
[0059] In this way, the solar cell 100 is a heterojunction cell, which has good stability and can work in a relatively harsh environment. Moreover, the photoelectric conversion efficiency of the heterojunction cell is relatively high. The conductive layer 20 can be arranged on one side or both sides of the heterojunction cell, and the position is more flexible, which can adapt to more practical scenarios and needs.
[0060] In this embodiment, the conductive layer 20 is located on a side of the first doping layer 12 away from the first interface passivation layer 11 , and the conductive layer 20 is located on a side of the second doping layer 15 away from the second interface passivation layer 14 .
[0061] It can be understood that in other embodiments, the conductive layer 20 may be located on the side of the first doping layer 12 away from the first interface passivation layer 11, and not located on the side of the second doping layer 15 away from the second interface passivation layer 14; or the conductive layer 20 may be located on the side of the second doping layer 15 away from the second interface passivation layer 14, and not located on the side of the first doping layer 12 away from the first interface passivation layer 11.
[0062] Specifically, the silicon substrate 101 may be a P-type silicon substrate 101 or an N-type silicon substrate 101 .
[0063] Specifically, the first doping layer 12 is a P-type doping layer, and the second doping layer 15 is an N-type doping layer. In other embodiments, the first doping layer 12 may be an N-type doping layer, and the second doping layer 15 may be a P-type doping layer.
[0064] Specifically, the first interface passivation layer 11 includes an intrinsic amorphous silicon layer. It is understood that in other embodiments, the first interface passivation layer 11 may also include at least one of an intrinsic polycrystalline silicon layer, an intrinsic nanocrystalline silicon layer, an intrinsic mixed crystal silicon layer, a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a silicon carbide layer, and a carbon nitride silicon oxide layer. The specific type of the first interface passivation layer 11 is not limited here.
[0065] Specifically, the first doping layer 12 includes a doped amorphous silicon layer. It is understood that in other embodiments, the first doping layer 12 may also include at least one of a doped polycrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped mixed crystal silicon layer. The specific type of the first doping layer 12 is not limited here.
[0066] Specifically, the second interface passivation layer 14 includes an intrinsic amorphous silicon layer. It is understood that in other embodiments, the second interface passivation layer 14 may also include at least one of an intrinsic polycrystalline silicon layer, an intrinsic nanocrystalline silicon layer, an intrinsic mixed crystal silicon layer, a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a silicon carbide layer, and a carbon nitride silicon oxide layer. The specific type of the second interface passivation layer 14 is not limited here.
[0067] Specifically, the second doping layer 15 includes a doped amorphous silicon layer. It is understood that in other embodiments, the second doping layer 15 may also include at least one of a doped polycrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped mixed crystal silicon layer. The specific type of the second doping layer 15 is not limited here.
[0068] Embodiment 6
[0069] In some optional embodiments, the thickness of the first interface passivation layer 11 is 5 nm-10 nm, for example, 5 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
[0070] In this way, the thickness of the first interface passivation layer 11 is within an appropriate range, which can avoid the poor passivation effect and excessive defect states on the silicon wafer surface caused by the first interface passivation layer 11 being too small, which will affect the open circuit voltage of the battery. It can also avoid the serious parasitic absorption and small short-circuit current density caused by the first interface passivation layer 11 being too thick, which will reduce the tunneling effect of carriers and hinder the transmission of carriers.
[0071] In some optional embodiments, the thickness of the second interface passivation layer 14 is 5 nm-10 nm, for example, 5 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
[0072] In this way, the thickness of the second interface passivation layer 14 is within an appropriate range, which can avoid the poor passivation effect caused by the second interface passivation layer 14 being too thin, excessive defect states on the silicon wafer surface, and affecting the open circuit voltage of the battery. It can also avoid the serious parasitic absorption, small short-circuit current density, reduced carrier tunneling effect, and hindered carrier transmission caused by the first interface passivation layer 11 being too thick.
[0073] Embodiment 7
[0074] In some optional embodiments, the thickness of the first doping layer 12 is 5 nm-10 nm, for example, 5 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
[0075] In this way, the thickness of the first doping layer 12 is within an appropriate range, which can avoid the weakening of the electron or hole transmission capacity due to too small thickness, incomplete substrate coverage, and leakage, and can also avoid the serious parasitic absorption and reduced battery short-circuit current density due to too large thickness.
[0076] In some optional embodiments, the thickness of the second doping layer 15 is 5 nm-10 nm, for example, 5 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
[0077] In this way, the thickness of the second doping layer 15 is within an appropriate range, which can avoid the weakening of the electron or hole transmission capacity, incomplete substrate coverage, and leakage caused by too small thickness, and can also avoid the serious parasitic absorption and reduced battery short-circuit current density caused by too large thickness.
[0078] Embodiment 8
[0079] In some optional embodiments, the solar cell 100 includes a first electrode 31 and a second electrode 32, and the thickness of the first electrode 31 is 30 μm-40 μm, for example, 30 μm, 32 μm, 35 μm, 38 μm, or 40 μm.
[0080] In this way, the thickness of the first electrode 31 is within an appropriate range, which can avoid the poor effect of transmitting current caused by too small a thickness, and can also avoid the waste of materials and increase in cost caused by too large a thickness.
[0081] In some optional embodiments, the thickness of the second electrode 32 is 30 μm-40 μm, for example, 30 μm, 32 μm, 35 μm, 38 μm, or 40 μm.
[0082] In this way, the thickness of the second electrode 32 is within an appropriate range, which can avoid the poor effect of transmitting current caused by too small a thickness, and can also avoid the waste of materials and increase in cost caused by too large a thickness.
[0083] Embodiment 9
[0084] See also Figure 1 and Figure 2 The method for manufacturing the conductive layer 20 of the solar cell 100 according to the embodiment of the present application comprises:
[0085] Step S10: providing a battery substrate 10 on which a conductive layer 20 is to be fabricated;
[0086] Step S11: forming a first ITO film 21 on the battery substrate 10;
[0087] Step S12: forming an IFO:H film 22 on the first ITO film 21;
[0088] Step S13 : forming a second ITO film 23 on the IFO:H film 22 .
[0089] The method for manufacturing the conductive layer 20 of the solar cell 100 of the embodiment of the present application, since the conductive layer 20 includes the first ITO film 21, the IFO:H film 22 and the second ITO film 23 sequentially stacked on the battery substrate 10, can increase the ability of the conductive layer 20 to transmit carriers, improve the light transmittance, and increase the light absorption utilization rate of the silicon substrate 101, thereby increasing the short-circuit current density of the solar cell 100. Moreover, the first ITO film 21 and the second ITO film 23 can form good contact with the battery substrate 10 and the electrode respectively, thereby improving the short-circuit current density and fill factor of the solar cell 100. In this way, the conductive layer 20 can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell 100.
[0090] Specifically, before step S10, a first interface passivation layer 11 and a first doping layer 12 may be fabricated on the first surface of the silicon substrate 101, and a second interface passivation layer 14 and a second doping layer 15 may be fabricated on the second surface of the silicon substrate 101. In this way, a cell substrate 10 on which a conductive layer 20 is to be fabricated may be formed. After step S13, a first electrode 31 and a second electrode 32 may be fabricated. In this way, a solar cell 100 may be formed.
[0091] Furthermore, the first interface passivation layer 11, the first doping layer 12, the second interface passivation layer 14 and the second doping layer 15 can be manufactured by plasma enhanced chemical vapor deposition (PECVD) process, so that the film layers are uniform, dense and of good quality.
[0092] Furthermore, the first electrode 31 and the second electrode 32 may be formed by screen printing paste, thereby achieving high efficiency and precision.
[0093] Specifically, before depositing a film layer on the silicon substrate 101, the silicon substrate 101 may be cleaned by RCA, so that impurities and oxides on the surface of the silicon substrate 101 can be removed by RCA cleaning, which facilitates the subsequent film layer formation.
[0094] Specifically, after RCA cleaning, the silicon substrate 101 may be subjected to a texturing process, so that a pyramid-shaped texturing surface may be formed on the silicon substrate 101, thereby reducing the reflection of light.
[0095] Embodiment 10
[0096] In some optional embodiments, step S11 includes:
[0097] A first ITO film 21 is formed on the battery substrate 10 by using a magnetron sputtering process;
[0098] The target materials include In2O3 and SnO2, the mass ratio of In2O3 to SnO2 is (85-95):(5-15), the deposition temperature is 100℃-150℃, the Ar flow rate is 50sccm-70sccm, the O2 flow rate is 10sccm-20sccm, and the sputtering pressure is 3×10 -3 Pa-4×10 -3 Pa, sputtering power density is 1 W cm -2 -3Wcm -2 .
[0099] In this way, the first ITO film 21 is manufactured by the magnetron sputtering process, so that the first ITO film 21 has better adhesion and better manufacturing efficiency. In addition, the target material is more suitable, and the process parameters for manufacturing the first ITO film 21 are more suitable, which is conducive to improving the quality of the first ITO film 21.
[0100] Specifically, the mass ratio of In2O3 to SnO2 is, for example, 85:5, 85:10, 85:15, 95:5, 95:10, 95:15. In this way, the mass ratio of In2O3 to SnO2 is within a suitable range, ensuring the formation of a good quality ITO film.
[0101] In this embodiment, the mass ratio of In2O3 to SnO2 is 90:10. This is beneficial to further improve the quality of the first ITO film 21.
[0102] Specifically, the deposition temperature is, for example, 100° C., 110° C., 120° C., 130° C., 140° C., and 150° C. In this way, the deposition temperature is within an appropriate range, which can avoid poor film quality or even failure to form an ITO film due to a deposition temperature that is too low, and can also avoid wasting energy and increasing costs due to a deposition temperature that is too high.
[0103] Specifically, the Ar flow rate is 50 sccm-70 sccm, for example, 50 sccm, 55 sccm, 60 sccm, 68 sccm, and 70 sccm.
[0104] Specifically, the O2 flow rate is 10 sccm-20 sccm, for example, 10 sccm, 12 sccm, 15 sccm, 18 sccm, and 20 sccm.
[0105] Specifically, the sputtering gas pressure is, for example, 3×10 -3 Pa, 3.2×10 -3 Pa, 3.5×10 -3 Pa, 3.8×10 -3 Pa, 4×10 -3 Pa.
[0106] Specifically, the sputtering power density is, for example, 1 W cm -2 、1.2Wcm -2 , 2Wcm -2 、2.8Wcm -2 、3Wcm -2 .
[0107] Embodiment 11
[0108] In some optional embodiments, step S12 includes:
[0109] An IFO:H film 22 is formed on the first ITO film 21 by using a magnetron sputtering process;
[0110] The target material includes fluorine-doped indium oxide, the mass ratio of In2O3 to F is (97-99):(1-3), the deposition temperature is 100℃-150℃, the Ar flow rate is 50sccm-60sccm, the water vapor flow rate is 1sccm-5sccm, and the sputtering pressure is 2×10 -3 Pa-3×10 -3 Pa, sputtering power density is 1 W cm -2 -3Wcm -2 .
[0111] In this way, the IFO:H film 22 is made by the magnetron sputtering process, so that the IFO:H film 22 has better adhesion and higher production efficiency. In addition, the process parameters for making the IFO:H film 22 are more appropriate, which is conducive to improving the quality of the IFO:H film 22.
[0112] Specifically, the mass ratios of In2O3 to F are 97:1, 97:1.5, 97:2, 97:2.5, 97:3, 98:1, 98:1.5, 98:2, 98:2.5, 98:3, 99:1, 99:1.5, 99:2, 99:2.5, and 99:3.
[0113] In this embodiment, the mass ratio of In2O3 to F is 98:2.
[0114] Specifically, the deposition temperature is, for example, 100°C, 110°C, 120°C, 130°C, 140°C, or 150°C.
[0115] Specifically, the Ar flow rate is, for example, 50 sccm, 52 sccm, 55 sccm, 58 sccm, or 60 sccm.
[0116] Specifically, the water vapor flow rate is, for example, 1 sccm, 2 sccm, 3 sccm, 4 sccm, or 5 sccm.
[0117] Specifically, the sputtering gas pressure is, for example, 3×10-3 Pa, 3.2×10 -3 Pa, 3.5×10 -3 Pa, 3.8×10 -3 Pa, 4×10 -3 Pa.
[0118] Specifically, the sputtering power density is, for example, 1 W cm -2 、1.2Wcm -2 , 2Wcm -2 、2.8Wcm -2 、3Wcm -2 .
[0119] Embodiment 12
[0120] In some optional embodiments, step S13 includes:
[0121] A second ITO film 23 is formed on the IFO:H film 22 by using a magnetron sputtering process;
[0122] The target materials include In2O3 and SnO2, the mass ratio of In2O3 to SnO2 is (85-95):(5-15), the deposition temperature is 100℃-150℃, the Ar flow rate is 50sccm-70sccm, the O2 flow rate is 10sccm-20sccm, and the sputtering pressure is 3×10 -3 Pa-4×10 -3 Pa, sputtering power density is 1 W cm -2 -3Wcm -2 .
[0123] In this way, the second ITO film 23 is manufactured by the magnetron sputtering process, so that the second ITO film 23 has better adhesion and a higher manufacturing efficiency. In addition, the target material is more suitable, and the process parameters for manufacturing the second ITO film 23 are more suitable, which is conducive to improving the quality of the second ITO film 23.
[0124] Specifically, the mass ratio of In2O3 to SnO2 is, for example, 85:5, 85:10, 85:15, 95:5, 95:10, 95:15. In this way, the mass ratio of In2O3 to SnO2 is within a suitable range, ensuring the formation of a good quality ITO film.
[0125] In this embodiment, the mass ratio of In2O3 to SnO2 is 90:10. This is beneficial to further improve the quality of the second ITO film 23.
[0126] Specifically, the deposition temperature is, for example, 100° C., 110° C., 120° C., 130° C., 140° C., and 150° C. In this way, the deposition temperature is within an appropriate range, which can avoid poor film quality or even failure to form an ITO film due to a deposition temperature that is too low, and can also avoid wasting energy and increasing costs due to a deposition temperature that is too high.
[0127] Specifically, the Ar flow rate is 50 sccm-70 sccm, for example, 50 sccm, 55 sccm, 60 sccm, 68 sccm, and 70 sccm.
[0128] Specifically, the O2 flow rate is 10 sccm-20 sccm, for example, 10 sccm, 12 sccm, 15 sccm, 18 sccm, and 20 sccm.
[0129] Specifically, the sputtering gas pressure is, for example, 3×10 -3 Pa, 3.2×10 -3 Pa, 3.5×10 -3 Pa, 3.8×10 -3 Pa, 4×10 -3 Pa.
[0130] Specifically, the sputtering power density is, for example, 1 W cm -2 、1.2Wcm -2 , 2Wcm -2 、2.8Wcm -2 、3Wcm -2 .
[0131] Embodiment 13
[0132] The solar cell 100 of the embodiment of the present application, the conductive layer 20 of the solar cell 100 is manufactured by the manufacturing method of the conductive layer 20 of the solar cell 100 of any one of the ninth to twelfth embodiments.
[0133] In the solar cell 100 of the embodiment of the present application, since the conductive layer 20 includes the first ITO film 21, the IFO:H film 22 and the second ITO film 23 sequentially stacked on the cell substrate 10, the ability of the conductive layer 20 to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate 101 can be increased, thereby increasing the short-circuit current density of the solar cell 100. Moreover, the first ITO film 21 and the second ITO film 23 can form good contact with the cell substrate 10 and the electrode respectively, thereby increasing the short-circuit current density and fill factor of the solar cell 100. In this way, the conductive layer 20 can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell 100.
[0134] Embodiment 14
[0135] The battery assembly of the embodiment of the present application includes the solar cell 100 of any one of the first to eighth embodiments or the thirteenth embodiment.
[0136] In the battery assembly of the embodiment of the present application, since the conductive layer 20 in the solar cell 100 includes the first ITO film 21, the IFO:H film 22 and the second ITO film 23 sequentially stacked on the battery substrate 10, the ability of the conductive layer 20 to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate 101 can be increased, thereby increasing the short-circuit current density of the solar cell 100. Moreover, the first ITO film 21 and the second ITO film 23 can form good contact with the battery substrate 10 and the electrode respectively, thereby increasing the short-circuit current density and fill factor of the solar cell 100. In this way, the conductive layer 20 can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell 100.
[0137] In this embodiment, multiple back-contact batteries in the battery assembly can be connected in series in sequence to form a battery string, thereby realizing the series bus output of the current. For example, the series connection of the battery cells can be achieved by setting welding strips (bus bars, interconnecting bars), conductive back plates, etc.
[0138] It is understandable that in such an embodiment, the battery assembly may further include a metal frame, a back plate, photovoltaic glass and an adhesive film. The adhesive film may be filled between the front and back sides of the back contact battery and the photovoltaic glass, adjacent battery cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the adhesive film may be an EVA adhesive film or a POE adhesive film. The specific selection may be based on actual conditions and is not limited here.
[0139] Photovoltaic glass can cover the adhesive film on the front of the back contact cell. The photovoltaic glass can be ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical and optical properties. For example, the light transmittance of ultra-white glass can reach more than 92%, which can protect the back contact cell without affecting the efficiency of the back contact cell as much as possible. At the same time, the adhesive film can bond the photovoltaic glass and the back contact cell together. The presence of the adhesive film can seal and insulate the back contact cell and prevent water and moisture.
[0140] The backplane can be attached to the film on the back of the back contact battery. The backplane can protect and support the back contact battery and has reliable insulation, water resistance and aging resistance. There are multiple options for the backplane, which can usually be tempered glass, organic glass, aluminum alloy TPT composite film, etc. The specific configuration can be made according to the specific situation and is not limited here. The whole composed of the backplane, back contact battery, film and photovoltaic glass can be set on a metal frame. The metal frame serves as the main external support structure of the entire battery assembly and can stably support and install the battery assembly. For example, the battery assembly can be installed at the required location through the metal frame.
[0141] Embodiment 15
[0142] The photovoltaic system of the embodiment of the present application includes the battery assembly of the fourteenth embodiment.
[0143] In the photovoltaic system of the embodiment of the present application, since the conductive layer 20 in the solar cell 100 includes the first ITO film 21, the IFO:H film 22 and the second ITO film 23 sequentially stacked on the cell substrate 10, the ability of the conductive layer 20 to transmit carriers can be increased, the light transmittance can be improved, and the light absorption utilization rate of the silicon substrate 101 can be increased, thereby increasing the short-circuit current density of the solar cell 100. Moreover, the first ITO film 21 and the second ITO film 23 can form good contact with the cell substrate 10 and the electrode respectively, thereby increasing the short-circuit current density and fill factor of the solar cell 100. In this way, the conductive layer 20 can take into account both good conductivity and light transmittance, which is conducive to improving the photoelectric conversion efficiency of the solar cell 100.
[0144] In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple battery components. For example, multiple battery components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.
[0145] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0146] In addition, the above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A solar cell, characterized in that: It includes a battery substrate and a conductive layer, wherein the conductive layer includes a first ITO film, an IFO:H film and a second ITO film sequentially stacked on the battery substrate; the first ITO film and the second ITO film are both tin-doped indium oxide films, and the IFO:H film is an indium oxide film doped with hydrogen and fluorine.
2. The solar cell according to claim 1, characterized in that The thickness of the first ITO film is 10nm-20nm.
3. The solar cell according to claim 1, characterized in that The thickness of the IFO:H film is 70nm-80nm.
4. The solar cell according to claim 1, characterized in that The thickness of the second ITO film is 10nm-20nm.
5. The solar cell according to claim 1, characterized in that: The battery substrate comprises a silicon substrate, a first interface passivation layer, a first doping layer, a second interface passivation layer and a second doping layer, wherein the first interface passivation layer and the first doping layer are sequentially stacked on one side of the silicon substrate, and the second interface passivation layer and the second doping layer are sequentially stacked on the other side of the silicon substrate; The conductive layer is located on a side of the first doped layer away from the first interface passivation layer, and / or the conductive layer is located on a side of the second doped layer away from the second interface passivation layer.
6. The solar cell according to claim 5, characterized in that: The thickness of the first interface passivation layer is 5nm-10nm; And / or, the thickness of the second interface passivation layer is 5nm-10nm.
7. The solar cell according to claim 5, characterized in that: The thickness of the first doping layer is 5nm-10nm; And / or, the thickness of the second doping layer is 5nm-10nm.
8. The solar cell according to claim 1, characterized in that The solar cell comprises a first electrode and a second electrode, wherein the thickness of the first electrode is 30 μm-40 μm; And / or, the thickness of the second electrode is 30 μm-40 μm.
9. A battery assembly, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 8.
10. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 9.