Avionics control test system based on FPGA and CAN bus
By designing an avionics control test system based on FPGA and CAN bus, we solve the existing problems of long development cycle, high complexity, poor versatility and low degree of automation of the avionics control system CAN bus, and achieve a more efficient and automated system. testing process.
Patent Information
- Application Number
- CN202420410362.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-04
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-03-04
AI Technical Summary
The CAN bus development cycle of the existing avionics control system is long, has high complexity, poor versatility and low automation, resulting in high requirements for testers and equipment and complex operations.
Design an avionics control test system based on FPGA and CAN bus. The RS422 interface module realizes the data interaction between the host computer and the FPGA module. The CAN interface module realizes the data interaction between the FPGA module and the avionics control system. The discrete line interface module realizes the data interaction between the avionics control system and the avionics control system. Adjustment and testing of electrical control systems. The FPGA module deframes and frames test instructions to improve the automation and versatility of the test system.
It simplifies the testing process of the avionics control system, reduces the development cycle and complexity, improves the automation and versatility of the test system, and reduces the requirements for testers and equipment.
Smart Images
Figure CN222380012U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of avionics control system testing, in particular to an avionics control testing system based on FPGA and CAN bus. Background Art
[0002] With the rapid development of aviation and aerospace electronic technology, CAN bus has been widely used in avionics control systems. At present, most CAN buses used in avionics control systems are developed and used based on PowerPC, single-chip microcomputers and other controllers. For the functional testing of such avionics control systems, testers + test instruments are basically used to manually test functions and indicators.
[0003] The existing CAN bus development based on PowerPC, single-chip microcomputer and other controllers has a long development cycle, high complexity, poor versatility and high labor costs;
[0004] Due to the development of electronic technology, the functions of avionics control systems have become increasingly diversified and complex, and the requirements for testers, test instruments, and test environments have become increasingly higher. The manual testing method based on testers + test instruments is complex to operate, has a low degree of automation, and is not very versatile. Utility Model Content
[0005] In view of the problems of long development cycle, high complexity, poor versatility and low automation of the CAN bus of the existing test system, the utility model proposes an avionics control test system based on FPGA and CAN bus, which realizes data interaction between a host computer and an FPGA module by setting an RS422 interface module; realizes data interaction between the FPGA module and the avionics control system according to the CAN bus by setting a CAN interface module; realizes adjustment and detection of the avionics control system by setting a discrete line interface module; deframes the protocol frame of the test instruction by setting the FPGA module, and forwards it to the avionics control system through the CAN interface module; assembles the protocol frame of the return instruction, and forwards the return instruction to the host computer through the RS422 interface module; generates the excitation signal required by the avionics control system by parsing the test instruction, realizes discrete line control and detection of the avionics control system, and improves the automation and versatility of the test system.
[0006] The specific implementation contents of the utility model are as follows:
[0007] An avionics control test system based on FPGA and CAN bus, connected with a host computer and an avionics control system; including an FPGA module, an RS422 interface module, a CAN interface module, and a discrete line interface module;
[0008] One end of the RS422 interface module is connected to the host computer, and the other end is connected to the FPGA module;
[0009] One end of the CAN interface module is connected to the FPGA module, and the other end is connected to the avionics control system;
[0010] One end of the discrete line interface module is connected to the FPGA module, and the other end is connected to the avionics control system;
[0011] The RS422 interface module is used to perform data exchange between the host computer and the FPGA module according to the RS422 interface;
[0012] The CAN interface module is used to exchange data between the FPGA module and the avionics control system according to the CAN bus;
[0013] The discrete line interface module is used to adjust and detect the avionics control system according to the output instructions obtained from the FPGA module;
[0014] The FPGA module is used to deframe the protocol frame of the test instruction obtained from the host computer, and forward the deframed test instruction to the avionics control system through the CAN interface module; frame the protocol frame of the return instruction obtained from the CAN interface module and the discrete line interface module, and forward the framed return instruction to the host computer through the RS422 interface module.
[0015] In order to better implement the utility model, further, the FPGA module includes a serial port transceiver module, a frame de-framing module, and an instruction processing module;
[0016] One end of the serial port transceiver module is connected to the RS422 interface module, and the other end is connected to the de-framing and framing module via a FIFO interface;
[0017] The instruction processing module is connected with the discrete line module, the de-framing module and the CAN interface module;
[0018] The de-framing and framing module is connected with the CAN interface module and the discrete line interface module;
[0019] The serial port transceiver module is used to transmit the test instructions obtained from the host computer to the de-framing and framing module through the FIFO interface;
[0020] The de-framing module is used to de-frame the test instruction, and determine whether to forward it to the CAN interface module according to the de-framed instruction type and instruction content. If so, the de-framed instruction type and instruction content are forwarded to the CAN interface module, otherwise, they are forwarded to the instruction processing module; it is also used to frame the return instruction obtained from the CAN interface module, and forward the framed protocol frame to the host computer through the RS422 interface module;
[0021] The instruction processing module is used to determine the instruction type and instruction content obtained from the de-framing module, and determine the return instruction obtained from the discrete line interface module and the CAN interface module.
[0022] In order to better implement the utility model, further, the CAN interface module includes a CAN transceiver module and a CAN receive buffer module;
[0023] The CAN transceiver module is connected to the de-framing module via a FIFO interface and is connected to the avionics control system via a CAN bus;
[0024] The CAN receiving buffer module is connected to the de-framing and framing module via a FIFO interface, and is connected to the avionics control system via a CAN bus;
[0025] The CAN transceiver module is used to exchange data between the avionics control system and the de-framing and framing module through the FIFO interface;
[0026] The CAN receiving buffer module is used to store and count the feedback data obtained from the avionics control system, and determine the end time of receiving the feedback data by delay judgment, and forward the data content and counting length of the feedback data to the host computer through the deframing and framing module.
[0027] In order to better implement the utility model, further, the discrete line interface module includes a discrete line control module;
[0028] One end of the discrete line control module is connected to the instruction processing module, and the other end is connected to the avionics control system;
[0029] The discrete line control module is used to configure the discrete line output state of the discrete line interface module according to the discrete line output state control instruction obtained from the instruction processing module.
[0030] In order to better implement the utility model, further, the discrete line interface module also includes a discrete line detection module;
[0031] The discrete line detection module is connected to the avionics control system, the instruction processing module, and the de-framing and framing module;
[0032] The discrete line detection module is used to forward the discrete line detection status instruction obtained from the instruction processing module to the de-framing and framing module for framing in a byte-sorting manner, and forward the framed discrete line detection status instruction to the host computer.
[0033] In order to better implement the utility model, further, the CAN interface module is a CAN bus data transceiver; the CAN bus data transceiver is SN65HVD230.
[0034] In order to better implement the utility model, further, the RS422 interface module is a serial port transceiver; the serial port transceiver is a MAX3491 transceiver.
[0035] In order to better realize the utility model, further, the discrete line control module is a discrete line output simulator; the discrete line output simulator is an AD7303 analog-to-digital converter.
[0036] In order to better realize the utility model, further, the discrete line detection module is a discrete line isolator; the discrete line isolator is a SN74LVC16T245 transceiver.
[0037] In order to better implement the utility model, further, the avionics control test system based on FPGA and CAN bus also includes a storage unit, a clock unit, and a reset unit;
[0038] The storage unit is a FLASH memory, and the FLASH memory is connected to the FPGA module;
[0039] The clock unit is a 50MHz crystal oscillator, and the 50MHz crystal oscillator is connected to the clock pin of the FPGA module;
[0040] The reset unit is a CAT811 reset chip, and the CAT811 reset chip is connected to the reset pin of the FPGA module.
[0041] The utility model has the following beneficial effects:
[0042] (1) The utility model communicates with the host computer through the RS422 serial port and is responsible for generating control instructions, test instructions and printing test results; communicates with the avionics control system through the CAN bus and completes the work of setting up the test environment based on the host computer instructions, supporting communication functions, detecting and controlling the discrete line status, and reporting test results; the CAN bus is developed based on the FPGA platform and the mature IP core in the FPGA development tool, which shortens the development cycle of the CAN bus and improves the efficiency and versatility of the CAN bus. The technical requirements for developers are relatively low, and the reliability during operation is high, the testing is convenient, and the maintenance is simple.
[0043] (2) When testing the utility model, the test can be completed by simply operating the host computer to send test instructions and then observing the test results. It is simple and convenient to use and has low technical requirements for testers. It performs all-round automated testing on different functions of the avionics control system, ensuring the reliability of the test process and the accuracy of the test results. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 The utility model provides an overall schematic block diagram of the connection between the avionics control test system based on FPGA and CAN bus and the host computer and avionics control system.
[0045] Figure 2 A schematic diagram of a test case editing workflow provided by an embodiment of the utility model.
[0046] Figure 3 A schematic diagram of a test case workflow provided for an embodiment of the utility model.
[0047] Figure 4 A schematic diagram of a test flow of test instructions provided in an embodiment of the utility model.
[0048] Figure 5 A schematic diagram of a FLASH circuit provided in an embodiment of the utility model.
[0049] Figure 6 A schematic diagram of a FLASH circuit mode configuration circuit provided in an embodiment of the utility model.
[0050] Figure 7 A schematic diagram of a clock unit circuit provided in an embodiment of the utility model.
[0051] Figure 8 A schematic diagram of a reset unit circuit provided in an embodiment of the utility model.
[0052] Fig. 9 A schematic diagram of a first CAN bus data transceiver circuit provided in an embodiment of the utility model.
[0053] Fig.10 A schematic diagram of a second CAN bus data transceiver circuit provided in an embodiment of the utility model.
[0054] Fig.11 A schematic diagram of a first optocoupler isolator circuit provided in an embodiment of the utility model.
[0055] Fig.12 A schematic diagram of a second optocoupler isolator circuit provided in an embodiment of the utility model.
[0056] Fig.13 A schematic diagram of an RS422 serial port transceiver circuit provided in an embodiment of the utility model.
[0057] Fig.14 This is a circuit diagram of the first part of the discrete line simulator provided in an embodiment of the utility model.
[0058] Fig.15 This is a circuit diagram of the second part of the discrete line simulator provided in an embodiment of the utility model.
[0059] Fig.16 This is a circuit schematic diagram of the third part of the discrete line simulator provided in an embodiment of the utility model.
[0060] Fig.17 This is a circuit schematic diagram of the fourth part of the discrete line simulator provided in an embodiment of the utility model.
[0061] Fig.18 This is a circuit diagram of the fifth part of the discrete line simulator provided in an embodiment of the utility model.
[0062] Fig.19 This is a schematic diagram of the first circuit of the discrete line isolator provided in an embodiment of the utility model.
[0063] Fig. 20 This is a schematic diagram of the second circuit of the discrete line isolator provided in an embodiment of the utility model.
[0064] Fig.21 This is a schematic diagram of the third circuit of the discrete line isolator provided in an embodiment of the utility model.
[0065] Fig. 22 This is a schematic diagram of the fourth circuit of the discrete line isolator provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0066] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. It should be understood that the described embodiments are only part of the embodiments of the utility model, not all of the embodiments, and therefore should not be regarded as limiting the scope of protection. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technical personnel in this field without creative work are within the scope of protection of the utility model.
[0067] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0068] Embodiment 1:
[0069] This embodiment proposes an avionics control test system based on FPGA and CAN bus, which is connected to a host computer and an avionics control system; it includes an FPGA module, an RS422 interface module, a CAN interface module, and a discrete line interface module;
[0070] One end of the RS422 interface module is connected to the host computer, and the other end is connected to the FPGA module;
[0071] One end of the CAN interface module is connected to the FPGA module, and the other end is connected to the avionics control system;
[0072] One end of the discrete line interface module is connected to the FPGA module, and the other end is connected to the avionics control system;
[0073] The RS422 interface module is used to perform data exchange between the host computer and the FPGA module according to the RS422 interface;
[0074] The CAN interface module is used to exchange data between the FPGA module and the avionics control system according to the CAN bus;
[0075] The discrete line interface module is used to adjust and detect the avionics control system according to the output instructions obtained from the FPGA module;
[0076] The FPGA module is used to deframe the protocol frame of the test instruction obtained from the host computer, and forward the deframed test instruction to the avionics control system through the CAN interface module; frame the protocol frame of the return instruction obtained from the CAN interface module and the discrete line interface module, and forward the framed return instruction to the host computer through the RS422 interface module.
[0077] Working principle: This embodiment realizes data interaction between the host computer and the FPGA module by setting up the RS422 interface module; realizes data interaction between the FPGA module and the avionics control system according to the CAN bus by setting up the CAN interface module; realizes adjustment and detection of the avionics control system by setting up the discrete line interface module; deframes the protocol frame of the test instruction by setting up the FPGA module, and forwards it to the avionics control system through the CAN interface module; assembles the protocol frame of the return instruction, and forwards the return instruction to the host computer through the RS422 interface module; generates the excitation signal required by the avionics control system by parsing the test instruction, realizes discrete line control and detection of the avionics control system, realizes CAN communication with the avionics control system and RS422 communication with the host computer, and improves the automation and versatility of the test system.
[0078] This embodiment uses XC6SLX45-2CSG324I FPGA as the main processor. The FPGA has rich logic resources, DSP resources and RAM storage resources. It mainly completes CAN bus communication with the avionics control system, RS422 serial port communication with the host computer, parses the instructions of the host computer, generates the excitation signal required by the avionics control system, and controls and detects the discrete lines of the avionics control system.
[0079] This embodiment uses MAX3491 as the RS422 serial communication data transceiver, which has full-duplex communication function and a transmission rate of up to 10Mbps; this chip contains a driver and a receiver inside, the driver has short-circuit current limitation, and uses a thermal protection circuit to prevent excessive power consumption from causing the driver output to be in a high-impedance state; the receiver input has a fault protection function, and if both inputs are open, the output is always in a logic high state.
[0080] Embodiment 2:
[0081] This embodiment describes the specific structure of the FPGA module based on the above-mentioned embodiment 1.
[0082] The FPGA module includes a serial port transceiver module, a frame de-framing module, and an instruction processing module;
[0083] One end of the serial port transceiver module is connected to the RS422 interface module, and the other end is connected to the de-framing and framing module via a FIFO interface;
[0084] The instruction processing module is connected with the discrete line module, the de-framing module and the CAN interface module;
[0085] The de-framing and framing module is connected with the CAN interface module and the discrete line interface module;
[0086] Working principle: This embodiment sets a serial port transceiver module to transmit the test instructions obtained from the host computer to the deframing and framing module through the FIFO interface; sets the deframing and framing module to deframe the test instructions, and determines whether to forward them to the CAN interface module based on the deframed instruction type and instruction content. If so, the deframed instruction type and instruction content are forwarded to the CAN interface module, otherwise, they are forwarded to the instruction processing module; and frames the return instructions obtained from the CAN interface module, and forwards the framed protocol frame to the host computer through the RS422 interface module; sets the instruction processing module to determine the instruction type and instruction content obtained from the deframing and framing module, and determines the return instructions obtained from the discrete line interface module and the CAN interface module.
[0087] This embodiment uses the RS422 interface module as the main communication protocol processing unit, which includes a serial port transceiver module, a de-framing module, and a command processing module;
[0088] The serial port transceiver module mainly completes the serial port communication task with the host computer. This module interacts with the de-framing and framing module through the standard FIFO interface.
[0089] The de-framing module mainly completes the protocol de-framing and protocol framing tasks. When de-framing the protocol, this module is responsible for parsing the instruction type and instruction content from the complete protocol frame, and preliminarily determines whether it needs to be forwarded to the CAN interface module. If not, the instruction type and instruction content are forwarded to the instruction processing module; when framing the protocol, this module is responsible for receiving the return data from the CAN interface module or other modules and forming a complete protocol frame, and then forwarding it to the serial port transceiver module, and then transmitting it back to the host computer through the serial port;
[0090] The instruction processing module mainly completes the task of forwarding instruction content. It forwards the instruction content to the corresponding functional module by judging the instruction type, thereby achieving the purpose of forwarding without operating the instruction content.
[0091] The other parts of this embodiment are the same as those of the above-mentioned embodiment 1, and thus will not be described in detail.
[0092] Embodiment 3:
[0093] This embodiment, based on any one of the above-mentioned embodiments 1-2, takes the SN65HVD230 transceiver as an example to illustrate the specific structure of the CAN interface module.
[0094] The CAN interface module includes a CAN transceiver module and a CAN receive buffer module;
[0095] The CAN transceiver module is connected to the de-framing module via a FIFO interface and is connected to the avionics control system via a CAN bus;
[0096] The CAN receiving buffer module is connected to the de-framing and framing module via a FIFO interface, and is connected to the avionics control system via a CAN bus;
[0097] The CAN transceiver module is used to exchange data between the avionics control system and the de-framing and framing module through the FIFO interface;
[0098] The CAN receiving buffer module is used to store and count the feedback data obtained from the avionics control system, and determine the end time of receiving the feedback data by delay judgment, and forward the data content and counting length of the feedback data to the host computer through the deframing and framing module.
[0099] Working principle: This embodiment uses SN65HVD230 as the CAN bus data transceiver, and uses optical couplers to isolate the CAN bus and FPGA to avoid crosstalk between the bus and FPGA; the CAN bus is divided into two channels, CANA and CANB, which backup each other to ensure that when one of the channels fails, the system can still perform CAN bus communication.
[0100] This embodiment uses a CAN interface module as the main CAN bus communication unit, which includes a CAN transceiver module and a CAN receive buffer module;
[0101] The CAN transceiver module mainly completes the CAN bus communication task with the avionics control system. This module interacts with the de-framing and framing module through the standard FIFO interface.
[0102] The CAN receiving buffer module mainly completes the task of storing and counting the received data of the CAN bus. This module uses the standard FIFO to complete the data storage and counting, and determines the end time of data reception by delay judgment. The data content and count length are forwarded to the deframing and framing module for a series of operations such as framing, and then transmitted back to the host computer.
[0103] The other parts of this embodiment are the same as any one of the above-mentioned embodiments 1-2, so they will not be repeated here.
[0104] Embodiment 4:
[0105] This embodiment, based on any one of the above embodiments 1 to 3, takes the AD7303 simulator and the SN74LVC16T245 transceiver as examples to illustrate the specific structure of the offline line interface module.
[0106] The discrete line interface module includes a discrete line control module;
[0107] One end of the discrete line control module is connected to the instruction processing module, and the other end is connected to the avionics control system;
[0108] The discrete line control module is used to configure the discrete line output state of the discrete line interface module according to the discrete line output state control instruction obtained from the instruction processing module.
[0109] In order to better implement the utility model, further, the discrete line interface module also includes a discrete line detection module;
[0110] The discrete line detection module is connected to the avionics control system, the instruction processing module, and the de-framing and framing module;
[0111] The discrete line detection module is used to forward the discrete line detection status instruction obtained from the instruction processing module to the de-framing and framing module for framing in a byte-sorting manner, and forward the framed discrete line detection status instruction to the host computer.
[0112] Working Principle: This embodiment uses AD7303 as a discrete line output state simulator, which is a dual 8-bit voltage output DAC. The on-chip precision output buffer allows the DAC to output in a rail-to-rail manner. The device uses a 3-wire serial interface, runs at a clock rate of up to 30MHz, and is compatible with QSPI, SPI, Microwire, and digital signal processor interface standards.
[0113] This embodiment uses SN74LVC16T245 as an isolator for discrete line inputs, with configurable level shifting and tri-state outputs, and overvoltage tolerant inputs and outputs allowing mixed voltage mode data communications.
[0114] This embodiment uses a discrete line interface module as the main discrete line control and discrete line detection unit, which includes a discrete line control part and a discrete line detection part;
[0115] The discrete line control part is composed of some logic circuits and AD7303 control module. It mainly completes the task of controlling the output state of the discrete lines of the test platform. After receiving the discrete line state control instruction from the instruction processing module, it configures the output state of the logic circuit or the output state of AD7303 according to the instruction content.
[0116] The discrete line detection part mainly completes the task of detecting the discrete line status of the avionics control system. After receiving the discrete line status detection instruction from the instruction processing module, it detects the discrete line status of some parts according to the instruction content, and forwards it to the deframing and framing module in byte arrangement for a series of operations such as framing, and then sends it back to the host computer.
[0117] The other parts of this embodiment are the same as any one of the above-mentioned embodiments 1 to 3, so they will not be repeated here.
[0118] Embodiment 5:
[0119] In this embodiment, based on any one of the above-mentioned embodiments 1 to 4, the avionics control test system based on FPGA and CAN bus further includes a storage unit, a clock unit and a reset unit mounted on the FPGA module;
[0120] The storage unit is a FLASH memory, and the FLASH memory is connected to the FPGA module;
[0121] The clock unit is a 50MHz crystal oscillator, and the 50MHz crystal oscillator is connected to the clock pin of the FPGA module;
[0122] The reset unit is a CAT811 reset chip, and the CAT811 reset chip is connected to the reset pin of the FPGA module.
[0123] Working principle: This embodiment uses a 64M-byte SPI FLASH, mounted under the FPGA, as the memory for FPGA initialization configuration; uses a 50MHz crystal oscillator, mounted under the global clock tube foot of the FPGA, as the system clock signal for the FPGA; uses a CAT811 reset chip, mounted under the global reset tube foot of the FPGA, as the system reset signal for the FPGA.
[0124] The other parts of this embodiment are the same as any one of the above-mentioned embodiments 1 to 4, so they are not repeated here.
[0125] Embodiment 6:
[0126] This embodiment is based on any one of the above embodiments 1 to 5. Figure 1 , Figure 2 , Figure 3 As shown, a specific embodiment is used to describe in detail the test process of the avionics control test system based on FPGA and CAN bus.
[0127] This embodiment communicates with the host computer through the RS422 serial port and is responsible for generating control instructions, test instructions and printing test results; FPGA, as an auxiliary unit, is a device for the avionics control system. It communicates with the avionics control system through the CAN bus and is responsible for completing tasks such as setting up the test environment based on the host computer instructions, communication function support, discrete line status detection and control, and reporting of test results.
[0128] In order to better illustrate the test process, a specific protocol frame is taken as an example. The protocol frame definition is shown in Table 1, and the protocol instruction type and instruction content are shown in Table 2.
[0129] Table 1 Protocol frame definition table
[0130]
[0131] Among them, all protocol frames are represented by hexadecimal numbers; the frame header is a fixed starting value; the frame length is the length of the instruction, and the FPGA receives the instruction content according to the length of the instruction; the frame type is the type of instruction, and the FPGA forwards the instruction content according to the type of instruction; the frame data is the content of the instruction, and the FPGA performs corresponding functional operations according to the content of the instruction; the frame tail is a fixed end value.
[0132] Table 2 Protocol definition of command type and command content
[0133]
[0134]
[0135] This embodiment uses serial communication to communicate with the host computer. After the test case file is input into the host computer, the host computer executes the steps set in the test case and the order in which the test cases are arranged to complete the automatic test.
[0136] The test case consists of multiple steps, each of which consists of optional instruction type, sending protocol type, frame information, sending data and judgment conditions, sending waiting time, and instruction description; the optional instructions include four types: single send, single receive, send and wait, and single wait; the sending protocol type includes CAN type and LVDS type; the frame information includes frame header, frame type, optional frame length, optional CRC and frame tail; the sending data consists of hexadecimal numbers, and the length and value can be freely edited; the judgment condition consists of hexadecimal numbers, and the judgment range can be formed by setting the maximum and minimum values.
[0137] By setting the content of each step of the test case and arranging the order of the steps reasonably, automatic testing of any function can be achieved.
[0138] Describe the test system usage process.
[0139] The tester correctly connects the avionics control system to the test platform, correctly connects the host computer to the test platform via a serial port line, and then correctly connects the power supply and starts it.
[0140] The tester turns on the host computer, then opens the host computer serial port, sets the serial port baud rate to 115200, data bits to 8 bits, stop bits to 1 bit, check bits to none, and clicks on the serial port connection.
[0141] The tester opens the test case corresponding to the avionics control system. If there is no test case, you can edit it according to the needs, then click Start Test, wait for the test system to complete the automatic test, and the host computer will display all test cases and the test results of each step; when the test result is displayed as Passed, it means that the test result meets the judgment conditions and the test passes; when the test result is displayed as Failed, it means that the test result does not meet the judgment conditions and the test fails. You can view the specific return value through the log window of the host computer and perform error analysis on the failed items.
[0142] Use the host computer to edit the test case; select the instruction type: send, select the sending protocol type: CAN, set the frame information: frame header 7E, type B1, frame tail ED, check the data length, and set the sending data to 30; after completing the test case, click Start Test to set the MARK address of the test platform to 30.
[0143] Use the host computer to edit the test case; select the command type: send, select the sending protocol type: CAN, set the frame information: frame header 7E, type 61, frame tail ED, check the data length, and set the sending data to: 66 99; after completing the test case, click Start Test to set the two outputs of the first AD7303 of the test platform, i.e. FPGA, to 3V and 2V respectively.
[0144] Use the host computer to edit the test case; select the command type: send and wait for response, select the sending protocol type: CAN, frame information settings: frame header 7E, type 01, frame tail ED, check the data length, send data settings: 01 50 09 00 070101; after completing the test case, click Start Test, the test platform will send data to the avionics control system through the CAN bus, read the electronic tag of the avionics control system and send it back to the host computer.
[0145] Use the host computer to edit the test cases; arrange multiple completed test cases in order, and insert a test case with the instruction type of waiting and the time of 500ms between each test case; after completing the test case, click Start Test, and the host computer will execute all test cases in the order of arrangement and display the test results of each test case.
[0146] The other parts of this embodiment are the same as any one of the above-mentioned embodiments 1 to 5, so they are not repeated here.
[0147] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.
Claims
1. An avionics control test system based on FPGA and CAN bus, connected to a host computer and an avionics control system; characterized in that: Including FPGA module, RS422 interface module, CAN interface module, discrete line interface module; One end of the RS422 interface module is connected to the host computer, and the other end is connected to the FPGA module; One end of the CAN interface module is connected to the FPGA module, and the other end is connected to the avionics control system; One end of the discrete line interface module is connected to the FPGA module, and the other end is connected to the avionics control system; The RS422 interface module is used to perform data exchange between the host computer and the FPGA module according to the RS422 interface; The CAN interface module is used to exchange data between the FPGA module and the avionics control system according to the CAN bus; The discrete line interface module is used to adjust and detect the avionics control system according to the output instructions obtained from the FPGA module; The FPGA module is used to deframe the protocol frame of the test instruction obtained from the host computer, and forward the deframed test instruction to the avionics control system through the CAN interface module; frame the protocol frame of the return instruction obtained from the CAN interface module and the discrete line interface module, and forward the framed return instruction to the host computer through the RS422 interface module.
2. The avionics control test system based on FPGA and CAN bus according to claim 1, characterized in that: The FPGA module includes a serial port transceiver module, a frame de-framing module, and an instruction processing module; One end of the serial port transceiver module is connected to the RS422 interface module, and the other end is connected to the de-framing and framing module via a FIFO interface; The instruction processing module is connected with the discrete line interface module, the de-framing module and the CAN interface module; The de-framing and framing module is connected with the CAN interface module and the discrete line interface module; The serial port transceiver module is used to transmit the test instructions obtained from the host computer to the de-framing and framing module through the FIFO interface; The de-framing module is used to de-frame the test instruction, and determine whether to forward it to the CAN interface module according to the de-framed instruction type and instruction content. If so, the de-framed instruction type and instruction content are forwarded to the CAN interface module, otherwise, they are forwarded to the instruction processing module; it is also used to frame the return instruction obtained from the CAN interface module, and forward the framed protocol frame to the host computer through the RS422 interface module; The instruction processing module is used to determine the instruction type and instruction content obtained from the de-framing module, and determine the return instruction obtained from the discrete line interface module and the CAN interface module.
3. The avionics control test system based on FPGA and CAN bus according to claim 2, characterized in that: The CAN interface module includes a CAN transceiver module and a CAN receive buffer module; The CAN transceiver module is connected to the de-framing module via a FIFO interface and is connected to the avionics control system via a CAN bus; The CAN receiving buffer module is connected to the de-framing and framing module via a FIFO interface, and is connected to the avionics control system via a CAN bus; The CAN transceiver module is used to exchange data between the avionics control system and the de-framing and framing module through the FIFO interface; The CAN receiving buffer module is used to store and count the feedback data obtained from the avionics control system, and determine the end time of receiving the feedback data by delay judgment, and forward the data content and counting length of the feedback data to the host computer through the deframing and framing module.
4. The avionics control test system based on FPGA and CAN bus according to claim 2, characterized in that: The discrete line interface module includes a discrete line control module; One end of the discrete line control module is connected to the instruction processing module, and the other end is connected to the avionics control system; The discrete line control module is used to configure the discrete line output state of the discrete line interface module according to the discrete line output state control instruction obtained from the instruction processing module.
5. The avionics control test system based on FPGA and CAN bus according to claim 4, characterized in that: The discrete line interface module also includes a discrete line detection module; The discrete line detection module is connected to the avionics control system, the instruction processing module, and the de-framing and framing module; The discrete line detection module is used to forward the discrete line detection status instruction obtained from the instruction processing module to the de-framing and framing module for framing in a byte-sorting manner, and forward the framed discrete line detection status instruction to the host computer.
6. The avionics control test system based on FPGA and CAN bus according to claim 1, characterized in that: The CAN interface module is a CAN bus data transceiver; the CAN bus data transceiver is SN65HVD230.
7. The avionics control test system based on FPGA and CAN bus according to claim 1, characterized in that: The RS422 interface module is a serial port transceiver; the serial port transceiver is a MAX3491 transceiver.
8. The avionics control test system based on FPGA and CAN bus according to claim 4, characterized in that: The discrete line control module is a discrete line output simulator; the discrete line output simulator is an AD7303 analog-to-digital converter.
9. The avionics control test system based on FPGA and CAN bus according to claim 5, characterized in that: The discrete line detection module is a discrete line isolator; the discrete line isolator is a SN74LVC16T245 transceiver.
10. The avionics control test system based on FPGA and CAN bus according to any one of claims 1 to 9, characterized in that: The avionics control test system based on FPGA and CAN bus also includes a storage unit, a clock unit, and a reset unit; The storage unit is a FLASH memory, and the FLASH memory is connected to the FPGA module; The clock unit is a 50MHz crystal oscillator, and the 50MHz crystal oscillator is connected to the clock pin of the FPGA module; The reset unit is a CAT811 reset chip, and the CAT811 reset chip is connected to the reset pin of the FPGA module.