Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes a substrate having a circuit region and a seal ring region surrounding the circuit region; a plurality of first active regions having a first width and disposed in the circuit region; a plurality of second active regions having a second width and disposed in the seal ring region; a plurality of first gate structures disposed on the first active region; the plurality of second gate structures are disposed on a plurality of longitudinal edges of the second active region. The first gate structure is longitudinally oriented to be orthogonal to the first active region. The second gate structure is longitudinally oriented to be parallel to the second active region. The second width is greater than the first width.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor structure, and in particular to a sealing ring structure of a multi-gate device. Background Art

[0002] In semiconductor technology, semiconductor wafers are processed through various manufacturing steps to form integrated circuits (ICs). Typically, several circuits or IC dies are formed on the same semiconductor wafer. The wafer is then diced to cut out the circuits formed thereon. To protect the circuits from moisture degradation, ion contamination, and the effects of the dicing process, a seal ring is formed around each circuit die. This seal ring is formed during the manufacture of the many layers that comprise the circuits, including the front-end-of-line (FEOL) process, the middle-end-of-line (MEOL) structure, and the back-end-of-line (BEOL) process. The FEOL and MEOL include forming transistors, capacitors, diodes, and / or resistors on a semiconductor substrate. The BEOL includes forming metal layer interconnects and vias to provide routing for the FEOL components.

[0003] Although existing seal ring structures and methods of manufacturing the same generally meet their intended purposes, improvements are still needed. For example, the seal ring structure is not robust and cannot provide protection for the circuit device. For at least these reasons, improvements are needed to the seal ring structure and methods of manufacturing the same to address these problems. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0005] An embodiment of the utility model provides a semiconductor structure, including a substrate having a circuit area and a sealing ring area surrounding the circuit area; a plurality of first active areas having a first width and arranged in the circuit area; a plurality of second active areas having a second width and arranged in the sealing ring area, wherein the second width is greater than the first width; a plurality of first gate structures arranged on the first active area, wherein the first gate structures are longitudinally oriented to be orthogonal to the first active area; and a plurality of second gate structures arranged on a plurality of longitudinal edges of the second active area, wherein the second gate structures are longitudinally oriented to be parallel to the second active area.

[0006] According to one embodiment of the present invention, a ratio of the second width to the first width ranges from 1.1 to 5.

[0007] According to one embodiment of the present invention, the plurality of first gate structures have a third width, and the plurality of second gate structures have a fourth width, and the fourth width is substantially equal to the third width.

[0008] According to one embodiment of the present invention, it also includes: a plurality of contact structures, which are arranged on the plurality of second active areas and completely landed on the plurality of second active areas, wherein the plurality of contact structures land on the plurality of second active areas with a plurality of boundaries, so that the plurality of longitudinal edges of each contact structure are located within the plurality of longitudinal edges of a corresponding one of the plurality of second active areas.

[0009] According to one embodiment of the present invention, each second active region is a continuous ring-shaped structure surrounding the circuit region, and each second gate structure is a continuous ring-shaped structure surrounding the circuit region.

[0010] According to one embodiment of the utility model, it also includes: a plurality of third active areas, arranged in a plurality of corner areas of the sealing ring area, wherein the plurality of third active areas are arranged in segments; and a plurality of third gate structures, arranged on a plurality of edges of the plurality of third active areas, wherein each third gate structure completely surrounds a corresponding one of the plurality of third active areas.

[0011] An embodiment of the utility model provides a semiconductor structure, comprising an active region, which extends longitudinally in a first direction in the region of the semiconductor structure; a first gate structure, which is arranged on a first edge of the active region, and the first gate structure extends longitudinally in the first direction in the region of the semiconductor structure; a second gate structure, which is arranged on a second edge of the active region, the second edge is relative to the first edge, and the second gate structure extends longitudinally in the first direction in the region of the semiconductor structure; and a contact structure, which completely lands on the active region, and the contact structure extends longitudinally in the first direction in the region of the semiconductor structure.

[0012] According to one embodiment of the present invention, each of the active area, the first gate structure, the second gate structure, and the contact structure is annular, wherein the ring shape of the contact structure completely surrounds the ring shape of the first gate structure, and the ring shape of the second gate structure completely surrounds the ring shape of the contact structure.

[0013] According to one embodiment of the present invention, it also includes: an isolation component surrounding the active area; and a third gate structure completely disposed on the isolation component, the third gate structure extending longitudinally in the first direction in the region of the semiconductor structure, and the first gate structure and the third gate structure sandwich the second gate structure.

[0014] According to one embodiment of the present invention, the contact structure is a first contact structure, and the semiconductor structure also includes: an isolation component surrounding the active area; and a second contact structure completely disposed on the isolation component, the second contact structure extending longitudinally in the first direction in the region of the semiconductor structure, and the first contact structure and the second contact structure clamp the second gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present invention are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, the sizes of various components may be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0016] Figure 1 is a schematic top view of a semiconductor structure according to various aspects of the present disclosure.

[0017] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A as well as Figure 5B 1 and 2 are schematic top views of region A, region B, and region C of the semiconductor structure 100 according to various aspects of the present disclosure.

[0018] Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A as well as Fig. 9B According to various aspects of the present disclosure, Figure 1 A schematic cross-sectional view of the semiconductor structure in region A and region B.

[0019] Fig.10 According to various aspects of the present disclosure, it is shown that Figure 1 Schematic diagram of a process for producing a semiconductor structure in a semiconductor device.

[0020] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 as well as Fig.21 According to various aspects of the present disclosure, Fig.10A schematic cross-sectional view of a semiconductor structure during a manufacturing process of the method.

[0021] The reference numerals are as follows:

[0022] 1-1': Section line

[0023] 2-2': Section line

[0024] 3-3': Section line

[0025] 4-4': Section line

[0026] 100:Semiconductor structure

[0027] 102: Circuit area

[0028] 104: Closed loop area

[0029] 106: Closed loop structure

[0030] 108:Inner corner area

[0031] 110:Outer corner area

[0032] 202:Substrate

[0033] 204: Epitaxial stacking

[0034] 206: epitaxial layer

[0035] 208: Epitaxial layer

[0036] 220: Active area

[0037] 222: Channel layer

[0038] 223: Sacrificial layer

[0039] 224: Source / drain component

[0040] 224a: buffer epitaxial layer

[0041] 224b: Insulating film

[0042] 224c: Upper epitaxial layer

[0043] 226: Source / drain groove

[0044] 230: Isolation Structure

[0045] 238: Virtual gate structure

[0046] 240: Gate structure

[0047] 242: Gate spacer

[0048] 244:Internal spacer

[0049] 250:ILD layer

[0050] 250a: Lower ILD layer

[0051] 250b: Upper ILD layer

[0052] 260: Contact structure

[0053] 270: Etching stop layer

[0054] 272: Dielectric layer

[0055] 274: Insulation layer

[0056] 282: Source / drain contact vias

[0057] 284: Gate contact

[0058] 286:Metal Wire

[0059] 288: Guide hole

[0060] 320: Active area

[0061] 322: Channel component

[0062] 323: Sacrificial layer

[0063] 324: Source / drain component

[0064] 324a: buffer epitaxial layer

[0065] 324b: Insulation film

[0066] 324c: Upper epitaxial layer

[0067] 326: Source / drain groove

[0068] 330: Isolation Structure

[0069] 338: Virtual gate structure

[0070] 340: Gate structure

[0071] 340d: Virtual gate structure

[0072] 342: Gate spacer

[0073] 344:Internal spacer

[0074] 350:ILD layer

[0075] 350a: Lower ILD layer

[0076] 350b: Upper ILD layer

[0077] 360: Contact structure

[0078] 360d: Virtual contact structure

[0079] 370: Etching stop layer

[0080] 372: Dielectric layer

[0081] 374: Insulation layer

[0082] 382: Source / drain contact vias

[0083] 386:Metal Wire

[0084] 388: Guide hole

[0085] 400:Method

[0086] 402,404,406: Operation

[0087] 408,410,412: Operation

[0088] 414,416,418: Operation

[0089] A: Area

[0090] B: Area

[0091] C: Region

[0092] D0: Width

[0093] P1: First pitch

[0094] P2: Second pitch

[0095] W1: First width

[0096] W2: Second width

[0097] W3: Width

[0098] W4: Width

[0099] W c :width

[0100] X: Direction

[0101] Y: direction

[0102] Z: Direction DETAILED DESCRIPTION

[0103] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the utility model. Of course, these are merely examples and are not intended to limit the embodiments of the utility model. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the utility model may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0104] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "higher" and the like, to facilitate description of the relationship between one (or some) parts or features and another (or some) parts or features in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation. Furthermore, when "approximately", "approximately", etc. are used to describe a number or a range of numbers, this term is intended to cover numbers within a reasonable range, which is based on the variations inherent in the manufacturing process understood by those skilled in the art. For example, based on the known manufacturing tolerances for manufacturing parts having the features related to the number, the number or range of numbers covers a reasonable range including the number, such as within + / -10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with deposited material layers is + / - 10%, and a material layer having a thickness of "about 5 nanometers" may cover a size range of 4.5 nanometers to 5.5 nanometers, or a size range of 4.0 nanometers to 5.0 nanometers, etc.

[0105] A semiconductor substrate, such as an integrated circuit chip, includes a circuit area surrounded by a seal ring area. The seal ring area provides protection for the integrated circuit in the circuit area from various environmental damages, such as moisture and chemicals. The seal ring structure includes a plurality of film layers extending vertically from the substrate, through the interconnect structure, and up to the passivation layer. The seal ring structure can be formed simultaneously with the circuit components in the circuit area (or circuit region, chip region, device region, chip die) through various manufacturing stages, such as in the front-end (FEOL) structure, the middle-end (MEOL) structure, and / or the back-end (BEOL) structure. As used herein, the FEOL structure includes the structural components of the transistor or other semiconductor device manufactured on the semiconductor substrate; the MEOL structure includes the source / drain contact via or the gate contact via; and the BEOL structure includes the interconnect structure and the passivation structure above the interconnect structure. In the BEOL process, the wires or vias are formed in a plurality of metal layers stacked above the semiconductor substrate to connect various components in the circuit area. At the same time, conductive rings and via rings are formed in the seal ring area of ​​each metal layer. Elements in the seal ring area, such as transistors, conductive rings, and via rings, do not provide electrical functions to the semiconductor structure like their counterparts in the circuit area. Instead, the elements in the seal ring area seal and protect the circuit area from moisture, mechanical stress, or other defect generation mechanisms. The difference in functionality causes the seal ring area to have different characteristics than the circuit area, such as pattern size and / or pattern density. The difference in characteristics may cause processing problems, such as dishing in chemical mechanical planarization (CMP) processing, especially in the area between the seal ring area and the circuit area, and / or uneven etching in etching processes.

[0106] The present disclosure relates to a semiconductor structure and a manufacturing process thereof, and in particular to a sealing ring area of ​​a semiconductor structure and a manufacturing process thereof. The sealing ring area is designed to have appropriate characteristics (e.g., appropriate line width, line pitch, and / or line pattern density) that help buffer the difference between the circuit area and the sealing ring area, thereby providing a smooth transition from the circuit area to the sealing ring area. The smooth transition alleviates process problems, such as recesses during subsequent CMP processing and / or uneven etching during subsequent etching processes. It should be understood by those skilled in the art to which the present invention belongs that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein.

[0107] Figure 11 is a schematic top view of a semiconductor structure 100 according to the present disclosure. The semiconductor structure 100 (such as a manufactured wafer or a portion of a wafer) includes a circuit area 102 surrounded by a seal ring area 104. In some embodiments, the semiconductor structure 100 may include other seal ring areas surrounding the seal ring area 104 or other seal ring areas surrounded by the seal ring area 104. In addition, the seal ring area 104 may surround other circuit areas. The circuit area 102 may include any circuit, such as a memory, a processor, a transmitter, a receiver, etc. The specific function of the circuit area 102 is not limited by the present disclosure.

[0108] In an embodiment of the present invention, the sealing ring area 104 includes a sealing ring structure 106, which has a rectangular or substantially rectangular periphery that completely surrounds the circuit area 102. The four corners of the rectangular periphery are replaced by bevel lines connecting adjacent edges of the rectangle. In an embodiment of the present invention, each bevel line is substantially 45° to the direction X. The sealing ring area 104 also includes four inner corner areas 108, which are arranged along the corresponding bevel lines and are located between the sealing ring structure 106 and the circuit area 102. The sealing ring area 104 also includes four outer corner areas 110, which are arranged at the corners of the sealing ring area 104. Each outer corner area 110 is arranged outside the sealing ring structure 106 and is arranged along the corresponding bevel line. The inner corner area 108 and the outer corner area 110 provide further mechanical strength for the sealing ring area 104. The outer corner area 110 is substantially triangular and the inner corner area 108 is substantially trapezoidal. In some embodiments, the seal ring structure 106 may provide openings at selected locations and / or in selected film layers to allow the circuit region 102 to be connected to the circuit region 102. Figure 1 In some embodiments, the seal ring region 104 may have a non-rectangular shape.

[0109] Figure 2 yes Figure 1An enlarged schematic top view of region A in the circuit region 102 is shown. The circuit region 102 includes a plurality of active regions 220 oriented longitudinally along a direction X, an isolation structure 230 disposed between and separating the active regions 220, a gate structure 240 oriented longitudinally along a direction Y and spanning the active regions 220, and a contact structure 260 oriented longitudinally along the direction Y and spanning the active regions 220. The above elements form a matrix, and transistors are formed in the intersections between the active regions 220 and the gate structures 240. The transistors may be planar metal-oxide-semiconductor field effect transistors (MOSFETs) or multi-gate transistors. A multi-gate device generally refers to a device having a gate structure or a portion of a gate structure disposed above one or more sides of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular. FinFETs have an elevated channel that is wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors can also be called surrounding gate transistors (SGT) or gate-all-around (GAA) transistors. The active region can be an "oxide-definition (OD) region" that forms the source, drain, and channel under the gate of the transistor. In a multi-gate device, the active region 220 can be a continuous active region that protrudes from the substrate like a "fin", or a set of channel layers (channel components) that are vertically stacked to form a fin shape and suspended above the substrate, so that the top surface of the active region 220 is located above the top surface of the isolation structure 230. The active region 220 in a multi-gate device is also called a fin-shaped active region. The isolation structure 230 surrounds each active region 220 to separate and isolate the various active regions 220 from each other.

[0110] It is worth noting that although Figure 2 The active region 220 and the gate structure 240 in FIG. 1 are shown to extend continuously along the direction X or the direction Y, but they may be divided into a plurality of segments by dielectric members according to the circuit design of the semiconductor structure 100 .

[0111] Figure 3A yes Figure 1 The enlarged schematic top view of the region B in the seal ring region 104 is shown. The seal ring region 104 includes active regions (e.g., fin-shaped active regions) 320 arranged longitudinally along the direction Y, isolation structures 330 arranged between and separating the active regions 320, gate structures 340 arranged longitudinally along the direction Y, and contact structures 360 arranged above the active regions 320 and longitudinally along the direction Y. Back to Figure 1 , each of the active area 320, the gate structure 340, the contact structure 360, and the isolation structure 330 forms a continuous ring that completely surrounds the circuit region 102, and thus may be referred to as an active area ring 320, a gate ring 340, a contact ring 360, and an isolation ring 330. Each of the active area ring 320, the gate ring 340, the contact ring 360, and the isolation ring 330 substantially concentrically surrounds (or completely surrounds) the circuit region 102 and extends substantially parallel to each other.

[0112] Figure 3B yes Figure 1 An enlarged schematic top view of region C in the seal ring region 104 is shown. The active region 320, isolation structure 330, gate structure 340, and contact structure 360 ​​in the corner are longitudinally oriented at an inclined angle (e.g., 45° to direction X) such that those elements in the seal ring structure 106 are connected to adjacent elements to form a continuous ring. Figure 3B , the other active regions 320 for filling the outer corner regions 110 and the inner corner regions 108 are segmented.

[0113] The seal ring area 104 may include elements of FinFET transistors, elements of GAA transistors, other types of transistors, and combinations thereof. The elements of the transistors in the seal ring area 104 are formed simultaneously with the transistors in the circuit area 102 and have the same transistor type as the circuit area 102. For example, if the circuit area 102 includes FinFET transistors, the seal ring area 104 includes elements that are similar to and correspond to the FinFET transistors. In another example, if the circuit area 102 includes GAA transistors, the seal ring area 104 includes elements that are similar to and correspond to the elements in the GAA transistors.

[0114] See together Figure 2 and Figure 3A as well as Figure 3B, the active area 220 in the circuit area 102 has a first width W1 and the active area 320 in the seal ring area 104 has a second width W2 different from the first width W1. In particular, the second width W2 is substantially greater than the first width W1. In some embodiments, the first width W1 ranges from 0.02μm to 0.08μm; the second width W2 ranges from 0.04μm to 0.16μm. The ratio of W2 / W1 ranges from about 1.1 to about 5. This range is not insignificant. If the ratio of W2 / W1 is greater than about 5, the widths of the active areas in the circuit area 102 and the seal ring area 104 will have significant differences, and this non-uniformity may cause a recess effect in a subsequent planarization process (e.g., a CMP process), especially in the area between the seal ring area 104 and the circuit area 102. If the ratio of W2 / W1 is less than about 1.1, in the subsequent BEOL process, the width of the active area 320 in the seal ring area 104 is insufficient to support a conductive ring and a via ring with sufficient width formed thereon, so that the protection function of the seal ring structure against environmental damage, such as moisture and chemicals, is impaired.

[0115] The active area 220 in the circuit area 102 has a first pitch P1 and the active area 320 in the seal ring area 104 has a second pitch P2 that is different from the first pitch P1. In particular, the second pitch P2 is substantially greater than the first pitch P1. In some embodiments, the first pitch P1 ranges from 0.05 μm to 0.2 μm; and the second pitch P2 ranges from 0.1 μm to 0.4 μm. The ratio of P2 / P1 ranges from about 1.1 to about 5. This range is not insignificant. If the ratio of P2 / P1 is greater than about 5, the active area density in the circuit area 102 and the seal ring area 104 will have a significant difference, and this non-uniformity may cause a recess effect in a subsequent planarization process (e.g., a CMP process), especially in the area between the seal ring area 104 and the circuit area 102. If the ratio of P2 / P1 is less than about 1.1, adjacent active regions in the seal ring area 104 are too close to each other, so that the conductive ring and via ring formed thereon in the subsequent BEOL process are not wide enough and the protection function of the seal ring structure against environmental damage, such as moisture and chemicals, is impaired.

[0116] The first width W1 and the first pitch P1 together define a first active area antenna density in the circuit area 102, and the second width W2 and the second pitch P2 together define a second active area antenna density in the seal ring area 104. Figure 3AFor example, the active area antenna density is calculated as the area occupied by the segment of active area 320 within region B (dashed box) divided by the total area of ​​region B. In some embodiments, each of the first active area antenna density and the second active area antenna density ranges from about 20% to about 60%. Specifically, the difference between the first active area antenna density and the second active area antenna density is within 10%. For example, if the first active area antenna density is about 40% (of region A), the second active area antenna density ranges from about 30% to about 50% (of region B). Maintaining the difference between the first active area antenna density and the second active area antenna density within 10% is not arbitrary. If the difference exceeds 10%, the active area densities in the circuit area 102 and the seal ring area 104 will have significant differences. This non-uniformity may cause a recess effect in a subsequent planarization process (e.g., a CMP process), especially in the area between the seal ring area 104 and the circuit area 102. In addition, in a subsequent etching process, over etching may occur in the area with lower density.

[0117] The active area 320 in the seal ring area 104 is more different in continuity from the active area 220 in the circuit area 102. Depending on the individual circuits and design layout, the active area 220 in the circuit area 102 is discontinuous and segmented. However, the active area 320 in the seal ring area 104 extends continuously around the circuit area 102. Figure 3A Three (3) active areas 320 are shown in the seal ring area 104, each extending continuously in a ring shape. Figure 3B Further shown is one (1) segmented active region 320 in the inner corner region 108 and one (1) segmented active region 320 in the outer corner region 110. It is worth noting that the number of continuous and segmented active regions 320 in the seal ring region 104 is not limited to Figure 3A as well as Figure 3B The number shown in , and may include any appropriate number, depending on the individual circuit and design.

[0118] The contact structure 260 in the circuit area 102 is longitudinally oriented in direction Y, which is generally perpendicular to the orientation of the active area 220 in the circuit area 102 (direction X). In contrast, the contact structure 360 ​​in the seal ring area 104 is longitudinally oriented along direction Y, which is parallel to the orientation of the active area 320 in the seal ring area 104 (direction Y). In addition, the contact structure 360 ​​is completely landed on the corresponding active area 320. For example, the contact structure 360 ​​lands in the center of the active area 320 and leaves a margin on both sides, such as leaving an equal margin on both sides. In this case, the width W of the contact structure 360 ​​is cis smaller than the second width W2 of the active region 320. In some embodiments, W2 / W c The ratio of is in the range of about 1.5 to about 2. The configuration of the contact structure 360 ​​and the active area 320 in the seal ring area 104 makes the seal ring structure more robust. The continuity from the active area 320 to the contact structure 360 ​​provides a better sealing effect. In some embodiments, since the active area 320 in the seal ring area 104 is relatively wide, the width of the contact structure 360 ​​in the seal ring area 104 is greater than the width of the contact structure 260 in the circuit area 102.

[0119] The gate structures 240 in the circuit region 102 are oriented longitudinally in a direction Y, which is generally perpendicular to the orientation of the active regions 220 in the circuit region 102 (direction X). In contrast, the gate structures 340 in the seal ring region 104 are oriented longitudinally in a direction Y, which is parallel to the orientation of the active regions 320 in the seal ring region 104 (direction Y). In addition, the gate structures 340 land on (or cover) the edges of the corresponding active regions 320 (shown as Figure 3A as well as Figure 3B ). For the active area ring 320, the first gate ring 340 lands on the inner edge of the active area ring 320 and overlaps the inner part of the top surface of the active area ring 320 in the top view schematic diagram, while the second gate ring 340 lands on the outer edge of the active area ring 320 and overlaps the outer part of the top surface of the active area ring 320. The second gate ring 340 surrounds (or completely surrounds) the first gate ring 340. Each of the first and second gate rings 340 overlaps the corresponding edge portion of the active area ring 320 by a width D0 of about 5 nm to about 15 nm. For the segmented active area 320 in the inner corner region 108 or the outer corner region 110, the gate ring 340 lands on all four edges of the segmented active area 320 and partially overlaps the edge portion of the segmented active area 320, so that in the top view schematic diagram, the gate ring 340 surrounds (or completely surrounds) the segmented active area 320. The gate ring 340 overlaps each edge portion of the corresponding segmented active area ring 320 by a width D0 of about 5 nm to about 15 nm.

[0120] In an embodiment of the present invention, the gate structure 240 in the circuit area 102 and the gate structure 340 in the seal ring area 104 are formed simultaneously with the same composition, such as by gate replacement. For example, the gate structure 240 and the gate structure 340 include a gate dielectric layer (such as an interface layer and a high dielectric constant dielectric material layer) and a gate electrode (such as a metal material further including a work function metal layer and a filling metal layer). For a GAA transistor, the active area includes a plurality of vertically stacked channel layers, each of which is surrounded by a gate structure. During the gate replacement process, in the circuit area, the sacrificial layer stacked between adjacent channel layers is removed to leave space for the gate structure to be filled. Since in the seal ring area 104, the gate structure 340 extends longitudinally in the same direction as the active area 320, the gate structure 340 is deposited on the edge of the active area 320, so that the gate structure 340 only partially overlaps the active area 320, allowing the sacrificial layer in the seal ring area 104 and the circuit area 102 to be removed. This configuration allows for uniform material composition in the active regions in both the circuit region 102 and the seal ring region 104. The uniformity of material composition effectively mitigates over-etching and recessing effects in subsequent planarization processes (e.g., CMP processes), especially in the region between the seal ring region 104 and the circuit region 102. This configuration also allows for relatively larger source / drain region widths and thus relatively wider contact structures 360 in the seal ring region 104, which provides a more robust seal ring structure to resist external stress and moisture.

[0121] The gate structure 240 in the circuit region 102 has a width W3, and the gate structure 340 in the seal ring region 104 has a width W4 substantially the same as the width W3 (W3=W4). The first gate structure antenna density in the circuit region 102 is substantially similar to the second gate structure antenna density in the seal ring region 104. Figure 3AFor example, the gate structure antenna density is calculated as the area occupied by the segment of the gate structure 340 within the region B (dashed box) divided by the total area of ​​the region B. In some embodiments, each of the first and second gate structure antenna densities ranges from about 10% to about 50%. Specifically, the difference between the first and second gate structure antenna densities is within 10%. For example, if the first gate structure antenna density is about 30% (of region A), the second gate structure antenna density ranges from about 20% to about 40% (of region B). Maintaining the difference between the first and second gate structure antenna densities within 10% is not arbitrary. If the difference exceeds 10%, the gate structure density of the circuit area 102 and the seal ring area 104 will have a significant difference, and this non-uniformity may cause a recess effect in a subsequent planarization process (e.g., a CMP process), especially in the area between the seal ring area 104 and the circuit area 102, and in a subsequent etching process, the area with less density may be over-etched. Maintaining the width of the gate structures to be substantially the same also ensures uniformity of devices between the circuit region 102 and the seal ring region 104 .

[0122] In some embodiments, especially when the second pitch P2 of the active area 320 is greater than the first pitch P1 of the active area 220 to a certain extent, the gate structures 340 may become sparse in the seal ring area 104, so that the difference between the gate structure antenna density in the circuit area 102 and the seal ring area 104 exceeds 10%. In this case, dummy gate structures 340d may be inserted between the gate structures 340 to increase the gate structure antenna density. Figure 4A as well as Figure 4B Such an embodiment is shown. Figure 4A In FIG. 3 , the dummy gate structure 340d is interspersed between two adjacent active area rings 320. The dummy gate structure 340d also forms a ring. Figure 4B In the embodiment, the dummy gate structure 340d is interspersed between the active area ring 320 and the segmented active area 320 in the corner area. The dummy gate structure 340d may be a ring or a segment. Figure 4B However, within each of the inner corner region 108 and the outer corner region 110, the segmented dummy gate structure 340d may be interspersed between two adjacent segmented active regions 320. The dummy gate structure 340d is deposited on the isolation structure 330 and away from the edge of the nearby active region 320. Figure 4A as well as Figure 4B One (1) dummy gate structure 340d is shown interspersed between two adjacent active regions 320. It should be noted that the number of interspersed dummy gate structures 340d is not limited to Figure 4A as well as Figure 4BThe number shown is, and may include any appropriate number, depending on the adjustment of the gate structure density. For example, there may be two (2) or three (3) dummy gate structures 340d between two adjacent gate structures 340. In some embodiments, the dummy gate structure 340d and the gate structure 340 have the same width. Since the dummy gate structure 340d and the gate structure 340 are formed simultaneously with the same composition, the dummy gate structure 340d and the gate structure 340 may both be labeled as gate structure 340.

[0123] In some alternative embodiments, dummy contact structures 360 d may be interspersed between the contact structures 360 to increase the contact structure antenna density. Figure 5A as well as Figure 5B This embodiment is shown. Figure 5A In FIG. 3 , the dummy contact structure 360d is inserted between two adjacent active area rings 320. The dummy contact structure 360d also forms a ring. Figure 5B In the embodiment, the dummy contact structure 360d is interspersed between the active area ring 320 and the segmented active area 320 in the corner area. The dummy contact structure 360d may be a ring or a segment. Although not shown in FIG. Figure 5B However, within each of the inner corner region 108 and the outer corner region 110, a segmented dummy contact structure 360d may be interspersed between two adjacent segmented active regions 320. The dummy contact structure 360d is deposited above the isolation structure 330 and away from the edge of the nearby active region 320. Figure 5A as well as Figure 5B One (1) dummy contact structure 360d is shown interspersed between two adjacent active regions 320. It should be noted that the number of interspersed dummy contact structures 360d is not limited to Figure 5A as well as Figure 5B The number shown is, and may include any appropriate number, depending on the adjustment of the gate structure density. For example, there may be two (2) or three (3) dummy contact structures 360d between two adjacent contact structures 360. In some embodiments, the dummy contact structure 360d and the contact structure 360 ​​have the same width. Since the dummy contact structure 360d and the contact structure 360 ​​are formed simultaneously with the same composition, the dummy contact structure 360d and the contact structure 360 ​​may both be labeled as the contact structure 360.

[0124] According to some embodiments, Fig. 6A yes Figure 1 The semiconductor structure 100 in region A is Figure 1 or Figure 2 A schematic cross-sectional view of the section line 1-1'; Figure 6B yes Figure 1The semiconductor structure 100 in region A is Figure 1 or Figure 2 A schematic cross-sectional view of the section line 2-2'; Fig. 7A yes Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 3A A schematic cross-sectional view of the section line 3-3'; Figure 7B for Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 3A Schematic diagram of the cross section cut along the section line 4-4'. Fig. 8A yes Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 4A Schematic diagram of alternative sections for cutting along section line 3-3'; Figure 8B yes Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 4A A schematic cross-sectional view of the section line 4-4'; Fig.9A yes Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 5A Schematic diagram of alternative cross-sections for cutting along section line 3-3'; Fig. 9B yes Figure 1 The semiconductor structure 100 in region B is Figure 1 or Figure 5A 4-4'. It is worth noting that only the substrate, active area, isolation structure, gate structure, inner spacer, gate spacer, interlayer dielectric (ILD) layer, and contact structure are shown in these drawings. Other components such as interconnect structure will be described below.

[0125] exist Fig. 6A as well as Figure 6BIn the embodiment, the circuit region 102 includes a multi-gate device, such as a functional GAA transistor, formed on a substrate 202. The GAA transistor includes a plurality of channel layers (or channel components) 222 vertically stacked on top of the substrate 202. The channel layer 222 may include silicon (Si). The top of the substrate 202 protrudes from the rest of the substrate 202 and is surrounded by an isolation structure 230. The isolation structure 230 may be a shallow trench isolation (STI) structure. The gate structure 240 extends to surround and couple with each of the plurality of vertically stacked channel layers 222. The gate structure 240 includes a gate dielectric layer (also including a high-k dielectric material) and a gate electrode (also including a metal). A gate spacer 242 is disposed on the sidewalls of the gate structure 240. The gate spacer 242 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0126] Source / drain (S / D) epitaxial components (or source / drain components) 224 are disposed on both sides of the gate structure 240 and connect each of the plurality of vertically stacked channel layers 222. As used herein, a source / drain component or "S / D component" may refer to a source or drain of a device. It may also refer to a region that provides a source and / or drain for a plurality of devices. The source / drain component 224 is isolated from the gate structure 240 by a gate spacer 242 and an inner spacer 244. The inner spacer 244 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. An interlayer dielectric (ILD) layer 250 is disposed on the sidewalls and top surfaces of the gate structure 240, the gate spacer 242, the source / drain component 224, and the isolation structure 230. The ILD layer 250 may include or be formed of a dielectric material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 250 may be a multi-layer structure, such as including a lower ILD layer and an upper ILD layer.

[0127] The contact structure 260 is disposed on the top surface of the source / drain feature 224 and extends through the ILD layer 250. The contact structure 260 may also be referred to as a source / drain contact. In some embodiments, a silicide feature (not shown) is formed between the source / drain feature 224 and the contact structure 260 to reduce contact resistance. The contact structure 260 may include any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, TiN, TaN, Ta, and / or other suitable conductive materials.

[0128] exist Fig. 7A as well as Figure 7B In the embodiment of the present invention, the seal ring area 104 includes a multi-gate device formed on the substrate 202, such as a non-functional GAA transistor. Similar to the functional GAA transistor, the non-functional GAA transistor includes a plurality of channel layers (or referred to as channel components) 322 vertically stacked on top of the substrate 202. The channel component 322 may include silicon (Si). The top of the substrate 202 protrudes from the rest of the substrate 202 and is surrounded by an isolation structure 330. The isolation structure 330 may be a shallow trench isolation (STI) structure. The gate structure 340 is deposited on the edge portions of the plurality of vertically stacked channel components 322 and extends to fill the gaps between adjacent channel components in the plurality of vertically stacked channel components 322. For each channel component 322, the gate structure 340 covers the top surface, the sidewall surface, and the bottom surface of the outer edge portion of the corresponding channel component 322. The gate structure 340 includes a gate dielectric layer (also including a high-k dielectric material) and a gate electrode (also including a metal). The gate spacer 342 is disposed on the sidewalls of the gate structure 340. The gate spacer 342 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0129] The source / drain epitaxial components (or source / drain components) 324 are disposed on both sides of the vertically stacked plurality of channel components 322 and connect the other edge portions of the vertically stacked plurality of channel components 322. That is, each channel component 322 has one end partially surrounded by the gate structure 340, and the other end in physical contact with the source / drain component 324. The source / drain component 324 is isolated from the gate structure 340 by the gate spacer 342 and the inner spacer 344. The inner spacer 344 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. An interlayer dielectric (ILD) layer 350 is disposed on the sidewalls and top surfaces of the gate structure 340, the gate spacer 332, the source / drain component 324, and the isolation structure 330. The ILD layer 350 may include or be formed of a dielectric material such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 350 may be a multi-layer structure, such as including a lower ILD layer and an upper ILD layer.

[0130] The contact structure 360 ​​is disposed on the top surface of the source / drain component 324 and extends through the ILD layer 350. The contact structure 360 ​​may also be referred to as a source / drain contact. In some embodiments, a silicide component (not shown) is formed between the source / drain component 324 and the contact structure 360 ​​to reduce the contact resistance. Alternatively, in some embodiments, the source / drain component and the silicide component between the source / drain contact only exist in the circuit area 102 and not in the seal ring area 104, because the silicide component can reduce the contact resistance for the functional circuit, but is not so critical for non-functional elements, so its formation can be skipped. For example, during the silicide formation process of the source / drain component, the source / drain component in the seal ring area 104 may be covered by a resist layer and thus skipped from the formation of the silicide. The contact structure 360 ​​may include any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, TiN, TaN, Ta, and / or other suitable conductive materials.

[0131] See also Fig. 8A as well as Figure 8B In an alternative embodiment, Fig. 8A as well as Figure 8B The sealing ring structure in Fig. 7A as well as Figure 7B320. One difference is the dummy gate structure 340d disposed between two adjacent active regions 320. The dummy gate structure 340d improves the uniformity of the overall gate structure. The dummy gate structure 340d lands just above the top surface of the isolation structure 330. The dummy gate structure 340d and the gate structure 340 can be formed simultaneously with the same composition. The top surfaces of the dummy gate structure 340d and the gate structure 340 can be coplanar.

[0132] See also Fig.9A as well as Fig. 9B In an alternative embodiment, Fig.9A as well as Fig. 9B The sealing ring structure in Fig. 7A as well as Figure 7B 320. One difference is the dummy contact structure 360d disposed between two adjacent active areas 320. The dummy contact structure 360d improves the uniformity of the overall contact structure. The dummy contact structure 360d is suspended directly above the isolation structure 330 and has a certain distance from the top surface of the isolation structure 330. The dummy contact structure 360d and the contact structure 360 ​​can be formed simultaneously by etching the ILD layer 350 to form a contact through hole and filling the contact through hole with the same composition. Although the contact through hole of the contact structure 360 ​​terminates at the top surface of the source / drain component 324, the contact through hole of the dummy contact structure 360d can be further extended into the ILD layer 350. Therefore, the top surfaces of the dummy contact structure 360d and the contact structure 360 ​​can be coplanar, and the bottom surface of the dummy contact structure 360d can be lower than the bottom surface of the contact structure 360 ​​and lower than the top surface of the source / drain component 324. In further embodiments, the bottom surface of the dummy contact structure 360 ​​d may be lower than the bottom surface of the topmost channel feature 322 .

[0133] Fig.10 According to various aspects of the present disclosure, the above is shown in the manufacturing method. Figures 1 to 9B Schematic diagram of a flow chart of a method 400 for the discussed semiconductor structure 100. Additional operations may be provided before, during, and after the method 400, and some of the described operations may be moved, replaced, or removed for additional embodiments of the method 400. Figures 11 to 21 Describing method 400, Figures 11 to 21 4 are various cross-sectional views of the semiconductor structure 100 at various steps of manufacturing according to the method 400 according to some embodiments. In these drawings, Figures 11 to 18 The semiconductor structure 100 is shown along Figure 1 Schematic cross-sectional view of section line 1-1' and section line 3-3'; Fig.19 The semiconductor structure 100 is shown along Figure 1 Schematic cross-sectional views of section line 1-1', section line 2-2', section line 3-3', and section line 4-4'; Fig. 20 as well as Fig.21 An alternative embodiment of the semiconductor structure 100 is shown along Figure 1 Schematic cross-sectional view of section line 3-3' and section line 4-4'.

[0134] The semiconductor structure 100 discussed in detail below shows elements of a functional GAA transistor in the circuit region 102 and elements of a non-functional GAA transistor in the seal ring region 104, such as in combination with Figures 11 to 21 As shown. The embodiments of the present disclosure are provided for simplicity and ease of understanding, and are not necessarily limited to the embodiments as structures of any type of device, any number of devices, any number of regions, or any configuration of regions. For example, the same inventive concepts can be applied to the manufacture of devices having FinFET transistors. In addition, the semiconductor structure 100 can be an intermediate device or part of an intermediate device manufactured during the processing of an IC, which can include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as PFETs (P-type FET), NFETs (N-type FET), FinFETs, GAAFET, MOSFET, complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations of the above. Throughout this disclosure, unless otherwise specified, similar reference numerals are used to represent similar components.

[0135] At operation 402, see Fig.10 as well as Fig.11 , method 400 provides (or receives) a semiconductor structure 100 having a semiconductor substrate (or substrate) 202 and an epitaxial stack 204 above the substrate 202. The substrate 202 is a silicon substrate in an embodiment of the present invention. Alternatively, the substrate 202 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In yet another alternative embodiment, the substrate 202 is a semiconductor-on-insulator (SOI), such as a buried dielectric layer.

[0136] The epitaxial stack 204 extends continuously from the circuit area 102 to the seal ring area 104. The epitaxial stack 204 includes an epitaxial layer 206 of a first component interspersed by an epitaxial layer 208 of a second component. The first component may be different from the second component. The epitaxial layer 206 may include the same composition as the substrate 202. In the illustrated embodiment, the epitaxial layer 208 is silicon germanium (SiGe) and the epitaxial layer 206 is silicon (Si). However, other embodiments are also possible, including embodiments that provide a first component and a second component with different oxidation rates and / or etching selectivities. For example, in some embodiments, either the epitaxial layer 206 of the first component or the epitaxial layer 208 of the second component may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, or combinations thereof. In some embodiments, the epitaxial layer 206 and the epitaxial layer 208 are substantially free of dopants, wherein, for example, no intentional doping is performed during the epitaxial growth process. For example, the epitaxial growth of the first and second composition epitaxial layers 206 and 208 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial processes. In various embodiments, the substrate 202 is a crystalline substrate, and the epitaxial layer 206 and the epitaxial layer 208 are crystalline semiconductor layers.

[0137] In some embodiments, each epitaxial layer 206 has a thickness ranging from about 4 nanometers (nm) to about 8nm. Epitaxial layer 206 can have a substantially uniform thickness. In some embodiments, each epitaxial layer 208 has a thickness ranging from about 4nm to about 8nm. In some embodiments, stacked epitaxial layer 208 has a substantially uniform thickness. As described in more detail below, epitaxial layer 206 or a portion of epitaxial layer 206 can be formed as a channel component of a multi-gate device to be formed subsequently, and its thickness can be selected based on considerations of device performance. The term channel component (or channel layer) is used throughout this disclosure to refer to any material portion of a channel with nanometer or even micrometer-sized dimensions in a transistor, and has an elongated shape, regardless of the cross-sectional shape of this portion. Therefore, this term represents a circular and substantially circular cross-sectional elongated material portion, and a beam or strip material portion including, for example, a cylindrical or substantially rectangular cross-section. The epitaxial layer 208 in the channel region can be removed eventually, and is used to define the vertical distance between adjacent channel components of the multi-gate device to be formed later, and its thickness is selected based on device performance considerations. Therefore, the epitaxial layer 208 can also be called a sacrificial layer, and the epitaxial layer 206 can also be called a channel layer.

[0138] It is worth noting that the three (3) layers of epitaxial layers 206 and the three (3) layers of epitaxial layers 208 are arranged alternately, as shown in FIG. Fig.11 , which is shown for illustrative purposes only, and is not intended to limit the present disclosure except to the extent expressly recited in the claims. It should be understood that any number of epitaxial layers may be formed in the epitaxial stack 204; the number of layers depends on the number of channel components desired for the multi-gate device. In some embodiments, the number of epitaxial layers 206 ranges from 2 to 10. It should also be noted that although the epitaxial layers 206 and 208 are shown as having a particular stacking order in which the epitaxial layer 206 is the topmost layer of the epitaxial stack 204, other configurations are possible. For example, in some cases, the epitaxial layer 208 may alternatively be the topmost layer of the epitaxial stack 204. In other words, the order of growth of the epitaxial layers 206 and 208, as well as their stacking order, may be swapped or performed in other ways than those shown in the accompanying drawings while still within the scope of the present disclosure.

[0139] In operation 404, see Fig.10 as well as Fig.12, the method 400 patterns the epitaxial stack 204 and the top of the substrate 202 to form fin-shaped active areas, in particular, the fin-shaped active area 220 in the circuit area 102 and the fin-shaped active area 320 in the seal ring area 104. In various embodiments, each fin-shaped active area 220, 320 includes a base portion formed by the substrate 202 and an epitaxial stack portion formed from a portion of each epitaxial layer of the initial epitaxial stack 204 including the epitaxial layer 206 and the epitaxial layer 208. After patterning, the epitaxial layer 206 in the fin-shaped active area 220 is labeled as a channel layer (or channel component) 222, and the epitaxial layer 206 in the fin-shaped active area 320 is labeled as a channel layer (or channel component) 322; the epitaxial layer 208 in the fin-shaped active area 220 is labeled as a sacrificial layer 223, and the epitaxial layer 208 in the fin-shaped active area 320 is labeled as a sacrificial layer 323. The fin-shaped active areas 220, 320 can be manufactured using a suitable process, including a double patterning or multiple patterning process. In general, the double patterning or multiple patterning process combines a photolithography process with a self-alignment process to create, for example, a pattern with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as a mask to etch the initial epitaxial stack 204 to pattern the fin-shaped active areas 220, 320. The etching process can include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes.

[0140] The method 400 also forms isolation structures 230, 330, such as shallow trench isolation (STI) features, between the fin-shaped active regions 220, 320, respectively, at operation 404. Fig.12, STI components are multiple portions of an STI layer disposed on the substrate 202, which are interspersed between the fin-shaped active areas 220, 320. Multiple portions of the STI layer surrounding the fin-shaped active area 220 in the circuit area 102 are labeled as STI components (isolation structures 230), and multiple portions of the STI layer surrounding the fin-shaped active area 320 in the seal ring area 104 are labeled as STI components (isolation structures 330). For example, in some embodiments, a dielectric layer is first deposited on the substrate 202 to fill the trenches between the fin-shaped active areas with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a chemical vapor deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable CVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, and / or other suitable processes. In some embodiments, after depositing the dielectric layer, the semiconductor structure 100 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer may include a multi-layer structure, for example, with one or more liner layers. After depositing the dielectric layer, the deposited dielectric material is thinned and planarized, for example, by chemical mechanical polishing (CMP). Subsequently, the dielectric layer interspersed between the fin-shaped active regions 220 and 320 is recessed. In some embodiments, the recessed etching process may include a dry etching process, a wet etching process, and / or a combination thereof. In some embodiments, the recessed depth is controlled (for example, by controlling the etching time) to expose each layer of the initial epitaxial stack 204.

[0141] At operation 406, see Fig.10 as well as Fig.13, method 400 forms dummy gate structures 238, 338 above active areas 220, 320, respectively. Although the present disclosure is about a replacement gate (or gate-last) process, that is, forming a dummy gate structure (or sacrificial gate structure) and then replacing it, other configurations are also possible. The dummy gate structures 238, 338 will be replaced by metal gate structures in subsequent process stages of method 400. The dummy gate structures 238, 338 can also define source / drain regions of corresponding active areas, for example, multiple portions of the active area between adjacent dummy gate structures. In the circuit area 102, the dummy gate structure 238 is deposited above the central portion and two end portions of the active area 220. In the seal ring area 104, the dummy gate structure 338 is deposited above the active area 320 and the edge portion of the STI component (isolation structure 330).

[0142] In some embodiments, the dummy gate structures 238, 338 are formed by various process steps, such as film deposition, patterning, etching, and other suitable process steps. Exemplary film deposition processes include CVD (including low-pressure CVD, plasma-enhanced chemical vapor deposition (PECVD) and / or flowable CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In some embodiments, the dummy gate structure includes a dummy dielectric layer and a dummy electrode layer. In some embodiments, the dummy dielectric layer may include SiO2, silicon nitride, a high-k dielectric material, and / or other suitable materials. Subsequently, a dummy electrode layer is deposited. In some embodiments, the dummy electrode layer may include polysilicon. For example, when forming a dummy gate structure, the patterning process includes a photolithography process (e.g., optical lithography or electron beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the dummy gate structure is patterned by a patterned hard mask.

[0143] Still see Fig.13, method 400 also forms gate spacers 242 on the sidewall surfaces of dummy gate structure 238, and gate spacers 342 on the sidewall surfaces of dummy gate structure 338 at operation 406. In some embodiments, after forming dummy gate structures 238, 338, a blanket layer of insulating material for sidewall spacers is conformally formed by using CVD or other suitable methods. The blanket layer is deposited in a conforming manner so that it is formed to have substantially equal thickness on various surfaces, such as the sidewalls, horizontal surfaces, and top of the dummy gate structure. In some embodiments, the blanket layer is deposited to a thickness ranging from about 2 nm to about 10 nm. In one embodiment, the insulating material of the blanket layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. The blanket layer is then etched using an anisotropic process to form gate spacers 242 on opposite sidewalls of the dummy gate structure 238 and gate spacers 342 on opposite sidewalls of the dummy gate structure 338. The anisotropic etching performed on the blanket layer may be, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from the horizontal surfaces, leaving the dielectric spacer layer as gate spacers 242, 342 on the vertical sidewall surfaces of the dummy gate structures 238, 338, respectively.

[0144] At operation 408, see Fig.10 as well as Fig.14 , the method 400 recesses the source / drain regions in the active regions 220, 320 to form source / drain recesses 226, 326, respectively. In some embodiments, a source / drain etching process is performed to form the S / D recesses 226, 326 by removing portions of the active regions 220, 320 not covered by the dummy gate structures 238, 338 (e.g., in the source / drain regions) and the previously exposed portions. In particular, the source / drain etching process may be used to remove portions of the channel layer 222, the sacrificial layer 223, and the channel layer 322, the sacrificial layer 323 exposed in the source / drain regions of the semiconductor structure 100 to expose the top of the substrate 202. In some embodiments, the source / drain etching process may include a dry etching process, a wet etching process, and / or a combination thereof. In some embodiments, the recess depth is controlled (eg, by controlling the etching time) such that the top of the substrate 202 is recessed below the top surface of the STI features (isolation structures 230 , 330 ).

[0145] Still see Fig.14, the method 400 also forms an inner spacer at operation 408. In some embodiments, the inner spacer recess is formed by laterally etching the sacrificial layer 223 through the S / D groove 226 and laterally etching the sacrificial layer 323 through the S / D groove 326, and then the inner spacer is formed in the inner spacer recess. Multiple portions of the inner spacer in the circuit area 102 are labeled as inner spacers 244, and multiple portions of the inner spacer in the seal ring area 104 are labeled as inner spacers 344. In the circuit area 102, the inner spacer 244 is disposed on both ends of the sacrificial layer 223; in the seal ring area 104, the inner spacer 344 is disposed on one end of the sacrificial layer 323 because the other end of the sacrificial layer 323 is covered by the dummy gate structure 338. In some embodiments, lateral etching (or horizontal etching) is performed to etch back the sacrificial layers 223, 323 and form the inner spacer recess. In some embodiments, the etching amount of the sacrificial layers 223, 323 ranges from about 2nm to about 10nm. When the sacrificial layers 223, 323 are SiGe, the lateral etching process may use an etchant selected from, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), and potassium hydroxide (KOH) solutions. Subsequently, an insulating layer is formed on the lateral ends of the sacrificial layers 223, 323 to fill the inner spacer recesses, thereby forming inner spacers 244, 344, respectively. The insulating layer may include a dielectric material such as SiN, SiOC, SiOCN, SiCN, SiO2 and / or other suitable materials. In some embodiments, the insulating layer is conformally deposited in the S / D recesses 226, 326, for example, by ALD or any other suitable method. After the insulating layer is conformally deposited, an etch back process is performed to partially remove the insulating layer from the outside of the inner spacer recesses. By this etching, the insulating layer is substantially retained within the inner spacer recesses.

[0146] At operation 410, see Fig.10 as well as Fig.15The method 400 forms a buffer epitaxial layer 224a at the bottom of the S / D groove 226 in the circuit region 102 and forms a buffer epitaxial layer 324a at the bottom of the S / D groove 326 in the seal ring region 104. The buffer epitaxial layers 224a, 324a are epitaxially grown from the top of the recess of the substrate 202 in the S / D region. The buffer epitaxial layers 224a, 324a may also be referred to as lower epitaxial layers. For example, the epitaxial growth of the buffer epitaxial layers 224a, 324a may be performed by vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, the buffer epitaxial layers 224a, 324a include the same material as the substrate 202, such as silicon (Si). In some alternative embodiments, the buffer epitaxial layers 224a, 324a include a semiconductor material different from the substrate 202 (Si), such as SiGe, SiSn, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layers 224a, 324a are free of dopants, wherein, for example, no intentional doping is performed during the epitaxial growth process. In contrast, in one case, the substrate 202 is lightly doped and has a higher doping concentration than the buffer epitaxial layers 224a, 324a. The buffer epitaxial layers 224a, 324a provide a high resistance path from the S / D region to the semiconductor substrate, so that leakage current in the semiconductor substrate is suppressed. The method 400 may optionally deposit an insulating film, such as a nitride film, on the buffer epitaxial layers 224a, 324a in operation 410 to further block the path of leakage current. The insulating film covering the multiple portions of the buffer epitaxial layer 224a in the circuit area 102 is labeled as the insulating film 224b, and the insulating film covering the multiple portions of the buffer epitaxial layer 324a in the seal ring area 104 is labeled as the insulating film 324b. The insulating films 224b and 324b can be deposited by ALD or any other suitable method. In the seal ring area 104, compared with depositing the dummy gate structure 338 on the central portion of the active area 320, depositing the dummy gate structure 338 on the edge portion of the active area 320 as in the embodiment of the utility model can reserve a larger opening for the S / D groove 326, which promotes the deposition of the insulating film 324b.

[0147] At operation 412, see Fig.10 as well as Fig.16, the method 400 forms an upper epitaxial layer 224c on the buffer epitaxial layer 224a and forms an upper epitaxial layer 324c on the buffer epitaxial layer 324a. The buffer epitaxial layer 224a and the upper epitaxial layer 224c (and the optional insulating film 224b) together define the source / drain component 224 in the circuit region 102. The buffer epitaxial layer 324a and the upper epitaxial layer 324c (and the optional insulating film 324b) together define the source / drain component 324 in the seal ring region 104. For example, the epitaxial growth of the upper epitaxial layers 224c, 324c can be performed by vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes. The upper epitaxial layer 224c, 324c may include Si, SiP, SiAs, SiC, SiGe, SiSn, or other suitable semiconductor materials. The upper epitaxial layer 224c, 324c may be doped with dopants such as arsenic (As), phosphorus (P), germanium (Ge), or boron (B). Generally speaking, the upper epitaxial layer 224c, 324c includes a higher dopant concentration than the buffer epitaxial layer 224a, 324a. In some embodiments, the upper epitaxial layer 224c, 324c includes the same semiconductor material as the buffer epitaxial layer 224a, 324a but has a higher dopant concentration. In some embodiments, the upper epitaxial layer 224c, 324c includes a semiconductor material different from the buffer epitaxial layer 224a, 324a and has a higher dopant concentration. The upper epitaxial layer 224c, 324c may have the same crystal arrangement direction as the substrate 202 and the buffer epitaxial layer 224a, 324a.

[0148] At operation 414, see Fig.10 as well as Fig.17, method 400 forms a lower interlayer dielectric (ILD) layer over the source / drain features 224, 324, the gate spacer 242, the dummy gate structures 238, 338, and the isolation structure 230. A contact etch stop layer (CESL) (not shown) may be deposited as a blanket layer before forming the lower ILD layer, and the lower ILD layer is deposited over the CESL. Portions of the lower ILD layer in the circuit area 102 are labeled as lower ILD layer 250a, and portions of the lower ILD layer in the seal ring area 104 are labeled as lower ILD layer 350a. In some embodiments, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art to which the present invention belongs. The CESL may be formed by a plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the lower ILD layer includes a dielectric material such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The lower ILD layer can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the lower ILD layer, the semiconductor structure 100 can be subjected to a high thermal budget process to anneal the lower ILD layer. After depositing the lower ILD layer, a planarization process can be performed to remove excess dielectric material. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the lower ILD layer (and CESL, if present) overlying the dummy gate structures 238, 338 and planarizes the top surface of the semiconductor structure 100.

[0149] At operation 416, see Fig.10 as well as Fig.18, method 400 replaces the dummy gate structures 238, 338 with metal gate structures 240, 340, respectively. In some embodiments, operation 416 may include one or more etching processes to remove the dummy gate structures 238, 338 in forming the gate trenches. For example, the removal of the dummy gate structures 238, 338 may be performed using a selective etching process such as selective wet etching, selective dry etching, or a combination thereof. Operation 416 also removes the sacrificial layer (epitaxial layer) 223, 323 from the gate trenches. In an embodiment, the sacrificial layer 223, 323 includes SiGe, while the channel layer or channel component (epitaxial layer) 222, 322 is silicon, thereby allowing for the selective removal of the sacrificial layer 223, 323. In an embodiment, the sacrificial layer 223, 323 is removed by a selective wet etching process. In some embodiments, the selective wet etching includes APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes first oxidizing SiGe and then oxidizing SiGeO. x For example, the oxidation can be provided by O3 cleaning, followed by removal of SiGeO by an etchant such as NH4OH. x Subsequently, operation 416 forms a metal gate structure 240 , 340 in the gate trench.

[0150] In some embodiments, each metal gate structure 240, 340 includes an interface layer (not shown), a high dielectric constant gate dielectric layer formed above the interface layer, and a gate electrode layer formed above the high dielectric constant gate dielectric layer. As used and described herein, the high dielectric constant gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). The gate electrode layer may include a metal, a metal alloy, or a metal silicide. In addition, the formation of the metal gate structures 240, 340 may include deposition to form various gate materials, one or more liner layers, and one or more planarization processes, such as CMP processes, to remove excess gate material and thereby planarize the top surface of the semiconductor structure 100. As described above, the ratio of the active area width ranges from about 1.1 to about 5, the difference in active area antenna density is within about 10%, the difference in metal gate structure antenna density is within about 10% for similar metal gate structure widths, and the implementation of other measures improves the uniformity of components in the circuit area and the seal ring area, which mitigates the recess effect during the planarization process.

[0151] The metal gate structure 240 includes a plurality of portions interpenetrating and surrounding the middle portion of each channel layer 222, which forms a channel of a functional multi-gate device in the circuit region 102. The two end portions of each channel layer 222 are in contact with two opposing source / drain components 224. The metal gate structure 340 includes a plurality of portions interpenetrating and partially surrounding the end on one side of the channel component 322. The end portions on both sides of the channel component 322 are in contact with the source / drain component 324. In some embodiments, the interface layer of the metal gate structures 240 and 340 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable methods. The high dielectric constant gate dielectric layer of the metal gate structures 240 and 340 may include a high dielectric constant dielectric such as hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer may include other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate electrode layer may include a single film layer or alternatively a multi-layer structure, such as various combinations of metal layers with selected work functions to improve device performance (work function metal layers), liners, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the gate electrode layer may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, gate electrode layers may be formed separately for NFET and PFET transistors in the circuit region 102, which may use different metal layers (e.g., for providing n-type or p-type work functions), while the gate electrode layer may be formed simultaneously in the seal ring region 104 and thus have the same composition as one of the NFET or PFET transistors in the circuit region 102.

[0152] At operation 418, see Fig.10as well as Fig.19 , method 400 forms contact structures, vias, and overlying interconnect structures. In some embodiments, operation 418 includes depositing upper ILD layers 250 b, 350 b over lower ILD layers 250 a, 350 a, respectively; forming source / drain contacts 260, 360 through the upper and lower ILD layers and landing on source / drain features 224, 324, respectively; depositing etch stop layers 270, 370 and dielectric layers 272, 372 on upper ILD layers 250 b, 350 b, respectively; forming gate contacts 284 through dielectric layers 272, etch stop layers 270, and upper ILD layers 250 b and landing on gate structure 240; forming source / drain contact vias 282, 382 through dielectric layers 272, etch stop layers 270 and landing on source / drain contacts 260, 360, respectively; and forming interconnect structures including a plurality of insulating layers 274, 374 (also referred to as intermetallic dielectrics) The interconnect structure may further include an etch stop layer (not shown) stacked between adjacent insulating layers, such as dielectric layers 274, 374, and conductive features such as metal lines 286, 386 and vias 288, 388 in insulating layers 274, 374, respectively. Insulating layers 274, 374 may be formed of an extra-low-k (ELK) dielectric material having a dielectric constant value of less than 2.5. The interconnect structure may further include an etch stop layer (not shown) stacked between adjacent insulating layers.

[0153] In the seal ring region 104, the seal ring structure extends vertically from the substrate, through the interconnect structure, and all the way to the passivation layer (not shown) in the semiconductor structure 100. Fig.19 In the illustrated embodiment, the seal ring structure extends to the interconnect structure through the source / drain contacts 360 and the source / drain contact vias 382, ​​while the gate structure 340 in the seal ring area 104 does not contact the gate contact landed thereon. Furthermore, due to the spacing between adjacent seal ring structures, not all source / drain features 324 are connected to the interconnect structure to make room for the conductive features above the adjacent source / drain features 324 to have sufficient width.

[0154] About Shangfanghe Fig. 8A as well as Figure 8B The alternative embodiment discussed, Fig. 20 A cross-sectional schematic diagram of an alternative embodiment is shown after forming an interconnect structure, wherein a dummy gate structure 340d is disposed between gate structures 340. The dummy gate structure 340d may not have a gate contact landed thereon.

[0155] About Shangfanghe Fig.9A as well as Fig. 9B The alternative embodiment discussed, Fig.21A cross-sectional schematic diagram of an alternative embodiment after forming an interconnect structure is shown, wherein a dummy contact structure 360d is disposed between gate structures 340 and covers the underlying etch stop layer 370. In addition, the seal ring structure may extend to the interconnect structure through a gate contact 384 rather than through a source / drain contact structure 360. In the illustrated embodiment, a metal line 386 connects the gate contacts 384 extending from two adjacent gate structures 340, and the source / drain features 324 in the seal ring area 104 may not even have a contact structure 360 ​​landing thereon to make room for the interconnect structure formed above.

[0156] The present disclosure provides a seal ring structure including an active area, a gate structure, and a contact structure that effectively protects devices in a circuit area. The active area, the gate structure, and the contact structure in the seal ring area are designed and configured to maintain consistency with corresponding elements in the circuit area in terms of size, spacing, orientation, and other parameters.

[0157] In an exemplary aspect, the present disclosure is about a semiconductor structure. The semiconductor structure includes a substrate having a circuit area and a seal ring area surrounding the circuit area, a plurality of first active areas having a first width and disposed in the circuit area, a plurality of second active areas having a second width and disposed in the seal ring area, the second width being greater than the first width, a plurality of first gate structures disposed on the first active area, the first gate structures being oriented longitudinally to be orthogonal to the first active area, and a plurality of second gate structures disposed on a plurality of longitudinal edges of the second active area, the second gate structures being oriented longitudinally to be parallel to the second active area. In some embodiments, the ratio of the second width to the first width ranges from 1.1 to 5. In some embodiments, the first gate structure has a third width, and the second gate structure has a fourth width, the fourth width being substantially equal to the third width. In some embodiments, each second gate structure overlaps a corresponding one of the second active areas by a width ranging from 5 nanometers to 15 nanometers, the width being measured from a corresponding one of the longitudinal edges toward a centerline of the corresponding one of the second active areas. In some embodiments, the first active area occupies a first percentile of a first area in the circuit area, the second active area occupies a second percentile of a second area in the seal ring area, and the difference between the first percentile and the second percentile is within 10%. In some embodiments, the first gate structure occupies a first percentile of a first area in the circuit area, the second gate structure occupies a second percentile of a second area in the seal ring area, and the difference between the first percentile and the second percentile is within 10%. In some embodiments, the semiconductor structure further includes a plurality of contact structures disposed on the second active area and completely landed on the second active area. In some embodiments, the contact structure lands on the second active area with a plurality of margins, so that a plurality of longitudinal edges of each contact structure are located within a plurality of longitudinal edges of a corresponding one of the second active areas. In some embodiments, each second active area is a continuous ring to surround the circuit area, and each second gate structure is a continuous ring to surround the circuit area. In some embodiments, the semiconductor structure further includes a plurality of third active regions disposed in a plurality of corner regions of the sealing ring region, the third active regions being segmented, and includes a plurality of third gate structures disposed on a plurality of edges of the third active regions, each third gate structure completely surrounding a corresponding one of the third active regions.

[0158] In another exemplary aspect, the present disclosure is about a semiconductor structure. The semiconductor structure includes an active region extending longitudinally in a first direction in a region of the semiconductor structure, a first gate structure disposed on a first edge of the active region, the first gate structure extending longitudinally in the first direction in the region of the semiconductor structure; a second gate structure disposed on a second edge of the active region, the second edge being opposite to the first edge, the second gate structure extending longitudinally in the first direction in the region of the semiconductor structure, and a contact structure completely landing on the active region, the contact structure extending longitudinally in the first direction in the region of the semiconductor structure. In some embodiments, each of the active region, the first gate structure, the second gate structure, and the contact structure is annular. In some embodiments, the ring of the contact structure completely surrounds the ring of the first gate structure, and the ring of the second gate structure completely surrounds the ring of the contact structure. In some embodiments, the region is an edge region of the semiconductor structure, the active region extends longitudinally in a second direction in a corner region of the semiconductor structure, and the second direction is inclined about 45 degrees relative to the first direction. In some embodiments, the active region includes a plurality of channel elements stacked vertically. In some embodiments, the semiconductor structure further includes an isolation component, which surrounds the active region, and a third gate structure, which is completely disposed on the isolation component, the third gate structure extends longitudinally in the first direction in the region of the semiconductor structure, and the first gate structure and the third gate structure sandwich the second gate structure. In some embodiments, the contact structure is a first contact structure, and the semiconductor structure further includes an isolation component, which surrounds the active region, and a second contact structure, which is completely disposed on the isolation component, the second contact structure extends longitudinally in the first direction in the region of the semiconductor structure, and the first contact structure and the second contact structure sandwich the second gate structure.

[0159] In another exemplary aspect, the present disclosure relates to a method for forming a semiconductor structure. The method includes forming an epitaxial stack above a substrate, the epitaxial stack including a plurality of first epitaxial layers and a plurality of second epitaxial layers of different material compositions and stacked alternately in a vertical direction perpendicular to the substrate, patterning the epitaxial stack to form a fin, depositing a first dummy gate structure on a first longitudinal edge of the fin, and depositing a second dummy gate structure on a second longitudinal edge of the fin, each of the first dummy gate structure and the second dummy gate structure extending longitudinally parallel to the fin, etching a portion of the fin between the first dummy gate structure and the second dummy gate structure to form a recess, forming an epitaxial component in the recess, removing the first dummy gate structure and the second dummy gate structure to form a first gate trench and a second gate trench, respectively, removing the second epitaxial layer from the first gate trench and the second gate trench, and depositing a first metal gate structure in the first gate trench, and depositing a second metal gate structure in the second gate trench. In some embodiments, the method of forming a semiconductor structure further comprises forming a contact structure landing on the epitaxial component, the contact structure being completely confined within the first longitudinal edge and the second longitudinal edge of the fin. In some embodiments, the first metal gate structure has a first ring shape, and the second metal gate structure has a second ring shape, the second ring shape being substantially concentric with the first ring shape.

[0160] The features of several embodiments are summarized above so that those skilled in the art to which the utility model belongs can better understand the viewpoints of the embodiments of the utility model. Those skilled in the art to which the utility model belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the utility model to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the utility model belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the utility model, and various changes, substitutions, and replacements can be made without violating the spirit and scope of the utility model. Therefore, the scope of protection of the utility model shall be defined as defined by the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a circuit area and a sealing ring area surrounding the circuit area; A plurality of first active regions having a first width and disposed in the circuit region; A plurality of second active regions having a second width and disposed in the seal ring region, wherein the second width is greater than the first width; a plurality of first gate structures disposed on the plurality of first active regions, wherein the plurality of first gate structures are longitudinally oriented to be orthogonal to the plurality of first active regions; as well as A plurality of second gate structures are disposed on a plurality of longitudinal edges of a plurality of the second active regions, wherein the plurality of the second gate structures are longitudinally oriented to be parallel to the plurality of the second active regions.

2. The semiconductor structure according to claim 1, wherein: The ratio of the second width to the first width ranges from 1.1 to 5.

3. The semiconductor structure according to claim 1, wherein: The first gate structures have a third width, and the second gate structures have a fourth width, which is substantially equal to the third width.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Also includes: A plurality of contact structures are arranged on the plurality of second active regions and completely land on the plurality of second active regions, wherein the plurality of contact structures land on the plurality of second active regions with a plurality of boundaries, so that the plurality of longitudinal edges of each contact structure are located within the plurality of longitudinal edges of a corresponding one of the plurality of second active regions.

5. The semiconductor structure according to claim 1, wherein: Each second active region is a continuous ring shape to surround the circuit region, and each second gate structure is a continuous ring shape to surround the circuit region.

6. The semiconductor structure according to claim 5, characterized in that Also includes: A plurality of third active regions are arranged in a plurality of corner regions of the sealing ring region, wherein the plurality of third active regions are arranged in sections; as well as A plurality of third gate structures are disposed on a plurality of edges of the plurality of third active regions, wherein each third gate structure completely surrounds a corresponding one of the plurality of third active regions.

7. A semiconductor structure, characterized in that: include: an active region extending longitudinally in a first direction in a region of the semiconductor structure; a first gate structure disposed on a first edge of the active region, the first gate structure extending longitudinally in the first direction in the region of the semiconductor structure; a second gate structure disposed on a second edge of the active region, the second edge being opposite to the first edge, the second gate structure extending longitudinally in the first direction in the region of the semiconductor structure; as well as A contact structure is completely landed on the active area, and the contact structure extends longitudinally in the first direction in the region of the semiconductor structure.

8. The semiconductor structure according to claim 7, wherein: Each of the active region, the first gate structure, the second gate structure, and the contact structure is annular, wherein the ring shape of the contact structure completely surrounds the ring shape of the first gate structure, and the ring shape of the second gate structure completely surrounds the ring shape of the contact structure.

9. The semiconductor structure according to claim 7, wherein: Also includes: an isolation member surrounding the active region; as well as A third gate structure is completely disposed on the isolation component. The third gate structure extends longitudinally in the first direction in the region of the semiconductor structure. The first gate structure and the third gate structure sandwich the second gate structure.

10. The semiconductor structure according to claim 7, wherein: The contact structure is a first contact structure, and the semiconductor structure further includes: an isolation member surrounding the active region; and A second contact structure is completely disposed on the isolation component. The second contact structure extends longitudinally in the first direction in the region of the semiconductor structure. The first contact structure and the second contact structure sandwich the second gate structure.

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