Solar cell, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a solar cell piece, a cell assembly and a photovoltaic system, in the solar cell piece, a P-type silicon substrate is adopted as a base layer, the first surface of the P-type silicon substrate is not completely covered by a P-type doping layer, and the second surface of the P-type silicon substrate is not completely covered by an N-type doping layer, so that the P-type silicon substrate is not completely covered by a P-type doping layer, and the N-type doping layer is not completely covered by an N-type doping layer. Parasitic absorption of the P-type doping layer and the N-type doping layer to light can be effectively reduced, meanwhile, the passivation effect is improved, and then the conversion efficiency is improved. Moreover, on the P-type silicon substrate, the P-type doping layer is arranged on the light-facing surface and is locally arranged, so that the passivation effect can be improved while parasitic absorption is reduced; the N-type doping layer is locally arranged on the backlight face, and the sum of the areas of all the third areas is set to be larger than the sum of the areas of all the first areas, so that parasitic absorption of the back face can be reduced, and meanwhile efficiency reduction caused by the fact that the area of a PN junction is too small is avoided.

Description

[0001] Priority information

[0002] This application claims priority and benefits of patent applications with patent application numbers 202310996449.7 and 202322129692.7 filed with the State Intellectual Property Office of China on August 8, 2023, and the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a solar cell sheet, a battery assembly and a photovoltaic system. Background Art

[0004] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductor pn junction to convert sunlight into electrical energy.

[0005] In the related art, a front emitter region is usually formed on the entire front surface of a silicon wafer, and a back emitter region is formed on the front surface of the back surface, and then a passivation film layer and an electrode are provided to form a double-sided solar cell that can receive light. However, in such a scheme, the entire front and back surfaces are covered by a doped layer that forms an emitter or back field region, and the doped layer has a high parasitic absorption of light, resulting in a low conversion efficiency of the solar cell.

[0006] In order to solve the problem of high parasitic absorption, a local contact solution can be adopted. However, the local passivation contact of the prior art does not consider how to balance the relationship between parasitic absorption and the area of ​​the PN junction. Although it effectively reduces the parasitic absorption, it is easy to cause the PN junction area to be too small and affect the efficiency. Especially in the technical solution using a P-type silicon substrate, the passivation effect of the P-type polysilicon layer on the P-type silicon substrate is poor. If the P-type doped layer is set on the entire front side and the N-type doped layer is set on the entire back side, it will lead to large parasitic absorption and poor passivation effect. If the P-type polysilicon is set on the entire back side and the N-type doped layer is set on the front side, on the one hand, the area of ​​the P-type polysilicon is relatively large, resulting in poor passivation effect of the battery and thus low efficiency. On the other hand, the N-type doped layer is set on the front side, and the parasitic absorption of light is high, which will also lead to a decrease in conversion efficiency. At the same time, if the N-type doped layer on the front side and the P-type doped layer on the back side are set as local contacts, it is easy to cause the PN junction area to be too small and reduce efficiency.

[0007] Therefore, how to reduce parasitic absorption while ensuring the efficiency of solar cells has become a technical problem studied by technicians. Utility Model Content

[0008] The present application provides a solar cell sheet, a battery assembly and a photovoltaic system, aiming to solve the technical problem of how to reduce parasitic absorption while ensuring the efficiency of the solar cell.

[0009] The present application is implemented in this way. The solar cell of the embodiment of the present application includes:

[0010] A P-type silicon substrate, the P-type silicon substrate having a first surface and a second surface opposite to the first surface, the first surface being a light-facing surface, the second surface being a light-backed surface, the first surface having a plurality of first regions and second regions alternately arranged in sequence, and the second surface having a plurality of third regions and fourth regions alternately arranged in sequence;

[0011] A P-type doped layer disposed on the first region and not covering the second region;

[0012] a first dielectric layer disposed between the P-type doped layer and the first surface;

[0013] An N-type doped layer disposed on the third region and not covering the fourth region, wherein the sum of areas of all the third regions is greater than the sum of areas of all the first regions;

[0014] a second dielectric layer disposed between the N-type doped layer and the second surface; and

[0015] A first electrode and a second electrode, wherein the first electrode contacts the P-type doping layer, and the second electrode contacts the N-type doping layer.

[0016] Furthermore, an area of ​​at least a portion of the third region is larger than an area of ​​at least a portion of the first region.

[0017] Furthermore, an area of ​​each of the third regions is larger than an area of ​​each of the first regions.

[0018] Furthermore, the number of the first regions is less than or equal to the number of the third regions.

[0019] Furthermore, the number of the first electrodes is less than or equal to the number of the second electrodes.

[0020] Furthermore, the ratio of the area of ​​the first region to the area of ​​the first surface is less than 8%.

[0021] Furthermore, the ratio of the area of ​​the first region to the area of ​​the first surface is less than 6%.

[0022] Furthermore, the ratio of the area of ​​the first region to the area of ​​the first surface is less than 5%.

[0023] Furthermore, the ratio of the area of ​​the third region to the area of ​​the second surface is greater than or equal to 30% and less than 100%.

[0024] Furthermore, an area ratio of the third region to the second surface is greater than or equal to 40% and less than 100%.

[0025] Furthermore, the area ratio of the third region to the second surface is greater than or equal to 50% and less than 100%.

[0026] Furthermore, an area ratio of the third region to the second surface is greater than or equal to 60% and less than 100%.

[0027] Furthermore, the oxygen content in the P-type silicon substrate is less than or equal to 12.5 ppma.

[0028] Furthermore, the oxygen content in the P-type silicon substrate is less than or equal to 12 ppma.

[0029] Furthermore, the oxygen content in the P-type silicon substrate is less than or equal to 11 ppma.

[0030] Furthermore, the oxygen content in the P-type silicon substrate is less than or equal to 10 ppma.

[0031] Furthermore, the surface of the P-type silicon substrate corresponding to the first region has a flat structure; and / or

[0032] The surface of the P-type silicon substrate corresponding to the first region has a tower base or a micro-texture structure.

[0033] Furthermore, the surface of the P-type silicon substrate corresponding to the second region has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

[0034] Furthermore, the surface of the P-type silicon substrate corresponding to the third region has a planarized structure; or

[0035] The surface of the P-type silicon substrate corresponding to the third region has a tower base or a micro-texture structure.

[0036] Furthermore, the surface of the P-type silicon substrate corresponding to the fourth region has a flat structure; or

[0037] The surface of the P-type silicon substrate corresponding to the fourth region has a tower base or a micro-texture structure; or

[0038] The surface of the P-type silicon substrate corresponding to the fourth region has a pyramid structure, an inverted pyramid structure, or a chain pyramid velvet structure.

[0039] Furthermore, the thickness of the N-type doping layer is smaller than the thickness of the P-type doping layer.

[0040] Furthermore, the P-type doped layer and the N-type doped layer both include doped semi-insulating polysilicon layers.

[0041] Furthermore, the width of the third region is greater than the width of the first region.

[0042] Furthermore, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

[0043] Furthermore, both the first dielectric layer and the second dielectric layer are porous dielectric layers, and the size of the holes in the first dielectric layer is larger than the size of the holes in the second dielectric layer.

[0044] Furthermore, both the first dielectric layer and the second dielectric layer are porous dielectric layers, and the number of holes per unit area in the first dielectric layer is greater than the number of holes per unit area in the second dielectric layer.

[0045] Furthermore, the second region and the fourth region are both groove regions.

[0046] Furthermore, the trench corresponding to the second region extends to below the P-type doped layer, and the P-type doped layer includes a suspended portion suspended above the trench.

[0047] Furthermore, a width of a surface of the N-type doped layer in contact with the second dielectric layer is greater than a width of a surface of the N-type doped layer on which the second electrode is disposed.

[0048] Furthermore, a first inner expansion layer is formed between the first dielectric layer and the P-type silicon substrate, and a first preset distance exists between the first inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

[0049] Furthermore, a second inner expansion layer is formed between the second dielectric layer and the P-type silicon substrate, and a second preset distance exists between the second inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

[0050] Furthermore, the thickness of the second inner expansion layer is greater than the thickness of the first inner expansion layer; and / or

[0051] The doping concentration of the second inner extension layer is greater than the doping concentration of the first inner extension layer; and / or

[0052] The width of the second inner expansion layer is greater than the width of the first inner expansion layer.

[0053] Furthermore, the second preset distance is greater than the first preset distance.

[0054] Furthermore, the distance between the N-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate is greater than the distance between the P-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

[0055] The present application also provides a battery assembly, which includes any of the solar cell sheets described above.

[0056] The present application also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0057] In the solar cell, battery assembly and photovoltaic system of the embodiment of the present application, a P-type silicon substrate is used as the base layer of the solar cell, the P-type doped layer only covers the first area of ​​the first surface and does not cover the second area, the N-type doped layer only covers the third area of ​​the second surface and does not cover the fourth area, and the sum of the areas of all the third areas is greater than the sum of the areas of all the first areas. In this way, the P-type silicon substrate is used as the base layer, the first surface of the P-type silicon substrate is not completely covered by the P-type doped layer, and the second surface of the P-type silicon substrate is not completely covered by the N-type doped layer, that is, only the P-type doped layer is set on the first area for local passivation, and the second area is directly passivated by the first passivation film layer, the passivation performance is better, and the passivation effect of the first surface can be improved. In this way, the parasitic absorption of light by the P-type doped layer and the N-type doped layer can be effectively reduced while the passivation effect is improved, thereby improving the conversion efficiency. Furthermore, on a P-type silicon substrate, setting a P-type doped layer on the light-facing surface and setting it locally can reduce parasitic absorption while improving the passivation effect, while setting an N-type doped layer locally on the backlight surface and setting the sum of the areas of all third regions to be larger than the sum of the areas of all first regions can reduce the parasitic absorption on the back side while avoiding the area of ​​the PN junction being too small to cause a decrease in efficiency.

[0058] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a module schematic diagram of a photovoltaic system provided in an embodiment of the present application;

[0060] Figure 2 is a module schematic diagram of a battery assembly provided in an embodiment of the present application;

[0061] Figure 3 is a schematic diagram of the cross-sectional structure of a solar cell provided in an embodiment of the present application;

[0062] Figure 4is a schematic diagram of a partial structure of a solar cell provided in an embodiment of the present application;

[0063] Figure 5 is another partial structural schematic diagram of a solar cell provided in an embodiment of the present application;

[0064] Figure 6 is another schematic cross-sectional structure diagram of a solar cell provided in an embodiment of the present application;

[0065] Figure 7 is another schematic cross-sectional structure diagram of a solar cell provided in an embodiment of the present application;

[0066] Figure 8 It is a schematic diagram of a process for preparing a solar cell provided in an embodiment of the present application;

[0067] Fig. 9 is another schematic flow chart of the method for preparing a solar cell provided in an embodiment of the present application;

[0068] Fig.10 This is another schematic flow chart of the method for preparing a solar cell provided in an embodiment of the present application.

[0069] Description of main component symbols:

[0070] Photovoltaic system 1000, battery assembly 200, solar cell 100, P-type silicon substrate 10, first surface 11, first region 111, second region 112, second surface 12, third region 121, fourth region 122, P-type doping layer 20, first dielectric layer 30, N-type doping layer 40, second dielectric layer 50, first electrode 60, second electrode 70, first passivation film layer 80, second passivation film layer 90, first inner expansion layer 110, second inner expansion layer 120. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0072] In the description of the present application, it should be understood that the terms "upper", "lower", "length", "width", "back" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0073] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0074] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0075] Embodiment 1

[0076] See also Figure 1-Figure 2 The photovoltaic system 1000 in the embodiment of the present application may include the battery assembly 200 in the embodiment of the present application. The battery assembly 200 in the embodiment of the present application may include multiple solar cells 100 in the embodiment of the present application. The multiple solar cells 100 in the battery assembly 200 may be connected in series in sequence to form a battery string. The battery strings may be connected in series, in parallel, or in series-parallel combination to realize current bus output. For example, the connection between the battery cells may be achieved by welding welding strips, and the connection between the battery strings may be achieved by bus bars.

[0077] See also Figure 3 The solar cell 100 in the embodiment of the present application may include a P-type silicon substrate 10 , a P-type doping layer 20 , a first dielectric layer 30 , an N-type doping layer 40 , a second dielectric layer 50 , a first electrode 60 , and a second electrode 70 .

[0078] like Figure 3 As shown, the P-type silicon substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, the first surface 11 is a light-facing surface, and the second surface 12 is a backlight surface, the light-facing surface can be understood as the side facing the sunlight when the solar cell 100 is installed, and the backlight surface can be understood as the side facing away from the sunlight when the solar cell 100 is installed. The first surface 11 has a plurality of first regions 111 and second regions 112 alternately arranged in sequence, and the second surface 12 has a plurality of third regions 121 and fourth regions 122 alternately arranged in sequence.

[0079] The P-type doped layer 20 is disposed on the first region 111 and does not cover the second region 112. That is, on the first surface 11, a plurality of P-type doped layers 20 are disposed at intervals through the second region 112, and two adjacent P-type doped layers 20 are separated by one second region 112. The first dielectric layer 30 is disposed between the P-type doped layer 20 and the first surface 11.

[0080] Specifically, the first dielectric layer 30 may be a tunneling oxide layer, such as a silicon dioxide film layer, and the first dielectric layer 30 may cover the entire first region 111 or the first dielectric layer 30 may cover the entire first region 111 and at least a portion of the second region 112 , which is not specifically limited herein.

[0081] The N-type doped layer 40 is disposed on the third region 121 and does not cover the fourth region 122. The second dielectric layer 50 is disposed between the N-type doped layer 40 and the second surface 12. The polarity of the N-type doped layer 40 is opposite to that of the P-type doped layer 20. That is, on the second surface 12, a plurality of N-type doped layers 40 are disposed at intervals through the fourth region 122, and two adjacent N-type doped layers 40 are separated by a fourth region 122. The sum of the areas of all the third regions 121 is greater than the sum of the areas of all the first regions 112. It can be understood that in the P-type silicon substrate 10, the overall areas of the first surface 11 and the second surface 12 are equal. The sum of the areas of all the third regions 121 is greater than the sum of the areas of all the first regions 112, which means that in the solar cell 100, the sum of the overall areas of all the N-type doped layers 40 is greater than the sum of the areas of all the P-type doped layers 20.

[0082] Specifically, the second dielectric layer 50 may also be a tunneling oxide layer, such as a silicon dioxide film layer. The second dielectric layer 50 may cover the entire third region 121 to achieve carrier tunneling, or the second dielectric layer 50 may cover the entire third region 121 and at least part of the fourth region 122. There is no specific limitation here.

[0083] The first electrode 60 contacts the P-type doping layer 20 , and the second electrode 70 contacts the N-type doping layer 40 .

[0084] In the solar cell 100, the battery assembly 200 and the photovoltaic system 1000 of the embodiment of the present application, a P-type silicon substrate 10 is used as the base layer of the solar cell 100, the P-type doped layer 20 only covers the first area 111 of the first surface 11 and does not cover the second area 112, the N-type doped layer 40 only covers the third area 121 of the second surface 12 and does not cover the fourth area 122, and the sum of the areas of all the third areas 121 is greater than the sum of the areas of all the first areas 112.

[0085] In this way, the P-type silicon substrate 10 is used as the base layer, the first surface 11 of the P-type silicon substrate 10 is not completely covered by the P-type doping layer 20, and the second surface 12 of the P-type silicon substrate is not completely covered by the N-type doping layer 40, that is, only the P-type doping layer is set on the first area 111 for local passivation, and the second area 112 is directly passivated by the first passivation film layer 80, which has good passivation performance and can improve the passivation effect of the first surface 11. In this way, the parasitic absorption of light by the P-type doping layer 20 and the N-type doping layer 40 can be effectively reduced while improving the passivation effect, thereby improving the conversion efficiency. In addition, on the P-type silicon substrate 10, the P-type doping layer 20 is set on the light-facing surface and the local setting can reduce the parasitic absorption and improve the passivation effect, while the N-type doping layer 40 is set locally on the backlight surface and the sum of the areas of all the third areas 121 is set to be greater than the sum of the areas of all the first areas 112, which can reduce the parasitic absorption of the back while avoiding the area of ​​the PN junction being too small to reduce the efficiency.

[0086] It can be understood that since the passivation effect of the P-type doping layer 20 on the P-type silicon substrate 10 is poor and there is parasitic absorption, it is necessary to reduce the area of ​​the P-type doping layer 20 as much as possible to reduce parasitic absorption and improve the passivation effect. At the same time, for the solar cell 100, the parasitic absorption on the light-facing side has a greater impact on the efficiency than the parasitic absorption on the back side. Therefore, the P-type doping layer 20 is set on the light-facing surface and is set locally, which can improve the passivation effect while reducing parasitic absorption. At the same time, the area of ​​the PN junction will also affect the effect of the solar cell 100. If the N-type doping layer 40 is set on the light-facing surface and the P-type doping layer 20 is set on the backlight surface, in order to reduce the parasitic absorption on the light-facing side as much as possible, the area of ​​the N-type doping layer 40 needs to be set smaller. At the same time, in order to improve the passivation effect, the area of ​​the P-type doping layer 20 should also be set smaller. In this case, the area of ​​the PN junction of the solar cell 100 will be smaller and affect the efficiency, which forms a contradiction.

[0087] Therefore, in the embodiment of the present application, a P-type silicon substrate 10 is used, the P-type doped layer 20 is locally arranged on the light-facing surface, the N-type doped layer 40 is arranged on the backlight surface, and the sum of the areas of all the third regions 121 is set to be larger than the sum of the areas of all the first regions 112. This can improve the passivation effect while reducing the parasitic absorption of the light-facing layer and the backlight side. At the same time, it can also avoid the area of ​​the N-type doped layer 40 being too small, which will cause the area of ​​the PN junction to be too small and affect the efficiency.

[0088] That is to say, in the embodiment of the present application, by designing the structure of the silicon substrate, the P-type doping layer 20 and the N-type doping layer 40 of the solar cell 100, and setting the sum of the areas of the third region 121 to be greater than the sum of the areas of the first region 111, the parasitic absorption on the light-facing side and the backlight side can be reduced at the same time, while the passivation effect can be improved and the area of ​​the PN junction can be guaranteed as much as possible, thereby improving the efficiency of the solar cell 100. In other words, although the P-type doping layer 20 and the N-type doping layer 40 are in local contact with the P-type silicon substrate 10, due to the reduction of parasitic absorption and the improvement of the passivation effect, and by reasonably setting the areas of the third region 121 and the first region 111, it can also improve the efficiency of the solar cell 100.

[0089] Specifically, in an embodiment of the present application, the solar cell 100 is a solar cell with a double-sided passivation contact structure, the first dielectric layer 30 and the P-type doped layer 20 form a tunneling passivation structure of the first surface 11, and the second dielectric layer 50 and the N-type doped layer 40 form a tunneling passivation structure of the second surface 12.

[0090] It is understandable that if Figure 3 As shown, a first passivation film layer 80 is further provided on the first surface 11 of the solar cell 100 of the present application. The first passivation film layer 80 covers the entire first surface 11 , that is, the first passivation film layer 80 covers the P-type doping layer 20 and the second region 112 .

[0091] A second passivation film layer 90 is provided on the second surface 12 , and the second passivation film layer 90 covers the entire second surface 12 , that is, the second passivation film layer 90 covers the N-type doped layer 40 and the fourth region 122 , the first electrode 60 contacts the P-type doped layer 20 through the first passivation film layer 80 , and the second electrode 70 contacts the N-type doped layer 40 through the second passivation film layer 90 .

[0092] The first passivation film layer 80 may include at least one of an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer, or a combination of multiple thereof. For example, in some embodiments, the first passivation film layer 80 may include an aluminum oxide film layer and a silicon nitride film layer stacked in sequence, which is not specifically limited herein. The second passivation film layer 90 may also include at least one of an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer, or a combination of multiple thereof.

[0093] It is understood that in the embodiment of the present application, the battery assembly 200 may also include a metal frame, a back plate, a photovoltaic glass and an adhesive film (not shown in the figure). The adhesive film may be filled between the front and photovoltaic glass, the back and the back plate of the solar cell 100, and between adjacent cells, etc. As a filler, it may be a transparent colloid with good light transmission and aging resistance. For example, the adhesive film may be an EVA adhesive film or a POE adhesive film, which may be selected according to actual conditions and is not limited here.

[0094] Photovoltaic glass can cover the adhesive film on the front side of the solar cell 100. The photovoltaic glass can be ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical and optical properties. For example, the light transmittance of ultra-white glass can reach more than 92%, and it can protect the solar cell 100 without affecting the efficiency of the solar cell 100 as much as possible. At the same time, the adhesive film can bond the photovoltaic glass and the solar cell 100 together, and the existence of the adhesive film can seal and insulate the solar cell 100 and make it waterproof and moisture-proof.

[0095] The back plate can be attached to the adhesive film on the back of the solar cell 100. The back plate can protect and support the solar cell 100 and has reliable insulation, water resistance and aging resistance. There are multiple options for the back plate, which can usually be tempered glass, organic glass, aluminum alloy TPT composite adhesive film, etc. It can be set according to specific circumstances and is not limited here. The whole composed of the back plate, solar cell 100, adhesive film and photovoltaic glass can be set on a metal frame. The metal frame serves as the main external support structure of the entire battery assembly 200 and can stably support and install the battery assembly 200. For example, the battery assembly 200 can be installed at the required installation position through the metal frame.

[0096] Furthermore, in this embodiment, the photovoltaic system 1000 can be applied to photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system 1000 are not limited to this, that is, the photovoltaic system 1000 can be applied in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system 1000 may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple battery assemblies 200. For example, multiple battery assemblies 200 may form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0097] In some embodiments, the area of ​​at least part of the third region 121 is larger than the sum of the areas of at least part of the first region 111. In this way, by making the area of ​​at least part of the third region 121 larger, the sum of the areas of all the third regions 121 is also larger than the sum of the areas of all the first regions 111, thereby ensuring the area of ​​the PN junction to ensure efficiency while reducing parasitic absorption.

[0098] In some embodiments, it is preferred that the area of ​​each third region 121 is larger than the area of ​​each first region 111 so that the sum of the areas of all the third regions 121 is larger than the sum of the areas of all the first regions 111 .

[0099] Further, in some embodiments, the number of the first regions 111 is less than or equal to the number of the third regions 121 .

[0100] Furthermore, in some embodiments, the number of the first electrodes 60 is less than the number of the second electrodes 70. Thus, when each first electrode 60 corresponds to a P-type doped layer 20 and each second electrode 70 corresponds to an N-type doped layer 40, the number of the N-type doped layers 40 is relatively large, so that the sum of the areas of all the N-type doped layers 40 is greater than the sum of the areas of all the P-type doped layers 20, so as to reduce parasitic absorption while ensuring the area of ​​the PN junction to ensure efficiency.

[0101] In some embodiments, the sum of the areas of all the second regions 112 is greater than the sum of the areas of all the fourth regions 122. Thus, by reasonably setting the areas of the second region 112 and the fourth region 122, the sum of the areas of all the third regions 121 can be made greater than the sum of the areas of all the first regions 111. That is, by controlling the area of ​​the second region 112 to be larger, the contact area between the P-type doped layer 20 and the P-star silicon substrate can be reduced as much as possible, and the passivation effect can be improved while reducing parasitic absorption, and at the same time, the area of ​​the N-type doped layer 40 can be prevented from being too small, resulting in a reduction in the area of ​​the PN junction and affecting the efficiency.

[0102] Furthermore, in some embodiments, it is preferred that the area of ​​a single second region 112 is larger than the area of ​​a single fourth region 122 , so that the sum of the areas of all second regions 112 is larger than the sum of the areas of all fourth regions 122 .

[0103] In some embodiments, the thickness of the N-type doping layer 40 is less than the thickness of the P-type doping layer 20 .

[0104] Thus, in the P-type silicon substrate 10 , setting the thickness of the P-type doping layer 20 to be thicker can improve the passivation effect of the first surface 11 , thereby improving the electrical performance of the cell. That is, the passivation effect can be improved by increasing the thickness of the P-type doping layer 20 .

[0105] In some embodiments, both the P-type doping layer 20 and the N-type doping layer 40 may include a doped semi-insulating polysilicon layer. In this way, the materials of the P-type doping layer 20 and the N-type doping layer 40 are both semi-insulating polysilicon, which has less parasitic absorption than traditional polysilicon, that is, using such a material can reduce parasitic absorption and improve conversion efficiency.

[0106] Embodiment 2

[0107] In some embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the first surface 11 (ie, the area proportion of the first region 111 ) is less than 8%.

[0108] Thus, setting the area ratio of the first region 111 to the first surface 11 within a range of less than 8% can greatly reduce the area ratio of the P-type doping layer 20, thereby reducing the parasitic absorption of the P-type doping layer 20 and improving efficiency. At the same time, setting the area of ​​the first region 111 to be smaller can increase the area of ​​the second region 112, thereby improving the passivation effect of the first surface 11, that is, the passivation effect of the first surface 11 can be improved while reducing the parasitic absorption, thereby improving efficiency.

[0109] Further, in such an embodiment, the ratio of the area of ​​the first region 111 to the area of ​​the first surface 11 is preferably less than 6%, and most preferably less than 5%. In this way, the area of ​​the first region 111 can be set as small as possible to reduce parasitic absorption while improving the passivation effect.

[0110] Embodiment 3

[0111] In some embodiments, the ratio of the area of ​​the third region 121 to the area of ​​the second surface 12 is greater than or equal to 30% and less than 100%.

[0112] In this way, the area of ​​the third region 121 of the second surface 12 is set larger, which can ensure the area ratio of the N-type doped layer 40 while reducing parasitic absorption, balance the passivation contact area (PN junction area) and parasitic absorption of the N-type doped layer 40, and thus improve the conversion efficiency.

[0113] Further, in such an embodiment, the area ratio of the third region 121 to the second surface 12 is preferably greater than or equal to 40% and less than 100%, and further, in such an embodiment, the area ratio of the third region 121 to the second surface 12 is more preferably greater than or equal to 50% and less than 100%, and most preferably greater than or equal to 60% and less than 100%. In this way, the parasitic absorption and the area of ​​the PN junction can be balanced, thereby reducing the parasitic absorption while ensuring the area of ​​the PN junction as much as possible to ensure efficiency.

[0114] Embodiment 4

[0115] In some embodiments, the oxygen content in the P-type silicon substrate 10 is less than or equal to 12.5 ppma.

[0116] In this way, the oxygen content of the P-type silicon substrate 10 is set to be lower than 12.5 ppma, which can avoid the oxygen content in the P-type silicon substrate 10 being too high, resulting in the formation of oxygen precipitation in the P-type silicon substrate 10 when the P-type doping layer 20 and the N-type doping layer 40 are subsequently formed, thereby reducing the minority carrier lifetime in the P-type silicon substrate 10 and improving the conversion efficiency.

[0117] Specifically, it is not difficult to understand that in the manufacturing process of the battery cell, high temperature is usually used for processing to realize the preparation of the front emitter and the back field (that is, the P-type doping layer 20 and the N-type doping layer 40). During the high temperature process, if the oxygen content in the P-type silicon substrate 10 is too high, it will cause the P-type silicon substrate 10 to produce radially distributed annular or spiral oxygen precipitation during the high temperature process, which will cause the lifetime of the minority carriers in the P-type silicon substrate to decrease, resulting in higher photoinduced decay and lower conversion efficiency.

[0118] In the present application, the inventors of the present application have found through research and verification that by controlling the oxygen content in the P-type silicon substrate 10 to be within 12.5 ppma, the formation of oxygen precipitation can be effectively suppressed, thereby improving the conversion efficiency.

[0119] Further, in such an embodiment, the oxygen content in the P-type silicon substrate 10 may preferably be less than or equal to 12 ppma. Further, in such an embodiment, the oxygen content in the P-type silicon substrate 10 is preferably less than or equal to 11 ppma, and most preferably less than 10 ppma. Specifically, the inventors of the present application have found through research and verification that by reducing the oxygen content to 12 ppma, 11 ppma, or even below 10 ppma, the formation of oxygen precipitation can be further suppressed and the lifetime of minority carriers can be increased.

[0120] Embodiment 5

[0121] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the first region 111 may have a flat structure, that is, the surface area corresponding to the first region 111 may be a planarized surface.

[0122] Of course, in some embodiments, the surface of the P-type silicon substrate 10 corresponding to the first region 111 has a tower base or micro-texture structure, that is, the surface area corresponding to the first region 111 is a tower base plane or a micro-texture surface.

[0123] It can be understood that, in some implementations, the surface of the P-type silicon substrate 10 corresponding to the first region 111 may also have a flat structure and a tower base or a micro-texture structure at the same time, which is not specifically limited here.

[0124] Embodiment 6

[0125] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the second region 112 has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

[0126] Embodiment 7

[0127] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the third region 121 has a planarized structure, that is, the surface area corresponding to the third region 121 may be a planarized surface.

[0128] Of course, in some embodiments, the surface of the P-type silicon substrate 10 corresponding to the third region 121 has a tower base or micro-texture structure, that is, the surface area corresponding to the third region 121 is a tower base surface or a micro-texture surface.

[0129] It can be understood that, in some implementations, the surface of the P-type silicon substrate 10 corresponding to the third region 121 may also have a flat structure and a tower base or a micro-texture structure at the same time, which is not specifically limited here.

[0130] Embodiment 8

[0131] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the fourth region 122 has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

[0132] Embodiment 9

[0133] See also Figure 3 In some embodiments, the width H2 of the third region 121 is greater than the width H1 of the first region 111 .

[0134] In this way, the width of the N-type doped layer 40 on the third region 121 on the backlight surface is greater than the width of the P-type doped layer 20 on the first region 111 on the light-facing surface, which can reduce the parasitic absorption of the N-type doped layer 40 while avoiding the passivation contact area (i.e., the area of ​​the PN junction) of the N-type doped layer 40 to the P-type silicon substrate 10 being too small to significantly affect the efficiency. It can be understood that in such an embodiment, the length of the first region 11 is consistent with the length of the third region 121.

[0135] Embodiment 10

[0136] In some embodiments, the thickness of the first dielectric layer 30 is greater than the thickness of the second dielectric layer 50 .

[0137] Thus, setting the thickness of the first dielectric layer 30 to be thicker can ensure the passivation effect of the first surface 11 .

[0138] Specifically, in such an embodiment, in the P-type silicon substrate 10 , since the passivation effect of the P-type doping layer 20 is relatively poor, in order to ensure the passivation effect of the light-facing surface, the thickness of the first dielectric layer 30 may be set thicker to improve efficiency.

[0139] Embodiment 11

[0140] In some embodiments, both the first dielectric layer 30 and the second dielectric layer 50 may be porous dielectric layers, and the size of the pores in the first dielectric layer 30 is larger than the size of the pores in the second dielectric layer 50 .

[0141] In this way, the first dielectric layer 30 and the second dielectric layer 50 are both configured as porous dielectric layers and the pore size of the first dielectric layer 30 is relatively large, so that the longitudinal resistance of the first dielectric layer 30 can be controlled at a reasonable level.

[0142] Furthermore, in some embodiments, both the first dielectric layer 30 and the second dielectric layer 50 are porous dielectric layers, and the number of holes per unit area in the first dielectric layer 30 is greater than the number of holes per unit area in the second dielectric layer 50 .

[0143] In this way, the more holes per unit area in the first dielectric layer 30 are, the more the longitudinal resistance of the first dielectric layer 30 can be controlled at a reasonable level.

[0144] Embodiment 12

[0145] In some embodiments, the second region 112 and the fourth region 122 are both trench regions, that is, in the second region 112 and the fourth region 122 , the P-type silicon substrate 10 is sunken to form a groove.

[0146] In this way, by forming a groove area, the P-type doped layer 20 and the first dielectric layer 30 covering the second area 112 and the N-type doped layer 40 and the second dielectric layer 50 covering the fourth area 122 can be removed, thereby forming an exposed second area 112 and fourth area 122, so that the first passivation film layer 80 and the second passivation film layer 90 can directly cover the second area 112 and the fourth area 122 directly on the P-type silicon substrate 10, thereby improving the passivation performance.

[0147] Specifically, in such an embodiment, a first dielectric layer 30 and a P-type doped layer 20 may be formed on the first surface 11, and then a portion of the first dielectric layer 30 and the N-type doped layer 40 may be etched away by etching to form a second region 112 (i.e., a groove region). Similarly, for the fourth region 122, a second dielectric layer 50 and an N-type doped layer 40 may be formed on the second surface 12, and then a portion of the second dielectric layer 50 and the fourth doped layer may be etched away by etching to form a fourth region 122 (i.e., a groove region).

[0148] Embodiment 13

[0149] For further information, see Figure 4 In some embodiments, the trench corresponding to the second region 112 extends to below the P-type doped layer 20, and the P-type doped layer 20 includes a suspended portion 31 suspended above the trench.

[0150] In this way, when the second area 112 of the groove area is formed, the groove extends and etches away part of the P-type silicon substrate 10 below the P-type doped layer 20 so that the P-type doped layer 20 has a suspended portion 31, which can further reduce the passivation contact area of ​​the P-type doped layer 20 with the P-type silicon substrate 10, thereby improving the passivation effect.

[0151] Embodiment 14

[0152] See also Figure 5In some embodiments, the width of the surface of the N-type doping layer 40 in contact with the second dielectric layer 50 is greater than the width of the surface of the N-type doping layer 40 where the second electrode 70 is disposed.

[0153] In this way, it is possible to avoid the passivation contact area of ​​the N-type doped layer 40 to the P-type silicon substrate 10 being too small, thereby significantly affecting the battery efficiency.

[0154] Specifically, Figure 5 As shown, in such an embodiment, the N-type doping layer 40 may be in an inverted trapezoidal shape, and the width of the N-type doping layer 40 gradually decreases along the direction from the first surface 11 to the second surface 12 .

[0155] Embodiment 15

[0156] See also Figure 6 In some embodiments, a first inner expansion layer 110 is formed between the first dielectric layer 30 and the P-type silicon substrate 10 , and a first preset distance L1 is present between the first inner expansion layer 110 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 .

[0157] In this way, when the P-type doped layer 20 is formed, a first inner expansion layer 110 is formed on the P-type silicon substrate 10. The first inner expansion layer 110 at the edge position is set to have a certain distance from the side surface of the P-type silicon substrate 10, which can avoid the first inner expansion layer 110 extending to the edge of the P-type silicon substrate 10 and contacting the N-type doped layer 40 on the second surface 12 to cause leakage.

[0158] Specifically, the “first inner expansion layer 110 located at the edge of the P-type silicon substrate 10” refers to the first inner expansion layer 110 located at the edge of both sides of the first region 111 and the second region 112 on the first surface 11 of the P-type silicon substrate 10. Figure 6 As shown, the first inner expansion layer 110 located at the edge of the P-type silicon substrate 10 is Figure 6 The leftmost first inner expansion layer 110 and the rightmost first inner expansion layer 110 in FIG. 1 are shown in FIG. 1 , and the side surface of the P-type silicon substrate 10 refers to Figure 6 The left and right sides.

[0159] In such an embodiment, the size of the first preset distance may be 0.3um-50um, for example, the size of the first preset distance may be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 15um, 20um, 25um, 30um, 40um, 45um, 50um or any value between 0.3um-50um, which is not limited here. In an embodiment of the present application, the size of the first preset distance may preferably be 1um-20um.

[0160] Embodiment 16

[0161] See also Figure 7 In some embodiments, a second inner expansion layer 120 is formed between the second dielectric layer 50 and the P-type silicon substrate 10 , and a second preset distance L2 is present between the second inner expansion layer 120 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 .

[0162] In this way, when the N-type doped layer 40 is formed, a second inner expansion layer 120 is formed on the P-type silicon substrate 10. The second inner expansion layer 120 at the edge position is set to have a certain distance from the side of the P-type silicon substrate 10, which can avoid the second inner expansion layer 120 extending to the edge of the P-type silicon substrate 10 and contacting the first inner expansion layer 110 to cause leakage.

[0163] Specifically, the “second inner expansion layer 120 located at the edge of the P-type silicon substrate 10” refers to the second inner expansion layer 120 located at the edge of both sides of the third region 121 and the fourth region 122 on the second surface 12 of the P-type silicon substrate 10. Figure 7 As shown, the second inner expansion layer 120 located at the edge of the P-type silicon substrate 10 is Figure 7 The leftmost second inner expansion layer 120 and the rightmost second inner expansion layer 120 in FIG. 1 are shown in FIG. 1 . The side surface of the P-type silicon substrate 10 refers to Figure 7 The left and right sides.

[0164] In such an embodiment, the size of the second preset distance may be 0.3um-50um, for example, the size of the second preset distance may be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 15um, 20um, 25um, 30um, 40um, 45um, 50um or any value between 0.3um-50um, which is not limited here. In an embodiment of the present application, the size of the second preset distance may preferably be 1um-20um.

[0165] In some embodiments, the thickness of the second inner expansion layer 120 may be greater than the thickness of the first inner expansion layer 110. Thus, the thickness of the second inner expansion layer 120 is greater, which can further increase the area of ​​the PN junction to improve the efficiency of the solar cell 100.

[0166] In addition, in some embodiments, the width of the second inner expansion layer 120 may also be greater than the width of the first inner expansion layer 110. In this way, the area of ​​the PN junction can be further increased to improve the efficiency of the solar cell 100.

[0167] Furthermore, in some embodiments, the doping concentration of the second inner extension layer 120 may be greater than the doping concentration of the first inner extension layer 110. Thus, the passivation effect of the PN junction contact region may be improved by setting the doping concentration of the second inner extension layer 120 to be greater.

[0168] See also Figure 7 In some embodiments, the second preset distance L2 may be preferably greater than the first preset distance L1. In this way, the second inner expansion layer 120 with a deeper diffusion depth may be prevented from contacting the first inner expansion layer 110 at the edge of the P-type silicon substrate 10.

[0169] In addition, in some embodiments, the distance between the N-type doped layer 40 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 is greater than the distance between the P-type doped layer 20 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10. In this way, the second inner expansion layer 120 formed by the N-type doped layer 40 can be further prevented from contacting the first inner expansion layer 110 formed by the P-type doped layer 20 at the edge of the P-type silicon substrate 10.

[0170] Embodiment 17

[0171] See also Figure 8 This embodiment provides a method for preparing a solar cell 100, which includes the following steps:

[0172] S10: providing a P-type silicon substrate 10;

[0173] The P-type silicon substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, the first surface 11 is a light-facing surface, the second surface 12 is a backlight surface, the first surface 11 has a plurality of first regions 111 and second regions 112 alternately arranged in sequence, and the second surface 12 has a plurality of third regions 121 and fourth regions 122 alternately arranged in sequence; the sum of the areas of all the third regions 121 is greater than the sum of the areas of all the first regions 112;

[0174] S20: sequentially forming a first dielectric layer 30 and a P-type doping layer 20 on the first region 111;

[0175] S30: sequentially forming a second dielectric layer 50 and an N-type doping layer 40 on the third region 121;

[0176] S40: preparing a first passivation film layer 80 on the first surface 11 and preparing a second passivation film layer 90 on the second surface 12;

[0177] S50 : preparing a first electrode 60 and a second electrode 70 on the first passivation film layer 80 and the second passivation film layer 90 , respectively. The first electrode 60 penetrates the first passivation film layer 80 and contacts the P-type doped layer 20 , and the second electrode 70 penetrates the second passivation film layer 90 and contacts the N-type doped layer 40 .

[0178] In this way, the P-type silicon substrate 10 is used as the base layer, the first surface 11 of the P-type silicon substrate 10 is not completely covered by the P-type doping layer 20, and the second surface 12 of the P-type silicon substrate is not completely covered by the N-type doping layer 40, that is, only the P-type doping layer is set on the first area 111 for local passivation, and the second area 112 is directly passivated by the first passivation film layer 80, which has good passivation performance and can improve the passivation effect of the first surface 11. In this way, the parasitic absorption of light by the P-type doping layer 20 and the N-type doping layer 40 can be effectively reduced while improving the passivation effect, thereby improving the conversion efficiency. In addition, on the P-type silicon substrate 10, the P-type doping layer 20 is set on the light-facing surface and the local setting can reduce the parasitic absorption and improve the passivation effect, while the N-type doping layer 40 is set locally on the backlight surface and the sum of the areas of all the third areas 121 is set to be greater than the sum of the areas of all the first areas 112, which can reduce the parasitic absorption of the back while avoiding the area of ​​the PN junction being too small to reduce the efficiency.

[0179] Embodiment 18

[0180] See also Fig. 9 In some embodiments, step S20 may be implemented by the following steps:

[0181] S21: preparing a first dielectric layer 30 on the entire first surface 11;

[0182] S22: preparing a P-type doped layer 20 on the first dielectric layer 30;

[0183] S23: removing the plating layer formed in the process of preparing the P-type doping layer 20;

[0184] S24: The P-type doped layer 20 and the first dielectric layer 30 are patterned to form a plurality of spaced grooves on the P-type doped layer 20 and the first dielectric layer 30 to expose a portion of the P-type silicon substrate 10 in the grooves. The portion of the first surface 11 exposed from the grooves is the second region 112, and the unexposed portion is the first region 111.

[0185] Specifically, in step S21 and step S22, the first dielectric layer 30 can be realized by thermal oxidation, chemical liquid oxidation, chemical vapor deposition, plasma treatment, etc., and the preparation of the P-type doping layer 20 can be formed by physical vapor deposition or chemical vapor deposition.

[0186] In step S23, the plating layer formed during the deposition process can be removed by laser or wet etching. In step S24, the P-type doped layer 20 and the first dielectric layer 30 can be patterned by acid etching, alkali etching, laser etching, or a combination of at least two of them. For example, in one example, laser patterning can be performed first, and then alkali etching can be used to remove part of the P-type doped layer 20 and the first dielectric layer 30, thereby forming a number of grooves, so that the P-type silicon substrate 10 forms a first region 111 having a P-type doped layer 20 and an exposed second region 112.

[0187] Embodiment 19

[0188] See also Fig.10 In some embodiments, step S30 may be implemented by the following steps:

[0189] S31: preparing a second dielectric layer 50 on the entire second surface 12;

[0190] S32: preparing an N-type doped layer 40 on the second dielectric layer 50;

[0191] S33: removing the plating layer formed in the process of preparing the N-type doping layer 40;

[0192] S34: The N-type doped layer 40 and the second dielectric layer 50 are patterned to form a plurality of spaced grooves on the N-type doped layer 40 and the second dielectric layer 50, thereby partially exposing the P-type silicon substrate 10 at the grooves, and the portion of the second surface 12 exposed from the grooves is the fourth region 122, and the unexposed portion is the third region 121.

[0193] Specifically, in step S31 and step S32, the second dielectric layer 50 can be realized by thermal oxidation, chemical liquid oxidation, chemical vapor deposition, plasma treatment, etc., and the preparation of the N-type doped layer 40 can be formed by physical vapor deposition or chemical vapor deposition, which is not limited here.

[0194] In step S33, the plating layer formed during the deposition process can also be removed by laser or wet etching. In step S34, the N-type doped layer 50 and the second dielectric layer 50 are patterned by acid etching, alkali etching, laser etching, or a combination of at least two of them. For example, in one example, a patterning process can be first performed by laser, and then a portion of the N-type doped layer 40 and the second dielectric layer 50 can be removed by alkali etching to form a plurality of grooves, thereby forming a third region 121 having an N-type doped layer 40 and an exposed fourth region 122 on the P-type silicon substrate 10.

[0195] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0196] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: A P-type silicon substrate, the P-type silicon substrate having a first surface and a second surface opposite to the first surface, the first surface being a light-facing surface, the second surface being a light-backed surface, the first surface having a plurality of first regions and second regions alternately arranged in sequence, and the second surface having a plurality of third regions and fourth regions alternately arranged in sequence; A P-type doped layer disposed on the first region and not covering the second region; a first dielectric layer disposed between the P-type doped layer and the first surface; An N-type doped layer disposed on the third region and not covering the fourth region, wherein the sum of areas of all the third regions is greater than the sum of areas of all the first regions; a second dielectric layer disposed between the N-type doped layer and the second surface; and A first electrode and a second electrode, wherein the first electrode contacts the P-type doping layer, and the second electrode contacts the N-type doping layer.

2. The solar cell according to claim 1, characterized in that: An area of ​​at least a portion of the third region is larger than an area of ​​at least a portion of the first region.

3. The solar cell according to claim 1, characterized in that: The area of ​​each of the third regions is greater than the area of ​​each of the first regions.

4. The solar cell according to claim 1, characterized in that: The number of the first regions is less than or equal to the number of the third regions.

5. The solar cell according to claim 4, characterized in that: The number of the first electrodes is less than or equal to the number of the second electrodes.

6. The solar cell according to claim 1, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 8%.

7. The solar cell according to claim 6, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 6%.

8. The solar cell according to claim 7, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 5%.

9. The solar cell according to claim 1, characterized in that: An area ratio of the third region to the second surface is greater than or equal to 30% and less than 100%.

10. The solar cell according to claim 9, characterized in that: An area ratio of the third region to the second surface is greater than or equal to 40% and less than 100%.

11. The solar cell according to claim 10, characterized in that: An area ratio of the third region to the second surface is greater than or equal to 50% and less than 100%.

12. The solar cell according to claim 11, characterized in that: An area ratio of the third region to the second surface is greater than or equal to 60% and less than 100%.

13. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the first region has a flat structure; and / or The surface of the P-type silicon substrate corresponding to the first region has a tower base or a micro-texture structure.

14. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the second region has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

15. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the third region has a planarized structure; or The surface of the P-type silicon substrate corresponding to the third region has a tower base or a micro-texture structure.

16. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the fourth region has a flat structure; or The surface of the P-type silicon substrate corresponding to the fourth region has a tower base or a micro-texture structure; or The surface of the P-type silicon substrate corresponding to the fourth region has a pyramid structure, an inverted pyramid structure, or a chain pyramid velvet structure.

17. The solar cell according to claim 1, characterized in that: The thickness of the N-type doping layer is smaller than the thickness of the P-type doping layer.

18. The solar cell according to claim 1, characterized in that: The P-type doping layer and the N-type doping layer both include doped semi-insulating polysilicon layers.

19. The solar cell according to claim 1, characterized in that: The width of the third region is greater than the width of the first region.

20. The solar cell according to claim 1, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

21. The solar cell according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are both porous dielectric layers, and the size of the holes in the first dielectric layer is larger than the size of the holes in the second dielectric layer.

22. The solar cell according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are both porous dielectric layers, and the number of holes per unit area in the first dielectric layer is greater than the number of holes per unit area in the second dielectric layer.

23. The solar cell according to claim 1, characterized in that: The second region and the fourth region are both groove regions.

24. The solar cell according to claim 1, characterized in that: The trench corresponding to the second region extends to below the P-type doping layer, and the P-type doping layer includes a suspended portion suspended above the trench.

25. The solar cell according to claim 1, characterized in that: A width of a surface of the N-type doping layer in contact with the second dielectric layer is greater than a width of a surface of the N-type doping layer provided with the second electrode.

26. The solar cell according to claim 1, characterized in that: A first inner expansion layer is formed between the first dielectric layer and the P-type silicon substrate, and a first preset distance exists between the first inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

27. The solar cell according to claim 26, characterized in that: A second inner expansion layer is formed between the second dielectric layer and the P-type silicon substrate, and a second preset distance exists between the second inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

28. The solar cell according to claim 27, characterized in that: The thickness of the second inner expansion layer is greater than the thickness of the first inner expansion layer; and / or The width of the second inner expansion layer is greater than the width of the first inner expansion layer.

29. The solar cell according to claim 27, characterized in that: The second preset distance is greater than the first preset distance.

30. The solar cell according to claim 1, characterized in that: The distance between the N-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate is greater than the distance between the P-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

31. A battery assembly, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 30.

32. A photovoltaic system, characterized in that: Comprising the battery assembly of claim 31.

Images