End-side comprehensive processing device suitable for cluster unmanned aerial vehicle

Abstract

The utility model provides an end-side comprehensive processing device suitable for a cluster unmanned aerial vehicle, and aims to solve the problem that in a mainstream comprehensive processing device in the prior art, the parallel computing power of a CPU chip is insufficient, so that the requirement of the cluster unmanned aerial vehicle on the comprehensive capability of the chip cannot be met. The end side comprehensive processing device suitable for the cluster unmanned aerial vehicle comprises a peripheral and sensor interface, a storage chip, a comprehensive processing chip RK3588J and a parallel computing chip Ascend 310B. The RK3588J is a universal SoC (System on Chip) adopting an ARM (Advanced RISC Machines) architecture. According to the end-side comprehensive processing device suitable for the cluster unmanned aerial vehicle, through the combination of the SoC and the AI chip, the comprehensive capability of the processing device is remarkably improved, and the problem that in a mainstream comprehensive processing device in the prior art, the parallel computing power of a CPU chip is insufficient, so that the requirement of the cluster unmanned aerial vehicle for the comprehensive capability of the chip cannot be met is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of unmanned aerial vehicles, and in particular to a terminal-side comprehensive processing device suitable for clustered unmanned aerial vehicles. Background Art

[0002] As a product with intelligent mission capabilities, swarm drones need to have both individual intelligence and group intelligence. Individual intelligence mainly includes: target detection, recognition, tracking, positioning, real-time obstacle avoidance based on vision and laser, and vision-based denial navigation, etc.; group intelligence mainly includes: cluster formation, collaborative reconnaissance, collaborative positioning, collaborative evaluation, etc.; all of the above intelligent capabilities are inseparable from strong hardware support.

[0003] In the prior art, due to the complexity of CPU circuit elements and poor performance in processing a large number of computing tasks, the parallel computing power of CPU chips in mainstream integrated processing devices is insufficient, thereby being unable to meet the requirements of cluster drones for the comprehensive capabilities of chips. Utility Model Content

[0004] The utility model provides a terminal-side integrated processing device suitable for cluster drones to solve the problem of mismatch between the processing capacity and parallel computing capacity of the integrated processing device in the prior art.

[0005] The technical solution adopted by the utility model is:

[0006] A terminal-side integrated processing device suitable for clustered drones, comprising:

[0007] Peripheral device and sensor interface, which is a channel for connecting the terminal-side integrated processing device with external devices and various sensors;

[0008] A memory chip, wherein the memory chip is used for data storage, data caching, and historical data recording;

[0009] An integrated processing chip, the integrated processing chip is connected to the peripheral device and sensor interface, and the data obtained by the peripheral device and the sensor is transmitted to the integrated processing chip through the peripheral device and the sensor interface;

[0010] A parallel computing chip is connected to the integrated processing chip.

[0011] Furthermore, it also includes:

[0012] The carrier board is a PCB board. The peripheral and sensor interface, the storage chip, the integrated processing chip, and the parallel computing chip are installed on the same carrier board to improve the integration while solving electromagnetic compatibility and overload problems.

[0013] Furthermore, the integrated processing chip is a general-purpose SoC using an ARM architecture.

[0014] Furthermore, the integrated processing chip is a Rockchip RK3588J chip.

[0015] Furthermore, the parallel computing chip is Huawei Ascend 310B chip.

[0016] Furthermore, the RK3588J chip and the Ascend 310B chip communicate in a master-slave mode based on the PCIe protocol; wherein the RK3588J chip is a master device of the PCIe bus, and the Ascend 310B chip is a slave device of the PCIe bus.

[0017] Furthermore, it also includes: a clock buffer chip, which is connected to the integrated processing chip and the parallel computing chip respectively, and is used to provide a clock signal to the RK3588J chip and the Ascend 310B chip.

[0018] Furthermore, the clock buffer chip is an INS6310A chip, and the INS6310A chip is connected to the RK3588J chip and the Ascend 310B chip respectively through a PCIe bus.

[0019] Furthermore, the peripherals and sensor interfaces include: TTL serial port interface, RS232 interface, RS485 interface, GPIO interface, PWM interface, USB interface, camera interface, Gigabit network interface. It is used to support different types of interfaces and adapt to different peripherals and sensors. Among them, the PWM interface is used to support PWM control.

[0020] Furthermore, the memory chip includes: LPDDR4 memory chip and FLASH memory chip, which are used to achieve larger storage space and faster storage efficiency and reading efficiency.

[0021] The beneficial effects of the utility model are:

[0022] RK3588J is a general-purpose SoC using ARM architecture. Ascend 310B chip is an AI chip independently developed by Huawei. The terminal-side integrated processing device of the utility model, which is suitable for cluster drones, significantly improves the comprehensive capabilities of the processing device through the combination of SoC and AI chip, and realizes 8-core CPU processing capability and 26TOPS AI processing capability, solving the problem that the parallel computing power of CPU chips in mainstream integrated processing devices in the prior art is insufficient, thus failing to meet the requirements of cluster drones for chip comprehensive capabilities.

[0023] The terminal-side integrated processing device suitable for cluster UAVs of the utility model realizes the localization of the terminal-side integrated processing device through the combined design of RK3588J and Ascend310B.

[0024] The terminal-side integrated processing device suitable for cluster drones of the utility model is highly integrated on the same PCB circuit board through RK3588J and Ascend310B, which solves the impact resistance and electromagnetic compatibility problems brought about by traditional module integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 This is a functional block diagram of an end-side integrated processing device suitable for clustered drones. DETAILED DESCRIPTION

[0027] The utility model provides an end-side integrated processing device suitable for cluster drones to solve the problem that the parallel computing power of the CPU chip in the mainstream integrated processing device in the prior art is insufficient, thereby being unable to meet the demand of cluster drones for the comprehensive capabilities of the chip.

[0028] The embodiments provided in the following disclosure are merely examples and are not intended to limit the present invention.

[0029] The embodiments of the utility model are described in detail below with reference to the accompanying drawings.

[0030] A terminal-side integrated processing device suitable for clustered drones, as shown in the attached Figure 1 As shown, including:

[0031] Peripheral device and sensor interface, which is a channel for connecting the terminal-side integrated processing device with external devices and various sensors;

[0032] A memory chip, wherein the memory chip is used for data storage, data caching, and historical data recording;

[0033] An integrated processing chip, the integrated processing chip is connected to the peripheral device and sensor interface, and the data obtained by the peripheral device and the sensor is transmitted to the integrated processing chip through the peripheral device and the sensor interface;

[0034] A parallel computing chip is connected to the integrated processing chip.

[0035] This embodiment adopts a solution of combining the above-mentioned one integrated processing chip (CPU) with a dedicated parallel computing chip (NPU), which improves the CPU processing capacity and NPU processing capacity of the integrated processing device at the same time.

[0036] Furthermore, it also includes:

[0037] The carrier board is a PCB board. The peripheral and sensor interface, the storage chip, the integrated processing chip, and the parallel computing chip are installed on the same carrier board to improve the integration while solving electromagnetic compatibility and overload problems.

[0038] Furthermore, the integrated processing chip is a general-purpose SoC using the ARM architecture. The reasons are as follows: The ARM architecture adopts a reduced instruction set design, and the instruction execution operation is relatively small, which can improve the processing speed. At the same time, its design focuses on reducing energy consumption, and achieves a good balance between high performance and low power consumption, so that the device can maintain good performance while extending battery life or reducing overall energy consumption. The ARM architecture has good multi-core thread driving performance, can achieve better parallel processing and task processing capabilities, and can meet complex multi-tasking requirements. The ARM architecture provides a wealth of peripheral interfaces and extension functions, which is convenient for developers to customize and develop according to needs, reducing the development threshold and development cycle. The ARM architecture has better fault tolerance, can operate stably in a complex working environment, provides higher reliability and stability, reduces the probability of system failure, and reduces the risks of data loss and system downtime caused by failures.

[0039] Furthermore, the integrated processing chip is Rockchip RK3588J chip. The reasons are as follows:

[0040] RK3588J is a general-purpose SoC using ARM architecture, integrating quad-core Coretex-A76 and quad-core Coretex-A55, G610 MP4 graphics processor, and separate NEON coprocessor, integrated independent 8K video hardware encoder and hardware decoder. RK3588J also introduces a new generation of fully hardware-based ISP (image processor) with a maximum of 84 million pixels, and implements many algorithm accelerators, such as HDR, 3A, LSC, 3DNR, sharpening, dehaze, fisheye correction, gamma correction, etc., which are widely used in graphics post-processing. RK3588J supports up to 8K@60fps decoding and output, supports HDMI2.1 output interface, and also supports HDMI RX, and supports up to 4K@60fps video input. RK3588J integrates Rockchip's self-developed third-generation NPU processor with a maximum computing power of 6TOPS, which can meet the computing power requirements of some artificial intelligence models.

[0041] Furthermore, the parallel computing chip uses Huawei Ascend 310B chip. The reasons are as follows:

[0042] Ascend 310B chip is an AI chip independently developed by Huawei, which integrates a self-developed Da Vinci V300AI core and four domestically-developed TAISHAN V200M processor cores. Compared with the previous generation Ascend 310, its core has realized a nationally-made architecture and supports larger memory and richer interface types. And considering that the Ascend 310 processor only has MXM modules, the module interface method is very difficult for EMC processing, and it is difficult to pass the overload test, so Ascend 310B and RK3588J are directly attached to a PCB, which solves the problem that the parallel computing power of the CPU chip in the mainstream integrated processing device of the existing technology is insufficient, and thus cannot meet the demand of cluster drones for the comprehensive capabilities of the chip.

[0043] Furthermore, the RK3588J chip and the Ascend 310B chip communicate in a master-slave mode based on the PCIe protocol; wherein the RK3588J chip is the master device of the PCIe bus, and the Ascend 310B chip is the slave device of the PCIe bus. Different from the conventional solution, this embodiment adopts the above master-slave mode to improve the coordination efficiency between the RK3588J chip and the Ascend 310B chip. This is equivalent to the two chips using the same operating system and communicating using the bus protocol.

[0044] Furthermore, it also includes: a clock buffer chip, which is connected to the integrated processing chip and the parallel computing chip respectively, and is used to provide a clock signal to the RK3588J chip and the Ascend 310B chip.

[0045] Furthermore, the clock buffer chip is an INS6310A chip, and the INS6310A chip is connected to the RK3588J chip and the Ascend 310B chip respectively through a PCIe bus.

[0046] The INS6310A chip is a versatile, low-jitter, low-power differential clock fanout buffer that provides the following benefits:

[0047] Strong signal processing capability: Any one of the three input clocks can be fanned out to 10 low-jitter differential clock outputs and one LVCMOS single-ended output, which can provide a rich clock signal for multiple components in the system and meet the needs of complex systems for multiple clock signals. Flexible level conversion: The level conversion of input clock and output clock can be flexibly realized. The input clock supports differential signals, single-ended signals and passive crystal inputs. The level of the output clock can be configured according to different application scenarios and chip requirements, which enhances the applicability and flexibility of the chip and facilitates connection with circuits of different level standards. Low jitter performance: The chip has excellent low jitter characteristics and can output stable and accurate clock signals, which is critical for applications with high clock accuracy requirements, helps improve system performance and reliability, and reduces data transmission error rates.

[0048] Furthermore, the peripherals and sensor interfaces include: TTL serial port interface, RS232 interface, RS485 interface, GPIO interface, PWM interface, USB interface, camera interface, Gigabit network interface. It is used to support different types of interfaces and adapt to different peripherals and sensors. Among them, the PWM interface is used to support PWM control.

[0049] Furthermore, the memory chip includes: LPDDR4 memory chip and FLASH memory chip, which are used to achieve larger storage space and faster storage efficiency and reading efficiency.

Claims

1. A terminal-side integrated processing device suitable for cluster drones, characterized in that: include: Peripheral device and sensor interface, the peripheral device and sensor interface is a channel for connecting the terminal-side integrated processing device with external devices and sensors; A memory chip, wherein the memory chip is used for data storage, data caching, and historical data recording; An integrated processing chip, the integrated processing chip is connected to the peripheral device and sensor interface, and the data obtained by the peripheral device and the sensor is transmitted to the integrated processing chip through the peripheral device and the sensor interface; A parallel computing chip is connected to the integrated processing chip.

2. The terminal-side integrated processing device suitable for cluster drones according to claim 1, characterized in that: Also includes: A carrier board, wherein the carrier board is a PCB circuit board, and the peripheral and sensor interface, the storage chip, the integrated processing chip, and the parallel computing chip are installed on the same carrier board.

3. The terminal-side integrated processing device suitable for cluster drones according to claim 1, characterized in that: The integrated processing chip is a general-purpose SoC using ARM architecture.

4. A terminal-side integrated processing device suitable for cluster drones according to any one of claims 1 to 3, characterized in that: The integrated processing chip is Rockchip RK3588J chip.

5. The terminal-side integrated processing device suitable for cluster drones according to claim 4, characterized in that: The parallel computing chip is Huawei Ascend 310B chip.

6. The terminal-side integrated processing device suitable for cluster drones according to claim 5, characterized in that: The RK3588J chip and the Ascend 310B chip communicate in a master-slave mode based on the PCIe protocol; wherein the RK3588J chip is a master device of the PCIe bus, and the Ascend 310B chip is a slave device of the PCIe bus.

7. The terminal-side integrated processing device suitable for cluster drones according to claim 6, characterized in that: Also includes: A clock buffer chip, wherein the clock buffer chip is respectively connected to the integrated processing chip and the parallel computing chip, and the clock buffer chip is used to provide a clock signal to the RK3588J chip and the Ascend 310B chip.

8. The terminal-side integrated processing device suitable for cluster drones according to claim 7, characterized in that: The clock buffer chip is an INS6310A chip, and the INS6310A chip is connected to the RK3588J chip and the Ascend 310B chip respectively through a PCIe bus.

9. The terminal-side integrated processing device suitable for cluster drones according to claim 1, characterized in that: The peripherals and sensor interfaces include: TTL serial port interface, RS232 interface, RS485 interface, GPIO interface, PWM interface, USB interface, camera interface, and Gigabit network interface.

10. The terminal-side integrated processing device applicable to cluster drones according to claim 1, characterized in that: The memory chip includes: LPDDR4 memory chip and FLASH memory chip.

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