Complementary metal oxide semiconductor image sensor

Abstract

A complementary metal oxide semiconductor image sensor includes a unit pixel array including a photodiode array, a color filter array, a microlens array, and a grid isolation structure laterally separating adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid, and a metal grid, the first low-n grid being narrower than the second low-n grid. The color filter array comprises color filter matrixes, and all the color filter matrixes have the same configuration pattern. The size of the color filters in each color filter matrix varies depending on the position of the color filters in the color filter matrix. In the edge portion, a distance between a center of the color filter matrix and a center of the corresponding unit pixel matrix in a plan view varies depending on a position of the unit pixel matrix in the CMOS image sensor.

Description

Technical Field

[0001] The present disclosure relates to complementary metal oxide semiconductor image sensors. Background Art

[0002] As the semiconductor industry has progressed to nanometer technology process nodes in pursuit of higher device density, better performance and lower cost, the challenges of both the design and manufacture of integrated circuits have greatly increased. Today, CMOS image sensors are widely used. However, due to the continuous reduction in pixel size in pursuit of higher resolution, CMOS image sensors may face challenges or risks, such as insufficient quantum efficiency (QE) and inconsistent pixel performance. Therefore, there is a need for technologies to improve the performance of CMOS image sensors. Utility Model Content

[0003] According to aspects of the present disclosure, a CMOS image sensor includes: a photodiode layer including a photodiode array disposed in a semiconductor substrate; a color filter layer including a color filter array disposed above and substantially aligned with the photodiode array; a microlens layer including a microlens array disposed above and aligned with the color filter array; and a first isolation structure disposed in the color filter layer to laterally separate adjacent color filter units of the color filter array, and including a first dielectric grid, a second dielectric grid underlying the first dielectric grid, and a metal grid at least partially surrounded by the second dielectric grid. A first width of the first dielectric grid is less than a second width of the second dielectric grid.

[0004] According to an aspect of the present disclosure, a CMOS image sensor includes a plurality of unit pixels, each of which includes a photodiode surrounded by an isolation structure, a color filter disposed above the photodiode, and a microlens disposed above the color filter. The CMOS image sensor includes a plurality of matrices, each of which includes: an n×n matrix consisting of a plurality of unit pixels, the n×n matrix consisting of a plurality of unit pixels having an n×n matrix consisting of a plurality of color filters, wherein n is an even number; and a 2×2 matrix consisting of a plurality of color filter regions, covering the n×n matrix consisting of a plurality of unit pixels. Each region of the 2×2 matrix consisting of a plurality of color filter regions is composed of a (n / 2)×(n / 2) matrix consisting of a plurality of color filters having the same color. The distance between the centroid of the 2×2 matrix consisting of the plurality of color filter regions and the centroid of the n×n matrix consisting of the plurality of unit pixels varies in a plan view depending on the position of the plurality of matrices in the CMOS image sensor. The size of at least one color filter of the n×n matrix composed of a plurality of unit pixels varies depending on the position of the at least one color filter in the n×n matrix composed of a plurality of unit pixels.

[0005] According to aspects of the present disclosure, a CMOS image sensor includes: a photodiode array; a plurality of color filters, wherein the color filters are substantially aligned with a plurality of corresponding photodiodes of the photodiode array; and a plurality of microlenses respectively overlying the color filters; a metal grid surrounding the color filters; a first dielectric grid overlying the metal grid, the first dielectric grid at least partially wrapping the metal grid; and a second dielectric grid overlying the first dielectric grid, wherein a width of the second dielectric grid is smaller than a width of the first dielectric grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A cross-sectional view illustrating a CMOS image sensor (CIS) including a pixel image sensor according to an embodiment; Figure 1B A plan (layout) diagram illustrating a pixel defined by a first isolation structure according to an embodiment;

[0008] Figure 2A , Figure 2B , Figure 2C and Figure 2D A cross-sectional view illustrating a first isolation structure of a CMOS image sensor according to an embodiment;

[0009] Figure 2E A top plan view illustrating a first isolation structure of a CMOS image sensor according to an embodiment;

[0010] Figure 3 A top plan view illustrating a color filter array of a pixel sensor of a CMOS image sensor according to an embodiment;

[0011] Figure 4A , Figure 4B and Figure 4C A top plan view illustrating various color filter matrices of a color filter array according to an embodiment;

[0012] Figure 5A , Figure 5B and Figure 5C A cross-sectional view illustrating “global shift” of a color filter matrix of a CMOS image sensor according to an embodiment;

[0013] Figure 5D , Figure 5E and Fig. 5FA coordinate curve diagram for illustrating different ways of changing the global offset according to an embodiment;

[0014] Figure 6 A top plan view illustrating a first photomask of a first isolation structure and a second photomask of a second isolation structure relative to an upper surface of a CMOS image sensor;

[0015] Figure 7 A cross-sectional view illustrating “internal offset” of a color filter within a color filter matrix of a CMOS image sensor according to an embodiment;

[0016] Fig. 8A , Figure 8B and Figure 8C A top plan view illustrating the size or pitch variation (or gradation) of color filters within a color filter matrix due to “internal offset” according to an embodiment;

[0017] Fig. 9 indicating that the wall pattern of the first isolation structure is not offset relative to the wall pattern of the second isolation structure;

[0018] Fig.10 illustrating various offsets of a wall pattern of a first isolation structure relative to a wall pattern of a second isolation structure;

[0019] Fig.11A To illustrate the manufacturing method according to the embodiment Figure 1A Flow chart of the process of the CMOS image sensor shown in ;

[0020] Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F , Fig.11G , Fig.11H , Fig.11I , Fig.11J , Figure 11K , Fig.11L and Fig.11M To illustrate the Fig.11A Cross-sectional diagram of the manufacturing process.

[0021]

Explanation of symbols

[0022] 20: Photodiode array

[0023] 20': Photodiode

[0024] 22: Matrix

[0025] 40: Color filter array

[0026] 40': Color filter unit

[0027] 41: Opening

[0028] 42: Matrix

[0029] 42A: Matrix

[0030] 42B: Matrix

[0031] 44, 44G, 44R, 44B, 44G: Color filter unit

[0032] 45: Central Area

[0033] 45C: Center, center point

[0034] 47: Marginal Area

[0035] 47E: Edge

[0036] 51: First low-n dielectric grid

[0037] 51A: Materials

[0038] 52: Second Low-n Dielectric Grid

[0039] 52':Grid segment

[0040] 53:Metal grid

[0041] 54: Etching stop film

[0042] 60: Microlens array

[0043] 60': Microlens

[0044] 70: Transfer transistor array

[0045] 70': Transfer transistor

[0046] 100:CMOS image sensor

[0047] 105: Pixels

[0048] 110:Substrate

[0049] 115: Matrix

[0050] 120: Photodiode layer

[0051] 123: Dielectric layer

[0052] 140: Color filter layer

[0053] 150: first isolation structure, first isolation grid

[0054] 151: First mask

[0055] 157, 167: Wall pattern

[0056] 160': Microlens layer

[0057] 160: second isolation grid, second isolation structure

[0058] 161: Second light mask

[0059] 170: The third isolation structure

[0060] 180: Separation layer

[0061] 190:Ion implantation grid

[0062] 1100: Craftsmanship

[0063] 1110, 1120, 1130, 1140, 1150, 1160: Steps

[0064] C1-C1, C2-C2: vertical center line

[0065] C1, C2: Center

[0066] H1: First Height

[0067] H2: Second Height

[0068] H3: The third height

[0069] L 40 :length

[0070] L 45 :Side length

[0071] P1, P2, P3, P4: Spacing

[0072] S, S0: distance

[0073] S1: Global offset

[0074] S2: Global offset

[0075] Sv: global offset

[0076] W1: Width

[0077] W2: Width

[0078] W3: Width

[0079] W 40 :width

[0080] X1-X1: Line

[0081] x: row direction

[0082] y:column direction DETAILED DESCRIPTION

[0083] It should be understood that the following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, the size of the component is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired properties of the device. In addition, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed to be inserted between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features may be arbitrarily drawn in different proportions. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0084] In addition, for ease of description, spatially relative terms (such as "below", "below", "bottom", "above", "upper" and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "including" or "consisting of". In addition, in the following manufacturing process, there may be one or more additional operations in / between the operations, and the order of the operations may be changed. In the following embodiments, the terms "upper", "above" and / or "above" are defined along the direction of increasing distance from the front surface and the rear surface. The materials, configurations, dimensions, processes and / or operations explained with respect to one embodiment may be adopted in other embodiments, and a detailed description thereof may be omitted.

[0085] With the development of integrated circuit (IC) and semiconductor industry, the size or pitch of pixel image sensors of CMOS image sensor (CIS) has been greatly reduced to improve image resolution and reduce cost. However, as the size of CIS pixel image sensors continues to decrease to a level close to or within the visible light wavelength range, there is a problem or risk of reduced quantum efficiency (QE) and poor performance uniformity on the pixel image sensors, especially at the edge of the CMOS image sensor.

[0086] The present disclosure generally relates to a CMOS image sensor including a photodiode array formed in a semiconductor substrate, a color filter array above the photodiode array, a microlens array above the color filter array, and a composite grid isolation structure that laterally separates adjacent color filters in the color filter array. The CMOS image sensor may include an entire color filter array including a plurality of color filter matrices, all color filter matrices having the same configuration pattern, and each color filter matrix including 2×2 color filter units of three different colors. Each color filter unit includes a predetermined number (e.g., 1, 2×2, 3×3, 4×4) of color filter units of the same color.

[0087] More specifically, a composite grid isolation structure is provided to laterally separate adjacent color filters of a color filter array in a color filter layer of a CMOS image sensor. The composite grid isolation structure includes a first low-refractive index (low-n) grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid.

[0088] Furthermore, the size of the color filters in each color filter matrix may vary depending on the position of the color filters in the color filter matrix.The offset of the color filters within the color filter matrix may be referred to hereinafter as "internal offset".

[0089] Furthermore, in the edge portion outside the central region of the color filter array, the color filter matrix may be offset relative to the corresponding underlying photodiode by a certain offset amount depending on the position of the color filter matrix in the entire color filter array. For example, in the edge region, the color filter matrix may be offset by a gradually increasing offset amount in a direction from the center of the central region to the edge of the edge region. The offset of the color filter matrix in the entire color filter array of the CMOS image sensor is hereinafter referred to as "global offset".

[0090] Advantageously, due to the composite grid isolation structure and the configuration and adjustment (e.g., by global or internal offset) of the color filter matrix and the color filter cells within the color filter matrix, the quantum efficiency (QE) and performance uniformity of the pixel image sensor in the CMOS image sensor are improved.

[0091] Figure 1A A cross-sectional view of a CMOS image sensor 100 including a pixel image sensor is shown. Figure 1BFIG. 1 shows a portion of pixels of a CMOS image sensor 100 according to an embodiment. In some embodiments, the CMOS image sensor 100 includes: a photodiode layer 120 including a photodiode array 20 disposed in a semiconductor substrate 110; a color filter layer 140 including a color filter array 40 disposed above and substantially aligned with the photodiode array 20 (more details are shown in FIG. 1 ). Figure 3 and a microlens layer 160 ', comprising a microlens array 60 disposed above the color filter array 40 and aligned therewith.

[0092] CMOS image sensor 100 also includes: a first isolation structure 150 (more details of which are given in FIG. 2A to FIG. 2E ), a color filter unit (or color filter) 40′ and a second isolation structure 160 are arranged in the color filter layer 140 to laterally separate adjacent color filter arrays 40, and are arranged in the semiconductor substrate 110 to laterally separate adjacent photodiodes 20′ of the photodiode array 20 in the photodiode layer 120.

[0093] like Figure 1B As shown, each pixel is defined by an array of grid segments 52' of the first isolation structure and the second isolation structure. The array of grid segments 52' also defines a space or room for the color filter 40'. In some embodiments, the shape of the grid segments 52' (pixel shape) of the CMOS image sensor 100 is square, and in other embodiments is rectangular. Therefore, the plurality of grid segments of the first isolation structure and / or the second isolation structure as "walls" define a space for the color filter 40' in the color filter layer 140.

[0094] In some embodiments, the grid includes a metal grid 53 of the first isolation structure 150, and the metal grid 53 defines the space or size and position of the color filter 40' of the color filter array 40 in the color filter layer 140, such as Figure 1A shown.

[0095] The substrate 110 may include a single crystalline semiconductor material such as, but not limited to, Si.

[0096] In some embodiments, CMOS image sensor 100 includes a separation layer 180 that vertically separates microlens layer 160 ′ and color filter layer 140 .

[0097] In some embodiments, the second isolation structure 160 includes a deep trench isolation (DTI) grid extending vertically from the upper surface of the photodiode layer 120 into the substrate 110. In some embodiments, the DTI grid 160 is substantially aligned with the first isolation structure 150.

[0098] In some embodiments, CMOS image sensor 100 includes a transfer transistor array 70 of transfer transistors 70' disposed in semiconductor substrate 110. CMOS image sensor 100 includes a third isolation structure 170 that laterally separates adjacent transfer transistors 70' of transfer transistor array 70. Each transfer transistor 70' includes a gate structure, a source / drain region, and a gate dielectric. In the present disclosure, source and drain are used interchangeably. In some embodiments, third isolation structure 170 includes a shallow trench isolation (STI) grid aligned with DTI grid 160. In some embodiments, CMOS image sensor 100 also includes an ion implantation grid 190 disposed between DTI grid 160 and STI grid 170 in semiconductor substrate 110 to laterally separate adjacent photodiodes 20' of photodiode array 20. In some embodiments, ion implantation grid 190 is substantially aligned with DTI grid 160 and STI grid 170.

[0099] refer to Figure 1A and Figure 1B , the CMOS image sensor 100 includes a plurality of unit pixels 105. Each unit pixel 105 of the plurality of unit pixels includes a photodiode 20' surrounded by a section of a second isolation structure (such as a DTI) 160, a color filter 40' of a color (such as red, blue or green) disposed above the photodiode 20', and a microlens 60' disposed above the color filter 40'. Therefore, the photodiode 20', the color filter 40' and the microlens 60' of the unit pixel 105 form an optical channel. The incident light on the top surface of the unit pixel 105 is focused onto the effective area of ​​the color filter 40' through the microlens 60', filtered by the color filter 40' into a monochromatic light beam, and received by the photodiode 20'. The photodiode 20' converts the intensity of the received incident light into an electrical signal. The transfer transistor 70' corresponding to the photodiode 20' in the unit pixel 105 facilitates the readout of the electrical signal.

[0100] As the size of the unit pixel 105 continues to decrease to a range close to or within the visible light wavelength range in pursuit of higher resolution, there may be problems or risks of reduced quantum efficiency of the unit pixel 105 and non-uniform pixel performance, especially in the edge regions (e.g., right, left, top, and bottom regions) of the CMOS image sensor 100.

[0101] In the present disclosure, a novel isolation structure for a color filter is disclosed.

[0102] FIG. 2A to FIG. 2DA cross-sectional view illustrating first isolation structure 150 of a CMOS image sensor according to an embodiment. Figure 2E A top plan view of first isolation structure 150 of CMOS image sensor 100 is illustrated according to an embodiment. FIG. 2A to FIG. 2D To correspond to Figure 2E A cross-sectional view of line X1-X1. Figure 2E Shown corresponding to Figure 1B Portions of the intersections of the grid shown.

[0103] According to the embodiment, Figure 2A and Figure 2B As shown, the first isolation structure 150 includes a first low-refractive-index (low-n) dielectric grid 51, a second low-n dielectric grid 52 underlying the first low-n dielectric grid 51, and a metal grid 53 at least partially surrounded by the second low-n dielectric grid 52. In some embodiments, the first isolation structure 150 includes an etch stop film 54, which at least partially wraps the metal grid 53 in the second low-n dielectric grid 52 and thus separates the metal grid 53 from the second low-n dielectric grid 52. The etch stop film 54 is made of a dielectric material, such as aluminum oxide (e.g., Al 2 O 3 ), silicon nitride, hafnium oxide, zirconium oxide or any other suitable material.

[0104] In some embodiments, the materials of the second low-n dielectric grid 52 and the first low-n dielectric grid 51 are different from each other, such as Figure 2A and Figure 2B In other embodiments, the second low-n dielectric grid 52 and the first low-n dielectric grid 51 are made of the same material 51A, such as Figure 2C and Figure 2D shown.

[0105] In some embodiments, the upper corners of the second low-n dielectric grid 52 are substantially right angles, such as Figure 2A and Figure 2D In other embodiments, the upper corners of the second low-n dielectric grid 52 are rounded, such as Figure 2B and Figure 2C In some embodiments, the radius of the corner is about 1 nm to about 10 nm.

[0106] In some embodiments, the first low-n dielectric grid 51 is made of a dielectric material (such as silicon oxide, e.g., SiO 2 ) or ceramic material, and the second low-n dielectric grid 52 is made of a dielectric material (such as silicon oxide, for example SiO 2) or a ceramic material. In some embodiments, the metal grid 53 is made of a metal material (such as W, Al, Cu, or Cr) or a metal alloy material (such as TiN). In some embodiments, the color filters 40' of the color filter array 40 are made of an organic or inorganic dielectric material.

[0107] In some embodiments, the refractive index n1 of the first low-n dielectric grid 51 is in the range of a value greater than 1 (e.g., 1.01) to about 1.50, that is, 1 < n1 < 1.50. In some embodiments, the refractive index n2 of the second low-n dielectric grid 52 is in the range of a value greater than 1 (e.g., 1.01) to about 1.50, that is, 1 < n2 < 1.50. In some embodiments, the refractive index n1 of the first low-n dielectric grid 51 is equal to or greater than the refractive index n2 of the second low-n dielectric grid 52, that is, n1 = n2, or n1 > n2.

[0108] In some embodiments, the refractive index n1 of the first low-n dielectric grid 51 and the refractive index n2 of the second low-n dielectric grid 52 of the first isolation structure 150 are both less than the refractive index n of the color filters 40' of the color filter array 40, that is, n1 < n and n2 < n. In this way, total internal reflection in the color filters of the pixel image sensor array can be enhanced, and thus the quantum efficiency (QE) of the pixel image sensor array can be improved.

[0109] In some embodiments, the first width W1 of the first low-n dielectric grid 51 is in the range of about 50 nm to about 200 nm, and the first height H1 of the first low-n dielectric grid 51 is in the range of about 100 nm to about 1000 nm. In some embodiments, the second width W2 of the second low-n dielectric grid 52 is in the range of about 90 nm to about 300 nm, and the second height H2 of the second low-n dielectric grid 52 is in the range of about 100 nm to about 1000 nm. In some embodiments, the third width W3 of the metal grid 53 is in the range of about 20 nm to about 80 nm, and the third height H3 of the metal grid 53 is in the range of about 30 nm to about 500 nm.

[0110] In some embodiments, the first width W1 of the first low-n dielectric grid 51 is less than the second width W2 of the second low-n dielectric grid 52. In some embodiments, the ratio of W1 to W2 (W1 / W2) is in a range of about 0.2 to about 0.8 in some embodiments. In some embodiments, the first height H1 of the first low-n dielectric grid 51 is greater than the second height H2 of the second low-n dielectric grid 52. In some embodiments, the ratio of the first height H1 to the second height H2 (first height H1 / second height H2) is in a range of about 1.2 to about 10 in some embodiments. In this way, the space or room of each color filter 40' of the color filter array 40 of the CMOS image sensor 100 can be expanded, and thus the quantum efficiency (QE) of each unit pixel of the pixel image sensor array can be improved.

[0111] Figure 3 A top plan view of a color filter array 40 of a pixel sensor of a CMOS image sensor 100 according to an embodiment is shown. The color filter array 40 includes a central region 45 and an edge region (such as a right edge region 47) beyond the central region 45. For example, the color filter array 40 may be a plurality of pixels having a length L. 40 , Width W 40 (L 40 >W 40 ) and a rectangle centered at the center point 45C, and the center area 45 can be a rectangle with a side length L 45 The center point 45C is a square. In some embodiments, the side length L of the center area 45C is 45 The width W of the color filter array 40 40 The ratio is limited to a range of about 0.3 to about 0.8. Any region, such as Figure 3 The right region 47 shown beyond the central region 45 is defined as an edge region.

[0112] In some embodiments, the color filter array 40 includes a plurality of color filter units (or color filters) 40'. Color filter units and color filters are used interchangeably hereinafter. The plurality of color filters 40' are formed and horizontally arranged into a plurality of color filter matrices 42. Each color filter matrix 42 of the color filter array 40 has the same horizontal arrangement pattern on a plane. In some embodiments, each of the color filter matrices 42 includes an n×n square color filter matrix defined by a first isolation structure 150, where n=even number (e.g., n=4). There is an n×n square photodiode matrix under the color filter matrix 42. In some embodiments, the color filter matrix is ​​defined by the first isolation structure 150, and its boundaries are shared by adjacent matrices. In some embodiments, the color filter matrix corresponds to a photodiode matrix defined by a second isolation structure 160, and its boundaries are shared by adjacent matrices.

[0113] FIG. 4A to FIG. 4C FIG. 4 is a top plan view of some color filter matrices 42 of the color filter array 40 according to an embodiment. In some embodiments, each color filter matrix 42 includes 2×2 (four) color filter units 44 (see also FIG. 4 ). Figure 3 ), and each color filter unit 44 includes (n / 2)×(n / 2) color filters 40' of the same color. In some embodiments, the color of the color filter unit 44 is selected from red, blue, and green.

[0114] exist Figure 4A , n=2, each color filter matrix 42 includes 2×2 color filter units 44 (such as color filter units 44G, 44R, 44B, and 44G), and each color filter unit 44 includes one (i.e., 2 / 2×2 / 2) color filter 40' of the same color selected from red, blue, and green. For example, the green color filter unit 44R includes a single green color filter 40'.

[0115] exist Figure 4B , n=4, each color filter matrix 42 includes 2×2 color filter units 44 (such as color filter units 44G, 44R, 44B and 44G), and each color filter unit 44 includes 4 (i.e., 4 / 2×4 / 2) color filters 40' of the same color selected from red, blue and green. For example, the red color filter unit 44R includes 4 red color filters 40'.

[0116] exist Figure 4C, n=8, each color filter matrix 42 includes 2×2 color filter units 44 (such as color filter units 44G, 44R, 44B, and 44G), and each color filter unit 44 includes 16 (4×4) (i.e., 8 / 2×8 / 2) color filters 40' of the same color selected from red, blue, and green. For example, the red color filter unit 44R includes 16 red color filters 40'. When n is larger, the image dynamic range increases, and when n is smaller, the image resolution increases.

[0117] As described above, the CMOS image sensor 100 includes a plurality of unit pixels 105, each unit pixel 105 includes a photodiode 20' surrounded by a second isolation structure 160, a color filter 40' disposed above the photodiode 20', and a microlens 60' disposed above the color filter 40'. Figure 1A shown.

[0118] CMOS image sensor 100 includes a plurality of matrices 115 of unit pixels 105, each matrix 115 including an n×n matrix of unit pixels 105, where n is an even number. The n×n matrix 115 of unit pixels 105 includes an n×n matrix 42 of color filters 40' and an n×n matrix 22 of photodiodes 20' underlying the n×n matrix 42 of color filters 40'.

[0119] Also refer to FIG. 4A to FIG. 4C , the 2×2 matrix of color filter regions 44 covers the n×n matrix 115 of unit pixels 105. Each region 44 of the 2×2 matrix of color filter regions 44 is composed of (n / 2)×(n / 2) color filter matrices having the same color. Figure 4C For example, each region 44 (eg, region 44R, 44B, or 44G) of a 2×2 matrix of color filter regions 44 is composed of a 4×4 matrix of color filters 40 ′ having the same color (eg, red, blue, or green).

[0120] FIG. 5A to FIG. 5C To illustrate the color filter matrix 42 (eg, Figure 3 Cross-sectional views of the "global offset" of the matrix 42A, 42B and 42C) shown, where n=4. FIG. 5A to FIG. 5C The illustration shows a cross-sectional view of two green pixels (green color filter element 44G) and two red pixels (red color filter element 44R).

[0121] “Global offset” means that the color filter matrix 42 (e.g. FIG. 4A to FIG. 4C) are horizontally offset (or horizontally deviated) in a particular horizontal direction relative to the entire photodiode matrix, wherein the photodiode matrix includes corresponding photodiodes 20' underlying a plurality of color filters 40'.

[0122] In some embodiments, reference is also made to Figure 3 , the color filter matrix 42 does not perform any global offset in the central region 45 of the entire color filter array 40. However, the color filter matrix 42 performs a global offset in any edge region 47 of the color filter array 40. In some embodiments, in the edge region 47 (e.g., the right region) beyond the central region 45 of the entire color filter array 40, the color filter matrix 42 performs a global offset with a gradually increasing offset in a first horizontal direction from the center 45C of the central region 45 to the edge 47E of the edge region 47.

[0123] like FIG. 5A to FIG. 5C As shown, each segment of the metal grid 53 of the first isolation structure 150 defines the space and position of the color filter 40 ′ of the color filter matrix 42 , and thus defines the horizontal global offset of the color filter matrix 42 in the entire color filter array 40 in the color filter layer 140 .

[0124] exist FIG. 5A to FIG. 5C , the vertical center line C1-C1 represents the center (or center of gravity) of the n×n matrix 115 of the photodiodes 20'. The vertical center line C2-C2 represents the center (or center of gravity) of the n×n matrix 42 (color filter matrix) of the color filter 40'. The vertical center line C2-C2 corresponds to Figure 4B The nxn matrix 42 of color filter 40' is shown as the center (centre of mass) of a 2x2 matrix of color filter elements 44.

[0125] refer to Figure 5A and Figure 3 In the central region 45 of the color filter array 40 of the CMOS image sensor 100, the color filter matrix 42 has no global offset relative to the unit pixel matrix 115. The distance S0 between the vertical center line C1-C1 and the vertical center line C2-C2 is zero (S0=0).

[0126] refer to Figure 5B and Figure 3 In the edge region 47 (such as the right edge region) of the color filter array 40 of the CMOS image sensor 100, the color filter matrix 42 located in the right edge region 47 is as shown in FIG. Figure 3In the plan view shown, the photodiode grid underlying the color filter matrix 42 is offset to the right (e.g., +X) in the horizontal X direction by a first global offset S1. The first distance S1 between the center line C1-C1 and the center line C2-C2 is greater than zero (S1>0). Similarly, in some embodiments, the color filter matrix 42 located in the left edge area 47 is offset to the right (e.g., +X) by a first global offset S1. Figure 3 In the plan view shown in FIG. 1 , the first global offset is performed to the left (e.g., −X) in the horizontal X direction relative to the photodiode grid by a first global offset S1. In some embodiments, the color filter matrix 42 located in the upper edge region or the lower edge region and further away from the central region 45 is as shown in FIG. Figure 3 The global offset is shown in the plan view upward (e.g., +Y) or downward (e.g., -Y) in the vertical Y direction relative to the photodiode grid by a global offset. The global offset Sv in the vertical Y direction is the same as or different from the global offset S1 in the horizontal X direction in the plan view. In some embodiments, when the size of the CMOS image sensor 100 is a:b (e.g., 4:3 or 16:9), where a is the horizontal (X) dimension and b is the vertical (Y) dimension, the global offset S1:global offset Sv is equal to a:b at the edge of the image sensor.

[0127] refer to Figure 5C and Figure 3 In the edge region 47 (such as the right edge region) of the color filter array 40 of the CMOS image sensor 100, the color filter matrix 42 located in the right edge region 47 and further away from the central region 45 is as shown in FIG. Figure 3 In the plan view shown in FIG. 1 , the second global offset is performed rightward (e.g., +X) in the horizontal X direction (rightward) relative to the photodiode grid by a second global offset S2. The second distance S2 between the center line C1-C1 and the center line C2-C2 is greater than the global offset S1 (the second distance S2>global offset S1). In some embodiments, similarly, the color filter matrix 42 located in the left edge area 47 and further away from the center area 45 is as shown in FIG. Figure 3 In the plan view shown, a second global offset is performed to the left (eg, −X) in the horizontal X direction (to the left) relative to the photodiode grid by a second global offset amount S2.

[0128] Here are the references Figure 3An example of a global offset produced by color filter matrix 42 in a first direction from center region 45 of an edge region of CMOS image sensor 100 to edge 47E of the edge region (e.g., right region). In center region 45, color filter matrix 42 has no global offset relative to underlying unit pixel matrix 115. Outside center region 45, in the first direction from center region 45 to edge 47E, with respect to a first color filter matrix 42, an initial or starting global offset to first color filter matrix 42 is 0.01 nm; with respect to a second color filter matrix 42 subsequent to the initial color filter matrix 42, the global offset is increased by an increased offset of 0.01 nm, and thus the global offset of the second color filter matrix 42 is 2×0.01 nm (0.01 nm+0.01 nm); with respect to second color filter matrix 4 2, the global offset is further increased by an increased offset of 0.01 nm, and thus the global offset of the third color filter matrix 42 is 3×0.01 nm (0.01 nm+0.01 nm+0.01 nm); ... For the N-th color filter matrix 42 after the N-1-th color filter matrix 42, the global offset is further increased by an increased offset of 0.01 nm, and thus the global offset of the N-th color filter matrix 42 is N×0.01 nm. The CMOS image sensor 100 may include, for example, 200,000,000 pixels in total. In this example, the increased global offset of each color filter matrix is ​​0.01 nm, but is not limited to 0.01 nm. In some embodiments, depending on design and / or process requirements, the increased global offset of each color filter matrix is ​​in a range from about 0.008 nm to about 0.5 nm, about 0.01 nm to about 0.1 nm, or 0.02 nm to about 0.05 nm.

[0129] In some embodiments, in edge region 47 of color filter array 40 of CMOS image sensor 100, a distance (S, such as S1 or S2) between the centroid (C2-C2) of the 2×2 matrix of color filter regions 44 and the centroid (C1-C1) of the n×n matrix 115 of unit pixels 105 in a plan view varies depending on the position of matrix 115 in CMOS image sensor 100. Edge 47E of edge region 47 may be any edge (such as the right edge, the left edge, the top edge, or the bottom edge) in CMOS image sensor 100.

[0130] In some embodiments, reference Figure 3 as well as Figure 5B and Figure 5C, in edge region 47, a distance (S) between the centroid (C2-C2) of the 2×2 matrix of color filter region 44 and the centroid (C1-C1) of the n×n matrix 115 of unit pixel 105 gradually increases in a first direction from center 45C of central region 45 in CMOS image sensor 100 to edge 47E of edge region 47 in a plan view. In other words, in edge region 47, a global offset of n×n matrix 42 of color filter 40′ relative to n×n matrix 115 of unit pixel 105 gradually increases in a first direction from center 45C of central region 45 to edge 47E of edge region 47 in a plan view.

[0131] Figure 5D , Figure 5E and Fig. 5F 1 is a coordinate curve diagram illustrating different ways of changing the global offset according to embodiments. In some embodiments, the offset S is in the plane view as shown in FIG. Figure 3 As shown, the direction (X or Y) from the center 45C to the edge 47E increases linearly. Figure 5E As shown, the offset S is Figure 3 As shown, the center 45C increases nonlinearly (such as slowly and gradually) to the edge 47E in the edge. In some embodiments, as shown in FIG. Fig. 5F As shown, the offset S is stepped as Figure 3 As shown, the color filter increases from the center 45C to the edge 47E, so that the global offset S increases by a fixed offset (e.g., 1 nm) in each step from a group of color filter matrices 42 with a fixed number (e.g., 5) to the next group of color filter matrices 42 with a fixed number (e.g., 5) in the direction from the center 45C to the edge 47E. FIG. 5D to FIG. 5F Any combination of is possible. In the plan view, the direction of the global offset is along the horizontal direction and / or the vertical direction of the image sensor.

[0132] In some embodiments, the maximum offset at the edge of the color filter array is in a range from about 50 nm to about 300 nm.

[0133] In some embodiments, the size of the n×n matrix 42 of the color filter 40′ of the matrix 115 of the unit pixel 105 in the plan view in the color filter layer 140 varies depending on the position of the matrix 115 in the CMOS image sensor 100. In some embodiments, the size of the n×n matrix 42 of the color filter 40′ of the matrix 115 of the unit pixel 105 in the plan view gradually decreases in a first direction from the center 45C of the central region 45 to the edge 47E of the edge region 47. In other embodiments, the size of the n×n matrix 42 of the color filter 40′ of the matrix 115 of the unit pixel 105 in the plan view gradually increases in a first direction from the center 45C of the central region 45 to the edge 47E of the edge region 47.

[0134] Advantageously, in the color filter layer 140 (eg Figure 3 In the plan view shown in FIG. 1 , the matrix 115 of the color filter 40 ′ of the unit pixel 105 in the edge portion 47 beyond the center portion is globally offset (eg, as shown in FIG. 1 ). Figure 5B and Figure 5C ) increases the number of photodiodes 20' (as shown) reaching the matrix underlying the color filter 40'. Figure 1A The global offset can reduce the amount of incident light (as shown) in the edge region, thereby compensating for the reduction in incident light reaching the photodiodes 20' underlying the matrix of color filters 40' in the edge region due to the narrow channel width of the pixel 105 and the increased incident light angle in the edge portion. Therefore, the global offset can reduce the performance non-uniformity of the pixel imaging array of the CMOS image sensor.

[0135] In some embodiments, Figure 1A The first isolation structure 150 and the second isolation structure 160 are shown to be fabricated using one or more photolithography and etching operations using a first mask 151 for the first isolation structure 150 and a second mask 161 for the second isolation structure 160 . Figure 6 A top plan view illustrating a portion of first mask 151 of first isolation structure 150 and a portion of second mask 161 of second isolation structure 160 relative to a top surface of CMOS image sensor 100 according to an embodiment. Figure 1A and FIG. 2A to FIG. 2E The first isolation structure 150 shown may include a metal grid 53. Figure 1A The second isolation structure 160 shown may include a DTI structure. Each of the first mask and the second mask includes a layout pattern corresponding to a plurality of color filters and a photodiode matrix. Figure 6As shown, in the center portion of the top surface of the CMOS image sensor 100, the matrix pattern of the first mask 151 of the first isolation structure (and the metal grid) and the matrix pattern of the second mask 161 for DTI are aligned with each other without offset. In the edge portion away from the center portion, the matrix pattern of the first mask 151 deviates more and more from the matrix pattern of the second mask 161, in other words, the matrix pattern of the first mask 151 is more offset relative to the matrix pattern of the second mask 161. In this way, the global offset of the color filter matrix can be performed.

[0136] Figure 7 A cross-sectional view illustrating the “internal offset” of color filter 40 ′ within 4×4 color filter matrix 42 according to an embodiment, such as CMOS image sensor 100 FIG. 4A to FIG. 4C The first isolation structure 150 includes a metal grid 53, and the metal grid 53 is defined as follows. Figure 7 The sizes or pitches (such as sizes or pitches P1, P2, P3, and P4) of color filters 40' within the illustrated 4x4 color filter matrix 42. According to an embodiment, the sizes or pitches of color filters 40' in an nxn (e.g., n=4) color filter matrix 42 vary depending on the position of color filters 40' within and relative to the nxn color filter matrix 42 (more details will be explained below).

[0137] Fig. 8A , Figure 8B and Figure 8C A top plan view illustrating how the size or pitch of color filters within an n×n (e.g., 4×4) color filter matrix 42 changes due to internal offset according to an embodiment. Each n×n color filter matrix 42 includes a 2×2 matrix of color filter regions 44 (or color filter units 44) of three different colors (such as red, blue, and green). For example, each n×n color filter matrix 42 includes one red color filter region, one blue color filter region, and two green color filter regions. The color filter matrix 42 extends horizontally in a plane in a row direction x and a column direction y. As shown in FIG. Figure 7 As shown, the boundaries of the color filter 40 ′ are defined by a first isolation structure 150 , such as a metal grid 53 .

[0138] In some embodiments, the size and / or pitch of color filters 40' within each n×n color filter matrix 42 follows the same rule or pattern and varies or changes depending on the position of color filters 40' within the n×n color filter matrix 42 of CMOS image sensor 100 (see Fig. 8A , Figure 8B and Figure 8C). In some embodiments, due to internal offset, in each series of color filters 40' of the n×n color filter matrix 42 (such as in each row or column), the size or pitch of the red or blue color filter 40' is larger than the size of the green color filter 40'. In some embodiments, due to internal offset, in a first direction in a plane view from the center to the edge of the CMOS image sensor, the size or pitch of the color filter (e.g., color filter unit R2) following another color filter unit (e.g., color filter unit R1) of the same color is larger than the size of another color filter (e.g., color filter unit R1) in each series of color filters 40' of the n×n color filter matrix (such as in each row or column). The first direction may be any direction in a plane, such as a rightward, leftward, upward, or downward direction.

[0139] In short, in each column or row of the n×n color filter matrix, since the first color filter and the second color filter after the first color filter have the same color, the second color filter is larger than the first color filter. In each column or row of the n×n color filter matrix, the red color filter is larger than the green color filter, and the blue color filter is larger than the green color filter.

[0140] like Fig. 8A As shown, for example, in the direction from left to right, in the first row of the color filter matrix 42, G1 <G2,R1<R2,(R> G); in the second row of the color filter matrix 42, G3 <G4,R3<R4,(R> G); In the third row of the color filter matrix 42, B1 <B2,G5<G6,(B> G); and in the fourth row of the color filter matrix 42, B3 <B4,G7<G8,(B> G). Here, for example, G1 and G2 represent the sizes of the first green color filter and the second green color filter, respectively, and R1 and R2 represent the sizes of the first red color filter and the second red color filter in the first column of the color filter matrix 42, respectively. Fig. 8A As shown, in the direction from left to right, in each row of the color filters 40' in each color filter matrix 42, the color filters 40' are arranged in order from large to small, for example: R2>R1>G2>G1; R4>R3>G4>G3; B2>B1>G6>G5; and B4>B3>G8>G7.

[0141] Similarly, if Fig. 8AAs shown, for example, in the top-to-bottom direction, in the first column of the color filter matrix 42, G1 <G3,B1<B3,(B> G); in the second column of the color filter matrix 42, G2 <G4,B2<B4,(B> G); In the third column of the color filter matrix 42, R1 <R3,G5<G7,(B> G); and in the fourth column of the color filter matrix 42, R2 <R4,G6<G8,(R> G). Here, for example, G1 and G3 represent the sizes of the first green color filter and the second green color filter, respectively, and B1 and B3 represent the sizes of the first blue color filter and the second blue color filter in the first column of the color filter matrix 42, respectively. Fig. 8A As shown, in the top-to-bottom direction, in each column of the color filters 40' in each color filter matrix 42, the color filters 40' are arranged in order from large to small, for example: B3>B1>G3>G1; B4>B2>G4>G2; R3>R1>G7>G5; and R4>R2>G8>G6.

[0142] In some embodiments, the configuration of the internal offsets in the color filter matrix is ​​common to all color filters in the color filter matrix. In other embodiments, the configuration of the internal offsets in the color filter matrix varies depending on the position of the color filter matrix within the color filter matrix. That is, in addition to the common internal offsets described above, each color filter in the color filter matrix has an additional internal offset depending on the position of the color filter matrix in the entire color filter array. See, for example, Figure 3 , at the edge region 47, the second color filter matrix 42B is behind or follows the first color filter matrix 42A in the first direction from the center region 45 to the right edge region 47. In addition to the common internal offset described above, each color filter (e.g., G1) in the second color filter matrix 42B is additionally internally offset compared to the corresponding color filter (e.g., G1) in the first color filter matrix 42A. The additional internal offset may result in additional size changes (enlargement or reduction) of each color filter within each color filter matrix, which may result in size changes (i.e., global offset) of the color filter matrix as described above.

[0143] In some embodiments, reference Figure 8B , the configuration of the internal offset in the color filter matrix is ​​common to the color filter matrix located on one side (e.g., the left side) relative to the vertical center line of the color filter, and the configuration of the internal offset in the color filter matrix in the color filter matrix located on the other side (e.g., the right side) has a mirror image configuration or the same configuration as the left side configuration. In some embodiments, referring to Figure 8C, the configuration of the internal offset in the color filter matrix is ​​common to the color filter matrix located on the upper side relative to the horizontal center line of the color filter, and the configuration of the internal offset in the color filter matrix in the color filter matrix located on the lower side has a mirror configuration or the same configuration as the upper side configuration.

[0144] Fig. 9 and Fig.10 A first mask 151 for making a wall pattern 157 of a first isolation grid (such as a metal grid 53) 150 and a second mask 161 for making a wall pattern 167 of a second isolation grid 160 (such as a DTI) are shown. In some embodiments, the internal offset of the color filters 40' in the color filter matrix 42 is generated by adjusting or offsetting the wall pattern 157 of the metal grid 53 relative to the wall pattern 167 of the DTI so that the size or spacing of the color filters 40' on both sides of the wall pattern 157 in the color filter matrix 42 changes. Fig. 9 This indicates that the wall pattern formed by the first mask 151 is not offset from the wall pattern formed by the second mask 161 . Fig.10 Various offsets of the wall pattern 157 of the metal grid 53 of the first isolation grid 150 relative to the wall pattern 167 of the DTI grid of the second isolation grid 160 are described, resulting in internal offsets and / or global offsets. For example, various wall pattern offsets may result in various internal offsets or deviations of the color filter 40' relative to the photodiode 20' of the unit pixel 105. Various mask offsets may also result in global offsets of the color filter matrix 42 relative to the photodiode matrix 22 of the unit pixel matrix 115.

[0145] Fig.11A FIG. 1 is a flow chart showing a process 1100 for manufacturing a CMOS image sensor 100 according to an embodiment. As described above, Figure 1A As shown, the CMOS image sensor 100 includes: a photodiode array 20 disposed in a semiconductor substrate 110; a color filter array 40 disposed above the photodiode array 20 and substantially aligned therewith to laterally separate adjacent color filters 40' of the color filter array 40; and a microlens array 60 disposed above the color filter array 40 and aligned therewith. Figure 2A As shown, the first isolation structure 150 includes a first low-n dielectric grid 51 , a second low-n dielectric grid 52 underlying the first low-n dielectric grid 51 , and a metal grid 53 at least partially surrounded by the second low-n dielectric grid 52 .

[0146] Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F , Fig.11G , Fig.11H , Fig.11I , Fig.11J , Figure 11K , Fig.11L and Fig.11M To illustrate the Fig.11A Cross-sectional diagram of the manufacturing process.

[0147] refer to Fig. 11B CMOS image sensor 100 includes a photodiode array 20 formed and positioned in a semiconductor substrate 110. CMOS image sensor 100 includes a DTI grid 150 to laterally separate adjacent photodiodes of photodiode array 20 in semiconductor substrate 110.

[0148] refer to Fig.11A and Fig. 11C In step 1110, a dielectric layer 123 is formed on the photodiode array 20. The dielectric layer 123 may be formed by, for example, chemical vapor deposition or spin coating.

[0149] refer to Fig.11A and Fig.11D In step 1120, a metal grid 53 is formed in the dielectric layer 123 and defines a plurality of openings 41. The plurality of openings 41 are positioned to align with corresponding photodiodes 20' of the photodiode array 20. In some embodiments, one or more masks are used in a lithography process to pattern the metal grid 53 so that the color filter 40' formed later will be internally offset. In some embodiments, as shown in FIG. Fig.11E As shown, an etching stop film 54 is formed over the metal grid 53 and the semiconductor substrate 110, and then as shown in FIG. Fig.11F As shown, the etching stop film 54 above the semiconductor substrate 110 is etched. The metal grid 53 may be formed by, for example, deposition, lithography and / or etching.

[0150] refer to Fig.11A and Fig.11G and Fig.11H In step 1130, a low-n dielectric grid 52 is formed in the dielectric layer 123 and overlies the metal grid 53. In some embodiments, the low-n dielectric grid 52 at least partially wraps the metal grid 53. The formation method of the low-n dielectric grid 52 can be performed by, for example, deposition, lithography and / or etching.

[0151] refer to Fig.11A and Fig.11I and Fig.11JIn step 1140, another low-n dielectric grid 51 is formed in the dielectric layer 123 and overlies the low-n dielectric grid 52. In some embodiments, the width W1 of the other low-n dielectric grid 51 is less than the width W2 of the low-n dielectric grid 52. (See also Figure 2A ). Another method of forming the low-n dielectric grid 52 may be performed by, for example, deposition, lithography and / or etching.

[0152] refer to Fig.11A and Figure 11K and Fig.11L In step 1150, a plurality of color filters 40' are formed on the dielectric layer 123 by filling the plurality of openings 41 with a color filter material. The plurality of color filters 40' are substantially aligned with the corresponding photodiodes 20' underlying the plurality of color filters 40'. The formation method of the color filters 40' can be performed by, for example, deposition, lithography, spin coating and / or etching.

[0153] refer to Fig.11A and Fig.11M In step 1160, a plurality of microlenses 60' are formed to cover the plurality of color filters 40', respectively. The microlenses 60' may be made of a transparent material having a refractive index greater than that of the color filter 40' and less than that of the dielectric layer 123. For example, the transparent material may be made of glass or a transparent polymer.

[0154] In some embodiments, dielectric layer 123 is made of a dielectric material having a dielectric constant greater than or equal to that of silicon oxide.

[0155] In some embodiments, the refractive index of low-n dielectric grid 52 and another low-n dielectric grid 51 is less than the refractive index of the plurality of color filters 40'. In some embodiments, the refractive index of low-n dielectric grid 52 and another low-n dielectric grid 51 is in the range of greater than 1 and less than 1.5.

[0156] In some embodiments, the metal grid 53 is made of a metal material or a metal alloy material. In some embodiments, the metal material of the metal grid 53 includes W, Al, Cu or Cr. In some embodiments, the metal alloy material of the metal grid 53 includes but is not limited to TiN. In some embodiments, a dielectric etch stop film 54 is formed around the metal grid 53 to separate the metal grid 53 from the low-n dielectric grid 52. Therefore, when the low-n dielectric grid 52 is in an etching process, the dielectric etch stop film 54 protects the metal grid 53.

[0157] According to an embodiment of the present disclosure, a composite grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid is narrower than the second low-n grid, and the refractive index of the first low-n dielectric grid and the second low-n dielectric grid of the first isolation structure is less than the refractive index of the color filter unit. In addition, the size of the color filter in each color filter matrix in the color filter layer varies depending on the position of the color filter in the color filter matrix. In addition, in an edge portion beyond a central region of the color filter array, the color filter matrix can be offset (or deviated) from the corresponding unit pixel matrix by a gradually increasing offset in a direction from the center of the central region to the edge of the edge region. Advantageously, as a result of these, the quantum efficiency (QE) and performance uniformity of the pixel image sensor in the CMOS image sensor are improved.

[0158] According to an embodiment of the present disclosure, a CMOS image sensor includes a photodiode array, a color filter array, a microlens array, and a grid isolation structure that laterally separates adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid. According to an embodiment of the present disclosure, a CMOS image sensor includes a plurality of unit pixels, each of the plurality of unit pixels including a photodiode surrounded by an isolation structure, a color filter disposed above the photodiode, and a microlens disposed above the color filter. The CMOS image sensor includes a plurality of matrices, the matrix including an n×n unit pixel matrix. The n×n unit pixel matrix has an n×n color filter matrix and an n×n photodiode matrix. As a result of a global offset, a distance S (or an offset) between a center C2 of a color filter matrix and a center C1 of a photodiode matrix in a plan view varies depending on the positions of the plurality of matrices in the CMOS image sensor. As a result of the internal offset, the size of the color filter of the n×n unit pixel matrix varies depending on the position of the color filter in the n×n unit pixel matrix. In this way, the quantum efficiency (QE) and performance uniformity of the plurality of unit pixels of the CMOS image sensor are advantageously improved.

[0159] According to aspects of the present disclosure, a CMOS image sensor includes: a photodiode layer including a photodiode array disposed in a semiconductor substrate; a color filter layer including a color filter array disposed above and substantially aligned with the photodiode array; a microlens layer including a microlens array disposed above and aligned with the color filter array; and a first isolation structure disposed in the color filter layer to laterally separate adjacent color filter units of the color filter array, and including a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid at least partially surrounded by the second low-n dielectric grid. A first width of the first low-n dielectric grid is less than a second width of the second low-n dielectric grid. In one or more of the foregoing and / or following embodiments, the refractive index of the first low-n dielectric grid and the second low-n dielectric grid of the first isolation structure is less than the refractive index of the color filter unit, and the refractive index of the first low-n dielectric grid and the second low-n dielectric grid is in a range greater than 1 and less than 1.5. In one or more of the foregoing and / or the following embodiments, the metal grid is at least partially wrapped by a dielectric etch stop film to separate the metal grid from the second low-n dielectric grid, and the metal grid is made of a metal material or a metal alloy material. In one or more of the foregoing and / or the following embodiments, the CMOS image sensor further includes a second isolation structure, the second isolation structure is disposed in the semiconductor substrate to laterally separate adjacent photodiodes of the photodiode array in the photodiode layer. In one or more of the foregoing and / or the following embodiments, the second isolation structure includes a deep trench isolation grid extending vertically from the upper surface of the photodiode layer into the photodiode layer. In one or more of the foregoing and / or the following embodiments, the CMOS image sensor further includes: a transfer transistor array disposed in the semiconductor substrate; and a third isolation structure, including a shallow trench isolation grid to laterally separate adjacent transfer transistors of the transfer transistor array. In one or more of the foregoing and / or the following embodiments, the CMOS image sensor further includes a separation layer separating the microlens layer and the color filter layer.

[0160] According to an aspect of the present disclosure, a CMOS image sensor includes a plurality of unit pixels, each of which includes a photodiode surrounded by an isolation structure, a color filter disposed above the photodiode, and a microlens disposed above the color filter. The CMOS image sensor includes a plurality of matrices, each of which includes: an n×n matrix consisting of a plurality of unit pixels, the n×n matrix consisting of a plurality of unit pixels having an n×n matrix consisting of a plurality of color filters, wherein n is an even number; and a 2×2 matrix consisting of a plurality of color filter regions, covering the n×n matrix consisting of a plurality of unit pixels. Each region of the 2×2 matrix consisting of a plurality of color filter regions is composed of a (n / 2)×(n / 2) matrix consisting of a plurality of color filters having the same color. The distance between the centroid of the 2×2 matrix consisting of the plurality of color filter regions and the centroid of the n×n matrix consisting of the plurality of unit pixels varies in a plan view depending on the position of the plurality of matrices in the CMOS image sensor. The size of at least one color filter of the n×n matrix composed of a plurality of unit pixels varies depending on the position of the at least one color filter in the n×n matrix composed of a plurality of unit pixels. In one or more of the aforementioned and / or following embodiments, in the edge region of the CMOS image sensor, the distance between the centroid of the 2×2 matrix composed of the plurality of color filter regions and the centroid of the n×n matrix composed of the plurality of unit pixels gradually increases in a first direction from the center of the CMOS image sensor to the edge of the edge portion in a plan view. In one or more of the aforementioned and / or following embodiments, the size of the n×n matrix composed of the plurality of color filters of the plurality of matrices in a plan view varies depending on the position of the plurality of matrices in the CMOS image sensor. In one or more of the aforementioned and / or following embodiments, the size of the n×n matrix composed of the plurality of color filters of the plurality of matrices in a plan view gradually decreases in a first direction from the center of the CMOS image sensor to the edge of the edge portion in a plan view. In one or more of the aforementioned and / or following embodiments, the 2×2 matrix formed by the plurality of color filter regions has three colors of red, blue and green, and each n×n matrix formed by the plurality of color filters includes one red color filter region matrix, one blue color filter region matrix and two green color filter region matrices. In one or more of the aforementioned and / or following embodiments, in each color filter series of the n×n matrix formed by the plurality of color filters, the size of the red or blue color filter is larger than the size of the green color filter. In one or more of the aforementioned and / or following embodiments, in a first direction in a plan view starting from the center of the CMOS image sensor, the size of the color filter following another color filter unit of the same color is smaller than the size of another color filter in each color filter series of the n×n matrix formed by the plurality of color filters.

[0161] According to aspects of the present disclosure, a method of manufacturing a CMOS image sensor device includes: forming a dielectric layer over a photodiode array, the photodiode array being located in a substrate; forming a metal grid in the dielectric layer and defining a plurality of openings, the openings being positioned to align with corresponding photodiodes of the photodiode array; forming a low-n dielectric grid in the dielectric layer and overlying the metal grid, the low-n dielectric grid at least partially encapsulating the metal grid; forming another low-n dielectric grid in the dielectric layer and overlying the low-n dielectric grid, the width of the other low-n dielectric grid being less than the width of the low-n dielectric grid; forming a plurality of color filters by filling the plurality of openings in the dielectric layer, the plurality of color filters being substantially aligned with corresponding photodiodes; and forming a plurality of microlenses respectively overlying the plurality of color filters. In one or more of the foregoing and / or following embodiments, the dielectric layer is made of a dielectric material having a dielectric constant greater than or equal to that of silicon oxide. In one or more of the foregoing and / or following embodiments, the refractive index of the low-n dielectric grid and the other low-n dielectric grid is less than the refractive index of the plurality of color filters. In one or more of the foregoing and / or following embodiments, the refractive index of the low-n dielectric grid (52) and the other low-n dielectric grid (51) is in a range greater than 1 and less than 1.5. In one or more of the foregoing and / or following embodiments, a dielectric etch stop film is formed around the metal grid, and the dielectric etch stop film separates the metal grid from the low-n dielectric grid. In one or more of the foregoing and / or following embodiments, the metal grid is made of a metal material or a metal alloy material. The metal material includes W, Al, Cu or Cr, and the metal alloy material includes TiN.

[0162] According to aspects of the present disclosure, a CMOS image sensor includes: a photodiode array; a plurality of color filters, wherein the color filters are substantially aligned with a plurality of corresponding photodiodes of the photodiode array; and a plurality of micro lenses, respectively, overlying the color filters; a metal grid, surrounding the color filters; a first dielectric grid, overlying the metal grid, the first dielectric grid at least partially encapsulating the metal grid; and a second dielectric grid, overlying the first dielectric grid, wherein a width of the second dielectric grid is less than a width of the first dielectric grid. In some embodiments, the complementary metal oxide semiconductor image sensor further includes a dielectric etch stop film, wherein the dielectric etch stop film separates the metal grid from the first dielectric grid.

[0163] It should be understood that not all advantages must be discussed herein, not all embodiments or examples require a particular advantage, and other embodiments or examples may provide different advantages.

[0164] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A complementary metal oxide semiconductor image sensor, characterized in that: include: a photodiode layer, comprising a photodiode array disposed in a semiconductor substrate; a color filter layer, including a color filter array, disposed above the photodiode array and substantially aligned with the photodiode array; a microlens layer, comprising a microlens array, disposed above the color filter array and aligned with the color filter array; and A first isolation structure is arranged in the color filter layer to laterally separate multiple adjacent color filter units of the color filter array, and includes a first dielectric grid, a second dielectric grid underlying the first dielectric grid, and a metal grid at least partially surrounded by the second dielectric grid, wherein a first width of the first dielectric grid is smaller than a second width of the second dielectric grid.

2. The complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein: A second isolation structure is further included. The second isolation structure is disposed in the semiconductor substrate to laterally separate a plurality of adjacent photodiodes of the photodiode array in the photodiode layer.

3. The complementary metal oxide semiconductor image sensor as claimed in claim 2, wherein: The second isolation structure includes a deep trench isolation grid vertically extending from an upper surface of the photodiode layer to the photodiode layer.

4. The complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein: Further including: a transfer transistor array disposed in the semiconductor substrate; and a third isolation structure including a shallow trench isolation grid to laterally separate a plurality of adjacent transfer transistors of the transfer transistor array.

5. A complementary metal oxide semiconductor image sensor, characterized in that: include: A plurality of unit pixels, each of which comprises a photodiode surrounded by an isolation structure, a color filter disposed above the photodiode, and a microlens disposed above the color filter, wherein: The complementary metal oxide semiconductor image sensor includes a plurality of matrices, Each of the matrices includes: an n×n matrix consisting of a plurality of unit pixels, the n×n matrix consisting of the plurality of unit pixels having an n×n matrix consisting of a plurality of color filters, wherein n is an even number; and a 2×2 matrix consisting of a plurality of color filter regions covering the n×n matrix consisting of the plurality of unit pixels, Each area of ​​the 2×2 matrix composed of the plurality of color filter areas is composed of a (n / 2)×(n / 2) matrix composed of a plurality of color filters having the same color, A distance between a centroid of the 2×2 matrix formed by the plurality of color filter regions and a centroid of the n×n matrix formed by the plurality of unit pixels varies in a plan view depending on a plurality of positions of the matrices in the complementary metal oxide semiconductor image sensor, and A size of at least one color filter of the n×n matrix formed by the plurality of unit pixels varies depending on a position of the at least one color filter in the n×n matrix formed by the plurality of unit pixels.

6. The complementary metal oxide semiconductor image sensor as claimed in claim 5, wherein: Wherein, in an edge portion of the complementary metal oxide semiconductor image sensor, the distance between the centroid of the 2×2 matrix formed by the multiple color filter regions and the centroid of the n×n matrix formed by the multiple unit pixels slowly and gradually increases in a first direction from a center of the complementary metal oxide semiconductor image sensor to an edge of the edge portion in a plan view.

7. The complementary metal oxide semiconductor image sensor as claimed in claim 5, wherein: The 2×2 matrix formed by the plurality of color filters has three colors: red, blue and green, and each of the 2×2 matrices formed by the plurality of color filters includes a red color filter area, a blue color filter area and two green color filter areas.

8. The complementary metal oxide semiconductor image sensor as claimed in claim 7, wherein: Along each color filter series of the n×n matrix formed by the plurality of color filters, a size of a red or blue color filter is larger than a size of a green color filter.

9. A complementary metal oxide semiconductor image sensor, characterized in that: include: a photodiode array; a plurality of color filters, wherein the color filters are substantially aligned with corresponding photodiodes of the photodiode array; A plurality of micro lenses respectively cover the color filters; a metal grid surrounding the color filters; a first dielectric grid overlying the metal grid, the first dielectric grid at least partially encapsulating the metal grid; and A second dielectric grid is overlying the first dielectric grid, wherein a width of the second dielectric grid is smaller than a width of the first dielectric grid.

10. The complementary metal oxide semiconductor image sensor according to claim 9, wherein: Further including: A dielectric etch stop film is provided, wherein the dielectric etch stop film separates the metal grid from the first dielectric grid.

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