Chip test circuit board

Abstract

The utility model provides a chip test circuit board. The chip test circuit board comprises a test bottom plate; the plurality of first connectors are arranged in a preset area on the test bottom plate and are used for being connected to a plurality of pins of a chip to be tested respectively, and each first connector in the plurality of first connectors is connected to a chip interface bus through a wire on the test bottom plate; and the plurality of test interfaces are arranged at the edge of the test bottom plate and are used for being connected with external test equipment respectively, and each test interface is connected to the chip interface bus through the test bus via a wire on the test bottom plate. According to the invention, the structure of the chip test circuit board is simplified.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a chip testing circuit board. Background Art

[0002] In the field of integrated circuit design, chip tape-out is the process of converting the originally designed chip circuit diagram into an actual chip model. After chip tape-out, it must be tested to ensure that the functions of the chip leaving the factory meet the design requirements.

[0003] When performing multiple tests on the chip, such as operating voltage range test, digital domain / analog domain current test, integrated DCDC efficiency test, integrated LDO output test, GPIO port voltage variation range test and load capacity test, multiplexed peripheral function test, chip design performance test, etc., for different test experiments, the test equipment and test environment required for each test experiment are different. Manual wiring is required when rewiring in each test environment. There are many lines and the wiring work is complicated. In addition, manual wiring is easy to make mistakes, making it difficult to ensure test reliability, which in turn leads to low efficiency. Utility Model Content

[0004] In view of this, an object of the present application is to provide a chip testing circuit board to overcome at least one of the above-mentioned defects.

[0005] In the first aspect, an embodiment of the present application provides a chip test circuit board, which includes: a test baseboard; a plurality of first connectors, which are arranged in a preset area on the test baseboard, for respectively connecting to a plurality of pins of a chip to be tested, and each of the plurality of first connectors is connected to a chip interface bus via wiring on the test baseboard; a plurality of test interfaces, which are arranged at the edge of the test baseboard, for respectively connecting to a plurality of external test devices, and each test interface is connected to a chip interface bus via a test bus through wiring on the test baseboard.

[0006] In an optional embodiment of the present application, the chip test circuit board also includes: a core board; a chip positioning groove formed at a preset position on the first surface of the core board, a plurality of connection contacts are arranged in the chip positioning groove, and the size of the chip positioning groove matches the package size of the chip to be tested, so that when the chip to be tested is placed in the chip positioning groove, the plurality of connection contacts in the chip positioning groove are correspondingly connected to the plurality of pins of the chip to be tested; a plurality of second connectors are arranged on the second surface of the core board, each of the plurality of second connectors is connected to a corresponding connection contact via a wiring on the core board, and the setting positions of the plurality of second connectors on the core board correspond to the setting positions of the plurality of first connectors on the test base board, so that when the core board is fixed to the test base board, the plurality of second connectors on the core board are connected one-to-one with the plurality of first connectors on the test base board, and the first surface and the second surface of the core board are opposite to each other.

[0007] In an optional embodiment of the present application, the chip test circuit board also includes: a plurality of first relays, each of which is arranged on the test base board and located between the first connector and the chip interface bus; a plurality of second relays, each of which is arranged on the test base board and located between the test interface and the test bus.

[0008] In an optional embodiment of the present application, the test bus includes a positive bus and a negative bus, and each test interface includes a positive terminal led out from the positive bus and a negative terminal led out from the negative bus, the positive terminal is used to connect to the positive interface of an external test device, and the negative terminal is used to connect to the negative interface of an external test device.

[0009] In an optional embodiment of the present application, the chip test circuit board also includes: a single-chip microcomputer, which is arranged on the test base board, and each of the multiple data interfaces of the single-chip microcomputer is respectively connected to the control end of the multiple first relays and the control end of the multiple second relays via the system control bus through the wiring on the test base board to control the closing or opening of the multiple first relays and the multiple second relays.

[0010] In an optional embodiment of the present application, the chip test circuit board also includes: a peripheral verification bus, which is arranged on a side of the test baseboard close to the single-chip microcomputer, wherein each of the multiple communication interfaces of the single-chip microcomputer is connected to the chip interface bus via the peripheral verification bus through the routing of the test baseboard.

[0011] In an optional embodiment of the present application, the chip test circuit board also includes: an external antenna, which is arranged on the core board, and the external antenna is connected to a preset pin of the chip to be tested through a wiring on the core board, and the preset pin is a pin for receiving a signal from the external antenna to transmit the signal received by the external antenna to the chip to be tested.

[0012] In an optional embodiment of the present application, the chip test circuit board also includes: a first serial debugging interface, which is arranged at the edge of the test base board, for connecting an external device that supports a serial interface, the first serial debugging interface is connected to the serial interface of the microcontroller via the wiring on the test base board, and a second serial debugging interface, which is arranged at the edge of the test base board, for connecting an external device that supports a serial interface, the second serial debugging interface is connected to a first preset connector via the wiring on the test base board, and the first preset connector is a first connector for connecting to the serial pin of the chip to be tested.

[0013] In an optional embodiment of the present application, the chip test circuit board also includes: a first D-type connector, arranged at the edge of the test base board, for connecting to a universal input / output interface of an external device, the first D-type connector is connected to the I / O interface of the microcontroller via the wiring on the test base board, a second D-type connector, arranged at the edge of the test base board, for connecting to the universal input / output interface of an external device, the second D-type connector is also connected to a second preset connector via the wiring on the test base board, and the second preset connector is a first connector for connecting to the I / O pin of the chip to be tested.

[0014] In an optional embodiment of the present application, the chip test circuit board also includes: a power supply, which is arranged on the test base board and connected to a third preset connector through wiring on the test base board, and the third preset connector is a first connector for connecting to a power supply pin of the chip to be tested, so that the chip to be tested is powered by the power supply.

[0015] An embodiment of the present application provides a chip test circuit board. By arranging multiple first connectors for connecting multiple pins of a chip to be tested on a test base board, each first connector is connected to a chip interface bus via wiring on the test base board, thereby solving the problem in the prior art that manual wiring work is complicated and error-prone, thereby causing unreliable testing. This makes the wiring on the test base board simple and simplifies the structure of the chip test circuit board.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a chip test circuit board provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of the core board provided in the embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of another chip testing circuit board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0022] In the description of the embodiments of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the utility model product is usually placed when in use, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] In the description of the embodiments of the present application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "provided with", "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0024] First, the application scenarios to which the present application is applicable are introduced. The present application can be applied in the field of integrated circuit testing technology.

[0025] Research has found that, currently, in the field of integrated circuit design, multiple tests must be performed on the chip after chip tape-out to ensure that the functions of the chip leaving the factory meet the predetermined requirements. To perform multiple tests, different test equipment and test environment are required. Manual wiring is required when connecting the test equipment to the chip to be tested. There are many lines and the wiring work is complicated. In addition, manual wiring is easy to make mistakes, making it difficult to ensure test reliability, which in turn leads to low efficiency.

[0026] In response to at least one of the above-mentioned problems, an embodiment of the present application provides a chip test circuit board. By setting multiple first connectors and multiple test interfaces on the test baseboard, each first connector is connected to the chip interface bus via the wiring on the test baseboard, and multiple test interfaces are connected to the chip interface bus via the wiring on the test baseboard via the test bus. This solves the problem in the prior art that manual wiring work is complicated and error-prone, which leads to unreliable testing. It makes the wiring on the test baseboard simple and simplifies the structure of the chip test circuit board.

[0027] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a chip test circuit board provided in an embodiment of the present application. Figure 1 As shown in , a chip test circuit board provided in an embodiment of the present application includes: a test base plate 101 , a first connector 102 , and a test interface 103 .

[0028] Specifically, the test substrate 101 may be a printed circuit board (PCB).

[0029] A plurality of first connectors 102 are disposed in a preset area on the test substrate 101 to be respectively connected to a plurality of pins of the chip to be tested. Each of the plurality of first connectors is connected to the chip interface bus 104 via a trace on the test substrate.

[0030] Preferably, the preset area of ​​the multiple first connectors 102 may be the middle position of the test base plate, so as to facilitate the setting of multiple wirings of the test base plate 101 , and the multiple first connectors 102 may be fixed connector females.

[0031] A plurality of test interfaces 103 are disposed at the edge of the test substrate 101 for connecting to external test equipment respectively. Each test interface 103 is connected to the chip interface bus 104 via a test bus 105 through a wiring on the test substrate 101 .

[0032] For example, the test interface 103 may include a positive electrode interface and a negative electrode interface, which are respectively connected to the positive electrode and the negative electrode of the external test equipment. The external test equipment may be a programmable power supply, an electronic load, an ammeter, a voltmeter, an oscilloscope, etc. The network port of the external test equipment is connected to an external computer through a network cable, so that when the chip to be tested is tested, the test data and the screenshots taken during the test are transmitted to the external computer. When the external computer receives the test data and the screenshots taken during the test, it stores them in the folder corresponding to the test.

[0033] Specifically, the test bus 105 and the chip interface bus 104 are connected via a bus connector.

[0034] For example, when the external test equipment is a voltmeter, the positive pole of the voltmeter is connected to the positive interface of the test interface, the negative pole of the voltmeter is connected to the negative interface of the test interface, the network port of the voltmeter is connected to the external computer through a network cable, and the first connector connected to the power pin of the chip to be tested transmits the signal of the chip to be tested to the chip interface bus via the wiring on the test baseboard, and transmits it to the voltmeter through the test bus connected to the chip interface bus. The voltmeter detects the voltage value, and transmits the test data of the voltage value and the screenshot during the test to the external computer through the network cable connected to the network port of the voltmeter. The external computer saves the test data of the voltage value and the screenshot during the test of the voltmeter in the voltage test folder.

[0035] A chip test circuit board provided in an embodiment of the present application has multiple first connectors arranged on a test baseboard, each first connector is connected to a chip interface bus via wiring on the test baseboard, and multiple test interfaces are connected to the chip interface bus via the wiring on the test baseboard via the test bus, thereby solving the problem in the prior art that manual wiring work is complicated and error-prone, resulting in unreliable testing, making the wiring on the test baseboard simple and simplifying the design of the chip test circuit board.

[0036] In the connection between the chip to be tested and the first connector 102, based on the fact that there is only a test base plate 101, multiple pins of the chip to be tested are directly connected to the corresponding multiple first connectors 102. When making connections, multiple routing lines can be set between the chip to be tested and the first connector 102, and one end of each of the multiple routing lines is connected to the pin of the chip to be tested, and the other end of each of the multiple routing lines can be a male head of a fixed connector, which is connected to the female heads of the fixed connectors of the multiple first connectors 102, thereby simplifying the circuit, simplifying the routing, and saving costs.

[0037] In addition to the above-mentioned method of directly connecting the chip under test to the first connector 102, the connection between multiple pins of the chip under test and multiple first connectors can also be achieved by setting a core board, such as Figure 2 shown.

[0038] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of the core board provided in the embodiment of the present application. Figure 2 As shown, the chip test circuit board provided in the embodiment of the present application includes: a core board 201 , a chip positioning groove 202 , and a plurality of second connectors 203 .

[0039] Specifically, the core board 201 may be a printed circuit board.

[0040] The chip positioning groove 202 is formed at a preset position on the first surface of the core board 201. A plurality of connection contacts are arranged in the chip positioning groove 202. The size of the chip positioning groove 202 matches the package size of the chip to be tested, so that when the chip to be tested is placed in the chip positioning groove 202, the plurality of connection contacts in the chip positioning groove 202 are correspondingly connected to the plurality of pins of the chip to be tested.

[0041] Specifically, the first surface of the core board 201 can be the upper surface of the core board 201, and the preset position of the first surface can be the middle position of the upper surface, so as to facilitate the setting of multiple routing lines of the core board 201, and the multiple connection contacts of the chip positioning groove 202 can be multiple needles, and one end of each needle in the multiple needles is connected to multiple pins of the chip to be tested, and the other end of each needle in the multiple needles is correspondingly connected to the routing lines on the core board 201, so that the multiple connection contacts in the chip positioning groove are correspondingly connected to the multiple pins of the chip to be tested.

[0042] Here, four fixing holes are set at the four corners of the chip positioning slot 202, and the chip positioning slot 202 can be fixed to the core board 201 by means of screws and screw holes. Preferably, the chip positioning slot can be a chip test socket, which can improve the convenience and efficiency of replacing the chip to be tested.

[0043] In the first embodiment, if the plurality of pins of the chip under test are packaged around the chip under test, the plurality of connection contacts in the chip positioning groove 202 are relatively arranged around the chip positioning groove 202 to be correspondingly connected with the plurality of pins of the chip under test.

[0044] In the second embodiment, if the plurality of pins of the chip to be tested are packaged at the bottom of the chip to be tested through ball grid array (BGA) packaging technology, the plurality of connection contacts in the chip positioning groove 202 are relatively arranged at the bottom of the chip positioning groove 202 to be correspondingly connected with the plurality of pins of the chip to be tested.

[0045] For example, the chip to be tested may be 5 mm×5 mm and have 102 pins. The size of the chip positioning groove matches the size of the chip to be tested, and the multiple connection contacts in the chip positioning groove are arranged correspondingly to the multiple pins of the chip to be tested.

[0046] Multiple second connectors 203 are arranged on the second surface of the core board 201, and each of the multiple second connectors 203 is connected to a corresponding connection contact via the routing on the core board 201. The setting positions of the multiple second connectors 203 on the core board 201 correspond to the setting positions of the multiple first connectors 102 on the test base board 101, so that when the core board 201 is fixed to the test base board 101, the multiple second connectors 203 on the core board 201 are connected one-to-one with the multiple first connectors 102 on the test base board 101, and the first surface and the second surface of the core board are opposite to each other.

[0047] Among them, the second surface of the core board 201 can be the lower surface of the core board 201, and the multiple wirings on the core board 201 are arranged on the first surface of the core board 201, that is, the upper surface of the core board 201. For example, the second connector 203 can be a fixed connector male head, which is connected to the corresponding fixed connector female head. The connection method is simple and saves wiring. The male and female nature of the fixed connector can enhance safety or ensure the normal operation of the equipment. The fixed connector male head is usually inserted into the fixed connector female head to establish a circuit connection.

[0048] See also Figure 2 , the core board also includes: an external antenna 204.

[0049] Specifically, the external antenna 204 is arranged on the core board 201, and the external antenna 204 is connected to the preset pin of the chip to be tested through the wiring on the core board 201. The preset pin is a pin for receiving the signal of the external antenna to transmit the signal received by the external antenna to the chip to be tested.

[0050] For example, the preset pin may be an antenna pin.

[0051] Specifically, there can be two external antennas 204, and the two antennas can be antennas of the same model, both of which receive satellite signals from 1.1GGz to 1.6GHz, including but not limited to GPS, BDS and GLONASS. The external antenna 204 transmits positioning signals and angle determination signals to the chip to be tested through the wiring on the core board 201, determines the longitude and latitude information and attitude angle information of the chip to be tested, and transmits the longitude and latitude information and attitude angle information of the chip to be tested to the first connector 102 of the test base board 101 via multiple wirings on the core board 201 and the second connector 203, and then transmits the longitude and latitude information and attitude angle information of the chip to be tested to the external computer via the wiring on the test base board. The external computer determines whether there is a problem with the channel of the chip to be tested through the signal strength of the longitude and latitude information and attitude angle information output by the chip to be tested, and can transmit the working status of the chip to be tested in real time to achieve chip performance analysis.

[0052] The principle is that using only one of the antennas can only realize the positioning function. When two antennas are used to receive satellite signals respectively, due to the different positions of the two antennas, the positioning results solved by the two antennas at a given position are correlated and analyzed to achieve the attitude measurement effect. Here, we judge whether there are problems in the implementation of the chip function performance. First, we judge the signal strength of the two antennas input, that is, the input signal-to-noise ratio. Secondly, we make the next step of positioning and orientation performance judgment.

[0053] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of another chip test circuit board provided in an embodiment of the present application. Figure 3 As shown, another chip test circuit board provided in an embodiment of the present application includes: multiple first relays 301, multiple second relays 302, a single-chip microcomputer 303, a peripheral verification bus 304, a first serial debugging interface 305, a second serial debugging interface, a first D-type connector 306 and a second D-type connector.

[0054] Specifically, each of the plurality of first relays 301 is disposed on the test substrate and located between the first connector and the chip interface bus.

[0055] Each second relay in the plurality of second relays 302 is disposed on the test substrate and located between the test interface and the test bus.

[0056] The test bus includes a positive bus and a negative bus, and each test interface includes a positive terminal led out from the positive bus and a negative terminal led out from the negative bus, the positive terminal is used to connect to the positive interface of the external test equipment, and the negative terminal is used to connect to the negative interface of the external test equipment, wherein each of the multiple second relays is respectively arranged between the positive bus and the positive terminal, and / or between the negative bus and the negative terminal.

[0057] Specifically, the first relay is arranged between the first connector and the chip interface bus to control the on and off of the circuit, and the second relay 302 is arranged between the positive bus and the positive terminal, and / or between the negative bus and the negative terminal, to control the on and off of the positive terminal and / or the negative terminal.

[0058] The single-chip microcomputer 303 is arranged on the test baseboard, and each of the multiple data interfaces of the single-chip microcomputer is connected to the control end of the multiple first relays 301 and the control end of the multiple second relays 302 through the wiring on the test baseboard via the system control bus to control the closing or opening of the multiple first relays 301 and the multiple second relays 302.

[0059] Specifically, the single-chip microcomputer 303 can be an M4 core single-chip microcomputer. When determining the test items of the chip to be tested, for example, when testing the voltage of the chip to be tested, each of the multiple data interfaces of the single-chip microcomputer 303 is connected to the control ends of multiple first relays 301 and the control ends of multiple second relays 302 through the wiring on the test baseboard via the system control bus, thereby controlling the first relay 301, the second relay 302 on the positive terminal of the voltmeter, and the second relay 302 on the negative terminal to close, so as to test the voltage of the chip to be tested, and transmit the data measured by the voltmeter and the screenshots during the test to an external computer via a network cable, and the external computer stores them in the folder of the voltage test of the chip to be tested.

[0060] The peripheral verification bus 304 is arranged on a side of the test baseboard close to the single-chip microcomputer, wherein each of the multiple communication interfaces of the single-chip microcomputer is connected to the chip interface bus via the peripheral verification bus through the wiring of the test baseboard.

[0061] Specifically, the peripheral verification bus includes multiple communication protocols such as UART, IIC, SPI, CAN, PWM and ADC. The peripheral interface bus of the UART communication protocol and the CAN communication protocol includes a transmitting pin TX and a receiving pin RX. The peripheral interface bus of the IIC communication protocol includes a serial clock signal pin and a serial data pin. The peripheral interface bus of the SPI communication protocol includes a transmitting pin TX and a receiving pin RX and also includes a chip select signal pin CS and a clock pin CLK in addition to a transmitting pin TX and a receiving pin RX. Each pin is connected to the communication interface of the corresponding communication protocol among the multiple communication interfaces of the single-chip microcomputer via the peripheral verification bus through the routing of the test baseboard, so as to send and receive data of the corresponding communication protocol between the single-chip microcomputer and the chip to be tested, so as to realize the testing of multiple communication protocols.

[0062] For example, the transmit pin (TX) of the UART protocol is used to transmit data, and the receive pin (RX) is used to receive data.

[0063] The first serial debugging interface 305 is set at the edge of the test baseboard for connecting an external device that supports a serial interface. The serial debugging interface is connected to the serial interface of the microcontroller via the wiring on the test baseboard. The second serial debugging interface is set at the edge of the test baseboard for connecting an external device that supports a serial interface. The serial debugging interface is connected to the first preset connector via the wiring on the test baseboard. The first preset connector is a first connector used to connect to the serial pin of the chip to be tested.

[0064] Preferably, the serial debug interface is a SWD debug bus (Serial Wire Debug). SWD only requires two wires, namely: SWCLK and SWDIO. SWDIO is a single-wire debug interface data line, which is connected to the serial interface of the single-chip microcomputer and is used to transmit debug information and program data. SWCLK is a single-wire debug interface clock line, which is connected to the serial interface of the single-chip microcomputer and is used to synchronize data transmission. SWD is mainly used for code debugging and program burning. The single-chip microcomputer and the chip to be tested have their own independent SWD, which reduces the occupancy of the GPIO ports of the single-chip microcomputer and the chip to be tested, and realizes the transmission of chip automated test programs and test data records.

[0065] Specifically, the first D-type connector 306 is arranged at the edge of the test baseboard to connect the universal input and output interface of the external device. The first D-type connector is connected to the I / O interface of the microcontroller via the wiring and level conversion chip on the test baseboard, and is connected to the UART interface of the microcontroller to realize data transmission. The second D-type connector is arranged at the edge of the test baseboard to connect the universal input and output interface of the external device. The second D-type connector is also connected to the second preset connector via the wiring on the test baseboard. The second preset connector is a first connector for connecting to the I / O pin of the chip to be tested. The microcontroller and the chip to be tested both have D-type connector interfaces. The level conversion chip can convert the TTL level into the RS232 level and is placed on the test baseboard close to the first D-type connector.

[0066] The chip test circuit board also includes a USB interface 308 (Universal Serial Bus), which is arranged at the edge of the test baseboard and is used to connect the universal input and output interface of the external device. The USB interface 308 is connected to the I / O interface of the microcontroller via the wiring on the test baseboard to realize data transmission and communication between devices. The USB transmission rate is higher and can be connected to an external power supply interface for power supply.

[0067] The chip test circuit board also includes a power supply, which is arranged on the test baseboard and connected to a third preset connector through wiring on the test baseboard. The third preset connector is a first connector used to connect to the power supply pin of the chip to be tested so that the power supply can power the chip to be tested.

[0068] The chip test circuit board also includes a voltage divider resistor, which is arranged between the power supply and the third preset connector to adjust the power supply voltage of the chip to be tested and complete the chip function test. Here, the voltage divider resistor is connected to the I / O interface of the microcontroller through the wiring on the test baseboard to provide the microcontroller with the value of the power supply voltage. The microcontroller detects the size of the power supply voltage in real time to prevent the power supply voltage from being too high and causing damage to the chip to be tested, thereby ensuring the reliability of the test.

[0069] Here, before testing the chip to be tested, the chip to be tested is first fixed in the chip positioning groove, multiple pins of the chip to be tested are correspondingly connected to multiple connection contacts in the chip positioning groove, the required external test equipment is correspondingly connected to multiple test interfaces, the single-chip microcomputer receives a start experiment signal, and controls the corresponding first relay and second relay to be closed through the system control bus, so that the corresponding circuit is turned on, the single-chip microcomputer controls the power supply to supply power to the chip to be tested through multiple traces on the test baseboard, the first connector connected to the power pins of the chip to be tested, the second connector and multiple traces on the core board, and the voltage value is collected through the voltmeter, and the collected data is transmitted to an external computer for recording.

[0070] Depending on the different external test equipment and the on-off of the corresponding first relay and second relay, multiple tests such as voltage test, current test, power-on and power-off test, leakage detection, and driving capability test can be performed on the chip under test.

[0071] The present application pre-sets the wiring on the test baseboard, and multiple first relays and multiple second relays control the closing and opening of the circuit, without the need for manual wiring, thereby greatly improving the efficiency of verifying the screening piece, solving the problem of complex wiring work and high error rate for personnel, further improving work efficiency and reducing verification costs.

[0072] This application can realize the function verification of all ports of the chip in the peripheral interface bus part, and the performance of the chip to be tested can be verified through the antenna on the core board. At the same time, different external test equipment can be connected to multiple test interfaces to detect the physical layer test of the chip. Performing multiple tests can reduce the production defect rate and return rate of the chip to be tested, thereby reducing costs.

[0073] A chip test circuit board provided in an embodiment of the present application, by arranging multiple first connectors for connecting multiple pins of a chip to be tested on a test baseboard, each first connector is connected to a chip interface bus via wiring on the test baseboard, and multiple test interfaces are connected to the chip interface bus via the wiring on the test baseboard via the test bus, thereby solving the problem in the prior art that manual wiring work is complicated and error-prone, thereby causing unreliable testing, making the wiring on the test baseboard simple and simplifying the structure of the chip test circuit board.

[0074] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip test circuit board, characterized in that: The chip test circuit board comprises: Test the base plate; A plurality of first connectors are arranged in a preset area on the test base plate and are used to be respectively connected to a plurality of pins of the chip to be tested, and each of the plurality of first connectors is connected to a chip interface bus via a trace on the test base plate; A plurality of test interfaces are arranged at the edge of the test base plate and are used to respectively connect a plurality of external test devices. Each test interface is connected to the chip interface bus via a test bus through the wiring on the test base plate.

2. The chip testing circuit board according to claim 1, characterized in that: The chip test circuit board also includes: Core board; A chip positioning groove is formed at a preset position on the first surface of the core board, wherein a plurality of connection contacts are arranged in the chip positioning groove, and the size of the chip positioning groove matches the package size of the chip to be tested, so that when the chip to be tested is placed in the chip positioning groove, the plurality of connection contacts in the chip positioning groove are correspondingly connected to the plurality of pins of the chip to be tested; A plurality of second connectors are arranged on the second surface of the core board, each of the plurality of second connectors is connected to a corresponding connection contact via a wiring on the core board, and the arrangement positions of the plurality of second connectors on the core board correspond to the arrangement positions of the plurality of first connectors on the test base board, so that when the core board is fixed to the test base board, the plurality of second connectors on the core board are connected one-to-one with the plurality of first connectors on the test base board, and the first surface and the second surface of the core board are opposite to each other.

3. The chip testing circuit board according to claim 2, characterized in that: The chip test circuit board also includes: A plurality of first relays, each of which is arranged on the test base board and located between the first connector and the chip interface bus; A plurality of second relays, each of which is arranged on the test baseboard and located between the test interface and the test bus.

4. The chip testing circuit board according to claim 3, characterized in that: The test bus includes a positive bus and a negative bus, each test interface includes a positive terminal led from the positive bus and a negative terminal led from the negative bus, the positive terminal is used to connect to the positive interface of the external test equipment, and the negative terminal is used to connect to the negative interface of the external test equipment, Wherein, each of the plurality of second relays is respectively arranged between the positive bus and the positive terminal, and / or between the negative bus and the negative terminal.

5. The chip testing circuit board according to claim 4, characterized in that: The chip test circuit board also includes: A single-chip microcomputer is arranged on the test baseboard, and each of the multiple data interfaces of the single-chip microcomputer is respectively connected to the control end of the multiple first relays and the control end of the multiple second relays via the wiring on the test baseboard via the system control bus to control the closing or opening of the multiple first relays and the multiple second relays.

6. The chip testing circuit board according to claim 5, characterized in that: The chip test circuit board also includes: The peripheral verification bus is arranged on a side of the test baseboard close to the single chip microcomputer. Wherein, each of the multiple communication interfaces of the single-chip microcomputer is connected to the chip interface bus via the peripheral verification bus through the wiring of the test baseboard.

7. The chip testing circuit board according to claim 6, characterized in that: The chip test circuit board also includes: An external antenna is arranged on the core board. The external antenna is connected to a preset pin of the chip to be tested through a wiring on the core board. The preset pin is a pin for receiving a signal from the external antenna to transmit the signal received by the external antenna to the chip to be tested.

8. The chip testing circuit board according to claim 5, characterized in that: The chip test circuit board also includes: A first serial debugging interface is provided at the edge of the test base plate and is used to connect an external device supporting a serial interface. The first serial debugging interface is connected to the serial interface of the single-chip microcomputer via a wiring on the test base plate. A second serial debugging interface is arranged at the edge of the test baseboard and is used to connect an external device that supports a serial interface. The second serial debugging interface is connected to a first preset connector via wiring on the test baseboard. The first preset connector is a first connector used to connect to the serial pin of the chip to be tested.

9. The chip testing circuit board according to claim 5, characterized in that: The chip test circuit board also includes: A first D-type connector is provided at the edge of the test base plate and is used to connect to a universal input / output interface of an external device. The first D-type connector is connected to an I / O interface of the single-chip microcomputer via a wiring on the test base plate. A second D-type connector is arranged at the edge of the test base plate and is used to connect to the universal input and output interface of the external device. The second D-type connector is also connected to the second preset connector via the wiring on the test base plate. The second preset connector is a first connector used to connect to the I / O pin of the chip to be tested.

10. The chip testing circuit board according to claim 1, characterized in that: The chip test circuit board also includes: A power supply is arranged on the test baseboard and connected to a third preset connector through wiring on the test baseboard. The third preset connector is a first connector used to connect to a power supply pin of the chip to be tested so that the power supply can supply power to the chip to be tested.

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