BMS secondary protection circuit

Abstract

The utility model discloses a BMS secondary protection circuit comprising a secondary sampling control circuit (1) and a single-chip microcomputer signal circuit (4). The secondary sampling control circuit (1) comprises a plurality of sampling management chips (5), input pins of the sampling management chips (5) are connected with a battery end through a sampling circuit (6), and output pins of the sampling management chips (5) are connected with a signal output circuit (7); the plurality of signal output circuits (7) and the single-chip microcomputer signal circuit (4) are connected with a control protection circuit (2) together. The output end of the control protection circuit (2) is connected with a fusing circuit (10) used for cutting off a battery charging and discharging loop, and the input end of the fusing circuit (10) is further connected with a battery end. The battery protection circuit can output a signal to cut off a battery charging and discharging loop when a battery end is in an abnormal working state and BMS system software fails, so that the reliability of battery protection is improved.

Description

Technical Field

[0001] The utility model relates to the field of BMS circuits, in particular to a BMS secondary protection circuit. Background Art

[0002] BMS stands for Battery Management System. It is a device that monitors the status of energy storage batteries. It is mainly used for intelligent management and maintenance of each battery unit, preventing overcharging and over-discharging of the battery, extending the battery life, and monitoring the battery status. At present, the BMS battery protection circuit generally monitors each battery terminal through an acquisition chip. When the BMS system detects that the working status of the battery terminal is abnormal, it will actively cut off the circuit through software drive to protect the battery terminal. However, when the software fails, the circuit cutting function will be lost, so that the battery terminal cannot be effectively protected in time, and the reliability of use is poor. Utility Model Content

[0003] The purpose of the utility model is to provide a BMS secondary protection circuit. The utility model can output a signal to cut off the battery charging and discharging circuit when the battery end is in an abnormal working state and the BMS system software fails, thereby improving the reliability of battery protection.

[0004] The technical solution of the utility model: a BMS secondary protection circuit comprises a secondary sampling control circuit and a single-chip signal circuit; the secondary sampling control circuit comprises a plurality of sampling management chips, the input pins of the sampling management chips are connected to the battery end via the sampling circuit, and the output pins of the sampling management chips are connected to the signal output circuit; the plurality of signal output circuits are connected to a control protection circuit together with the single-chip signal circuit; the output end of the control protection circuit is connected to a fuse circuit for cutting off a battery charging and discharging circuit, and the input end of the fuse circuit is also connected to the battery end.

[0005] In the above-mentioned BMS secondary protection circuit, the control protection circuit includes a first resistor, an NMOS tube, a second resistor, a first capacitor and a first voltage-stabilizing diode. One end of the first resistor is connected to the signal output circuit and the single-chip signal circuit, and the other end of the first resistor is respectively connected to the gate of the NMOS tube, one end of the second resistor, one end of the first capacitor and the negative electrode of the first voltage-stabilizing diode. The source of the NMOS tube, the other end of the second resistor, the other end of the first capacitor and the positive electrode of the first voltage-stabilizing diode are grounded, and the drain of the NMOS tube is connected to the fuse circuit.

[0006] In the aforementioned BMS secondary protection circuit, the fuse circuit includes a third resistor, a PMOS tube, a fourth resistor, a second voltage-stabilizing diode and a fuse, one end of the third resistor is connected to the drain of the NMOS tube, the other end of the third resistor is respectively connected to the gate of the PMOS tube, one end of the fourth resistor and the positive electrode of the second voltage-stabilizing diode, the source of the PMOS tube, the other end of the fourth resistor and the negative electrode of the second voltage-stabilizing diode are connected to the battery terminal, and the drain of the PMOS tube is connected to the fuse.

[0007] In the aforementioned BMS secondary protection circuit, the signal output circuit includes a sixth resistor, a transistor, a diode, and a seventh resistor, one end of the sixth resistor is connected to the CO pin of the sampling management chip, the other end of the sixth resistor is connected to the emitter of the transistor, the collector of the transistor is connected to the positive electrode of the diode, the negative electrode of the diode is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the first resistor.

[0008] In the aforementioned BMS secondary protection circuit, the base of the transistor is connected to an eighth resistor, and the other end of the eighth resistor is connected to the VSS pin of the sampling management chip.

[0009] In the aforementioned BMS secondary protection circuit, the sampling circuit includes a fifth resistor, one end of the fifth resistor is connected to the corresponding battery terminal, and the other end of the fifth resistor is connected to the input pin corresponding to the sampling management chip.

[0010] In the aforementioned BMS secondary protection circuit, a voltage stabilizing circuit is connected to the VDD pin of the sampling management chip, and the voltage stabilizing circuit includes a third voltage stabilizing diode, a third capacitor, and a ninth resistor. The VDD pin of the sampling management chip is connected to one end of the third capacitor, the positive electrode of the third voltage stabilizing diode, and one end of the ninth resistor. The other end of the third capacitor is connected to the negative electrode of the third voltage stabilizing diode, and the other end of the ninth resistor is connected to the battery end.

[0011] In the aforementioned BMS secondary protection circuit, the single-chip microcomputer signal circuit includes a blocking diode, the anode of the blocking diode is connected to the single-chip microcomputer in the BMS, and the cathode of the blocking diode is connected to the first resistor.

[0012] Compared with the prior art, the utility model has the following beneficial effects:

[0013] 1. The utility model includes a secondary sampling control circuit and a single-chip computer signal circuit; the secondary sampling control circuit includes a plurality of sampling management chips, the input pins of the sampling management chips are connected to the battery end through the sampling circuit, and the output pins of the sampling management chips are connected to the signal output circuit; the plurality of signal output circuits are connected to the control protection circuit together with the single-chip computer signal circuit; the output end of the control protection circuit is connected to a fuse circuit for cutting off the battery charging and discharging circuit, and the input end of the fuse circuit is also connected to the battery end; the sampling management chip samples and monitors the working voltage of the battery end through the sampling circuit, and outputs a voltage signal as a battery abnormality signal through the output pin. At the same time, when the BMS system fails, the single-chip computer signal circuit can also output a voltage signal. When both signals act on the control protection circuit at the same time, the fuse circuit starts to cut off the battery charging and discharging circuit; a single-chip computer signal circuit is added, and when the battery end is in an abnormal working state and the BMS system software fails, an output signal is output to cut off the battery charging and discharging circuit, thereby improving the reliability of battery protection.

[0014] 2. The control protection circuit of the utility model includes a first resistor, an NMOS tube, a second resistor, a first capacitor and a first voltage-stabilizing diode. One end of the first resistor is connected to the signal output circuit and the single-chip signal circuit, and the other end of the first resistor is respectively connected to the gate of the NMOS tube, one end of the second resistor, one end of the first capacitor and the negative electrode of the first voltage-stabilizing diode. The source of the NMOS tube, the other end of the second resistor, the other end of the first capacitor and the positive electrode of the first voltage-stabilizing diode are grounded, and the drain of the NMOS tube is connected to the fuse circuit. When the voltage signal of the signal output circuit and the voltage signal of the single-chip signal circuit act on the NMOS tube at the same time and generate a sufficient voltage difference, the NMOS tube will be turned on and transmit the signal, thereby avoiding the accidental activation of the fuse circuit under normal state due to the circuit being always turned on, and the reliability of use is good.

[0015] 3. The fuse circuit of the utility model includes a third resistor, a PMOS tube, a fourth resistor, a second voltage-stabilizing diode and a fuse. One end of the third resistor is connected to the drain of the NMOS tube, and the other end of the third resistor is respectively connected to the gate of the PMOS tube, one end of the fourth resistor and the positive electrode of the second voltage-stabilizing diode. The source of the PMOS tube, the other end of the fourth resistor and the negative electrode of the second voltage-stabilizing diode are connected to the battery terminal, and the drain of the PMOS tube is connected to the fuse. When the PMOS tube receives the voltage signal of the control protection circuit, the voltage difference between its internal part and the battery terminal is reduced before it is turned on, and then the fuse is blown by the current at the battery terminal, thereby avoiding accidental blowing of the fuse under normal conditions due to the circuit being always turned on. At the same time, it relies on the battery terminal for power supply, reducing the demand for external power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of the utility model;

[0017] Figure 2 It is a structural schematic diagram of the secondary sampling control circuit of the utility model;

[0018] Figure 3 It is a structural schematic diagram of the control protection circuit of the utility model.

[0019] The markings in the attached drawings are: 1-secondary sampling control circuit; 2-control protection circuit; 4-single-chip computer signal circuit; 5-sampling management chip; 6-sampling circuit; 7-signal output circuit; 10-fuse circuit; 11-fuse; 12-first resistor; 13-NMOS tube; 14-second resistor; 15-first capacitor; 16-first voltage-stabilizing diode; 17-third resistor; 18-PMOS tube; 19-fourth resistor; 20-second voltage-stabilizing diode; 21-fifth resistor; 22-second capacitor; 23-sixth resistor; 24-transistor; 25-diode; 26-seventh resistor; 27-eighth resistor; 28-third voltage-stabilizing diode; 29-third capacitor; 30-isolating diode; 31-voltage-stabilizing circuit; 32-ninth resistor. DETAILED DESCRIPTION

[0020] The present invention is further described below in conjunction with the accompanying drawings and embodiments, but they are not intended to limit the present invention.

[0021] Embodiment: A BMS secondary protection circuit, as shown in the attached Figure 1 As shown in the attached Figure 1 As shown, it includes a secondary sampling control circuit 1 and a single chip signal circuit 4; as shown in the attached Figure 2 As shown, the secondary sampling control circuit 1 includes three sampling management chips 5, the input pins of the sampling management chips 5 are connected to the battery terminals via the sampling circuit 6, and the battery terminals are as shown in the attached Figure 2 As shown in B0-B13, the output pin of the sampling management chip 5 is connected to the signal output circuit 7; the plurality of signal output circuits 7 and the single chip signal circuit 4 are connected to the control protection circuit 2; Figure 3As shown, the output end of the control protection circuit 2 is connected to a fuse circuit 10 for cutting off the battery charging and discharging circuit, and the input end of the fuse circuit 10 is also connected to the battery end; the control protection circuit 2 includes a first resistor 12, an NMOS tube 13, a second resistor 14, a first capacitor 15 and a first voltage-stabilizing diode 16, one end of the first resistor 12 is connected to the signal output circuit 7 and the single-chip signal circuit 4, the other end of the first resistor 12 is respectively connected to the gate of the NMOS tube 13, one end of the second resistor 14, one end of the first capacitor 15 and the negative electrode of the first voltage-stabilizing diode 16, the source of the NMOS tube 13, the other end of the second resistor 14, the other end of the first capacitor 15 and the positive electrode of the first voltage-stabilizing diode 16 are grounded, and the drain of the NMOS tube 13 is connected to the fuse circuit 10; the fuse circuit 10 includes a third resistor 17, a PMOS tube 18, a fourth resistor 19, a second voltage-stabilizing diode 16 20 and fuse 11, the fuse is a three-terminal fuse, one end of the third resistor 17 is connected to the drain of the NMOS tube 13, the other end of the third resistor 17 is respectively connected to the gate of the PMOS tube 18, one end of the fourth resistor 19 and the positive electrode of the second voltage-stabilizing diode 20, the source of the PMOS tube 18, the other end of the fourth resistor 19 and the negative electrode of the second voltage-stabilizing diode 20 are connected to the battery terminal, and the drain of the PMOS tube 18 is connected to the fuse 11; the signal output circuit 7 includes a sixth resistor 23, a triode 24, a diode 25, and a seventh resistor 26, one end of the sixth resistor 23 is connected to the CO pin of the sampling management chip 5, the other end of the sixth resistor 23 is connected to the emitter of the triode 24, the collector of the triode 24 is connected to the positive electrode of the diode 25, the negative electrode of the diode 25 is connected to one end of the seventh resistor 26, and the other end of the seventh resistor 26 is connected to the first resistor 12, attached Figure 2The connection between the two is marked with a RUN pin; the base of the transistor 24 is connected to an eighth resistor 27, and the other end of the eighth resistor 27 is connected to the VSS pin of the sampling management chip 5; the sampling circuit 6 includes a fifth resistor 21, one end of the fifth resistor 21 is connected to the corresponding battery terminal, and the other end of the fifth resistor 21 is connected to the input pin corresponding to the sampling management chip 5, and a second capacitor 22 is connected between the input pin of the sampling management chip and the adjacent circuit on the VSS pin; the VDD pin of the sampling management chip 5 is connected to a voltage stabilizing circuit 31, and the voltage stabilizing circuit 31 includes a third voltage stabilizing circuit The diode 28, the third capacitor 29, the ninth resistor 32, the VDD pin of the sampling management chip 5 is connected to one end of the third capacitor 29, the positive electrode of the third voltage-stabilizing diode 28 and one end of the ninth resistor 32, the other end of the third capacitor 29 is connected to the negative electrode of the third voltage-stabilizing diode 28, the other end of the ninth resistor 32 is connected to the battery end, and the VSS pin of the sampling management chip is connected to the battery end; the single-chip signal circuit 4 includes a blocking diode 30, the positive electrode of the blocking diode 30 is connected to the single-chip microcomputer in the BMS, and the negative electrode of the blocking diode 30 is connected to the first resistor 12 to isolate the two signals.

[0022] Working principle: The sampling management chip samples and monitors the working voltage of the battery end through the sampling circuit, and outputs the voltage signal through the output pin as a battery abnormality signal. At the same time, when the BMS system fails, the single-chip signal circuit can also output the voltage signal. When both signals act on the control protection circuit at the same time, the fuse circuit starts to cut off the battery charging and discharging circuit; add a single-chip signal circuit to output a signal to cut off the battery charging and discharging circuit when the battery end is in an abnormal working state and the BMS system software fails, thereby improving the reliability of battery protection.

[0023] The above embodiments only express the implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. In this embodiment, up, down, left, right, front, and back only represent their relative positions and do not represent their absolute positions. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A BMS secondary protection circuit, characterized in that: The invention comprises a secondary sampling control circuit (1) and a single-chip computer signal circuit (4); the secondary sampling control circuit (1) comprises a plurality of sampling management chips (5); the input pins of the sampling management chips (5) are connected to a battery terminal via a sampling circuit (6); the output pins of the sampling management chips (5) are connected to a signal output circuit (7); the plurality of signal output circuits (7) and the single-chip computer signal circuit (4) are connected to a control protection circuit (2); the output end of the control protection circuit (2) is connected to a fuse circuit (10) for cutting off a battery charging and discharging circuit; the input end of the fuse circuit (10) is also connected to the battery terminal.

2. The BMS secondary protection circuit according to claim 1, characterized in that: The control protection circuit (2) comprises a first resistor (12), an NMOS transistor (13), a second resistor (14), a first capacitor (15) and a first voltage-stabilizing diode (16); one end of the first resistor (12) is connected to the signal output circuit (7) and the single-chip signal circuit (4); the other end of the first resistor (12) is respectively connected to the gate of the NMOS transistor (13), one end of the second resistor (14), one end of the first capacitor (15) and the negative electrode of the first voltage-stabilizing diode (16); the source of the NMOS transistor (13), the other end of the second resistor (14), the other end of the first capacitor (15) and the positive electrode of the first voltage-stabilizing diode (16) are grounded; and the drain of the NMOS transistor (13) is connected to the fuse circuit (10).

3. The BMS secondary protection circuit according to claim 2, characterized in that: The fuse circuit (10) comprises a third resistor (17), a PMOS tube (18), a fourth resistor (19), a second voltage-stabilizing diode (20) and a fuse (11); one end of the third resistor (17) is connected to the drain of the NMOS tube (13); the other end of the third resistor (17) is respectively connected to the gate of the PMOS tube (18), one end of the fourth resistor (19) and the positive electrode of the second voltage-stabilizing diode (20); the source of the PMOS tube (18), the other end of the fourth resistor (19) and the negative electrode of the second voltage-stabilizing diode (20) are connected to the battery terminal; and the drain of the PMOS tube (18) is connected to the fuse (11).

4. The BMS secondary protection circuit according to claim 2, characterized in that: The signal output circuit (7) comprises a sixth resistor (23), a triode (24), a diode (25), and a seventh resistor (26); one end of the sixth resistor (23) is connected to the CO pin of the sampling management chip (5); the other end of the sixth resistor (23) is connected to the emitter of the triode (24); the collector of the triode (24) is connected to the positive electrode of the diode (25); the negative electrode of the diode (25) is connected to one end of the seventh resistor (26); and the other end of the seventh resistor (26) is connected to the first resistor (12).

5. The BMS secondary protection circuit according to claim 4, characterized in that: The base of the transistor (24) is connected to an eighth resistor (27), and the other end of the eighth resistor (27) is connected to a VSS pin of the sampling management chip (5).

6. The BMS secondary protection circuit according to claim 1, characterized in that: The sampling circuit (6) comprises a fifth resistor (21), one end of the fifth resistor (21) is connected to a corresponding battery terminal, and the other end of the fifth resistor (21) is connected to a corresponding input pin of the sampling management chip (5).

7. The BMS secondary protection circuit according to claim 1, characterized in that: A voltage stabilizing circuit (31) is connected to the VDD pin of the sampling management chip (5), and the voltage stabilizing circuit (31) comprises a third voltage stabilizing diode (28), a third capacitor (29), and a ninth resistor (32). The VDD pin of the sampling management chip (5) is connected to one end of the third capacitor (29), the positive electrode of the third voltage stabilizing diode (28), and one end of the ninth resistor (32). The other end of the third capacitor (29) is connected to the negative electrode of the third voltage stabilizing diode (28), and the other end of the ninth resistor (32) is connected to a battery terminal.

8. The BMS secondary protection circuit according to claim 2, characterized in that: The single-chip computer signal circuit (4) comprises a blocking diode (30), the anode of the blocking diode (30) is connected to the single-chip computer in the BMS, and the cathode of the blocking diode (30) is connected to the first resistor (12).

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