Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a plurality of semiconductor structures extending over the substrate, a plurality of layers of interconnects disposed over the substrate and the semiconductor structures, and a substrate via extending vertically through the substrate and the plurality of layers of interconnects. The semiconductor structure includes a first semiconductor structure having a first metal gate on the first semiconductor structure and a second semiconductor structure having a second metal gate on the second semiconductor structure. A multi-layer interconnect (MLI) is connected to the first metal gate, and the multi-layer interconnect (MLI) is not electrically connected to the second metal gate. A spacer liner is formed on a sidewall of the second semiconductor structure and disposed between the sidewall and a first sidewall of the substrate via.

Description

Technical Field

[0001] The utility model relates to a semiconductor technology, in particular to a semiconductor structure with a through via. Background Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. In the course of IC development, functional density (that is, the number of interconnected devices per chip area) has generally increased, while geometry size (that is, the smallest component (or circuit) that can be formed using a manufacturing process) has shrunk. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Recent attempts have focused on vias, such as through silicon vias or through substrate vias (TSVs). TSVs have found application in three-dimensional (3D) integrated circuits for routing electronic signals from one side of the silicon substrate of the integrated circuit to the other side. Generally, TSVs are made by etching a vertical via through the substrate and filling the via with a conductive material. Although existing TSV structures and methods of making them are generally adequate for their intended purposes, they are not satisfactory in all respects. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0005] In some embodiments, a semiconductor structure is provided, comprising: a substrate; a plurality of semiconductor structures extending above the substrate, wherein the semiconductor structures include a first semiconductor structure having a first metal gate located thereon and a second semiconductor structure having a second metal gate located thereon; a multi-layer interconnect disposed above the substrate and the semiconductor structure, wherein the multi-layer interconnect is connected to the first metal gate and the multi-layer interconnect is not electrically connected to the second metal gate; and a substrate via extending vertically through the substrate and the multi-layer interconnect, wherein a spacer liner is formed on a side wall of the second semiconductor structure and disposed between the side wall and a first side wall of the substrate via.

[0006] According to one embodiment of the present invention, a third semiconductor structure is adjacent to a second sidewall of the substrate via, wherein the third semiconductor structure extends above the substrate, and the spacer liner is connected to an upper surface of the third semiconductor structure.

[0007] According to one embodiment of the present invention, the second semiconductor structure is a crown structure having a plurality of fins extending from a base portion.

[0008] According to one embodiment of the present invention, the side wall extends from a top of a fin among the plurality of fins, along the fin and along the base.

[0009] In some embodiments, a semiconductor structure is provided, comprising a plurality of semiconductor structures extending from a front side of a substrate; a plurality of metal gates formed on the plurality of the semiconductor structures; a multi-layer interconnect formed on the plurality of the metal gates; and a substrate via passing through the multi-layer interconnect and the plurality of the semiconductor structures and extending to the substrate.

[0010] According to one embodiment of the present invention, a conductive feature component is further included, which is formed on a back side of the substrate and connected to the substrate via.

[0011] According to one embodiment of the present invention, a first semiconductor structure among the plurality of semiconductor structures located outside the substrate via has a crown structure, and a plurality of fins extend from the crown structure.

[0012] According to one embodiment of the present invention, the substrate via hole includes: a metal filling layer; and a liner formed on two opposite side walls of the metal filling layer.

[0013] According to one embodiment of the present invention, a spacer liner is further included, extending through the multi-layer interconnect and separated from the metal filling layer by the liner.

[0014] According to one embodiment of the present invention, the height of the spacer lining is smaller than the height of the lining. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flow chart is shown of an embodiment of a method for forming a device structure and a via structure passing through the device structure according to various aspects of the present disclosure.

[0016] Figure 2A , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17A and Fig. 17BShows the various modes of the present disclosure. Figure 1 A non-holistic cross-sectional schematic diagram of a working component of an operating step of the method.

[0017] Figure 2B and Figure 2C Schematic top views of devices according to various aspects of the present disclosure are shown.

[0018] The reference numerals are as follows:

[0019] 100: Method

[0020] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130: Step Block

[0021] 106A, 106B, 106C: Sub-step blocks

[0022] 200,200': Installation

[0023] 202,202': base

[0024] 210: Installation area

[0025] 212: Via area

[0026] 214: Front End of Line (FEOL) Device

[0027] 300,300':Semiconductor structure

[0028] 302: Crown structure

[0029] 304: fin; fin-like structure

[0030] 400: Isolation feature

[0031] 402: Gate structure

[0032] 404: source / drain region; source / drain feature component

[0033] 406,502A: Interlayer dielectric (ILD) layer

[0034] 408: Front End Online (FEOL) Layer

[0035] 502: Middle section (MEOL) layer

[0036] 502B: contact plug; gate contact; drain / gate contact plug

[0037] 504: Back-end of line (BEOL) layer; Multi-layer interconnect (MLI) structure

[0038] 504A: Intermetal Dielectric (IMD) layer

[0039] 504B: Metallization layer

[0040] 504C:Through hole

[0041] 506,1102: mask component; mask layer

[0042] 506A,602,1102A,1202: Open

[0043] 802,802': Spacer lining

[0044] 1302: Lining

[0045] 1402: conductive layer; metal layer; metal filling layer

[0046] 1600:Through hole

[0047] 1702A: Insulation layer

[0048] 1702B:Internal connection layer

[0049] D: Dimensions

[0050] H1,H2: Height DETAILED DESCRIPTION

[0051] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0052] Spatially related terms such as "below", "beneath", "below", "above", "above", etc. are used herein to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0053] Furthermore, when "approximately," "approximately," etc. are used to describe a value or range of values, the terms include values ​​within a reasonable range that takes into account variations inherent in manufacturing, as understood by a person skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having features associated with the values, the size or range of the values ​​includes a reasonable range of the values, such as within + / -10% of the values. For example, a material layer with a thickness of "about 5 nm" may cover a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to a person skilled in the art to be + / -15%. Furthermore, the present disclosure may repeat numbers and / or text in various different examples. Repetition is for the purpose of simplicity and clarity, rather than listing the relationship between the various different embodiments and / or configurations discussed.

[0054] The interconnect structure electrically couples various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate, enabling the various components to operate as specified by the design requirements. The interconnect structure includes a combination of a dielectric layer and a conductive layer to provide electronic signal routing. The conductive layer includes vias and contact features that provide vertical connections and conductive lines that provide horizontal connections. In some embodiments, the interconnect structure may have multiple metal layers (or metallization layers) that are vertically interconnected through vias or contact features, which may be referred to as a multi-layer interconnect (MLI) structure. During operation of the IC device, the interconnect structure routes signals between components of the IC device and / or distributes signals (e.g., timing signals, voltage signals, and / or ground signals) to components. The interconnect structure is formed in the back-end-of-the-line (BEOL) process, usually after the front-end-of-the-line (FEOL) process forms active devices (e.g., transistors on a substrate) and the middle-end-of-the-line (MEOL) process forms contacts connected to the active devices (e.g., conductive plugs connected to source / drain regions and gate structures).

[0055] In some embodiments, it is desirable to provide a vertical interconnect that extends through an interconnect structure and / or a substrate to facilitate various device structures (e.g., CMOS image sensor (CIS), three-dimensional integrated circuit (3DIC), MEMS device, radio frequency (RF) device, wafer-on-wafer (WoW) device, etc.). The vertical interconnect may be referred to as a via, or a through silicon via, or a through substrate via (TSV), because it passes through a semiconductor substrate in whole or in part. The term via or TSV in the present disclosure broadly includes a through-hole structure that provides direct signal routing from the front side of a substrate to the back side of a substrate (or vice versa). TSVs may not only vertically pass through a silicon substrate, but may also vertically pass through the BEOL, MEOL, and / or FEOL regions of a device.

[0056] The vias (TSVs) and the areas in which the vias are formed typically span a relatively large area of ​​the substrate. In some embodiments, the vias are larger than the active devices of the device (e.g., transistors formed in a FEOL process). Therefore, the pattern density in the via area can be significantly different than the pattern density in the active device area. When forming active semiconductor features (e.g., when forming FEOL, MEOL, or BEOL structures), leaving a large cleared area to receive the vias can create process challenges. For example, inconsistent processing can occur in the via area due to the difference in pattern density. In one embodiment, dishing can occur in the via area during a process (e.g., a chemical mechanical polishing (CMP) process).

[0057] The vias may be formed after forming multiple film layers in the BEOL process, and formed on these film layers after the FEOL and MEOL processes. The present disclosure provides a method and a semiconductor structure to form sacrificial features in the via region during the FEOL process, thereby improving the pattern consistency of the entire die. Moreover, the challenges in the process, such as reducing the occurrence of dishing, can be alleviated. In some embodiments, the FEOL process includes forming active device features (e.g., an active area including a semiconductor structure (such as a fin or crown structure) extending from a substrate) and transistor features (e.g., a metal gate and source / drain region in the via region), while forming an active transistor device. In other words, in some embodiments, an active area extending from a substrate, such as a fin structure including a crown structure, is provided. A metal gate is formed not only in the device region, but also in the via region by a gate replacement process, and not only in the device region, and a source / drain region is grown on the active region of the device region. After forming the FEOL features, a MEOL structure (e.g., a contact) is formed and surrounds the dielectric layer. The BEOL features (eg, MLI structures, including their surrounding dielectric layers) are then formed. Thereafter, vias are formed to serve as conductive vias, and in some embodiments, liner materials are also formed to protect adjacent structures.

[0058] The various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 The device 200 (shown in FIG. 1 ) includes a via structure according to various aspects of the present disclosure. Figure 2A-Figure 17B ) is a flowchart of the method 100 of the device structure illustrated in FIG. The method 100 is merely an example and does not limit the present disclosure to the contents explicitly described in the method 100. Additional operation steps may be provided before, during, and after the method 100, and some of the operation steps described may be replaced, cancelled, or moved for use in other embodiments of the method. For the sake of simplicity, not all operation steps are described in detail here. Figure 2A-Figure 17B 1 and 2 to describe the method 100 , which are schematic, non-complete cross-sectional and top views of the device 200 at different stages of fabrication according to various embodiments of the method 100 . In the present disclosure, like reference numerals refer to like features unless explicitly stated otherwise.

[0059] The device 200 shown in the drawings of the present disclosure is simplified, and not all features of the device 200 are shown or described in detail. The device 200 shown in the drawings may be a portion of an IC chip, a system on chip (SoC) or a portion thereof, which may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFET), n-type field effect transistors (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components or combinations thereof. In some embodiments, the device 200 and the formed vias are connected to another device (e.g., another device 200), such as in a stacked form. Figures 11B and 17B illustrate a device 200', which is substantially similar to device 200, with another exemplary arrangement of vias relative to adjacent FEOL structures.

[0060] Please refer to Figure 1 and Figure 2A , Figure 2B , Figure 2C, method 100 includes a step block 102, in which a substrate 202 is provided. Substrate 202 is a portion of device 200, and will include further structures as method 100 progresses. In one embodiment, substrate 202 includes silicon (Si). Alternatively or additionally, substrate 202 may include another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In addition, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding and / or other suitable methods. According to the design requirements of the device 200, the substrate 202 may include various doped regions (not shown). In some embodiments, the substrate 202 includes a p-type doped region (e.g., a p-type well region) doped with a p-type dopant (e.g., boron (e.g., BF2), indium, other p-type dopants, or a combination thereof). In some embodiments, the substrate 202 includes an n-type doped region (e.g., an n-type well region) doped with an n-type dopant (e.g., phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof). In some embodiments, the substrate 202 includes a doped region formed with a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed on and / or in the substrate 202, for example, to provide a p-type well structure, an n-type well structure, a double well structure, a protrusion structure, or a combination thereof. Ion implantation, diffusion, and / or other suitable doping processes may be performed to form the various doped regions.

[0061] The method 100 includes a step block 104 in which an active region is formed on a substrate 202 in a FEOL process. The active region may be a semiconductor structure extending vertically (e.g., in the Z direction) from the substrate. In some embodiments, the active region is formed in a fin region, such as provided when forming a fin field effect transistor (FinFET). In some embodiments, the active region is formed in a crown structure. The crown structure may include a fin structure extending above a base portion of the crown structure, which structures together form a semiconductor structure extending above an upper surface of the substrate. In some other embodiments, the semiconductor structure and / or the active region are designed to form other multi-gate devices, such as a gate-all-around (GAA) transistor. A GAA transistor has a gate structure that may extend partially or completely around a channel region to provide access to the channel region on two or more sides. The channel region may include nanowires, nanosheets, or other nanostructures. In some embodiments, the active region is planar, such as formed when forming a planar transistor. Between the active regions, there may be isolation regions, such as shallow trench isolation (STI) features, extending between the active regions (eg, crown structures or planar regions), see isolation structure 400 .

[0062] In some embodiments, a crown structure with a fin (generally referred to as a semiconductor structure) can be formed by directly patterning a top portion of the substrate 202 so that the structure protrudes from the substrate 202. The semiconductor structure can also be formed by epitaxially growing a semiconductor layer on a substrate and then patterning the semiconductor layer to form each semiconductor structure. The semiconductor structure can be patterned by any suitable method. For example, the semiconductor structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formation of patterns (e.g., pitch) that are smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to form fins by etching the initial epitaxial semiconductor layer.

[0063] In some embodiments, certain areas of substrate 202 are designated as areas for forming devices, including front-end-of-line (FEOL) active devices such as transistors, capacitors, memory structures, passive devices, and / or other suitable structures. These areas are referred to as device areas. Figure 2A , Figure 2B , Figure 2C2 is shown as a device region 210. The device region 210 includes active regions and surrounding insulating regions (e.g., isolation structures such as STI) disposed between the active regions. Other regions of the substrate 202 are designated as regions for forming vias (also referred to as through-substrate vias (TSVs)). Figure 2A , Figure 2B , Figure 2C , which is shown as a via region 212. In some embodiments, the dimension D of the via region 212 is at least D. In some embodiments, the dimension D may be 5 microns (μm) or more. In one embodiment, the dimension D of the via region 212 is approximately 6 microns. In one embodiment, the dimension D of the via region 212 is approximately between 5 microns and 10 microns. It should be noted that each substrate 202 has multiple via regions 212 and device regions 210. The dimension D can be measured in any and / or all directions of the via region 212 in a top view. The dimension D can be much larger than the size of the front end (FEOL) device (for example, 5 times or more). As Figure 2C As shown, a plurality of front end of line (FEOL) devices (e.g., transistors) 214 may be formed within the device region 210. These may form active transistors of the final device 200. In the present disclosure, the front end of line (FEOL) devices (e.g., transistors) 214 are also formed throughout the via region 212 (where the FEOL devices are subsequently removed, as described below).

[0064] In some embodiments, the via region 212 is approximately circular in a top view. Figure 2B and Figure 2C As shown. In some embodiments, the via region 212 is elliptical in a top view, wherein at least one dimension is D, as described above. In some embodiments, the via region 212 is rectangular (including square) in a top view, wherein at least one dimension is D. These shapes are exemplary only, and other shapes are possible, such as an octagon. In some embodiments, the via region 212 is defined as being the same as the shape of a subsequently formed via or TSV. In other embodiments, the via region 212 may be different from the shape of a subsequently formed TSV. In various cases, the via region 212 surrounds the TSV to be formed. In other words, the via region 212 is at least as large as the TSV. In some embodiments, the area surrounding the TSV is included in the TSV region and includes, for example, a dummy device, a dummy feature component (e.g., a semiconductor structure, a gate, S / D) or a portion thereof.

[0065] Although shown on the substrate 202, the via region 212 and the device region 210 may also be defined in design data associated with the device 200. In one embodiment, the via region 212 and the device region 210 are defined in layout data associated with the device 200. The layout data may follow design rule checker (DRC) software or data that defines the via region in a manner that does not allow placement of active devices of the device 200 in the region. The layout defining the device region 210 and the via region 212 may be defined in a layout database (e.g., GDS, GDSII, OASIS, and / or other suitable layout formats).

[0066] Please refer to Figure 3 In an example, a plurality of semiconductor structures 300 are formed, on which a device is to be formed. The semiconductor structure 300 provides an active region, such as where a channel of a transistor is to be formed. In one embodiment, the semiconductor structure 300 is a crown structure having a base 302 and a fin structure 304 extending from the crown structure base 302. Figure 3 As shown, some of the semiconductor structures 300 defining active regions are fins 304 extending from the substrate 202 (without the crown structure). The semiconductor structures 300 are formed in the device region 210 and the via region 212 of the substrate 202. The semiconductor structures 300 in the via region 212 may be referred to as dummy semiconductor structures or dummy active regions because these structures are subsequently removed from the device 200.

[0067] Between the active regions, a plurality of semiconductor structures 300 and a plurality of isolation features are formed. In some embodiments, the isolation features are shallow trench isolation (STI) features. Figure 4A , Figure 4B, which shows an isolation feature 400 extending between semiconductor structures 300. The isolation feature 400 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon or other suitable isolation composition), or a combination thereof. The isolation feature 400 can be configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure. For example, the isolation feature 400 can be an STI feature that defines the semiconductor structures 300 and electrically isolates them from each other. In some embodiments, the isolation feature 400 includes an isolation material that isolates the local fin 304 on the crown structure 302. The STI feature can be formed by etching a trench in the substrate 202 (e.g., by using a dry etching process and / or a wet etching process) and filling the trench with an insulator material (e.g., using a chemical vapor deposition (CVD) process or a spin-on glass process). A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or planarize the upper surface of the isolated feature 400. The insulator material may then be etched back to form the semiconductor structure 300 elevated above the isolated feature 400. In another example, the isolation feature can be formed by depositing an insulator material on the substrate 202 after forming the semiconductor structure 300 (in some embodiments, the insulator material layer fills the gaps (trench) between the fins 304 on the crown semiconductor structure 302, and the insulator material layer is etched back to form the isolation feature 400. In some embodiments, the isolation feature includes a multi-layer structure filling the trench, such as a silicon nitride layer disposed on a thermal oxide liner. In another example, the isolation feature 400 includes a dielectric layer disposed on a doped liner (including, for example, boron silicate glass (BSG) or phosphosilicate glass (PSG)). In yet another example, the isolation feature includes a bulk dielectric layer disposed on the dielectric liner, wherein the bulk dielectric layer and the dielectric liner include materials according to the design requirements of the device 200.

[0068] The method 100 includes a step block 106 in which front end of line (FEOL) devices are formed in the device region and the via region of the substrate. In some embodiments, the front end of line (FEOL) devices include transistors composed of FEOL features, such as source / drain regions and / or gate structures. These front end of line (FEOL) devices are also referred to as active front end of line (FEOL) devices because they form the functionality of the device 200. While the active FEOL devices are formed in the device region, sacrificial front end of line (FEOL) devices commensurate with the active front end of line (FEOL) device structures can be formed in the via region 212 of the substrate. These sacrificial front end of line (FEOL) devices can be subsequently removed as described in the steps of the method 100 below.

[0069] Active and sacrificial front end of line (FEOL) devices may be formed by various steps, including, in one example, shown in sub-step block 106A, sub-step block 106B, and sub-step block 106C. These steps are exemplary only and are not limiting. Other methods may be used to form the front end of line (FEOL) devices. The formed front end of line (FEOL) devices, active front end of line (FEOL) devices, and / or sacrificial front end of line (FEOL) devices may be features of GAA devices, FinFET devices, CFET devices, planar transistors, and / or other device structures.

[0070] In one embodiment, step block 106 begins with sub-step block 106A, where a plurality of dummy gate structures are formed in the device region and the via region. The dummy gate structures are formed in both the device region 210 and the via region 212. In some embodiments, the pattern density of the gate structures formed in the device region 210 and the via region 212 is substantially the same. Figure 2C That is, in one embodiment, the pitch of the gate structures in the device region 210 is the same as the pitch of the gate structures in the via region 212 .

[0071] The dummy gate structure may be polysilicon, and is therefore called a poly gate (PG). The dummy gate structure is formed by appropriate patterning and etching to form a dummy gate structure with sidewalls. The dummy gate structure may be substantially as follows Figure 4A The gate structure 402 is configured as shown, and as shown. On the sidewalls of the gate structure 402, a spacer component, also referred to as a spacer (not shown). In some embodiments, the spacer is made of silicon dioxide (SiO2), silicon oxynitride (Si x O y N z ), composite (SiO2 / Si3N4), silicon nitride (Si3N4) and / or other suitable dielectric materials.

[0072] Block 106 continues to sub-block 106B, where source / drain features are formed adjacent to the dummy gate structure (and spacer features). The source / drain features may be formed in the device region 210 and the via region 212. In one embodiment, the source / drain features are epitaxially grown from the semiconductor structure 300 and / or a recess in the semiconductor structure 300 adjacent to the dummy gate structure. See Figure 4B , the source / drain region 404 is shown through a schematic cross-sectional view of the semiconductor structure 300 .

[0073] The source / drain feature 404 may be deposited using vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain feature is n-type, it may include silicon (Si) doped with n-type dopants (e.g., phosphorus (P) or arsenic (As)). When the source / drain feature is p-type, it may include silicon (SiGe) doped with p-type dopants (e.g., boron (B) or boron difluoride (BF2)). In some embodiments, the source / drain feature may include multiple layers, such as film layers with different dopant concentrations. In some embodiments, the semiconductor structure 300 (e.g., the fin 304) may be recessed to form an opening, and the source / drain electrical feature 404 may be grown on the recessed structure.

[0074] Step block 106 continues to sub-step block 106C, where a replacement gate (RPG) process is performed. The RPG process replaces the dummy gate structure (e.g., PG) described with reference to sub-step block 106A with a functional gate structure such as a metal gate. It should be noted that in step block 106, other methods of forming gate structures may be provided, including other processes, such as a gate-first process, and sub-step blocks 106A, 106B, and 106C are merely exemplary embodiments. The RPG process or other process for forming a functional gate is performed on both the dummy gate structure of the device region 210 and the via region 212.

[0075] In some embodiments, after forming the dummy polysilicon gate and the spacer, the RPG process may include forming an inter-layer dielectric (ILD) layer adjacent to the dummy polysilicon gate structure. The ILD layer may be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. Before depositing the ILD layer, a contact etch stop layer (CESL) may be deposited such that the CESL is disposed between the ILD layer and the source / drain feature 404. The CESL may include silicon nitride or silicon oxynitride, and may be deposited using CVD, ALD, or a suitable method.

[0076] After the ILD layer is deposited, a planarization process is performed to expose the upper surface of the dummy gate in the RPG process. The planarization process may include a CMP process. In some embodiments, since the semiconductor structure 300, the fin 304 and / or the dummy gate structure are present in the via region 212, the ILD layer in the via region 212 may be prevented from being dished during the CMP process. Figure 4B For example, an interlayer dielectric (ILD) layer 406 may be deposited. A substantially planar surface of the interlayer dielectric (ILD) layer 406 may be provided from the device region 210 across the via region 212 to the device region 210. After planarization, the dummy gate (e.g., polysilicon) is removed to form a trench in the replacement gate, as described above. Figure 4A A replacement gate is shown within the gate structure 402, which is configured substantially the same as the dummy gate structure. The gate structure 402 is disposed within the device region 210 and the via region 212. In one embodiment, the gate structure 402 includes a metal electrode, and is therefore referred to as a metal gate.

[0077] The gate structure 402 may include an interface layer connected to the semiconductor structure 300 (e.g., the fin 304), a gate dielectric layer located on the interface layer, and a gate electrode layer located on the gate dielectric layer. The interface layer of the gate structure 402 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer of the gate structure 402 may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate layer of the gate structure 402 may include a single layer or alternatively a multi-layer structure (e.g., a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner, a wetting layer, an adhesion layer, various combinations of metal alloys or metal silicides. For example, the gate layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbide (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof.

[0078] The gate structure 402 and the source / drain regions 404 are part of a front-end-of-line (FEOL) structure formed in a front-end-of-line (FEOL) layer 408. For example, these features form a transistor, such as Figure 2C The device (eg, transistor) 214 may also include a front end of line (FEOL) layer 408 that may include portions of the semiconductor structure 300 and portions of the diffusion regions in the substrate (as described above) and the isolation structure 400.

[0079] The method 100 includes step block 108, wherein a line MEOL structure is formed in the middle of line (MEOL) layer. The structure of the middle of line (MEOL) layer may include a local interconnect structure and / or a plug that provides a connection to the components of the FEOL structure, such as a source / drain contact plug connected to the source / drain region of a transistor or a gate contact plug connected to the gate structure of a transistor. Please refer to Figure 5 In an example of a substrate 202, a middle-of-line (MEOL) layer 502 is formed on the substrate 202. The middle-of-line (MEOL) layer 502 includes an interlayer dielectric (ILD) layer 502A and a contact plug 502B. In one embodiment, the middle-of-line (MEOL) layer 502 includes a gate contact plug and a source / drain contact plug extending through the interlayer dielectric (ILD) layer 502A and / or the interlayer dielectric (ILD) layer 406. A gate contact 502B extends through the interlayer dielectric (ILD) layer 502A to be physically and electrically coupled to one of the gate structures 402. A source / drain contact plug 502B extends through the interlayer dielectric (ILD) layer 502A (and / or the interlayer dielectric (ILD) layer 406) to be physically and electrically coupled to one of the source / drain feature components 404. In some embodiments, the interlayer dielectric (ILD) layer 502A may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG) and / or other suitable dielectric materials.

[0080] Contact 502B may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu) or other metals, as examples. In some embodiments, contact 502B may include a barrier layer to connect interlayer dielectric (ILD) layer 502A. The barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride or nickel nitride. In addition, in order to reduce contact resistance, a silicide feature may be provided between contact 502B and a transistor feature (e.g., gate 402). The silicide feature may include titanium silicide. Contact 502B may be deposited using CVD, PVD or a suitable method. The fabrication of middle-end-of-line (MEOL) layer 502 may end with a planarization process.

[0081] The method 100 includes a step block 110 in which a back-end-of-line (BEOL) layer including BEOL features is formed. The BEOL layer includes multi-layer interconnects (MLI) that are provided using metal lines or vias extending through dielectric layers. Figure 5 In an example of the present invention, the BEOL process forms a back-end of line (BEOL) layer 504, including a stack of metallization layers and interleaved dielectrics, also referred to as a multi-layer interconnect (MLI) structure 504. The multi-layer interconnect (MLI) structure 504 may include a plurality of metallization layers 504B, such as eight (8) to thirteen (13) metallization layers, denoted as metallization layers M1-Mn. These metallization layers 504B generally provide horizontal wiring. Vias 504C provide vertical wiring connecting the metallization layers 504B. Generally speaking, the metallization layers M1-Mn include conductive wiring layers, including conductive lines (e.g., metallization layers 504B extending laterally) and vias (e.g., vias 504C extending vertically between the metal lines) to electrically couple to the middle of line (MEOL) structure 502 (e.g., contacts 502B). The conductive wiring layers are formed on a dielectric material layer, such as an intermetallic dielectric (IMD) layer 504A. The IMD layer 504A may include a low dielectric constant or an extreme low dielectric constant (ELK) material, such as oxide, SiO2, borophosphosilicate glass (BPSG), tetraethyl silicate (TEOS), spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, or plasma-enhanced tetraethyl silicate (PETEOS). A planarization process (e.g., a CMP process) may be performed to planarize each IMD layer 504A.

[0082] The metallization layer including the metallization layer 504B and the through hole 504C may be formed using, for example, an electroplating and etching process or by a damascene or dual damascene process, wherein an opening is etched into a corresponding dielectric layer (IMD layer) and the opening is filled with a conductive material. The metallization layer 504B may be formed of any suitable conductive material, such as a highly conductive metal, a low resistance metal, an elemental metal, a transition metal, or the like. In one embodiment, the metallization layer 504B may be formed of copper, however other materials may also be used, such as tungsten, aluminum, gold, or the like. In embodiments where the metallization layer 504B is formed of copper, the metallization layer 504B may be deposited by electroplating techniques.

[0083] The metallization layer 504B and / or the via 504C may include a liner and / or a barrier layer. For example, a liner (not shown) may be formed on the dielectric layer within the opening, the liner covering the sidewalls and bottom of the opening. The liner may be tetraethyl orthosilicate (TEOS) or silicon nitride, however any suitable dielectric material may be used instead. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, however other suitable processes such as physical vapor deposition or thermal processes may also be used. The barrier layer (if present) may be formed on the liner and cover the sidewalls and bottom of the opening. The barrier layer may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), combinations of these processes, or the like. The barrier layer may include tantalum nitride, however other materials may be used instead, such as tantalum, titanium, titanium nitride, combinations of these materials, and the like.

[0084] It should be noted that the MEOL structure 502 and the BEOL layer 504 are formed through the via region 212. However, the MEOL structure 502 and / or the BEOL layer 504 in the via region 212 include a dielectric layer, an interlayer dielectric (ILD) layer 502A, and an intermetallic dielectric (IMD) layer 504A, respectively. In one embodiment, the MEOL layer 502 and / or the BEOL layer 504 in the via region 212 do not include a metallization layer. For example, the contact 502B is omitted from the MEOL structure 502 in the via region 212. In some embodiments, the metallization layer 504B and the through hole 504C are omitted from the via region 212. In some embodiments, conductive features of the middle of line (MEOL) layer 502 are formed within the via region 212 , but metallization features of the back end of line (BEOL) layer 504 are not.

[0085] The method 100 includes step block 112, wherein a mask feature is formed on the substrate (on the BEOL layer) to define via locations. Figure 5 In the example of FIG. 5 , a mask feature 506 having an opening 506A defining a via location is formed on a back-end-of-line (BEOL) layer 504. The mask feature 506 may be a photoresist. In some embodiments, the mask feature 506 may also include a hard mask layer. In some embodiments, the opening 506A has a size of about D, as described above. The mask feature 506 may be patterned using a suitable photolithography and etching process.

[0086] The mask layer 506 may include photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, titanium nitride or other suitable materials. The deposited mask layer is then subjected to a pre-exposure process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure bake process and a development process to form a patterned mask layer having an opening 506B, which is aligned with the opening to be formed for the via described below.

[0087] The method 100 includes step block 114, wherein a via opening defined by the mask feature of step block 114 is etched in the BEOL layer and the MEOL layer of the device. Figure 6 In the example of , an opening 602 extending through the back-end-of-line (BEOL) layer 504 and the middle-end-of-line (MEOL) layer 502 is etched. In some embodiments, the isolation region 400 between the semiconductor structures 300 may also be removed during etching. That is, since the etching targets the dielectric materials of the back-end-of-line (BEOL) layer 504 and the middle-end-of-line (MEOL) layer 502, the exposed isolation feature 400 is also removed. The front-end-of-line (FEOL) layer 408 feature including the semiconductor structure 300, the gate structure 402 and the source / drain feature 404 formed thereon is exposed in the opening 602. The opening 602 may be formed by a suitable etching process. The etching process may include dry etching, wet etching, active ion etching (RIE) and / or other suitable processes. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (such as CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (such as Cl2, CHCl3, CCl4 and / or BC l3 ), bromine-containing gases (such as HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof. For example, the wet etching process may include etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia water; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants. In some embodiments, multiple etching processes are performed. In one embodiment, the etching of opening 602 is an oxide targeting etch.

[0088] In some embodiments, the opening 602 is approximately circular in a top view. In some embodiments, the opening 602 is elliptical. In some embodiments, the opening 602 is rectangular (including square) in a top view. These shapes are merely exemplary and other shapes are possible, including, for example, an octagon. In some embodiments, the shape and / or size of the opening 602 is substantially the same as the via region 212 described above. In one embodiment, the height H1 of the opening 602 is approximately between 1.5 microns and 3 microns. In one embodiment, the height H1 is approximately 2 microns.

[0089] It should be noted that Figure 6 Two semiconductor structures 300 are exposed in the opening 602. This is only exemplary and is not limited to the claims. Any number of semiconductor structures 300 can be exposed in the opening 602. It should also be noted that if Figure 6 As shown in (left), the opening 602 exposes the sidewalls of the semiconductor structure 300. However, this is also exemplary, and other alignment methods of the sidewalls of the opening 602 may also be implemented. Figure 6 As shown, the opening 602 has opposing sidewalls that intersect the midpoint of the semiconductor structure 302 , which is also merely exemplary and other alignments of the opening 602 may be implemented.

[0090] The method 100 includes step block 116, wherein the mask component is removed. Figure 7 , removing the mask component 506 ( Figure 6 In some embodiments, the masking member 506 may be removed by a suitable process (eg, ashing). In some embodiments, ashing may be followed by a wet etching / cleaning process.

[0091] The method 100 includes step block 118, which includes depositing a spacer liner along the sidewalls of the opening of step block 114. Figure 8 In one embodiment, a spacer liner 802 is deposited. The spacer liner 802 can be deposited by atomic layer deposition (ALD) or other suitable deposition methods. In one embodiment, the spacer liner 802 is an oxide, such as silicon oxide. In other embodiments, the spacer liner 802 can include a dielectric material, such as another oxide, silicon nitride, silicon carbide, and / or other suitable materials. In one embodiment, the thickness of the spacer liner 802 is approximately between 150 and 300 nanometers (nm). In one embodiment, the thickness of the spacer liner 802 is less than 150 nanometers. Figure 8 As shown, in some embodiments, the deposition of the spacer layer 802 may be a compliant deposition.

[0092] The method 100 includes step block 120, wherein the liner layer deposited in step block 118 is etched. After etching, the spacer liner layer remains on the sidewalls of the via opening to provide protection. Fig. 9 In some embodiments, the spacer liner 802 is patterned to form a spacer liner 802' on the sidewalls of the opening 602. In some embodiments, the spacer liner 802' covers the sidewalls of the semiconductor structure 300 exposed by the opening 602. The etching of the spacer liner 802' may be anisotropic etching, such as dry plasma etching, wet etching and / or other suitable etching.

[0093] The method 100 includes step block 122, wherein the transistor features in the via region are removed by an etching process. Fig.10 , the gate structure 402 and the source / drain region 404 are removed. In some embodiments, the etching also removes a local semiconductor structure 300', such as the fin 304 on the crown structure 302. Therefore, the crown structure 302 may have a substantially planar upper surface. The etching may selectively etch the gate structure 402 and the source / drain region 404. Therefore, the spacer liner 802' may not be substantially etched. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. For example, the dry etching process may be performed with an oxygen-containing gas, a fluorine-containing gas (such as CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (such as Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (such as HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. For example, the wet etching process may include etching in a dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH), or other suitable wet etchants. In some embodiments, multiple etching processes are performed.

[0094] The method 100 includes step block 124, wherein another mask feature is formed on the BEOL structure on the substrate. The another mask feature may define a pattern substantially the same as the mask feature of step block 112. Fig.11AIn an example of a method of forming a mask component 1102 on a back-end-of-line (BEOL) layer 504, the mask component 1102 having an opening 1102A defining a location of a via relative to a substrate. The mask component 1102 may be a photoresist. In some embodiments, the mask component 1102 may also include a hard mask layer. In some embodiments, the size of the opening 1102A is approximately D, as described above. The mask component 1102 may be patterned using a suitable photolithography and etching process. In some embodiments, the mask component 1102 may be patterned using a photomask substantially the same as the mask component 506. The mask layer 1102 may include photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, titanium nitride, or other suitable material. The deposited mask layer is then subjected to a pre-exposure process, contact with radiation reflected from or transmitted through the photomask, a post-exposure bake process, and a development process to form a patterned mask layer having an opening aligned with the via to be formed.

[0095] Fig. 11B An apparatus 200 ′ is shown that is substantially similar to apparatus 200 . Fig. 11B The device 200' shows an opening 602 having sidewalls defined by an inter-layer dielectric (ILD) layer 502A and an inter-metal dielectric (IMD) layer 504A.

[0096] The method 100 includes step block 126, wherein a via opening is extended into the substrate by etching the substrate according to the pattern defined by the mask feature of step block 124. Fig.12 In the example of FIG. 2 , the substrate 202 of the device 200 has been etched to extend the opening 602 to the substrate to form an opening 1202. It should be noted that the bottom of the opening 1202 is non-planar because the substrate surface ( Fig.11A and Fig. 11B ) is also non-planar (due to the presence of semiconductor structure 300). That is, the bottom of opening 1202 includes a plurality of grooves corresponding to semiconductor structure 300. Etching can selectively etch substrate 202 (e.g., silicon) and leave spacer liner 802' substantially unetched. In some embodiments, the substrate is etched away by 25-100 microns (height H2). In one embodiment, height H2 is approximately 50 μm. The etching process can be a dry etching process (e.g., a reactive ion etching (RIE) process). In some cases, an exemplary dry etching process can be performed with an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (such as HBr), an iodine-containing gas, other suitable gases and / or plasmas, combinations thereof, and / or other suitable etching. The termination of etching can be controlled by time.

[0097] After etching the substrate 202 to form the opening 1202, an ashing process may be performed to remove the masking member 1102 from the substrate 202. After the ashing process, an additional wet etching / cleaning process may follow. And the device 200 may then be baked or annealed in a high temperature process.

[0098] The method 100 includes step block 128, wherein a through silicon via (TSV) is formed in the opening. In one embodiment, a liner layer is first deposited. Fig.13 In one embodiment, a liner 1302 is formed. In one embodiment, the liner 1302 is an oxide. A conductive material is formed on the liner. In some embodiments, a barrier or seed layer can be deposited on the liner 1302. And a block metallization layer is formed on the seed layer. Please refer to Fig.14 In the example of FIG. 1402 , a seed layer and a metallization layer are deposited to form a conductive layer 1402 .

[0099] In some embodiments, the liner 1302 is an oxide. In other embodiments, the liner 1302 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AlN), or a combination thereof. The layer 1302 may fill the groove at the bottom of the opening 1202. The metal layer 1402 may include copper (Cu), aluminum (Al), cobalt (Co), copper alloys, tantalum (Ta), titanium (Ti), tungsten (W), and / or other suitable materials. To form the via 1600, the liner 1302 is first deposited using PVD, CVD, MOCVD, ALD, or a combination thereof, as shown in the exemplary embodiment. Fig.11A and Fig. 11B As shown. Then, the metal filling layer 1402 is deposited using electroplating, PVD, CVD, electroless plating or a suitable method. In one embodiment, the metal filling layer 1402 is formed using electroplating. In this embodiment, the seed layer (of the metal filling layer 1402) can be deposited using PVD or a suitable process, including being located on the surface of the liner 1302. Then, the metal filling layer can be deposited on the seed layer using electroplating. In an embodiment using electroplating, the seed layer can include copper (Cu), titanium (Ti) or a combination thereof, and the metal filling layer can include copper (Cu). Similarly, the seed layer can be considered as part of the metal layer 1402.

[0100] After deposition, a planarization process may be performed to remove material from the upper surface of the device 200 to form the conductive vias. The planarization process may include chemical mechanical polishing (CMP) or other suitable etch-back processes. Fig.15 , the device 200 is planarized.

[0101] In order to complete the fabrication of the via hole, the semiconductor substrate 202 is thinned, for example, by chemical mechanical polishing or grinding, to expose the lower surface of the via hole. Fig.16 In the example of FIG. 1 , a portion of the substrate 202 is removed to form a thinned substrate 202 ′. The removal is continued to expose the via and the lower surface of the conductive material 1402. That is, the formed via 1600 now extends through the substrate 202 ′.

[0102] The method 100 continues to block 130 where further processing is performed. The method 100 may include forming additional conductive and / or insulating features on the substrate (front side or back side) connected to the TSV. It is noted that some front side processing may be performed before the substrate is thinned. Fig.17A , Fig. 17B In an embodiment, an insulating layer 1702A is formed on the back side of the device 200. The insulating layer may include silicon oxide, tetraethyl silicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In an embodiment, a conductive feature or interconnect layer 1702B is also formed on the back side of the substrate (which is connected to the via 1600). Exemplary metal materials for the interconnect layer 1702B may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), or a metal alloy (e.g., aluminum-copper alloy (Al-Cu)). Additional film layers may also be formed, such as passivation layers, bonding pads, external interconnects (e.g., solder balls, and the like).

[0103] Thus, method 100 and exemplary apparatus 200 illustrate embodiments for providing through silicon vias. In some embodiments, dishing is avoided because semiconductor structures or fins and associated transistor features are formed in the via region and subsequently removed after forming MEOL and BEOL features.

[0104] It should be noted that if Fig.17A and Fig. 17B In the illustrated devices 200, 200', the FEOL structures adjacent to the silicon vias may be dummy features. In some embodiments, the dummy features include the semiconductor structure 300, the gate structure 402, and the source / drain features 404. However, they are not electrically connected to the device. The dummy features are annotated with "A".

[0105] It should also be noted that if Fig.17AAs shown, a portion of the semiconductor structure 300 may remain adjacent to the via 1600. This may be provided by embodiments where the opening (e.g., opening 602) has sidewalls that sit on the semiconductor structure 300. In other embodiments, portions of the gate structure 402 and / or source / drain features 404 may remain on the remaining portion of the semiconductor structure 300. In some embodiments, no electrical connection is made to the device. The remaining features are annotated with a "B".

[0106] In an exemplary form, the present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a plurality of semiconductor structures extending from above a substrate. The method also includes forming a plurality of metal gates on the semiconductor structure and forming a multi-layer interconnect on the metal gate. A first etching process is performed to form a first opening extending through the multi-layer interconnect to expose a first metal gate structure in a metal gate on a first semiconductor structure in the semiconductor structure. A spacer liner is deposited on the sidewalls of the first opening. A second etching process is performed to remove the first metal gate structure. And a third etching process is performed to remove the first semiconductor structure and extend the first opening into the substrate to form an extended opening.

[0107] In a further embodiment, the method includes filling the extended opening with a conductive material. In some embodiments, the method includes thinning the substrate to expose a lower surface of the filled extended opening to form a substrate through-hole (TSV). In one embodiment, forming a plurality of semiconductor structures includes forming a first semiconductor structure into a crown structure having a plurality of fins extending from the crown structure. In one embodiment, forming a multi-layer interconnect on a metal gate includes forming a contact structure to a second metal gate structure in the metal gate, and forming a first metallization layer on the second metal gate structure and connected to the contact structure. In one embodiment, depositing a spacer liner on the sidewalls of the first opening includes: conformally depositing an oxide layer; and etching the oxide layer to expose the first metal gate structure.

[0108] In one embodiment, a second etching process is performed to remove the first metal gate structure, etching a portion of the first semiconductor structure. And in a further embodiment, the portion of the first semiconductor structure is a fin extending above the crown structure. In one embodiment, the extended opening has a non-planar lower surface, and the non-planar lower surface has a plurality of grooves. And in some embodiments, the above method includes depositing a dielectric barrier layer in the extended opening and filling the grooves.

[0109] In another exemplary form, the present disclosure provides an embodiment of a method for manufacturing a semiconductor structure. The method includes forming a front-end-of-line (FEOL) layer including a plurality of transistor features on a substrate; forming a middle-end-of-line (MEOL) layer including a plurality of contact features on the front-end-of-line (FEOL) layer; and forming a back-end-of-line (BEOL) layer including a plurality of metal lines and a plurality of vias on the middle-end (MEOL) layer. Etching an opening through the back-end-of-line (BEOL) layer and the middle-end (MEOL) layer. The opening is defined by a first mask component, the opening having a lower surface defined by the substrate. A spacer liner is deposited on a plurality of sidewalls of the opening. A second mask component is provided on the back-end-of-line (BEOL) layer, and the method includes etching the substrate in an area defined by the second mask component to extend the opening into the substrate. Filling the extended opening with a conductive material.

[0110] In another embodiment, the first masking member is removed before depositing the spacer liner. In one embodiment, a dummy transistor feature is exposed at the lower surface; and the spacer liner is deposited on the dummy transistor feature. In a further embodiment, after forming the opening and before providing the second masking member and etching the substrate, another etching process is performed to remove the dummy transistor feature. In one embodiment, the dummy transistor feature is a gate structure disposed on a fin. In one embodiment, the above method also includes thinning the substrate to expose a lower surface of the filled extended opening.

[0111] In another exemplary form, the present disclosure provides a semiconductor structure. The structure includes a substrate; a plurality of semiconductor structures extending above the substrate; a multi-layer interconnect (MLI) disposed above the substrate and the semiconductor structure; and a substrate via extending vertically through the substrate and the multi-layer interconnect (MLI). The semiconductor structure includes a first semiconductor structure having a first metal gate disposed thereon and a second semiconductor structure having a second metal gate disposed thereon. The multi-layer interconnect (MLI) is connected to the first metal gate, and the multi-layer interconnect (MLI) is not electrically connected to the second metal gate. A spacer liner is formed on a sidewall of the second semiconductor structure and is disposed between the sidewall and a first sidewall of the substrate via.

[0112] In another embodiment, the structure includes a third semiconductor structure adjacent to a second sidewall of the substrate via. The third semiconductor structure extends above the substrate, and the spacer liner is connected to an upper surface of the third semiconductor structure. In one embodiment, the second semiconductor structure is a crown structure having a plurality of fins extending from a base portion. And in another embodiment, the sidewall extends from a top of a fin of the fins, along the fin and along the base portion.

[0113] The above briefly describes the characteristic components of several embodiments of the utility model, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a base; A plurality of semiconductor structures extending above the substrate, wherein the plurality of semiconductor structures include a first semiconductor structure having a first metal gate disposed thereon and a second semiconductor structure having a second metal gate disposed thereon; a multi-layer interconnection disposed above the substrate and the plurality of semiconductor structures, wherein the multi-layer interconnection is connected to the first metal gate and the multi-layer interconnection is not electrically connected to the second metal gate; and A substrate via hole vertically extends through the substrate and the multi-layer interconnect, wherein a spacer liner is formed on a side wall of the second semiconductor structure and disposed between the side wall and a first side wall of the substrate via hole.

2. The semiconductor structure according to claim 1, wherein: A third semiconductor structure is adjacent to a second sidewall of the substrate through hole, wherein the third semiconductor structure extends above the substrate, and the spacer liner is connected to an upper surface of the third semiconductor structure.

3. The semiconductor structure according to claim 1, wherein: The second semiconductor structure is a crown structure having a plurality of fins extending from a base portion.

4. The semiconductor structure according to claim 3, characterized in that The side wall extends from a top of a fin among the plurality of fins, along the fin and along the base.

5. A semiconductor structure, characterized in that: include: A plurality of semiconductor structures extending from a front side of a substrate; A plurality of metal gates formed on the plurality of semiconductor structures; A multi-layer interconnect formed on the plurality of metal gates; as well as A substrate via passes through the multi-layer interconnect and the plurality of semiconductor structures and extends to the substrate.

6. The semiconductor structure according to claim 5, characterized in that Also included is a conductive feature formed on a back side of the substrate and connected to the substrate via.

7. The semiconductor structure according to claim 5, characterized in that A first semiconductor structure among the plurality of semiconductor structures located outside the substrate via has a crown structure, and a plurality of fins extend from the crown structure.

8. The semiconductor structure according to any one of claims 5, 6 or 7, characterized in that: The substrate via hole comprises: a metal filling layer; and A liner is formed on two opposite side walls of the metal filling layer.

9. The semiconductor structure according to claim 8, characterized in that A spacer liner is also included, extending through the multi-layer interconnection line and being separated from the metal filling layer by the liner.

10. The semiconductor structure according to claim 9, wherein: The height of the spacer lining is smaller than the height of the lining.

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