Wafer

Abstract

The utility model provides a wafer, relates to the technical field of chip detection, and aims to quickly test the electrical characteristics of the wafer. The wafer comprises a plurality of exposure units, each exposure unit comprises a plurality of manufacturing units arranged in an array, the plurality of exposure units at least comprise a plurality of first exposure units, and in the first exposure units, any row of manufacturing units are to-be-tested manufacturing units or non-to-be-tested manufacturing units, or any row of manufacturing units are to-be-tested manufacturing units or non-to-be-tested manufacturing units; any column of manufacturing units are to-be-tested manufacturing units or non-to-be-tested manufacturing units, and the to-be-tested manufacturing units comprise at least one test bonding pad.

Description

Technical Field

[0001] The present disclosure relates to the field of chip detection technology, and in particular to a wafer. Background Art

[0002] Semiconductor tape-out is a key step in the design and manufacturing of integrated circuits, and refers to the process of converting a complete chip design into a physical chip.

[0003] After tape-out, the wafer will also undergo an electrical characteristics (chip probing, CP) test. The CP test measures the electrical parameters on each manufacturing unit by contacting the test pads on the surface of the wafer with the probes of a test device (such as a needle card).

[0004] However, the existing single-station test efficiency is too low, and multi-station testing often causes the probes on the needle card to pierce non-test areas, resulting in sticking needles, dirty chips, and large test errors. Utility Model Content

[0005] The embodiments of the present disclosure provide a wafer, aiming to enable rapid electrical characteristic testing of the wafer.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] A wafer is provided. The wafer includes a plurality of exposure units, and the exposure units include a plurality of manufacturing units arranged in an array. The plurality of exposure units include at least a plurality of first exposure units, and in the first exposure units, any row of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested, or any column of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested. The manufacturing unit to be tested includes at least one test pad.

[0008] The wafer provided by the above embodiment of the present disclosure includes at least a plurality of first exposure units, and the electrical characteristics test is to detect a plurality of manufacturing units to be tested in the wafer exposure unit. Since any row of manufacturing units in the first exposure unit are all manufacturing units to be tested or are all non-manufacturing units to be tested, or any column of manufacturing units are all manufacturing units to be tested or are all non-manufacturing units to be tested, when a row or a column of manufacturing units in the first exposure unit are all manufacturing units to be tested, a multi-station test is performed, and when a row or a column of manufacturing units in the first exposure unit are all non-manufacturing units to be tested, the skipping path of the needle card is set according to the row or column, and the non-manufacturing units to be tested are skipped to detect the manufacturing units to be tested, and the electrical characteristics are detected by piercing the test pad with a probe. The above means make it easier to design the travel route of the needle card, and the moving route of the needle card is more scientific, and the area that does not need to be tested can be quickly skipped, thereby improving the detection efficiency. And since a row or a column of the first exposure unit are either all manufacturing units to be tested or are all non-manufacturing units to be tested, the regular arrangement method can effectively prevent the needle card from being inserted into the non-manufacturing unit to be tested, thereby reducing the wear of the equipment.

[0009] In some embodiments, the plurality of exposure units further include a plurality of second exposure units. The plurality of manufacturing units in the first exposure unit are all manufacturing units to be tested, and the plurality of manufacturing units in the second exposure unit are all manufacturing units not to be tested.

[0010] In some embodiments, the manufacturing unit to be tested includes: a substrate, a functional film layer group disposed on one side of the substrate, an insulating layer disposed on a side of the functional film layer group away from the substrate, and at least one test pad disposed on a side of the insulating layer away from the substrate. The insulating layer includes at least one via. The test pad includes a first conductive layer, and the first conductive layer is connected to the functional film layer group through at least one via.

[0011] In some embodiments, the first conductive layer includes at least one contact pattern. The test pad also includes at least one dielectric layer disposed on a side of the first conductive layer away from the substrate, the dielectric layer includes at least one slot, and the at least one slot exposes at least one contact pattern of the first conductive layer.

[0012] In some embodiments, at least one dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is farther away from the substrate than the first dielectric layer. The first dielectric layer includes at least one first slot, and the at least one first slot respectively exposes at least one contact pattern. The second dielectric layer includes at least one second slot, and the at least one second slot is respectively connected with the at least one first slot, and the boundary of the corresponding second slot is located outside the boundary of the first slot.

[0013] In some embodiments, the manufacturing unit to be tested further includes: a second conductive layer disposed between the functional film layer group and the insulating layer, and the second conductive layer contacts the functional film layer group. The second conductive layer includes at least one conductive pattern, and the contact pattern is connected to the conductive pattern through a via.

[0014] In some embodiments, the non-to-be-tested manufacturing unit includes a substrate and a functional film group disposed on one side of the substrate.

[0015] In some embodiments, the plurality of exposure units are all first exposure units. The plurality of manufacturing units in the first exposure unit include a plurality of manufacturing units to be tested and a plurality of manufacturing units not to be tested. At least two adjacent rows of manufacturing units are all manufacturing units to be tested, and the remaining rows of manufacturing units are all manufacturing units not to be tested. Alternatively, at least two adjacent columns of manufacturing units are all manufacturing units to be tested, and the remaining columns of manufacturing units are all manufacturing units not to be tested.

[0016] In some embodiments, the first exposure unit includes a first edge region, a first center region, and a second edge region arranged in sequence along the row direction. At least two adjacent rows of manufacturing units are manufacturing units to be tested and are located in the first center region, and the remaining rows of manufacturing units are manufacturing units not to be tested and are located in the first edge region and the second edge region.

[0017] In some embodiments, the first exposure unit includes a third edge region, a second center region, and a fourth edge region sequentially arranged along the column direction. At least two adjacent columns of manufacturing units are manufacturing units to be tested and are located in the second center region, and the remaining columns of manufacturing units are manufacturing units not to be tested and are located in the third edge region and the fourth edge region.

[0018] In some embodiments, the plurality of exposure units are all first exposure units. The plurality of manufacturing units in the first exposure unit are all manufacturing units to be tested, the manufacturing units to be tested include normal manufacturing units to be tested and virtual manufacturing units to be tested, the normal manufacturing units to be tested include at least one normal test pad, and the virtual manufacturing units to be tested include at least one virtual test pad. The size of the virtual test pad is smaller than the size of the normal test pad.

[0019] In some embodiments, the normal manufacturing unit to be tested includes: a substrate, a functional film layer group disposed on one side of the substrate, an insulating layer disposed on a side of the functional film layer group away from the substrate, and at least one normal test pad disposed on a side of the insulating layer away from the substrate, the insulating layer includes at least one via. The normal test pad includes a normal conductive layer, and the normal conductive layer is connected to the functional film layer group through at least one via.

[0020] In some embodiments, the virtual manufacturing unit to be tested includes a substrate, a functional film layer group arranged on one side of the substrate, an insulating layer arranged on a side of the functional film layer group away from the substrate, and at least one virtual test pad arranged on a side of the insulating layer away from the substrate, the virtual test pad includes a virtual conductive layer, and the virtual conductive layer is located in the same layer as the normal conductive layer.

[0021] In some embodiments, the normal conductive layer includes at least one normal contact pattern. The normal test pad also includes at least one dielectric layer disposed on a side of the normal conductive layer away from the substrate, the dielectric layer includes at least one groove, and the at least one groove respectively exposes at least one normal contact pattern of the normal conductive layer.

[0022] In some embodiments, at least one dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is farther away from the substrate than the first dielectric layer. The first dielectric layer includes at least one first slot, and the at least one first slot respectively exposes at least one normal contact pattern. The second dielectric layer includes at least one second slot, and the at least one second slot is respectively connected with the at least one first slot, and the boundary of the corresponding second slot is located outside the boundary of the first slot.

[0023] In some embodiments, the normal manufacturing unit to be tested further includes: a second conductive layer disposed between the functional film layer group and the insulating layer, and the second conductive layer contacts the functional film layer group. The second conductive layer includes at least one conductive pattern, and the normal contact pattern is connected to the conductive pattern through a via.

[0024] In some embodiments, the virtual conductive layer includes at least one virtual contact pattern, the virtual test pad also includes at least one dielectric layer arranged on the side of the virtual conductive layer away from the substrate, the dielectric layer includes at least one groove, and the at least one groove respectively exposes at least one virtual contact pattern of the virtual conductive layer.

[0025] In some embodiments, at least one dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is farther away from the substrate than the first dielectric layer. The first dielectric layer includes at least one first slot, and the at least one first slot respectively exposes at least one virtual contact pattern. The second dielectric layer includes at least one second slot, and the at least one second slot respectively penetrates the at least one first slot, and the boundary of the corresponding second slot is located outside the boundary of the first slot. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0027] Figure 1 A schematic diagram of a wafer in the prior art;

[0028] Figure 2 It is a schematic diagram of a manufacturing unit inside an exposure unit in the prior art when a multi-station needle card is tested;

[0029] Figure 3 is a schematic diagram of the composition of a wafer according to some embodiments;

[0030] Figure 4 is a schematic diagram of a first exposure unit according to some embodiments;

[0031] Figure 5 is a schematic diagram of a second exposure unit according to some embodiments;

[0032] Figure 6 is a composition diagram of a manufacturing unit to be inspected according to some embodiments;

[0033] Figure 7 is a composition diagram of another manufacturing unit to be inspected according to some embodiments;

[0034] Figure 8 is a composition diagram of a non-to-be-tested manufacturing unit according to some embodiments;

[0035] Fig. 9 is a schematic diagram of another first exposure unit according to some embodiments;

[0036] Fig.10 is a schematic diagram of another first exposure unit according to some embodiments;

[0037] Fig.11 is a schematic diagram of another first exposure unit according to some embodiments;

[0038] Fig.12 is a schematic diagram of another first exposure unit according to some embodiments;

[0039] Fig.13 is a schematic diagram of another first exposure unit according to some embodiments;

[0040] Fig.14 is a schematic diagram of a normal manufacturing unit to be tested according to some embodiments;

[0041] Fig.15 is a schematic diagram of another normal manufacturing unit to be tested according to some embodiments;

[0042] Fig.16 is a schematic diagram of a virtual manufacturing unit to be tested according to some embodiments;

[0043] Fig.17 is a schematic diagram of another virtual manufacturing unit under test according to some embodiments. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0045] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0050] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0052] Unless otherwise defined, all scientific and technological terms used herein have the same meanings as those known to those of ordinary skill in the art. In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which may represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, wherein A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c may be single or multiple.

[0053] In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0054] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0055] In the process of semiconductor manufacturing, wafers need to go through multiple processes such as photolithography and etching to form circuit patterns. In the process of forming circuit patterns, the uniformity and accuracy of the manufacturing process are very important. In order to detect the effects of these processes, manufacturers will place some patterns or structures on the wafer for process monitoring.

[0056] After tape-out, the wafer will also be subjected to electrical characteristics (chip probing, CP) testing. The CP test uses the probes of the test equipment (such as a needle card) to contact the test pads on the surface of the wafer to measure the electrical parameters of each manufacturing unit to be tested, such as voltage, current, power consumption, etc., to ensure that the electrical performance of each manufacturing unit to be tested meets the design rules after physical manufacturing. There are usually two methods for CP testing. One is multi-station testing, and the other is single-station testing.

[0057] Multi-station testing means that on a wafer, the test equipment (such as a probe card) can test multiple manufacturing units (stations) at the same time. For example, Figure 1 and Figure 2 As shown, Figure 1 is a schematic diagram of a wafer in the prior art, Figure 2 This is a schematic diagram of a manufacturing unit inside an exposure unit in the prior art when a multi-station needle card is tested. Figure 1 , Figure 1 The wafer 100 is a circular semiconductor material, which is the substrate that carries all circuits and components in the entire semiconductor manufacturing process. On the wafer 100, thousands of micro devices are formed through photolithography, etching, doping and other process steps, and these micro devices are cut into independent chips.

[0058] A small square on the wafer 100 is an exposure unit 1, which represents the area exposed each time during the photolithography process. The photolithography machine transfers the circuit pattern to the surface of the wafer 100 through a mask, and the wafer 100 usually needs to be repeatedly exposed multiple times to cover the entire surface of the wafer 100. Since each layer of circuits may require different patterns, the photolithography machine will repeatedly expose on the same wafer 100, gradually building a multi-layer circuit structure on each exposure unit 1 of the wafer 100 to ensure that all devices are correctly exposed and form the required circuit pattern. Each exposure unit 1 is not only an exposure area, it also determines the processing area in subsequent processing.

[0059] Figure 2 This shows the manufacturing unit 2 inside an exposure unit 1 during testing with a multi-station needle card. Figure 2 In each exposure unit 1, the wafer is further divided into smaller rectangular areas, which are called manufacturing units 2. When the pattern on the mask is projected onto the wafer, each manufacturing unit 2 cuts off a part of the entire mask pattern, and this part is the final circuit pattern of the manufacturing unit 2. Each manufacturing unit 2 is an independent integrated circuit unit, which is eventually cut into a separate chip. Each manufacturing unit 2 contains one or more micro devices, such as processors, storage units, etc., and each manufacturing unit 2 is divided by cutting lanes. The existence of cutting lanes ensures that the key circuits and structures in the manufacturing unit 2 will not be damaged when the wafer is cut. These channels are usually arranged in non-functional areas to ensure that the effective utilization of each wafer is maximized.

[0060] Figure 2 The manufacturing unit 2 shown in the figure includes two types, one is a manufacturing unit to be tested 21 that needs to be tested for electrical characteristics, and the other is a manufacturing unit not to be tested 22 that does not need to be tested for electrical characteristics. The manufacturing unit to be tested is provided with a test pad 3, and the manufacturing unit not to be tested 22 is provided with a process monitoring pattern 4. The probe of the needle card is inserted into the manufacturing unit to show a circular hole shape as shown in the figure.

[0061] The probe of the needle card contacts the test pad 3, and can measure the voltage, current or other electrical parameters to ensure that the performance of the device meets the design requirements under normal working conditions. The process monitoring graph 4 helps engineers monitor the process parameters in real time during the manufacturing process to ensure the manufacturing quality of the wafer.

[0062] Since the distribution of the manufacturing units to be tested 21 and the manufacturing units not to be tested 22 is relatively disordered, and the probes of the needle card are arranged in rows or columns, the test probes of the needle card may pierce the pattern 4 of the process monitoring, for example Figure 2 The exposure unit 1 shown in the figure is on the non-test manufacturing unit 22 in the upper left corner, not on the test pad 3. When the needle card is stuck in the non-test area, that is, the area where the non-test pad 3 is located, for example, it is stuck in the dielectric film layer (organic matter, silicon oxide or silicon nitride, etc.), resulting in needle sticking and dirty debris, which in turn leads to test errors. Frequent contact of the needle card with the non-test area will accelerate the wear of the needle card, increase the frequency of equipment maintenance and replacement, and lead to an increase in production costs.

[0063] Single-station testing refers to testing one manufacturing unit to be tested at a time. Although single-station testing can accurately test each manufacturing unit to be tested on the wafer, since only one manufacturing unit to be tested can be tested at a time, the testing time is significantly increased and the efficiency is low.

[0064] In view of this, the present application provides a wafer, the wafer includes a plurality of exposure units, and the exposure units include a plurality of manufacturing units arranged in an array. The plurality of exposure units include at least a plurality of first exposure units, and in the first exposure units, any row of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested, or any column of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested. The manufacturing unit to be tested includes at least one test pad.

[0065] The test pad is a key part for electrical testing. The test pad in the manufacturing unit to be tested provides a contact point with the needle card, so that the needle card can measure the electrical parameters of the manufacturing unit. The wafer provided in the embodiment of the present application includes at least a plurality of first exposure units. The manufacturing units to be tested or the manufacturing units not to be tested in the first exposure units are arranged in rows or columns, which can optimize the subsequent electrical testing process, that is, the process of inserting the probe for detection. The needle card can quickly identify the rows or columns to be tested and skip the manufacturing units not to be tested.

[0066] For example, when a row or a column of manufacturing units in the first exposure unit are all manufacturing units to be tested, multi-station testing is performed, and the probes of the needle card are directly inserted into the test according to the entire row or column; when a row or a column of manufacturing units in the first exposure unit are all manufacturing units not to be tested, the skip path of the needle card is set according to the row or column, and the manufacturing units not to be tested are skipped to detect the manufacturing units to be tested.

[0067] The row or column-based division method provided in the embodiment of the present application can simplify the design of the test path, which is essentially to plan the arrangement of the manufacturing units to be tested and the manufacturing units not to be tested. Originally, the needle card needed to use the size of a manufacturing unit as a step to plan the route, but with the wafer provided in the embodiment of the present application, the arrangement of the manufacturing units to be tested and the manufacturing units not to be tested is more regular, so the step of the needle card is larger, for example, the size of a row of manufacturing units, so the number of times the needle card moves is reduced, the movement route of the needle card is more scientific, and it can quickly skip the area that does not need to be tested, making the movement of the needle card more efficient and improving the detection efficiency. And because a row or a column of the first exposure unit is either a manufacturing unit to be tested or a manufacturing unit not to be tested, the regular arrangement method can effectively prevent the needle card from being inserted into the manufacturing unit not to be tested, reducing the wear of the equipment.

[0068] In some embodiments, for example, Figure 3 , Figure 4 as well as Figure 5 As shown, the plurality of exposure units include a plurality of second exposure units 12 in addition to the first exposure unit 11 .

[0069] Reference Figure 4 , the multiple manufacturing units in the first exposure unit 11 are all manufacturing units to be tested 21. Figure 5 , the multiple manufacturing units in the second exposure unit 12 are all non-test manufacturing units 22.

[0070] The fact that all the manufacturing units in the first exposure unit 11 are the manufacturing units 21 to be tested means that the needle card can plan the skip path with the size of one exposure unit as the preset step. When the needle card moves to the first exposure unit 11, there is no need to worry that the probe will pierce the non-test manufacturing unit 22. When the needle card moves to the second exposure unit 12, since all the manufacturing units in the second exposure unit 12 are non-test manufacturing units 22, they are skipped directly.

[0071] The centralized setting of the manufacturing unit to be tested 21 and the manufacturing unit not to be tested 22 allows for a larger step when setting the needle card skipping path, reduces the number of needle card movements, and thus makes the test route simpler, further shortening the test time. In addition, the second exposure unit 12 does not include the manufacturing unit to be tested, and does not require a test pad. The needle card can directly skip the entire second exposure unit 12 as a whole, so the probe will not contact the area, avoiding the problem of needle sticking caused by the probe piercing the non-metallic layer, thereby reducing the risk of needle card wear and dirty debris, greatly reducing the maintenance cost of the needle card while reducing the test error.

[0072] As a possible implementation, Figure 6As shown, the manufacturing unit to be tested 21 includes: a substrate 211, a functional film layer group 212 disposed on one side of the substrate 211, an insulating layer 213 disposed on a side of the functional film layer group 212 away from the substrate 211, and at least one test pad 214 disposed on a side of the insulating layer 213 away from the substrate 211. The insulating layer 213 includes at least one via 2131. The test pad 214 includes a first conductive layer 2141, and the first conductive layer 2141 is connected to the functional film layer group 212 through at least one via 2131.

[0073] Exemplarily, the functional film layer group 212 includes a buffer layer 2121, a barrier layer 2122, and a channel layer 2123 arranged in sequence in a direction away from the substrate. The insulating layer 213 is used for electrical isolation to prevent electrical interference between different functional film layers. The vias 2131 in the insulating layer 213 allow conductive connections to pass through the insulating layer 213. Since the test pad 214 includes a first conductive layer 2141, and the first conductive layer 2141 is connected to the functional film layer group 212 through at least one via 2131, when the probe is inserted into the first conductive layer 2141 (e.g. Figure 6 As shown by the arrow in FIG. 21 ), the external test circuit can be connected to the inside of the manufacturing unit to be tested through the via 2131.

[0074] In some embodiments, Figure 6 As shown, the first conductive layer 2141 includes at least one contact pattern. The test pad 214 also includes at least one dielectric layer 2142 disposed on a side of the first conductive layer 2141 away from the substrate 211, and the dielectric layer 2142 includes at least one groove 215, and the at least one groove 215 exposes at least one contact pattern of the first conductive layer 2141 respectively.

[0075] Figure 6 The first conductive layer 2141 in the embodiment includes two contact patterns, two vias 2131 and two test pads 214. The two contact patterns are respectively recorded as the first contact pattern 2141~1 and the second contact pattern 2141~2, the two vias 2131 are respectively recorded as the first via 2131~1 and the second via 2131~2, and the two test pads 214 are respectively recorded as the first test pad 214~1 and the second test pad 214~2.

[0076] The first contact pattern 2141~1 is connected to the functional film layer group 212 through the first via 2131~1. The second contact pattern 2141~2 is connected to the functional film layer group 212 through the second via 2131~2. Each slot 215 corresponds to a test pad 214, for example, the slot 215~1 corresponds to the first test pad 214~1, and the slot 215~2 corresponds to the second test pad 214~2. The slot 215~1 exposes the first contact pattern 2141~1 of the first conductive layer 2141, and the slot 215~2 exposes the second contact pattern 2141~2 of the first conductive layer 2141. The probe of the needle card can pass through the slot 215~1 and insert into the first contact pattern 2141~1 of the first conductive layer 2141. Since the first contact pattern 2141~1 is connected to the functional film layer group 212 through the first via 2131~1, the electrical characteristics of the manufacturing unit to be tested can be detected.

[0077] As a possible implementation, Figure 7 As shown, at least one dielectric layer includes a first dielectric layer 2143 and a second dielectric layer 2144, and the second dielectric layer 2144 is farther away from the substrate 211 than the first dielectric layer 2143. The first dielectric layer 2143 includes at least one first slot 2151, and at least one first slot 2151 exposes at least one contact pattern respectively. For example, the first slot 2151~1 exposes the first contact pattern 2141~1. The second dielectric layer 2144 includes at least one second slot 2152, and at least one second slot 2152 is connected with at least one first slot 2151 respectively, for example, the second slot 2152~1 is connected with the first slot 2151~1, and the probe can be inserted into the contact pattern through the second slot 2152 and the first slot 2151 in sequence. The boundary of the corresponding second slot 2152 is located outside the boundary of the first slot 2151, which means that the size of the second slot 2152 is larger than the size of the first slot 2151.

[0078] The boundary of the second slot 2152 is located outside the boundary of the first slot 2151, increasing the contact area between the test pad and the external test equipment. This allows the test equipment, such as the pin card, to establish an electrical connection with the pad more stably and accurately when in contact, thereby reducing the test error caused by poor contact. The boundary of the second slot 2152 is larger than the boundary of the first slot 2151, which means that the electrical signal will not be excessively disturbed when passing through the slot, thereby improving the integrity and transmission efficiency of the signal. The larger slot boundary can reduce the resistance or capacitance effect caused by the narrow signal path, which helps to improve the accuracy of the test.

[0079] In some embodiments, Figure 7As shown, the manufacturing unit to be tested further includes: a second conductive layer 2130 disposed between the functional film layer group 212 and the insulating layer 213, and the second conductive layer 2130 contacts the functional film layer group 212. The second conductive layer 2130 includes at least one conductive pattern, and the contact pattern is connected to the conductive pattern through a via 2131.

[0080] Figure 7 , three conductive patterns are shown, namely, a drain 2133, a gate 2132, and a source 2134. The source 2134 is connected to the first contact pattern 2141-1 through the first via 2131-1, and the drain 2133 is connected to the second contact pattern 2141-2 through the second via 2131-2.

[0081] The manufacturing unit in the second exposure unit is a non-test manufacturing unit, for example, Figure 8 As shown, the non-under-test manufacturing unit includes a substrate 211 and a functional film group 212 disposed on one side of the substrate 211. As a possible implementation, the functional film layer group 212 includes a buffer layer 2121, a barrier layer 2122 and a channel layer 2123 sequentially disposed in a direction away from the substrate.

[0082] In some other embodiments, the plurality of exposure units are all first exposure units. The plurality of manufacturing units in the first exposure unit include a plurality of manufacturing units to be tested and a plurality of manufacturing units not to be tested. At least two adjacent rows of manufacturing units are all manufacturing units to be tested, and the remaining rows of manufacturing units are all manufacturing units not to be tested. Alternatively, at least two adjacent columns of manufacturing units are all manufacturing units to be tested, and the remaining columns of manufacturing units are all manufacturing units not to be tested.

[0083] Different from the aforementioned (first type) embodiment, in the second type of embodiment, the first exposure units are no longer all manufacturing units to be tested, but the arrangement of manufacturing units to be tested and manufacturing units not to be tested has a certain regularity. By setting at least two adjacent rows or columns as manufacturing units to be tested, the area to be tested can be quickly identified, and the test can be concentrated on the manufacturing units to be tested. Since the manufacturing units to be tested are concentrated in adjacent rows or columns, the needle card can move along a regular path without frequent switching in different areas. The step size setting of the needle card skipping the path only needs to be the size occupied by a row or a column of manufacturing units, which reduces unnecessary jumps and makes the entire test process more concise and efficient.

[0084] In addition, by clearly dividing the non-tested manufacturing units and the tested manufacturing units, and arranging the tested manufacturing units in a centralized manner, the contact between the probe card and the non-tested area can be reduced, effectively reducing the wear of the equipment and extending the service life of the equipment. And due to the regular distribution of the non-tested manufacturing units and the tested manufacturing units, the occurrence of the probe contacting the functional film layer group of the non-tested manufacturing units is greatly reduced, and the measurement accuracy is also improved.

[0085] As a possible implementation, Fig. 9 The first exposure unit 11 includes a first edge region 20, a first center region 30, and a second edge region 40 arranged in sequence along the row direction. At least two adjacent rows of manufacturing units are manufacturing units to be tested 21 located in the first center region 20, and the remaining rows of manufacturing units are manufacturing units not to be tested 22 located in the first edge region 20 and the second edge region 40.

[0086] Since the manufacturing units to be tested are concentrated in the first central area 30 of the wafer, the testing equipment (such as a needle card) can focus on this area for testing, while the manufacturing units not to be tested are arranged in the edge areas, the first edge area 20 and the second edge area 40, so the testers can more easily distinguish which areas need to be tested and which areas can be skipped during the production and testing process.

[0087] For example, comparison Figure 2 and Fig. 9 , in the test Figure 2 When the exposure unit is shown, the probe card is configured to detect two manufacturing units 2 at the same time, that is, the probe of the probe card can be inserted into the test pads 3 of two different manufacturing units 21 to be tested at one time. The moving path of the probe card is configured to move from the upper left corner of the exposure unit to the lower right corner row by row. Figure 2 For example, the probe card first needs to skip the first non-test manufacturing unit 22 located in the upper left corner of the exposure unit, and the probes are simultaneously inserted into the test pads 3 of the two middle manufacturing units 21 to be tested in the first row. Then the probe card skips the last non-test manufacturing unit 22 in the first row and moves to the second row of the exposure unit.

[0088] The second row of the exposure unit and the third row of the exposure unit are both manufacturing units 21 to be tested, but due to the distribution pattern of the manufacturing units 21 to be tested and the manufacturing units 22 not to be tested on the exposure unit, the needle card is set to be able to detect two manufacturing units 2 at the same time, so it needs to move four times to complete the detection of the manufacturing units 21 to be tested in the second and third rows. The test of the last row is the same as that of the first row, so the needle card needs to perform four skip steps in the end, and needs to move 6 times (2*6) to complete the measurement of the 12 manufacturing units 21 to be tested in the figure.

[0089] Reference Fig. 9 , in the test Fig. 9 When the exposure unit is shown, the probe card is configured to detect twelve manufacturing units at the same time, that is, the probe of the probe card can be inserted into the test pads 3 of twelve different manufacturing units 21 to be tested at one time. The moving path of the probe card is still configured to move from the upper left corner of the exposure unit to the lower right corner row by row. Figure 2 For example, since all the test units in the first edge area 20, that is, the first row of the exposure area, are not the manufacturing units 22 to be tested, the needle card first needs to skip the first row of the exposure units, move to the second row, and then test the twelve manufacturing units 21 to be tested in the second row, the third row, and the fourth row at one time. The probes of the needle card are respectively inserted into the test pads of the twelve manufacturing units 21 to be tested at the same time. Then the needle card moves to the last row, that is, the second edge area 40. Since all the manufacturing units in the second edge area 40 are not the manufacturing units 22 to be tested, the needle card skips the entire row.

[0090] In summary, the needle card originally needed to execute four skip steps and move 6 times (2*6) to complete the measurement of the 12 manufacturing units 21 to be tested in the figure. Now it only needs to execute two skip steps and move one to complete the measurement of the 12 manufacturing units 21 to be tested in the figure.

[0091] This centralized design eliminates the need for test equipment to frequently jump across the entire range of the wafer with the size of a manufacturing unit as the size of the skip path. The step size of the skip path is increased from the size of a single manufacturing unit to the size of a row of manufacturing units, reducing the number of jumps of the pin card, thereby reducing the complexity of the test path. The pin card can move along a fixed path, reducing unnecessary jumps and complex path planning during the test process. This helps the test equipment remain efficient and accurate every time it moves. It shortens the test time and greatly improves the test efficiency.

[0092] The non-test manufacturing units 22 are placed in the edge areas to avoid unnecessary wear caused by the needle card probe penetrating these areas. The test equipment does not contact the non-test area, which can reduce the wear and tear of the equipment and the generation of dirty chips, thereby reducing the equipment maintenance cost. In addition, arranging the test manufacturing units 21 in the first central area 30 can effectively improve the space utilization of the wafer. For large-scale production, the test manufacturing units 21 in the first central area 30 are arranged more compactly, which helps to maximize the area of ​​the test area without affecting the edge functional area and improve production efficiency.

[0093] In some embodiments, Fig.10As shown, the first exposure unit includes a third edge region 50, a second center region 70, and a fourth edge region 60 arranged in sequence along the column direction. At least two adjacent columns of manufacturing units are manufacturing units to be tested 21 located in the second center region 70, and the remaining columns of manufacturing units are manufacturing units not to be tested 22 located in the third edge region 50 and the fourth edge region 60.

[0094] The third edge area 50 and the fourth edge area 60 are essentially the same as the first edge area 20 and the second edge area 40 mentioned above, and are both concentrated areas of the non-test manufacturing units 22. The difference is that the former is based on the row direction to centrally arrange the manufacturing units 21 to be tested and the non-test manufacturing units 22, and the latter is based on the column direction to arrange the manufacturing units 21 to be tested and the non-test manufacturing units 22. The needle card skipping path of the former is stepped by the size of a row of manufacturing units, and the needle card skipping path of the latter is stepped by the size of a column of manufacturing units. The needle card moving path of the former is horizontal row-by-row movement, and the needle card moving path of the latter is vertical column-by-column movement. The arrangement in the row direction is more suitable for the situation where the circuit characteristics are arranged along the row in some wafer designs. The test equipment can test multiple manufacturing units with similar functions or structures along the row. The arrangement in the column direction is more suitable for the situation where the circuit characteristics are arranged along the column, and the test equipment can test multiple manufacturing units with similar functions or structures along the column. Selecting a suitable arrangement method according to the size of the exposure unit and the number of manufacturing units therein can further optimize the test efficiency.

[0095] As a possible implementation, the arrangement of the manufacturing units to be tested and the manufacturing units not to be tested on the first exposure unit may also be as follows: Fig.11 or Fig.12 See Fig.11 The non-tested manufacturing units 22 are arranged in a row and concentrated in the left area of ​​the first exposure unit, and the tested manufacturing units 21 are arranged in a row and concentrated in the right area of ​​the first exposure unit. Fig.12 The non-tested manufacturing units 22 are arranged in a row and concentrated in the lower area of ​​the first exposure unit, and the tested manufacturing units 21 are arranged in a row and concentrated in the upper area of ​​the first exposure unit.

[0096] It should be understood that the non-tested manufacturing units 22 may also be arranged in a row and concentrated in the right area of ​​the first exposure unit, and the tested manufacturing units 21 may be arranged in a row and concentrated in the left area of ​​the first exposure unit. The non-tested manufacturing units 22 may be arranged in a row and concentrated in the upper area of ​​the first exposure unit, and the tested manufacturing units 21 may be arranged in a row and concentrated in the lower area of ​​the first exposure unit.

[0097] Regardless of the specific arrangement of the manufacturing units to be tested and the manufacturing units not to be tested, as long as the manufacturing units to be tested and the manufacturing units not to be tested are arranged in a concentrated manner in rows or columns, the increase in the unit step setting of the needle card skipping path can be ensured, and the movement route of the needle card can be simplified, thereby shortening the detection time and improving the detection efficiency.

[0098] In some other embodiments (embodiments of the third type), for example, Fig.13 As shown, the multiple exposure units are all first exposure units 11. The multiple manufacturing units in the first exposure unit 11 are all manufacturing units to be tested, and the manufacturing units to be tested include normal manufacturing units to be tested 24 and virtual manufacturing units to be tested 25. The normal manufacturing unit to be tested 24 includes at least one normal test pad 241, and the virtual manufacturing unit to be tested 25 includes at least one virtual test pad 251. The size of the virtual test pad 251 is smaller than the size of the normal test pad 241. A normal manufacturing unit to be tested 24 in the figure includes three normal test pads 241, and the virtual manufacturing unit to be tested 25 includes three virtual test pads 251.

[0099] The multiple manufacturing units in the first exposure unit 11 are divided into normal manufacturing units to be tested 24 and virtual manufacturing units to be tested 25, both of which belong to the manufacturing units to be tested, which means that the needle card does not need to skip the processing, and the probe of the needle card can be directly inserted into all the manufacturing units 25 on the first exposure unit 11. The probe is inserted into the normal test pad 241 on the normal manufacturing unit to be tested 24, and the probe is also inserted into the virtual test pad 251 on the virtual manufacturing unit to be tested 25. The virtual manufacturing unit to be tested 25 is a manufacturing unit with a pattern for process monitoring, which belongs to a non-manufacturing unit to be tested in the first type of embodiment and the second type of embodiment. The virtual manufacturing unit to be tested 25 usually does not contain key circuits, but by adding a virtual test pad 251, the probe is prevented from piercing the non-metallic layer, thereby avoiding damage and wear of the probe. Since a virtual test pad 251 is added to the virtual manufacturing unit 25 to be tested, even if the probe is inserted into all the manufacturing units on the first exposure unit 11, the probe will not pierce the non-metallic layer on the virtual manufacturing unit 25 to be tested, but will be inserted into the metal layer of the virtual test pad 251.

[0100] By designing the virtual manufacturing unit 25 to include a virtual test pad 251, the design effectively solves the problem of the probe penetrating the non-metallic layer during the wafer test process, simplifies the test path of the needle card, reduces the test time and equipment wear, and prevents the generation of dirty chips. This not only improves the test efficiency, but also extends the service life of the test equipment and improves the accuracy and process monitoring capabilities of the entire manufacturing process.

[0101] The virtual test pad 251 of the virtual manufacturing unit to be tested 25 is relatively small, which means that physical space is saved on the wafer. This helps to optimize the arrangement of manufacturing units on the wafer and improve space utilization. By reducing the size of the virtual test pad 251, more physical space can be provided for other key manufacturing units (such as the normal manufacturing unit to be tested 24), thereby improving the density and functional layout of the manufacturing units on the wafer. Especially in large-scale production, reducing the size of the test pads of manufacturing units that do not require complex testing can further reduce wafer waste and increase the chip yield of each wafer.

[0102] In some embodiments, Fig.14 As shown, the normal manufacturing unit to be tested includes: a substrate 211, a functional film layer group 212 arranged on one side of the substrate 211, an insulating layer 213 arranged on a side of the functional film layer group 212 away from the substrate 211, and at least one normal test pad 241 arranged on a side of the insulating layer 213 away from the substrate 211, and the insulating layer 213 includes at least one via 2131. The normal test pad 241 includes a normal conductive layer 2411, and the normal conductive layer 2411 is connected to the functional film layer group 212 through at least one via 2131.

[0103] The normal test pad 241 is connected to the functional film layer group 212 through the via 2131, and the functional film layer group 212 is the core part of the chip circuit, which is responsible for the transmission and processing of electrical signals. Through this structure, it is ensured that the normal conductive layer 2511 can be stably electrically connected to the functional film layer group 212, ensuring the smooth transmission of signals.

[0104] Fig.14 2 shows two normal test pads 241, two vias 2131 and two normal conductive layers 2411, and the two normal test pads 241 are respectively recorded as a first normal test pad 241~1 and a second normal test pad 241~2. The two vias 2131 are respectively recorded as a first via 2131~1 and a second via 2131~2.

[0105] The via 2131 provides a good electrical connection path, so that the test equipment (such as a pin card) can make reliable electrical contact with the functional film layer group 212 through the normal test pad 241. This connection method greatly improves the accuracy and reliability of electrical testing and ensures the accuracy of test results.

[0106] By setting the insulating layer 213 on the side of the functional film layer group 212 away from the substrate 211, a protective layer is added between the normal test pad 241 and the functional film layer group 212. This insulating layer 213 not only effectively prevents external electrical interference and ensures the signal integrity of the functional film layer group 212, but also structurally protects the functional film layer group 212 from mechanical damage. The existence of the insulating layer 213 ensures electrical isolation between the normal test pad 241 and the functional film layer group 212, avoids electrical noise or signal interference that may be caused during the test, and thus improves the accuracy of the electrical test.

[0107] In some embodiments, Fig.14 As shown, the normal conductive layer 2411 includes at least one normal contact pattern. The normal test pad 241 also includes at least one dielectric layer 2142 disposed on a side of the normal conductive layer 2411 away from the substrate 211, and the dielectric layer 2142 includes at least one slot 215, and the at least one slot 215 exposes at least one normal contact pattern of the normal conductive layer 2411 respectively.

[0108] Fig.14 Two normal contact patterns are shown, and the two normal contact patterns are respectively recorded as a first normal contact pattern 2411~1 and a second normal contact pattern 2411~2. The first normal contact pattern 2411~1 on the first normal test pad 241~1 is connected to the functional film layer group 212 through a first via 2131~1, and the second normal contact pattern 2411~2 on the second normal test pad 241~2 is connected to the functional film layer group 212 through a second via 2131~2. The probe of the needle card can be inserted into the first normal contact pattern 2411~1 through the groove 215~1, and the probe of the needle card can be inserted into the second normal contact pattern 2411~2 through the groove 215~2.

[0109] The design of the slot 215 structure allows the probe of the test equipment to directly contact the normal contact pattern of the normal conductive layer 2411, avoiding the obstruction of the dielectric layer or electrical interference. This exposed design provides a more precise contact surface, ensuring that the test equipment can accurately contact the normal conductive layer 2411, thereby improving the accuracy and reliability of electrical testing.

[0110] For chips with high-precision testing requirements, the contact points of the test probes must be very accurate. By exposing the normal contact pattern through the slots 215, it can be ensured that the physical contact surface of the probe is always consistent with the normal conductive layer 2411, reducing the error caused by incomplete contact.

[0111] The slotted design of the dielectric layer 2142 ensures that the probe only contacts the normal contact pattern of the normal conductive layer 2411, rather than the dielectric layer 2142 itself. This can reduce the damage and wear caused by the probe penetrating into the non-conductive area (such as the dielectric layer 2142), thereby extending the service life of the test equipment (such as the needle card) and reducing the equipment maintenance cost.

[0112] If the probe penetrates the dielectric layer 2142 instead of the metal conductive layer, it may cause needle sticking or wear. The groove 215 exposing the normal conductive layer 2411 can effectively avoid this situation, ensuring that the probe is always in contact with the conductive material, protecting the equipment and reducing the test error in the production process.

[0113] The exposure of the normal contact pattern can ensure that the signal can be directly transmitted from the test equipment to the normal conductive layer 2411, reducing the interference of the signal in the dielectric layer 2142. The dielectric layer 2142 may produce impedance or parasitic effects on high-frequency signals, and exposing the normal contact pattern through the slot 215 can improve the integrity of signal transmission and reduce signal loss.

[0114] The normal contact pattern exposed by the slot 215 makes the conductive path more direct, which can reduce the resistance and parasitic capacitance effects and ensure efficient signal transmission. This design is particularly beneficial for high-speed circuits or high-frequency signal testing.

[0115] The slotting process can ensure that the normal contact pattern of the normal conductive layer 2411 is effectively exposed by precisely controlling the position and depth of the slots 215 during the manufacturing process. This precise process design can improve the consistency between different wafers or chips during the production process and ensure that each manufacturing unit can provide reliable test contact points. The slotting process can precisely control the exposed area through steps such as development and etching to avoid errors in other unnecessary areas. This helps reduce yield issues in production and ensures reliability during testing.

[0116] In some embodiments, Fig.15 As shown, at least one dielectric layer includes a first dielectric layer 2143 and a second dielectric layer 2144, and the second dielectric layer 2144 is farther away from the substrate 211 than the first dielectric layer 2143. The first dielectric layer 2143 includes at least one first slot 2151, and at least one first slot 2151 exposes at least one normal contact pattern. The second dielectric layer 2154 includes at least one second slot 2152, and at least one second slot 2152 is connected to at least one first slot 2151, and the boundary of the corresponding second slot 2152 is located outside the boundary of the first slot 2151.

[0117] Fig.15The first normal test pad 241~1 is used as an example, the first dielectric layer 2143 includes a first groove 2151~1, the second dielectric layer 2144 includes a second groove 2152~1, the second groove 2152~1 is connected to the first groove 2151~1, and the boundary of the second groove 2152~1 is located outside the boundary of the first groove 2151~1.

[0118] By designing the through first slot 2151 and second slot 2152, it is ensured that the test probe can directly contact the normal contact pattern of the normal conductive layer 2411 without being blocked by the upper dielectric layer. The boundary of the second slot 2152 is larger than the boundary of the first slot 2151, so that the test probe can contact the normal conductive layer 2411 exposed by the first slot 2151 within a larger opening range. This design improves the contact area and accuracy between the probe and the normal conductive layer 2411, thereby enhancing the stability of the electrical connection and the accuracy of the test results.

[0119] In the through slot structure, the boundary of the second slot 2152 is located outside the boundary of the first slot 2151, ensuring that the probe can more easily contact the normal pattern under the first slot 2151 when inserted, without piercing into the dielectric layer. This reduces the contact between the probe and the non-metallic layer (such as the dielectric layer), effectively reduces the wear of the probe, and reduces the test error caused by contact with non-conductive materials.

[0120] The boundary of the second slot 2152 is larger than the boundary of the first slot 2151, providing a larger margin of error for the manufacturing process. In the actual manufacturing process, slight errors may occur in the photolithography or etching operation, especially in a multilayer structure. If the boundary of the second slot 2152 is smaller, it may cause inaccurate slot alignment, affecting the contact between the test probe and the normal conductive layer 2411. By designing a larger boundary of the second slot 2152, even in the presence of some manufacturing errors, the probe can still accurately contact the normal contact pattern in the first slot 2151, thereby improving the tolerance of the manufacturing process and the yield rate of the wafer.

[0121] The through slot structure not only ensures the physical contact between the probe and the normal conductive layer, but also reduces the signal interference caused by the dielectric layer blocking. The design of the first slot 2151 and the second slot 2152 helps to ensure that the signal can be transmitted from the normal conductive layer 2411 to the probe through a direct path, thereby reducing the reflection or attenuation of the signal in the dielectric layer and improving the integrity and efficiency of signal transmission. Especially in high-frequency signal testing, the signal transmission path and slot design are crucial to signal integrity. The larger and through slot design ensures low-loss transmission of the signal and avoids signal distortion caused by a long or discontinuous signal transmission path.

[0122] Although the through slots expose the normal conductive layer 2411, the structural design between the second slot 2152 and the first slot 2151 still maintains good electrical isolation and mechanical stability. The multi-layer structure of the dielectric layer can not only protect the normal conductive layer, but also provide additional structural support for the entire chip to avoid damage caused by mechanical stress or external influences. In addition, while providing electrical isolation, the first dielectric layer 2143 and the second dielectric layer 2144 also provide protection for the normal conductive layer and the normal contact pattern to prevent them from being affected by the external environment (such as moisture, dust, etc.), further improving the durability and reliability of the chip.

[0123] In some embodiments, Fig.15 As shown, the normal manufacturing unit to be tested further includes: a second conductive layer 2130 disposed between the functional film layer group 212 and the insulating layer 213, and the second conductive layer 2130 contacts the functional film layer group 212. The second conductive layer 2130 includes at least one conductive pattern, and the normal contact pattern is connected to the conductive pattern through a via 2131.

[0124] As a possible implementation, Fig.15 As shown, the conductive pattern includes a gate 2132 , a drain 2133 and a source 2134 , the first normal contact pattern 2411 - 1 is connected to the source 2134 through the first via 2131 - 1 , and the second normal contact pattern 2411 - 2 is connected to the drain 2133 through the second via 2131 - 2 .

[0125] In some embodiments, Fig.16 As shown, the virtual manufacturing unit to be tested includes a substrate 211, a functional film layer group 212 arranged on one side of the substrate 211, an insulating layer 213 arranged on a side of the functional film layer group 212 away from the substrate 211, and at least one virtual test pad 251 arranged on a side of the insulating layer 213 away from the substrate 211, the virtual test pad 251 includes a virtual conductive layer 2511, and the virtual conductive layer 2511 is located in the same layer as the normal conductive layer 2411.

[0126] contrast Fig.15 and Fig.16 It can be seen that in Fig.16There is no via to connect the virtual conductive layer 2511 with the functional film layer group 212, that is, the probe of the needle card will not test the electrical performance of the functional film layer group 212. In this way, there is no need to set the skip path of the needle card, and the probe is inserted into each manufacturing unit on the first exposure unit. When the inserted object belongs to a normal manufacturing unit to be tested, the probe is inserted into the contact pattern on the normal conductive layer, and connected to the conductive pattern through the via to achieve connectivity with the external test circuit. When the inserted object belongs to a virtual manufacturing unit to be tested, the probe is inserted into the virtual conductive layer 2511. Since it is no longer necessary to set the skip path of the needle card, and all manufacturing units on a first exposure unit can be inserted by the probe, the number of probes on the needle card can be set as much as possible, and the test can be completed in a shorter time. And since a virtual test pad 251 is set on the virtual manufacturing unit to be tested, the probe will not be inserted into the dielectric layer, which effectively avoids the wear of the probe and improves the accuracy of the test.

[0127] In some embodiments, the virtual conductive layer 2511 includes at least one virtual contact pattern, and the virtual test pad 251 also includes at least one dielectric layer 2142 arranged on the side of the virtual conductive layer away from the substrate, and the dielectric layer 2142 includes at least one groove 215, and the at least one groove 215 respectively exposes at least one virtual contact pattern of the virtual conductive layer 2511.

[0128] Fig.16 Two virtual contact patterns are shown, which are respectively recorded as the first virtual contact pattern 2511~1 and the second virtual contact pattern 2511~2. The first virtual test pad 251~1 includes a groove 215~1, and the probe of the needle card is inserted into the first virtual contact pattern 2511~1 through the groove 215~1. The second virtual test pad 251~2 includes a groove 215~2, and the probe of the needle card is inserted into the second virtual contact pattern 2511~2 through the groove 215~2.

[0129] In some embodiments, Fig.17 As shown, at least one dielectric layer 2142 includes a first dielectric layer 2143 and a second dielectric layer 2144, and the second dielectric layer 2144 is farther away from the substrate 211 than the first dielectric layer 2143. The first dielectric layer 2143 includes at least one first slot 2151-1, and at least one first slot 2151 respectively exposes at least one virtual contact pattern. The second dielectric layer 2144 includes at least one second slot 2152, and at least one second slot 2152 respectively penetrates at least one first slot 2151, and the corresponding boundary of the second slot 2152 is located outside the boundary of the first slot 2151.

[0130] For the first type of wafer provided in the embodiment of the present application, the process flow needs to go through layout preparation, substrate preparation, light exposure menu setting, wafer production, multi-station CP test menu setting and multi-station CP test.

[0131] For the second type of wafer provided in the embodiment of the present application, the process flow needs to go through layout preparation, substrate preparation, wafer production, multi-station CP test menu setting and multi-station CP test.

[0132] For the third type of wafer provided in the embodiment of the present application, the process flow needs to go through layout preparation, substrate preparation, wafer production and multi-station CP testing.

[0133] The setting of the light exposure menu refers to the control program or setting menu used by the lithography machine when exposing the wafer. The menu will specify in detail which areas need to be exposed, how to expose, and which areas need to be skipped or processed differently. The multi-station cp test menu setting means that during the multi-station test process, the needle card will not test certain areas that need to be tested, but will directly skip these areas. The test probe will move along the set path. For example, the first type of wafer uses the first exposure unit as the step for skip path planning, and the second type of wafer uses a whole row or a whole column of manufacturing units as the step for skip path planning.

[0134] The second type of wafer provided in the embodiment of the present application has planned the arrangement of the manufacturing units to be tested and the manufacturing units not to be tested during the layout planning, so there is no need to set the light exposure menu. The third type of wafer provided in the embodiment of the present application does not need to perform skip path planning because virtual test pads are added to the manufacturing units not to be tested, thereby reducing the setting of the light exposure menu and the setting of the multi-station cp test menu. The substrate preparation stage specifically includes forming normal test pads on normal manufacturing units to be tested and forming virtual test pads on virtual manufacturing units to be tested. The first dielectric layer and the second dielectric layer are sequentially formed on the test pads (including normal test pads and virtual test pads).

[0135] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A wafer, characterized in that: include: A plurality of exposure units, wherein the exposure unit comprises a plurality of manufacturing units arranged in an array; The multiple exposure units include at least multiple first exposure units, among which any row of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested, or any column of manufacturing units are all manufacturing units to be tested or are all manufacturing units not to be tested; the manufacturing unit to be tested includes at least one test pad.

2. The wafer according to claim 1, characterized in that The multiple exposure units further include multiple second exposure units; the multiple manufacturing units in the first exposure units are all manufacturing units to be tested, and the multiple manufacturing units in the second exposure units are all manufacturing units not to be tested.

3. The wafer according to claim 2, characterized in that The manufacturing unit to be tested comprises: substrate; A functional film layer group disposed on one side of the substrate; An insulating layer disposed on a side of the functional film layer group away from the substrate; the insulating layer comprises at least one via hole; At least one test pad is disposed on a side of the insulating layer away from the substrate, wherein the test pad comprises a first conductive layer, and the first conductive layer is connected to the functional film layer group through the at least one via hole.

4. The wafer according to claim 3, characterized in that The first conductive layer includes at least one contact pattern; The test pad further includes at least one dielectric layer disposed on a side of the first conductive layer away from the substrate, the dielectric layer includes at least one groove, and the at least one groove respectively exposes at least one contact pattern of the first conductive layer.

5. The wafer according to claim 4, characterized in that The at least one dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the second dielectric layer is farther away from the substrate than the first dielectric layer; The first dielectric layer comprises at least one first groove, and the at least one first groove respectively exposes the at least one contact pattern; The second dielectric layer includes at least one second slot, the at least one second slot is connected to the at least one first slot respectively, and the boundary of the corresponding second slot is located outside the boundary of the first slot.

6. The wafer according to claim 4 or 5, characterized in that: The manufacturing unit to be tested also includes: A second conductive layer is disposed between the functional film layer group and the insulating layer, and the second conductive layer contacts the functional film layer group; the second conductive layer includes at least one conductive pattern, and the contact pattern is connected to the conductive pattern through the via hole.

7. The wafer according to claim 2, characterized in that: The non-to-be-tested manufacturing unit comprises a substrate and a functional film group arranged on one side of the substrate.

8. The wafer according to claim 1, characterized in that The multiple exposure units are all first exposure units; The plurality of manufacturing units in the first exposure unit include a plurality of manufacturing units to be tested and a plurality of manufacturing units not to be tested; At least two adjacent rows of manufacturing units are all manufacturing units to be tested, and the manufacturing units in the remaining rows are all manufacturing units not to be tested; or at least two adjacent columns of manufacturing units are all manufacturing units to be tested, and the manufacturing units in the remaining columns are all manufacturing units not to be tested.

9. The wafer according to claim 8, characterized in that The first exposure unit includes a first edge region, a first center region, and a second edge region sequentially arranged along a row direction; The manufacturing units in at least two adjacent rows are all manufacturing units to be tested and are located in the first central area, and the manufacturing units in the remaining rows are all manufacturing units not to be tested and are located in the first edge area and the second edge area.

10. The wafer according to claim 8, characterized in that The first exposure unit includes a third edge region, a second center region and a fourth edge region sequentially arranged along a column direction; The manufacturing units in at least two adjacent columns are all manufacturing units to be tested and are located in the second central area, and the manufacturing units in the remaining columns are all manufacturing units not to be tested and are located in the third edge area and the fourth edge area.

11. The wafer according to claim 1, characterized in that The multiple exposure units are all first exposure units; The multiple manufacturing units in the first exposure unit are all manufacturing units to be tested, and the manufacturing units to be tested include normal manufacturing units to be tested and virtual manufacturing units to be tested, the normal manufacturing units to be tested include at least one normal test pad, and the virtual manufacturing units to be tested include at least one virtual test pad; Wherein, the size of the virtual test pad is smaller than the size of the normal test pad.

12. The wafer according to claim 11, characterized in that The normal manufacturing unit to be tested includes: substrate; A functional film layer group disposed on one side of the substrate; An insulating layer disposed on a side of the functional film layer group away from the substrate; the insulating layer comprises at least one via hole; At least one normal test pad is disposed on a side of the insulating layer away from the substrate, wherein the normal test pad comprises a normal conductive layer, and the normal conductive layer is connected to the functional film layer group through the at least one via hole.

13. The wafer according to claim 12, characterized in that The virtual manufacturing unit to be tested comprises: substrate; A functional film layer group disposed on one side of the substrate; An insulating layer disposed on a side of the functional film layer group away from the substrate; At least one virtual test pad is disposed on a side of the insulating layer away from the substrate, wherein the virtual test pad comprises a virtual conductive layer, and the virtual conductive layer is located in the same layer as the normal conductive layer.

14. The wafer according to claim 12, characterized in that: The normal conductive layer includes at least one normal contact pattern; The normal test pad further comprises at least one dielectric layer disposed on a side of the normal conductive layer away from the substrate, the dielectric layer comprises at least one slot, and the at least one slot respectively exposes at least one normal contact pattern of the normal conductive layer.

15. The wafer according to claim 14, characterized in that The at least one dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the second dielectric layer is farther away from the substrate than the first dielectric layer; The first dielectric layer comprises at least one first groove, and the at least one first groove respectively exposes the at least one normal contact pattern; The second dielectric layer includes at least one second slot, the at least one second slot is connected to the at least one first slot respectively, and the boundary of the corresponding second slot is located outside the boundary of the first slot.

16. The wafer according to claim 14, characterized in that The normal manufacturing unit to be tested also includes: A second conductive layer is disposed between the functional film layer group and the insulating layer, and the second conductive layer contacts the functional film layer group; the second conductive layer includes at least one conductive pattern, and the normal contact pattern is connected to the conductive pattern through the via hole.

17. The wafer according to claim 13, characterized in that The virtual conductive layer includes at least one virtual contact pattern, and the virtual test pad also includes at least one dielectric layer arranged on the side of the virtual conductive layer away from the substrate, and the dielectric layer includes at least one groove, and the at least one groove respectively exposes at least one virtual contact pattern of the virtual conductive layer.

18. The wafer according to claim 17, characterized in that The at least one dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the second dielectric layer is farther away from the substrate than the first dielectric layer; The first dielectric layer comprises at least one first groove, and the at least one first groove respectively exposes the at least one dummy contact pattern; The second dielectric layer includes at least one second slot, and the at least one second slot is respectively connected to the at least one first slot, and the boundary of the corresponding second slot is located outside the boundary of the first slot.

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