ESD (Electro-Static Discharge) protection device with low dynamic on-resistance

Abstract

The utility model discloses an ESD (Electro-Static Discharge) protection device with low dynamic on-resistance, which comprises a P + substrate material region, and an N-buffer layer, an N-epitaxial layer, a P well region, a P + diffusion region 1, a P + diffusion region 2 and an N + diffusion region which are sequentially arranged on the surface of the P + substrate material region from bottom to top, and is sequentially divided into a DIODE1 unit, a DIODE2 unit and an NPN unit from left to right through two groove region electrical isolation, the trench region extends from the upper surface to the P + substrate material region. According to the structure, electrical isolation is carried out through the trench region, and the breakdown voltage depends on the concentration distribution of the P + diffusion region and the Pwell region, so that the current path is shortened, the dynamic on-resistance is reduced, and the ESD current discharge capability is improved. And on the other hand, the new structure comprises an N-buffer layer and an N-epitaxial region which are grown on a P + substrate material, so that the influence of the parasitic effect of the conventional ESD protection device structure with low dynamic on-resistance is improved. Meanwhile, the trench region plays a role in electrical isolation, so that the area of the device is reduced.

Description

Technical Field

[0001] The utility model belongs to the field of integrated circuit electrostatic discharge (ESD-Electrostatic Discharge) protection. Background Art

[0002] The development trend of integrated circuit miniaturization, high integration and low operating voltage has made integrated circuit chips more and more sensitive to electrostatic discharge events, and they are easily damaged by static electricity and surges. As one of the effective means to protect internal circuits or devices from electrostatic discharge damage, electrostatic discharge protection devices are widely used in the integrated circuit industry, such as consumer electronics, automotive electronics, computers and other fields. The most important parameter of an ESD protection device is its ESD protection capability, and the size of the dynamic on-resistance can indirectly reflect the protection capability of the ESD protection device. Generally speaking, under the same area, the smaller the dynamic on-resistance, the stronger the ESD protection capability of the ESD protection device.

[0003] Commonly used ESD protection devices can be roughly divided into four categories, namely diodes, bipolar junction transistors (BJT), metal oxide semiconductor field effect transistors (MOSFET), and thyristors (SCR). Conventional low dynamic on-resistance ESD protection devices generally adopt the structure shown in Figure 1. A P-well region 102 is formed on an N+ substrate material 101, and a P-well region 103 is formed in the well region 102. The doping concentration of the P-well region 103 is higher than that of 102. A P+ diffusion region 104 and an N+ diffusion region 105 are formed in the P-well region 103, and a surface passivation layer 106 acts as a dielectric isolation. Metal layers 108 and 109 respectively represent the anode port and cathode port of the ESD protection device with low dynamic on-resistance. As shown in FIG. Figure 3 Shown Figure 1 The equivalent circuit diagram of the low dynamic on-resistance ESD protection device based on NPN structure is as follows: the DIODE1 unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, and an N+ substrate material region 101; the DIODE2 unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, a P well region 102, and an N+ substrate material region 101; and the NPN unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, a P well region 103, a P well region 102, and an N+ substrate material region.

[0004] like Figure 1 The volt-ampere characteristic curve of a conventional low dynamic on-resistance ESD protection device is shown in FIG. Figure 4 As shown, when the metal layer 108 is at a high potential and the metal layer 109 is at a low potential, the current flows from the DIODE1 unit through the metal layer 107 to the NPN unit, showing the shallow flyback characteristic of the transistor. Figure 1The protection structure of the ESD protection device shown is a BJT transistor. Since the transistor has an amplifying effect, its dynamic on-resistance is lower than that of a diode structure. At the same time, the transistor is a lateral structure, and the breakdown voltage depends on the concentration distribution of the N+ diffusion area 105 and the P-well area 103. The width of the P-well area 103 is wider, allowing a larger current to flow through, and the dynamic on-resistance is lower.

[0005] like Figure 1 The conventional low dynamic on-resistance ESD protection device shown in the figure achieves a lower dynamic on-resistance, and its breakdown voltage depends on the concentration distribution of the N+ diffusion region 105 and the P-well region 103. To obtain a lower dynamic on-resistance, the concentration of the P-well region 103 is required to be very high, which will cause an increase in BV and capacitance, and also make parasitic problems very serious. At the same time, Figure 1 In the structure shown, the electrical parameter isolation of the DIODE unit and the NPN unit requires a long distance, which will cause the area to increase, and the capacitance parameter will also increase with the increase of the area. The utility model provides a new technical solution, which can ensure that Figure 1 Under the same area of ​​the structure, the dynamic on-resistance of the ESD protection device is reduced and its ESD protection capability is increased, thereby obtaining a more ideal low dynamic on-resistance ESD protection device. Utility Model Content

[0006] The utility model aims to provide an ESD protection device with low dynamic on-resistance, which solves the problems of high dynamic on-resistance and parasitic effect of the existing ESD protection device.

[0007] The technical solution adopted by the utility model is an ESD protection device with low dynamic on-resistance, comprising a P+ substrate material area, an N-buffer layer, an N-epitaxial layer, a P well area, a P+ diffusion 1 area, a P+ diffusion 2 area and an N+ diffusion area arranged in sequence from bottom to top on the surface of the P+ substrate material area. The ESD protection device is electrically isolated by two groove areas and is divided into a DIODE1 unit, a DIODE2 unit and an NPN unit from left to right, and the groove area extends from the upper surface to the P+ substrate material area.

[0008] In some embodiments, the DIODE1 unit includes a first N+ diffusion region, a first P+ diffusion region, a first N-epitaxial layer, and a first N-buffer layer electrically isolated by the slot region, the DIODE2 unit includes a second N+ diffusion region, a second P+ diffusion region, a first Pwell well region, a second N-epitaxial layer, and a second N-buffer layer electrically isolated by the slot region, and the NPN unit includes a third N+ diffusion region, a P+ diffusion 2 region, a P+ diffusion 1 region, a second Pwell well region, a third N-epitaxial layer, and a third N-buffer layer electrically isolated by the slot region.

[0009] In some embodiments, a surface passivation layer is further disposed above the P+ diffusion 2 region and the N+ diffusion region.

[0010] In some embodiments, the first N+ diffusion region is connected to a first metal layer, the first P+ diffusion region and the second N+ diffusion region are connected through a second metal layer, and the second P+ diffusion region, the third N+ diffusion region and the P+ diffusion 2 region are connected through a third metal layer.

[0011] In some embodiments, a first LOCOS region is provided between the first N+ diffusion region and the first P+ diffusion region, a second LOCOS region is provided between the second N+ diffusion region and the second P+ diffusion region, and a third LOCOS region is provided between the third N+ diffusion region and the P+ diffusion 2 region.

[0012] Beneficial effects:

[0013] The structure is electrically isolated through the trench area, and the breakdown voltage depends on the concentration distribution of the P+ diffusion area and the Pwell well area, which shortens the current path, reduces the dynamic on-resistance, and improves the ESD current discharge capability. On the other hand, the new structure includes the growth of an N-buffer layer and an N-epitaxial area on the P+ substrate material, which improves the influence of the parasitic effects of the conventional low dynamic on-resistance ESD protection device structure. At the same time, the trench area plays an electrical isolation role, reducing the device area.

[0014] By introducing the P+ diffusion region, N-epitaxial layer, N-buffer layer, trench region, and LOCOS isolation region, parasitic problems in conventional low dynamic on-resistance ESD protection devices can be effectively avoided, and the dynamic on-resistance of the ESD protection device can be reduced. In addition, the P+ diffusion region improves the ESD protection capability of the NPN unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structural cross section of a conventional low dynamic on-resistance ESD protection device;

[0016] Figure 2 It is a schematic diagram of the structural cross-section of the low dynamic on-resistance ESD protection device of the utility model patent;

[0017] Figure 3 It is a schematic diagram of an equivalent circuit of a conventional ESD protection device with low dynamic on-resistance and a patent of the utility model;

[0018] Figure 4 It is a schematic diagram of the volt-ampere characteristic curve of the conventional ESD protection device with low dynamic on-resistance and the utility model patent. DETAILED DESCRIPTION

[0019] In view of the technical defects of the existing conventional low dynamic on-resistance ESD protection devices, the present utility model embodiment designs a low dynamic on-resistance ESD protection device, which can effectively avoid the following problems by introducing a P+ diffusion region 206, an N-epitaxial layer 203, an N-buffer layer 202, a trench region 209, and a LOCOS isolation region 205. Figure 1 The parasitic problems in the conventional low dynamic on-resistance ESD protection device shown in the figure are solved, and the dynamic on-resistance of the ESD protection device is reduced. Moreover, the P+ diffusion region 206 improves the ESD protection capability of the NPN cell.

[0020] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0021] The utility model embodiment designs an ESD protection device with low dynamic on-resistance, which can effectively avoid the following problems by introducing P+ highly doped diffusion region 206, N-epitaxial layer 203, N-buffer layer 202, trench region 209, and LOCOS isolation region 205. Figure 1 The parasitic problems in the conventional low dynamic on-resistance ESD protection device are shown, and the dynamic on-resistance of the ESD protection device is reduced.

[0022] like Figure 1 The structure of a conventional low dynamic on-resistance ESD protection device is shown, and its features include: a P well region 102 is formed on an N+ substrate material 101, and a P well region 103 is formed in the well region 102, and the doping concentration of the P well region 103 is higher than that of the well region 102. A P+ diffusion region 104 and an N+ diffusion region 105 are formed in the P well region 103, and a surface passivation layer 106 plays a dielectric isolation role. Metal layers 108 and 109 represent the anode port and cathode port of the ESD protection device with low dynamic on-resistance, respectively. Figure 3 Shown Figure 1 The equivalent circuit diagram of a conventional low dynamic on-resistance ESD protection device with a structure is as follows: the DIODE1 unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, and an N+ substrate material region 101; the DIODE2 unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, a P well region 102, and an N+ substrate material region 101; and the NPN unit is composed of a P+ diffusion region 104, an N+ diffusion region 105, a P well region 103, a P well region 102, and an N+ substrate material region.

[0023] like Figure 1 The volt-ampere characteristic curve of a conventional low dynamic on-resistance ESD protection device is shown in FIG. Figure 4 As shown, when the metal layer 108 is at a high potential and the metal layer 109 is at a low potential, the current flows from the DIODE1 unit through the metal layer 107 to the NPN unit, showing the shallow flyback characteristic of the transistor. Figure 1The protection structure of the ESD protection device shown is a BJT transistor. Since the transistor has an amplification effect, its dynamic on-resistance is low. At the same time, the transistor is a lateral structure, and the breakdown voltage depends on the concentration distribution of the N+ diffusion area 105 and the P-well area 103. The width of the P-well area 103 is wider, allowing a larger ESD current to flow, resulting in a lower dynamic on-resistance.

[0024] like Figure 1 The conventional low dynamic on-resistance ESD protection device shown in the figure achieves a lower dynamic on-resistance, and its breakdown voltage depends on the concentration distribution of the N+ diffusion region 105 and the P-well region 103. To obtain a lower dynamic on-resistance, the concentration of the P-well region 103 is required to be very high, which will cause an increase in BV and capacitance, and also make parasitic problems very serious. At the same time, Figure 1 In the structure shown, the electrical parameter isolation of the DIODE unit and the NPN unit requires a long distance, which will cause the area to increase and the capacitance parameter to increase with the area.

[0025] Figure 2 The figure shows a schematic cross-sectional view of a novel structure proposed by the utility model, which features include: a P+ substrate material area 201, an N-buffer layer 202 and an N-epitaxial layer 203 located above the P+ substrate material area, a P-well area 204 located above the N-epitaxial layer 203, a LOCOS area 205 for electrical isolation, a P+ diffusion 1 area 206, a P+ diffusion 2 area 207, and an N+ diffusion area 208 located above the P-well area 204, and electrical isolation between the DIODE1 unit and the DIODE2 unit and the NPN unit is formed by the groove area 209. The metal layer 212 and the metal layer 213 represent the two electrode ports of the ESD protection device with low dynamic on-resistance, namely, the anode and the cathode. The surface passivation layer 210 plays the role of dielectric isolation.

[0026] like Figure 2 The equivalent circuit diagram of the ESD protection device with low dynamic on-resistance is as follows: Figure 3 As shown, the DIODE1 unit is composed of an N+ diffusion region 208, a P+ diffusion region 207, an N-epitaxial layer 203, an N-buffer layer 202, and a P+ substrate material region 201; the DIODE2 unit is composed of an N+ diffusion region 208, a P+ diffusion region 207, a Pwell well region 204, an N-epitaxial layer 203, an N-buffer layer 202, and a P+ substrate material region 201; the NPN unit is composed of an N+ diffusion region 208, a P+ diffusion 2 region 207, a P+ diffusion 1 region 206, a Pwell well region 204, an N-epitaxial layer 203, an N-buffer layer 202, and a P+ substrate material region 201; and the electrical isolation between the DIODE1 unit and the DIODE2 unit and the electrical isolation between the DIODE2 unit and the NPN unit are composed of a trench region 209.

[0027] like Figure 2 The volt-ampere characteristic curve of the low dynamic on-resistance ESD protection device is shown in Figure 4 As shown, when metal layer 212 is connected to a high potential and metal layer 213 is connected to a low potential, current flows from DIODE1 unit through metal layer 211 to NPN unit, showing the shallow retrace characteristic of the transistor. Figure 2 The protection structure of the low dynamic on-resistance ESD protection device shown is a BJT transistor. Figure 1 The structure shown in FIG. 1 is electrically isolated by the trench region 209, and the breakdown voltage depends on the concentration distribution of the P+ diffusion region 206 and the Pwell well region 204, which shortens the current path, reduces the dynamic on-resistance, and improves the ESD current discharge capability. Figure 2 The new structure shown includes growing an N-buffer layer 202 and an N-epitaxial region 203 on a P+ substrate material 201, thereby improving the Figure 1 The parasitic effect of the structure shown in FIG. 2 is also affected. At the same time, the trench region 209 plays an electrical isolation role, reducing the device area.

[0028] The utility model has the advantage that by introducing the P+ diffusion region 206, the N-epitaxial layer 203, the N-buffer layer 202, the trench region 209, and the LOCOS isolation region 205, the following problems can be effectively avoided: Figure 1 The parasitic problems in the conventional low dynamic on-resistance ESD protection device shown in the figure are solved, and the dynamic on-resistance of the ESD protection device is reduced. Moreover, the P+ diffusion region 206 improves the ESD protection capability of the NPN cell.

[0029] Finally, it should be noted that the above examples are only used to illustrate the technical solution of the utility model and are not intended to limit it. Although the utility model has been described in detail with reference to the preferred examples, those skilled in the art should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. An ESD protection device with low dynamic on-resistance, characterized in that: The ESD protection device comprises a P+ substrate material region (201), an N-buffer layer (202) arranged on the surface of the P+ substrate material region (201) in sequence from bottom to top, an N-epitaxial layer (203), a P well region, a P+ diffusion 1 region, a P+ diffusion 2 region and an N+ diffusion region. The ESD protection device is electrically isolated by two groove regions (209) and is divided into a DIODE1 unit, a DIODE2 unit and an NPN unit from left to right. The groove region (209) extends from the upper surface to the P+ substrate material region (201).

2. The ESD protection device according to claim 1, characterized in that: The DIODE1 unit includes a first N+ diffusion region (208), a first P+ diffusion 2 region (207), a first N-epitaxial layer and a first N-buffer layer electrically isolated by the slot region (209); the DIODE2 unit includes a second N+ diffusion region, a second P+ diffusion 2 region, a first Pwell well region, a second N-epitaxial layer and a second N-buffer layer electrically isolated by the slot region (209); and the NPN unit includes a third N+ diffusion region, a third P+ diffusion 2 region, a P+ diffusion 1 region (206), a second Pwell well region (204), a third N-epitaxial layer and a third N-buffer layer electrically isolated by the slot region (209).

3. The ESD protection device according to claim 2, characterized in that: A surface passivation layer (210) is also disposed above the first P+ diffusion 2 region (207) and the first N+ diffusion region (208).

4. The ESD protection device according to claim 2, characterized in that: The first N+ diffusion region (208) is connected to a first metal layer (211), the first P+ diffusion region 2 (207) and the second N+ diffusion region are connected via a second metal layer (212), and the second P+ diffusion region 2, the third N+ diffusion region and the third P+ diffusion region 2 are connected via a third metal layer (213).

5. The ESD protection device according to claim 2, characterized in that: A first LOCOS region is provided between the first N+ diffusion region (208) and the first P+ diffusion region 2 (207), a second LOCOS region is provided between the second N+ diffusion region and the second P+ diffusion region 2, and a third LOCOS region (205) is provided between the third N+ diffusion region and the third P+ diffusion region 2.

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