Radar image acquisition device

Abstract

The utility model relates to a radar image acquisition device. The method is used in spaceflight testing field. Comprising an FPGA chip, a data storage circuit, an FPD-LINK image transceiver circuit, a USB interface circuit and an Ethernet interface circuit. The data storage circuit is connected with the FPGA chip; the FPD-LINK image transceiver circuit is connected between the FPGA chip and the radar equipment, and a radar image acquisition and self-test access is established between the radar equipment and the FPGA chip; the USB interface circuit and the Ethernet interface circuit are respectively connected between the FPGA chip and the upper computer; and a data transmission path is established between the FPGA chip and the upper computer. The device adopts an independent test box structure, is small and exquisite in shape and convenient to carry, and adapts to internal and external field tests and maneuverability requirements.

Description

Technical Field

[0001] The utility model relates to the field of aerospace testing and the technical field of image acquisition, in particular to a radar image acquisition device. Background Art

[0002] With the development of science and technology, the demand for radar image acquisition is becoming more and more widespread. The image acquisition device is used to collect image signals. The device adopts an independent test box structure, which is compact and easy to carry, and is suitable for indoor and outdoor field testing and mobility. The commonly used image acquisition card cannot meet this need. Utility Model Content

[0003] In view of the above analysis, the utility model aims to provide a radar image acquisition device to solve the above-mentioned problem of radar image acquisition.

[0004] The purpose of this utility model is mainly achieved through the following technical solutions:

[0005] The utility model discloses a radar image acquisition device, which comprises: an FPGA chip, a data storage circuit, an FPD-LINK image transceiver circuit, a USB interface circuit and an Ethernet interface circuit;

[0006] The data storage circuit is connected to the FPGA chip;

[0007] The FPD-LINK image transceiver circuit is connected between the FPGA chip and the radar device, and a radar image acquisition and self-test path is established between the radar device and the FPGA chip;

[0008] The USB interface circuit and the Ethernet interface circuit are respectively connected between the FPGA chip and the host computer; a data transmission path is established between the FPGA chip and the host computer.

[0009] Furthermore, the FPGA chip is the XC7A100T-2FGG484I in the Xilinx A7 series FPGA.

[0010] Furthermore, the data storage circuit includes one EEPROM and two SDRAMs.

[0011] Furthermore, the FPD-LINK image transceiver circuit includes an image transceiver connector, a receiving chip and a transmitting chip. The image transceiver connector is connected to the radar device; the receiving chip and the transmitting chip are distributed and connected between the image transceiver connector and the FPGA chip; the receiving chip converts the high-speed differential serial encoded data output by the radar device into parallel data and outputs it to the FPGA chip; the transmitting chip converts the parallel data output by the FPGA chip into high-speed differential serial encoded data and outputs it to the radar device.

[0012] Furthermore, the receiving chip is GM8914; the sending chip is GM8913.

[0013] Furthermore, the image transceiver connector is HJ30J-12ZKW.

[0014] Furthermore, the USB interface circuit includes a USB chip and a USB3.0 connector; wherein the USB chip is the FT601Q chip of FTDI Company; the USB3.0 connector is the U231-091N-1BLRC19-F5 of XKB Company, which is Type-A.

[0015] Furthermore, the Ethernet interface circuit includes a Gigabit Ethernet chip and a Gigabit Ethernet connector; wherein the Gigabit Ethernet chip is the KSZ9031RNXIA chip of Microchip Corporation of the United States; the Gigabit Ethernet connector is the X01AQ066BA2AD of XKB Company with an indicator light.

[0016] Furthermore, it also includes a JTAG connector connected to the FPGA chip, and the JTAG connector is J30J-9ZKWJ.

[0017] Furthermore, it also includes a circuit board and a test box; wherein the circuit board is placed inside the test box, and is used to carry the FPGA chip, data storage circuit, FPD-LINK image receiving circuit, FPD-LINK image sending circuit, USB interface circuit and Ethernet interface circuit and perform circuit connection; the test box is provided with fixing holes for fixing the USB3.0 connector, Gigabit Ethernet connector, image transceiver connector and JTAG connector.

[0018] The beneficial effects of the utility model are as follows:

[0019] The radar image acquisition device disclosed in the utility model fully considers the high efficiency of data processing and the stability of transmission, and is suitable for a variety of application scenarios. Through high-performance FPGA chips, reliable data storage circuits, high-speed image transceiver circuits, and multiple data transmission interfaces, the device can meet the high standard requirements of radar image acquisition and processing. The device adopts an independent test box structure, is compact, easy to carry, and adapts to indoor and outdoor field testing and mobility needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components.

[0021] Figure 1 This is a schematic diagram of the circuit composition and connection of a radar image acquisition device in an embodiment of the utility model;

[0022] Figure 2 This is a schematic diagram of an FPGA clock circuit in an embodiment of the utility model;

[0023] Figure 3 This is a schematic diagram of the FPGA SPI configuration circuit in the embodiment of the utility model;

[0024] Figure 4 This is the circuit diagram of HY57V281620HC in the embodiment of the utility model;

[0025] Figure 5 This is the circuit diagram of AT24C02 in the embodiment of the utility model;

[0026] Figure 6 This is a functional block diagram of GM8914 in an embodiment of the utility model;

[0027] Figure 7 The GM8914 circuit diagram in the embodiment of the utility model is shown in FIG.

[0028] Figure 8 This is a functional block diagram of GM8913 in an embodiment of the utility model;

[0029] Fig. 9 This is the circuit diagram of GM8913 in the embodiment of the utility model;

[0030] Fig.10 It is a functional block diagram of FT601Q in the embodiment of the utility model;

[0031] Fig.11 It is a functional block diagram of KSZ9031RNXIA in the embodiment of the utility model;

[0032] Fig.12 The figure is a schematic diagram of the appearance of the test box of the collection device in the embodiment of the utility model. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present application and are used together with the embodiments of the present invention to illustrate the principles of the present invention.

[0034] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved more clearly, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention,

[0035] All other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present utility model.

[0036] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0038] A specific embodiment of the utility model discloses a radar image acquisition device; Figure 1 As shown, it includes: FPGA chip, data storage circuit, FPD-LINK image transceiver circuit, USB interface circuit and Ethernet interface circuit;

[0039] The data storage circuit is connected to the FPGA chip;

[0040] The FPD-LINK image transceiver circuit is connected between the FPGA chip and the radar device, and a radar image acquisition and self-test path is established between the radar device and the FPGA chip;

[0041] The USB interface circuit and the Ethernet interface circuit are respectively connected between the FPGA chip and the host computer; a data transmission path is established between the FPGA chip and the host computer.

[0042] Specifically, the FPGA chip is the XC7A100T-2FGG484I in the Xilinx A7 series FPGA. This is a high-performance programmable logic device that can handle complex algorithms and logic control, and is very suitable for real-time processing and analysis of radar images.

[0043] More specifically, in the design of the FPGA clock circuit, the clock circuit uses an active crystal oscillator, and the clock signal is connected to the FPGA global clock pin. Figure 2 As shown,

[0044] More specifically, in the design of the FPGA configuration circuit, the solution of this embodiment adopts the SPI serial configuration method, that is, the FPGA chip is the master device and the SPI serial FLASH is the slave device.

[0045] SPI signal names and function descriptions are shown in Table 1.

[0046]

[0047] FPGA SPI configuration circuit interface diagram as shown below Figure 3 shown.

[0048] More specifically, the FPGA general IO design mainly involves the control design of the data storage circuit, FPD-LINK image transceiver circuit, USB interface circuit and Ethernet interface circuit, as well as the LED indicator design. Among them, the Bank_13 pin distribution is the network port signal and the EEPROM signal in the data storage circuit. The Bank_14 pin distribution is the FPGA configuration part, LED indicator and USB signal. The Bank_15 and 16 pin distributions are mainly SDRAM signals in the data storage circuit, and there are a few USB signals. The Bank34 pin distribution is DDR3 signals. The Bank_35 signal distribution is the transceiver signal of the FPD-LINK image transceiver circuit.

[0049] Since high-speed signals are not involved in this embodiment, the FPGA high-speed IO part is not used.

[0050] Specifically, the data storage circuit includes 1 EEPROM and 2 SDRAMs. The fastest image receiving rate is 62.5MB per second, and the SDRAM memory is 320M bytes in total. When the host computer does not read data, the SDRAM memory can cache for 5 seconds. It has been verified that the effective upload rate of the USB interface in this solution can reach 260MB / s, and the effective transmission rate of the Gigabit Ethernet interface can reach 100MB / s. Both interface modes can meet the requirements of data transmission.

[0051] More specifically, in the SDRAM circuit design, SDRAM uses two HY57V281620HC chips.

[0052] like Figure 4 Shown is the circuit diagram of HY57V281620HC.

[0053] More specifically, in the EEPROM circuit design, the EEPROM uses the AT24C02 chip from Microchip, Inc. AT24C02 is a 2K-bit serial CMOS EEPROM with 256 8-bit bytes inside.

[0054] like Figure 5Shown is the circuit diagram of AT24C02.

[0055] Specifically, the FPD-LINK image transceiver circuit includes an image transceiver connector, a receiving chip and a transmitting chip. The image transceiver connector is connected to the radar device; the receiving chip and the transmitting chip are distributed and connected between the image transceiver connector and the FPGA chip; the receiving chip converts the high-speed differential serial encoded data output by the radar device into parallel data and outputs it to the FPGA chip; the transmitting chip converts the parallel data output by the FPGA chip into high-speed differential serial encoded data and outputs it to the radar device.

[0056] Preferably, the receiving chip is GM8914, the sending chip is GM8913, and the image transceiver connector is HJ30J-12ZKW.

[0057] The GM8914 chip is a DC balanced bidirectional controlled deserializer that converts high-speed differential serial coded data into parallel data. It also outputs a clock signal synchronously. Figure 6 This is the functional block diagram of GM8914. Figure 7 This is the circuit diagram of GM8914.

[0058] The GM8913 chip is a DC-balanced bidirectional controlled serializer that converts parallel data and clock information into high-speed differential serial data. Figure 8 This is the functional block diagram of GM8913. Fig. 9 This is the circuit diagram of GM8913.

[0059] Specifically, the USB interface circuit includes a USB chip and a USB3.0 connector; the USB chip uses the FT601Q chip of FTDI Company to realize the communication between FPGA and USB; the USB3.0 connector uses the U231-091N-1BLRC19-F5 of XKB Company, which is Type-A.

[0060] Fig.10 This is the functional block diagram of the FT601Q.

[0061] Specifically, the Ethernet interface circuit includes a Gigabit Ethernet chip and a Gigabit Ethernet connector; the Gigabit Ethernet chip uses the KSZ9031RNXIA chip of Microchip, USA, which is used to realize the communication function between the network port and the FPGA; the Ethernet interface uses the RGMII interface for communication; the RGMII interface supports 10 / 100 / 1000Mbps data transmission. The Gigabit Ethernet connector uses the X01AQ066BA2AD of XKB, with an indicator light, and is RJ45 type.

[0062] Fig.11 This is the functional block diagram of KSZ9031RNXIA.

[0063] Furthermore, it also includes a JTAG connector connected to the FPGA chip, which is used to test and debug the functions of the FPGA chip, and the JTAG connector is J30J-9ZKWJ.

[0064] Specifically, the radar image acquisition device of this embodiment needs to use 5V to power the board. There are two ways to obtain 5V power. One is powered by USB3.0, and the other is powered by the power supply interface (push-pull self-locking connector). The core controller of the board is Xilinx 7 series FPGA. In order to meet the normal operation of FPGA, the voltages that the board needs to provide are VCCINT_1V0, VCC_1V5, VCC_1V8, VCCAUX_1V8 and VCC_3V3. The voltages that DDR3 needs to provide are DDR_VTT, DDR_VREF, and VCC1V5. The voltage that GM8913 and GM8914 need to provide is VCC_1V8. The voltage that EEPROM, SDRAM, and USB chips need to provide is VCC_3V3. The voltages required by Ethernet chips are VCC1V2 and VCC3V3.

[0065] Specifically, the radar image acquisition device of this embodiment also includes a circuit board and a test box; wherein the circuit board is placed inside the test box, and is used to carry an FPGA chip, a data storage circuit, an FPD-LINK image receiving circuit, an FPD-LINK image sending circuit, a USB interface circuit and an Ethernet interface circuit and perform circuit connections; the test box is provided with fixing holes for fixing the USB3.0 connector, the Gigabit Ethernet connector, the image transceiver connector and the JTAG connector.

[0066] The functions of the image acquisition device are integrated into a circuit board, and the reliability of the device is improved by adopting measures such as reinforcement, moisture-proof, mildew-proof, salt spray-proof, wind-proof, dust-proof and rust-proof. Moreover, these measures are mature in technology and have lower costs compared with the test system structure based on PXI and PCI buses.

[0067] More specifically, the test box has an outer dimension of 122.5*88*30 (mm), and is made of aluminum alloy in black oxide color. The left side of the device is equipped with a power interface, a network port, a USB interface, and 4 indicator lights, and the right side of the device is equipped with an image input interface and a JTAG debugging port. Fig.12 This is a schematic diagram of the appearance of the collection device test box.

[0068] The radar image acquisition device disclosed in this embodiment fully considers the efficiency of data processing and the stability of transmission, and is suitable for a variety of application scenarios. Through high-performance FPGA chips, reliable data storage circuits, high-speed image transceiver circuits, and multiple data transmission interfaces, the device can meet the high standards for radar image acquisition and processing. The device adopts an independent test box structure, is compact, and is easy to carry, which is suitable for indoor and outdoor field testing and mobility needs.

[0069] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

Claims

1. A radar image acquisition device; characterized in that, include: FPGA chip, data storage circuit, FPD-LINK image transceiver circuit, USB interface circuit and Ethernet interface circuit; The data storage circuit is connected to the FPGA chip; The FPD-LINK image transceiver circuit is connected between the FPGA chip and the radar device, and a radar image acquisition and self-test path is established between the radar device and the FPGA chip; The USB interface circuit and the Ethernet interface circuit are respectively connected between the FPGA chip and the host computer; a data transmission path is established between the FPGA chip and the host computer.

2. The radar image acquisition device according to claim 1, characterized in that: The FPGA chip is the XC7A100T-2FGG484I from the Xilinx A7 series FPGA.

3. The radar image acquisition device according to claim 2, characterized in that: The data storage circuit includes 1 EEPROM and 2 SDRAMs.

4. The radar image acquisition device according to claim 3, characterized in that: The FPD-LINK image transceiver circuit includes an image transceiver connector, a receiving chip and a transmitting chip. The image transceiver connector is connected to the radar device; the receiving chip and the transmitting chip are distributed and connected between the image transceiver connector and the FPGA chip; the receiving chip converts the high-speed differential serial coded data output by the radar device into parallel data and outputs it to the FPGA chip; the transmitting chip converts the parallel data output by the FPGA chip into high-speed differential serial coded data and outputs it to the radar device.

5. The radar image acquisition device according to claim 4, characterized in that: The receiving chip is GM8914; the sending chip is GM8913.

6. The radar image acquisition device according to claim 4, characterized in that: The image transceiver connector is HJ30J-12ZKW.

7. The radar image acquisition device according to claim 4, characterized in that: The USB interface circuit includes a USB chip and a USB3.0 connector. The USB chip is FT601Q chip from FTDI. The USB3.0 connector is U231-091N-1BLRC19-F5 from XKB, which is Type-A.

8. The radar image acquisition device according to claim 4, characterized in that: The Ethernet interface circuit includes a Gigabit Ethernet chip and a Gigabit Ethernet connector; the Gigabit Ethernet chip uses the KSZ9031RNXIA chip of Microchip Company of the United States; the Gigabit Ethernet connector uses the X01AQ066BA2AD of XKB Company with an indicator light.

9. The radar image acquisition device according to any one of claims 1 to 8, characterized in that: It also includes a JTAG connector connected to the FPGA chip, and the JTAG connector is J30J-9ZKWJ.

10. The radar image acquisition device according to claim 9, characterized in that: It also includes a circuit board and a test box; wherein the circuit board is placed inside the test box, and is used to carry the FPGA chip, data storage circuit, FPD-LINK image receiving circuit, FPD-LINK image sending circuit, USB interface circuit and Ethernet interface circuit and perform circuit connection; the test box is provided with fixing holes for fixing the USB3.0 connector, Gigabit Ethernet connector, image transceiver connector and JTAG connector.

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