Diode packaging structure and diode
By designing the limit cavity in the diode packaging structure, the soldering surface of the chip is exposed, and the problem of difficulty in positioning the chip and the packaging frame is solved, and higher packaging accuracy is achieved.
Patent Information
- Application Number
- CN202421181052.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-27
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-27
AI Technical Summary
During the packaging process of diode chips, it is difficult to position the chip and the packaging frame, resulting in the upper and lower surfaces of the chip being masked by the packaging frame, making it difficult to determine whether the soldering area of the chip matches.
A diode packaging structure is designed, wherein the packaging frame includes a first packaging frame and a second packaging frame to form a limit cavity, the chip is arranged in the limit cavity, and the soldering surface of the chip is exposed to the limit cavity, so that the image capture Positioning detection tools such as probes can directly observe the soldering surface of the chip.
By revealing the soldering surface of the chip, it is possible to directly confirm whether the chip is placed in place, reducing the difficulty of positioning the chip and the packaging frame, and improving the accuracy of the packaging process.
Smart Images
Figure CN222462915U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a diode packaging structure and a diode. Background Art
[0002] In the packaging of diode chips, SMD (Surface Mounted Devices) packaging is widely used. SMD packaging includes seagull-foot patch form and flat-angle patch form. The overall view is that the chip is fixed in two packaging frames in the vertical direction, and then pin pads are brought out on the two packaging frames to realize the electrical connection between the chip and the circuit. This packaging process allows the diode chip to form a stacked structure of a lower packaging frame, a middle chip and an upper packaging frame, so that the welding fixing surface between the chip and the two packaging frames is in a relative position.
[0003] In the related art, because the welding areas of the chip fixing packaging frame are arranged on the upper and lower surfaces thereof, the SMD packaging process causes the upper and lower surfaces of the chip to be shielded by the two packaging frames and cannot be exposed. Therefore, in the positioning process before the chip is fixed, it is necessary to use a camera probe to extend into the area between the two packaging frames to confirm whether the welding area of the chip matches the welding area of the packaging frame. As a result, it is difficult to determine the positioning position of the diode before the chip and the packaging frame are fixedly connected during the packaging process. Utility Model Content
[0004] The main purpose of the utility model is to provide a diode packaging structure, aiming to solve the problem of difficulty in positioning a chip and a packaging frame.
[0005] To achieve the above object, the diode packaging structure includes:
[0006] A packaging frame, the packaging frame comprising a first packaging frame and a second packaging frame, the first packaging frame and the second packaging frame forming a limiting cavity; and
[0007] A chip is disposed in the limiting cavity, and a chip welding surface of the chip is exposed in the limiting cavity.
[0008] In one embodiment, the first packaging frame, the second packaging frame and the chip are arranged in parallel.
[0009] In one embodiment, the first packaging frame is provided with a first packaging surface, the second packaging frame is provided with a second packaging surface, and the first packaging surface, the second packaging surface and the chip welding surface are arranged on the same plane.
[0010] In one embodiment, the first packaging frame includes a chip welding section and a chip wrapping section, the chip wrapping section is arranged at one end of the chip welding section, and the chip welding section, the chip wrapping section and the second packaging frame form the limiting cavity;
[0011] The chip welding section is provided with the first packaging surface, the first packaging surface is provided with a first welding bump, the second packaging surface is provided with a second welding bump, and the first welding bump and the second welding bump can be connected to the chip welding surface.
[0012] In one embodiment, the first packaging surface is provided with at least two of the first welding bumps, the second packaging surface is provided with at least two of the second welding bumps, and the at least two of the first welding bumps and the at least two of the second welding bumps are arranged at intervals along the length extension direction of the chip;
[0013] Wherein, each of the first welding bumps is aligned with one of the second welding bumps.
[0014] In one embodiment, the first packaging frame, the second packaging frame, and the chip are spaced apart, and a hollow area is formed between the chip and the first packaging frame and the second packaging frame, and the hollow area is filled with a protection structure.
[0015] In one embodiment, the diode packaging structure includes a plurality of packaging frames and a plurality of chips; each of the chips is disposed in one of the limiting cavities; and a plurality of the packaging frames are arranged in parallel.
[0016] In one embodiment, the diode packaging structure includes at least two of the first packaging frames and one of the second packaging frames, and any two adjacent packaging frames form a limiting cavity; each of the limiting cavities accommodates one of the chips, and the chip welding surface of each of the chips is exposed in one of the limiting cavities.
[0017] In one embodiment, both the first packaging frame and the second packaging frame are conductive frames, so that a plurality of the chips can be arranged in series.
[0018] In one embodiment, the diode packaging structure further includes a protective layer, and the protective layer covers the first packaging frame, the second packaging frame and a surface layer of the chip.
[0019] The utility model also provides a diode, and the diode comprises the diode packaging structure.
[0020] The utility model proposes a diode packaging structure, which includes a packaging frame and a chip, the packaging frame includes a first packaging frame and a second packaging frame, the first packaging frame and the second packaging frame form a limiting cavity, the chip is arranged in the limiting cavity, and the chip welding surface of the chip is exposed in the limiting cavity. At this time, positioning detection tools such as camera probes can directly observe whether the structure used for positioning and fixing on the chip welding surface of the chip and the structure used for positioning and fixing on the packaging frame match in position, and can directly confirm whether the position of the chip is placed in place, thereby reducing the problem of difficulty in positioning the chip and the packaging frame. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.
[0022] Figure 1 A schematic structural diagram of an embodiment of a diode packaging structure provided by the utility model;
[0023] Figure 2 A schematic structural diagram of another embodiment of the diode packaging structure provided by the utility model;
[0024] Figure 3 This is a structural schematic diagram of another embodiment of the diode packaging structure provided by the utility model.
[0025] Description of Figure Numbers:
[0026] 10. Packaging frame; 101. First packaging frame; 102. Second packaging frame; 101a. First packaging surface; 102a. Second packaging surface; 1011. Chip welding section; 1021. Chip edging section; 103. First welding bump; 104. Second welding bump; 105. Protection structure; 106. Pin pad; 20. Chip; 20a. Chip welding surface.
[0027] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0029] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.
[0030] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the utility model.
[0031] See also Figures 1 to 3 , the diode packaging structure includes:
[0032] The packaging frame 10 includes a first packaging frame 101 and a second packaging frame 102, and a limiting cavity is formed between the first packaging frame 101 and the second packaging frame 102: and
[0033] The chip 20 is disposed in the limiting cavity, and the chip welding surface of the chip 20 is exposed in the limiting cavity.
[0034] The utility model proposes a diode packaging structure, which includes a packaging frame 10 and a chip 20. The packaging frame 10 includes a first packaging frame 101 and a second packaging frame 102. The first packaging frame 101 and the second packaging frame 102 form a limiting cavity. The chip 20 is arranged in the limiting cavity. The chip welding surface of the chip 20 is exposed in the limiting cavity. At this time, positioning detection tools such as camera probes can directly observe whether the structure used for positioning and fixing on the welding surface of the chip 20 and the structure used for positioning and fixing on the packaging frame 10 match in position, and can directly confirm whether the chip 20 is placed in place, thereby reducing the problem of difficulty in positioning the chip 20 and the packaging frame.
[0035] In this embodiment, the packaging frame 10 includes a first packaging frame 101 and a second packaging frame 102. The end of the first packaging frame 101 and the end of the second packaging frame 102 can be connected end to end to make the packaging frame 10 a closed-loop structure. The first packaging frame 101 and the second packaging frame 102 can also be spaced apart to form a certain distance between them. No limitation is made here, and it is only necessary that a limiting cavity can be formed between the first packaging frame 101 and the second packaging frame 102.
[0036] The chip 20 is mostly a cubic structure, and the overall surface can be seen as two upper and lower surfaces (larger surface area) and a complete peripheral surface (smaller surface area). In order to facilitate welding and packaging, welding areas can be set on the upper and lower surfaces of the chip 20. When the chip 20 is set in the limiting cavity, the chip welding surface of the chip 20 is completely exposed to the limiting cavity. When the chip 20 is packaged, positioning detection tools such as camera probes can directly observe whether the structure used for positioning and fixing on the chip welding surface of the chip 20 and the structure used for positioning and fixing on the packaging frame 10 match in position, and can directly confirm whether the chip 20 is placed in place, thereby reducing the problem of difficulty in positioning the chip 20 and the packaging frame; further, the chip 20 is exposed to the limiting cavity, which also means that the heat generated by the chip 20 during operation can be dissipated in both directions upward and downward, reducing impedance. At the same time, due to the increase in the heat dissipation area, the impact of thermal stress is reduced.
[0037] In one embodiment, if Figure 1 As shown, the first packaging frame 101 , the second packaging frame 102 and the chip 20 are arranged in parallel.
[0038] In this embodiment, the first packaging frame 101, the second packaging frame 102 and the chip 20 are arranged in parallel, that is, the upper and lower surfaces of the first packaging frame 101, the second packaging frame 102 and the chip 20 are arranged coplanarly. At this time, the surface height difference between the first packaging frame 101, the second packaging frame 102 and the chip 20 can approach zero, thereby reducing the height of the position occupied in the diode and facilitating the structural arrangement of the diode.
[0039] In one embodiment, if Figure 1 As shown, the first packaging frame 101 has a first packaging surface 101a, the second packaging frame 102 has a second packaging surface 102a, and the first packaging surface 101a, the second packaging surface 102a and the chip welding surface are coplanarly arranged.
[0040] In this embodiment, the first packaging frame 101 is provided with two first packaging surfaces 101a, and the second packaging frame 102 is provided with two second packaging surfaces 102a. The two first packaging surfaces 101a are two surfaces of the first packaging frame 101 along the height direction, and the two second packaging surfaces 102a are two surfaces of the second packaging frame 102 along the height direction. Because the upper and lower surfaces of the first packaging frame 101, the second packaging frame 102 and the chip 20 are coplanar, the welding surfaces of the first packaging frame 101, the second packaging frame 102 and the chip 20 are all exposed, further reducing the difficulty of the positioning process required to fix the chip 20.
[0041] In one embodiment, if Figure 1 As shown, the first packaging frame 101 includes a chip welding section 1011 and a chip wrapping section 1021. The chip wrapping section 1021 is arranged at one end of the chip welding section 1011. The chip welding section 1011, the chip wrapping section 1021 and the second packaging frame 102 form a limiting cavity.
[0042] The chip welding section 1011 is provided with a first packaging surface 101a, the first packaging surface 101a is provided with a first welding bump 103, the second packaging surface 102a is provided with a second welding bump 104, and the first welding bump 103 and the second welding bump 104 can connect the chip welding surface.
[0043] In the present embodiment, the cross-sectional shape of the first packaging frame 101 is an "L" shape, which includes a chip welding section 1011 and a chip edging section 1021, the chip edging section 1021 is arranged at the end of the chip welding section 1011, and the cross-sectional shape of the second packaging frame 102 is an "I" shape, and the second packaging frame 102 is arranged close to the other end of the chip edging section 1021, so that a limiting cavity is formed between the second packaging frame 102 and the first packaging frame 101, when the chip 20 is arranged in the limiting cavity, the end of the chip 20 is close to the chip edging section 1021, and the two side surfaces are close to the chip welding section 1011 and the second packaging surface 102a frame; further, the chip welding section 1011 is provided with a first packaging surface 101a, the first packaging surface 101a is provided with a first welding bump 103, and the second packaging surface 102a is provided with a second welding bump 104, so that the first welding bump 103 and the second welding bump 1 04 can reach the chip welding surface of the chip 20 as short as possible, and the pin pad 106 is arranged at the chip edge section 1021 and the end of the second packaging frame 102, which can conveniently connect the wire pins to realize the electrical connection between the chip 20 and the circuit. At the same time, whether the chip edge section 1021 and the chip 20 are arranged at intervals or abutted, the chip edge section 1021 provides a fixed basis for fixing the position of the chip 20, increases the fixing area of the chip 20, and improves the fixing stability of the chip 20; further, each first packaging surface 101a is provided with two first welding bumps 103, and each second packaging surface 102a is provided with two second welding bumps 104, and the two first welding bumps 103 and the two second welding bumps 104 are arranged at intervals along the length extension direction of the chip 20, so as to form multiple fixing points on the chip welding surface of the chip 20, further improving the fixing stability of the chip 20.
[0044] In one embodiment, if Figure 1 As shown, the first packaging frame 101 , the second packaging frame 102 and the chip 20 are arranged at intervals, and the chip 20 and the first packaging frame 101 and the second packaging frame 102 are spaced apart to form a hollow area, and the hollow area is filled with a protection structure 105 .
[0045] In this embodiment, the first packaging frame 101, the second packaging frame 102 and the chip 20 are arranged at intervals, and the chip 20 and the first packaging frame 101 and the second packaging frame 102 are spaced apart to form a hollow area, which surrounds the outer peripheral side of the chip 20. The hollow area can be filled with a protective structure 105 such as protective glue, silicone grease, etc. The protective structure 105 not only protects the chip 20, but also enhances the connection reliability between the chip 20 and the packaging frame 10.
[0046] In one embodiment, if Figure 2As shown, the diode packaging structure includes a plurality of packaging frames 10 and a plurality of chips 20; each chip 20 is disposed in a limiting cavity; and a plurality of packaging frames 10 are arranged in parallel.
[0047] In this embodiment, the diode packaging structure includes multiple packaging frames 10 and multiple chips 20. Each chip 20 is arranged in a limiting cavity. The multiple packaging frames 10 are arranged in parallel. Each packaging frame 10 can lead out a pair of pin pads 106. The wire pins connected to each pair of pin pads 106 can be connected to a circuit so that the multiple chips 20 are arranged in parallel. This can improve the current carrying capacity of a diode.
[0048] In one embodiment, if Figure 3 As shown, a packaging frame 10 includes at least two first packaging frames 101 and one second packaging frame 102, and any two adjacent packaging frames form a limiting cavity; each limiting cavity accommodates a chip 20, and the chip welding surface of each chip 20 is exposed in a limiting cavity.
[0049] In this embodiment, a packaging frame 10 includes two first packaging frames 101 and a second packaging frame 102, and the two first packaging frames 101 and the second packaging frame 102 are arranged in sequence and spaced apart, and a limiting cavity is formed between any two adjacent packaging frames, and each limiting cavity accommodates a chip 20, so that the structural packaging of multiple chips 20 can be realized in a diode, and because the chip welding surface of each chip 20 is exposed in a limiting cavity, the difficulty of positioning multiple chips 20 in a diode can be greatly reduced; it can be understood that in this embodiment, along the length direction of the diode packaging structure, the packaging frame 10 can be regarded as consisting of a first packaging frame 101 located at the head, at least one first packaging frame 101 located in the middle, and a second packaging frame 102 located at the tail, and in order to enhance the connectivity between the packaging frame 10 and the chip 20, each first packaging frame 101 in the middle can be provided with a plurality of first welding bumps 103 in a mirror relationship, so that the first packaging frame 101 in the middle can be connected to any first packaging frame 101 or second packaging frame 102 on its adjacent two sides.
[0050] In one embodiment, if Figure 3 As shown, the first packaging frame 101 and the second packaging frame 102 are both conductive frames, so that multiple chips 20 can be arranged in series.
[0051] In this embodiment, the first packaging frame 101 and the second packaging frame 102 are both conductive frames, so that a plurality of chips 20 are arranged in series, thereby improving the high voltage resistance of the diode.
[0052] In one embodiment, the diode packaging structure further includes a protection layer, and the protection layer covers the first packaging frame 101 , the second packaging frame 102 and the surface of the chip 20 .
[0053] In this embodiment, the diode packaging structure also includes a protective layer, which is an epoxy plastic sealing protective layer. The protective layer covers the first packaging frame 101, the second packaging frame 102 and the surface of the chip 20, thereby sealing the chip 20 and the packaging frame 10, and preventing the diode packaging structure from being affected by moisture, temperature changes, pollutants, mechanical shock, etc.
[0054] The utility model also provides a diode, which includes a diode packaging structure. The specific structure of the diode packaging structure refers to the above embodiments. Since the diode adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.
[0055] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.
Claims
1. A diode packaging structure, characterized in that: The diode packaging structure comprises: A packaging frame (10), the packaging frame (10) comprising a first packaging frame (101) and a second packaging frame (102), the first packaging frame (101) and the second packaging frame (102) forming a limiting cavity; and a chip (20), the chip (20) being arranged in the limiting cavity, the chip welding surface of the chip (20) being exposed in the limiting cavity.
2. The diode packaging structure according to claim 1, characterized in that: The first packaging frame (101), the second packaging frame (102) and the chip (20) are arranged in parallel.
3. The diode packaging structure according to claim 2, characterized in that: The first packaging frame (101) is provided with a first packaging surface (101a), the second packaging frame (102) is provided with a second packaging surface (102a), and the first packaging surface (101a), the second packaging surface (102a) and the chip welding surface are arranged on the same plane.
4. The diode packaging structure according to claim 3, characterized in that: The first packaging frame (101) comprises a chip welding section (1011) and a chip wrapping section (1021); the chip wrapping section (1021) is arranged at one end of the chip welding section (1011); the chip welding section (1011), the chip wrapping section (1021) and the second packaging frame (102) form the limiting cavity; The chip welding section (1011) is provided with the first packaging surface (101a), the first packaging surface (101a) is provided with a first welding bump (103), the second packaging surface (102a) is provided with a second welding bump (104), and the first welding bump (103) and the second welding bump (104) can be connected to the chip welding surface.
5. The diode packaging structure according to claim 1, characterized in that: The first packaging frame (101), the second packaging frame (102) and the chip (20) are arranged at intervals, and the chip (20) and the first packaging frame (101) and the second packaging frame (102) are spaced to form a hollow area, and the hollow area is filled with a protective structure (105).
6. The diode packaging structure according to any one of claims 1 to 5, characterized in that: The diode packaging structure comprises a plurality of packaging frames (10) and a plurality of chips (20); each of the chips (20) is arranged in one of the limiting cavities; and a plurality of the packaging frames (10) are arranged in parallel.
7. The diode packaging structure according to any one of claims 1 to 5, characterized in that: The packaging frame (10) comprises at least two of the first packaging frames (101) and one of the second packaging frames (102), and any two adjacent packaging frames form a limiting cavity; each of the limiting cavities accommodates a chip (20), and a chip welding surface of each of the chips (20) is exposed in the limiting cavity.
8. The diode packaging structure according to claim 7, characterized in that: The first packaging frame (101) and the second packaging frame (102) are both conductive frames, so that a plurality of the chips (20) can be arranged in series.
9. The diode packaging structure according to claim 7, characterized in that: The diode packaging structure further comprises a protective layer, wherein the protective layer covers the first packaging frame (101), the second packaging frame (102) and the surface layer of the chip (20).
10. A diode, characterized in that: The diode comprises the diode packaging structure according to any one of claims 1 to 9.