LDO (Low Dropout Regulator) regulating circuit and ranging chip

Abstract

The utility model provides an LDO (Low Dropout Regulator) regulating circuit and a ranging chip. The LDO regulating circuit comprises an amplifier, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a plurality of resistors connected in series and a plurality of switches, the negative input end of the amplifier is connected with a reference voltage, the positive input end of the amplifier is connected to two nodes in a plurality of resistors connected in series through two switches, the head ends of the plurality of resistors connected in series are connected with a first PMOS tube, the tail ends of the plurality of resistors connected in series are grounded, and only one of the two switches is kept closed; the output end of the amplifier is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is used as the output of the LDO regulating circuit; the value of the output voltage is adjusted by switching the on and off states of the two switches. Corresponding voltages are switched and output by controlling the working states of the plurality of switches, so that the flexible adjustment of the output voltage value is realized, the requirements of different applications on communication voltages can be met, and the application range of the chip is widened.

Description

Technical Field

[0001] The utility model relates to the technical field of light detection, in particular to an LDO regulating circuit and a distance measuring chip. Background Art

[0002] With the increasing maturity of DTOF (Direct Time-of-flight) technology and the promotion of its application market, its application in the consumer market is becoming more and more extensive, such as sweepers, mobile phones, VR / AR, etc.

[0003] The diverse application requirements bring different communication voltage requirements. In some system applications, the communication voltage is the chip power supply voltage (generally 3.0V), some are 1.8V, and some are 1.2V. Under this requirement, it is usually necessary to launch three chips with basically the same main functions and only different communication voltages to meet market demand. This method makes the application scope of the ranging chip very small, brings great labor and maintenance costs to the enterprise, and thus increases the cost of the chip. Utility Model Content

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide an LDO regulation circuit and a ranging chip, aiming to achieve flexible adjustment of the communication voltage based on the LDO architecture, meet different application requirements and reduce the cost of the chip.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] The utility model provides a first aspect of an LDO regulating circuit, which includes an amplifier, a first PMOS tube, a plurality of resistors connected in series, and a plurality of switches;

[0007] The negative input terminal of the amplifier is connected to a reference voltage, the positive input terminal of the amplifier is connected to two nodes of a plurality of resistors connected in series through two switches, the head ends of the plurality of resistors connected in series are connected to a first PMOS tube, the ends of the plurality of resistors connected in series are grounded, and only one of the two switches remains closed;

[0008] The output end of the amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, and the drain of the first PMOS tube serves as the output of the LDO regulation circuit; the output voltage value is adjusted by switching the closed and open states of the two switches.

[0009] In one embodiment, the positive input terminal of the amplifier is connected to two nodes of a plurality of resistors connected in series through two switches, specifically comprising:

[0010] The positive input terminal of the amplifier is connected to a first node among multiple resistors connected in series through a first switch; the positive input terminal of the amplifier is connected to a second node among multiple resistors connected in series through a second switch, and the second node is closer to the ground than the first node.

[0011] In one embodiment, the LDO regulation circuit further includes a third switch connected between the gate of the first PMOS tube and ground.

[0012] In one embodiment, only one of the first switch, the second switch, and the third switch is turned on at a time.

[0013] The second aspect of the utility model provides an LDO regulating circuit, which includes an amplifier, a first PMOS tube, and two resistors connected in series;

[0014] The negative input terminal of the amplifier is connected to a reference voltage, the positive input terminal of the amplifier is connected to the middle node of two series resistors, the head ends of the two series resistors are connected to the drain of the first PMOS tube, and the ends of the two series resistors are grounded;

[0015] The output end of the amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, and the drain of the first PMOS tube serves as the output of the LDO regulating circuit;

[0016] The reference voltage is output by a voltage generating module; the voltage generating module comprises: a current source, a plurality of resistors connected in series and two switches;

[0017] The current source is connected to a plurality of resistors connected in series and is arranged between a power source and a ground;

[0018] Two nodes among the multiple resistors connected in series are connected to the reference voltage through two switches respectively; only one of the two switches is closed at a time; and the output voltage value of the regulating circuit is changed by controlling the closed and open states of the two switches.

[0019] In one embodiment, the resistance values ​​of the two resistors connected to the drain of the first PMOS tube are the same; and the resistance values ​​of the multiple series resistors in the voltage generating module are the same.

[0020] In one embodiment, two nodes among the multiple resistors connected in series are connected to the reference voltage through two switches, specifically: a first node among the multiple resistors connected in series is connected to the reference voltage through a first switch, and a second node is connected to the reference voltage through a second switch; the first node is closer to the ground than the second node.

[0021] In one embodiment, the LDO regulation circuit further includes a third switch connected between the gate of the first PMOS tube and ground.

[0022] In one embodiment, the LDO regulation circuit further includes a second PMOS tube, a fourth switch, and a fifth switch, wherein the fourth switch is connected between the gate of the second PMOS tube and ground, and the fifth switch is connected between the gate of the second PMOS tube and a power supply; the fourth switch and the third switch maintain the same closed and open states, while the fifth switch and the third switch maintain opposite closed and open states.

[0023] The third aspect of the utility model provides a ranging chip, which includes the LDO adjustment circuit as described above, and also includes a controller and a register;

[0024] The controller is used to control the value of the register, thereby changing the closed or open state of the switch.

[0025] The beneficial effects of the utility model are: providing an LDO regulation circuit and a ranging chip, switching the output corresponding voltage by controlling the working states of multiple switches, realizing flexible adjustment of the output voltage value, so as to meet the communication voltage requirements of different applications and improve the application range of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0027] Figure 1 A circuit schematic diagram of an LDO regulation circuit in an embodiment provided by the utility model;

[0028] Figure 2 A circuit schematic diagram of an LDO regulating circuit in another embodiment provided by the utility model;

[0029] Figure 3 A circuit schematic diagram of a voltage generating module in another embodiment provided by the utility model;

[0030] Figure 4 This is a structural block diagram of the ranging chip provided by the utility model.

[0031] Description of Reference Numerals

[0032] Amplifier EA, first PMOS transistor PM1, resistor R, first switch S1, second switch S2, third switch S3, current source I1, second PMOS transistor PM2, fourth switch S4, fifth switch S5, LDO regulating circuit 10, controller 20, register 30. DETAILED DESCRIPTION

[0033] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it can be directly on the other component or indirectly on the other component. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, connection can be used for fixing or for circuit connection.

[0035] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0037] The utility model provides a LDO regulation circuit, please refer to Figure 1 , which includes an amplifier EA, a first PMOS tube PM1, a plurality of resistors R connected in series and a plurality of switches, wherein the negative input end of the amplifier EA is connected to a reference voltage, the positive input end of the amplifier EA is connected to two nodes of the plurality of resistors R connected in series through two switches, the head ends of the plurality of resistors R connected in series are connected to the first PMOS tube PM1, the ends of the plurality of resistors R connected in series are grounded, and only one of the two switches remains closed; the output end of the amplifier EA is connected to the gate of the first PMOS tube PM1, the source of the first PMOS tube PM1 is connected to a power supply, and the drain of the first PMOS tube PM1 serves as the output of the LDO regulation circuit; the output voltage value is adjusted by switching the closed and open states of the two switches.

[0038] In this embodiment, a reference voltage is input to the negative input terminal of the amplifier EA, and the value of the reference voltage remains unchanged during the LDO adjustment process. By setting a plurality of resistors R in series at the output terminal of the amplifier EA, corresponding switches are respectively connected between two nodes of the plurality of resistors R and the positive input terminal of the amplifier EA. The working states of the two switches are controlled by registers, and only one of the two switches is closed at the same time, so that the resistance value connected between the positive input terminal of the amplifier EA and the ground can be adjusted when different switches are closed, thereby adjusting the amplifier EA's amplification factor for the reference voltage. By switching the closed and open states of the two switches, the reference voltage is amplified with different amplification factors, and then different voltages are output at the output terminal, thereby realizing flexible adjustment of the output voltage, so that the requirements of different applications for communication voltage can be met, and the application range of the chip is improved.

[0039] Further, the positive input terminal of the amplifier EA is connected to two nodes of a plurality of resistors R connected in series through a first switch S1 and a second switch S2, respectively, wherein the positive input terminal of the amplifier EA is connected to a first node of a plurality of resistors R connected in series through the first switch S1; the positive input terminal of the amplifier EA is connected to a second node of a plurality of resistors R connected in series through the second switch S2, and the second node is closer to the ground than the first node.

[0040] In this embodiment, Figure 1 As shown, the positive input terminal of the amplifier EA is connected to a node A in a plurality of series resistors R through a first switch S1, and is also connected to a node B in a plurality of series resistors R through a second switch S2. When controlling the working state of the two switches, if the first switch S1 is closed and the second switch S2 is disconnected, it is recorded as the first state, and the first switch S1 is disconnected and the second switch S2 is closed, it is recorded as the second state. Because the voltages of the positive input terminal and the negative input terminal of the amplifier EA are equal, the voltage of A or B is equal to the reference voltage VREF. Since node B is closer to the ground than node A, there will be more resistors R connected between the positive input terminal of the amplifier EA and the ground in the first state than in the second state, which reduces the current flowing through the plurality of series resistors R, thereby reducing the amplification factor of the amplifier EA, that is, the output voltage of the LDO regulation circuit in the first state will be less than the output voltage in the second state, so that the effect of adjusting the output voltage is achieved by switching the working state of the two switches when the reference voltage remains unchanged. It should be understood that the number of the plurality of series resistors R and the node positions connected to the two switches can be flexibly set according to the actual voltage output requirements, and the utility model does not limit this.

[0041] Furthermore, the LDO regulating circuit further includes a third switch S3, and the third switch S3 is connected between the gate of the first PMOS tube PM1 and the ground. Whether the first PMOS tube PM1 is turned on can be controlled by controlling the working state of the third switch S3. Since the source of the first PMOS tube PM1 is connected to the power supply, when the third switch S3 is closed, the first PMOS tube PM1 is fully opened, so that the output terminal VOUT of the LDO regulating circuit is directly connected to the power supply, so that on the basis of amplifying the reference voltage by different multiples to achieve different voltage outputs, the communication voltage can also be satisfied as the chip power supply voltage, further broadening the application range of the chip and reducing the chip cost.

[0042] Specifically, only one of the first switch S1, the second switch S2, and the third switch S3 is turned on at a time. That is, the switches in the LDO regulation circuit are controlled by the register so that only one of the three switches is turned on at a time, and a voltage of a corresponding magnitude is output at the output end through the current path currently turned on, thereby obtaining three output voltages of different magnitudes.

[0043] Further, the LDO regulating circuit further includes a second PMOS tube PM2, a fourth switch S4, and a fifth switch S5, wherein the fourth switch S4 is connected between the gate of the second PMOS tube PM2 and the ground, and the fifth switch S5 is connected between the gate of the second PMOS tube PM2 and the power supply; the fourth switch S4 and the third switch S3 maintain the same closed and open states, while the fifth switch S5 and the third switch S3 maintain opposite closed and open states. By simultaneously setting the first PMOS tube PM1 and the second PMOS tube PM2, and making the fourth switch S4 and the third switch S3 always maintain the same working state, while the fifth switch S5 and the third switch S3 maintain opposite working states, when the third switch S3 is controlled to be closed, the fourth switch S4 is synchronously closed, and the fifth switch S5 is opened, so that the first PMOS tube PM1 and the second PMOS tube PM2 can be fully opened, ensuring that VOUT is directly connected to the power supply, and better ensuring the accuracy of voltage switching.

[0044] Preferably, in this embodiment, the resistance values ​​of the multiple series resistors R are the same to reduce the complexity of circuit elements and improve production efficiency. Figure 1 When VREF = 0.6V, the registers are used to control the closing and opening states of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4 and the fifth switch S5, respectively, and the VOUT output can be adjusted to the following three voltage values:

[0045] (1) When the first switch S1 is closed, the second switch S2 is open, and the third switch S3 is open (the fourth switch S4 is open, and the fifth switch S5 is closed):

[0046]

[0047] (2) When the first switch S1 is open, the second switch S2 is closed, and the third switch S3 is open (the fourth switch S4 is open, and the fifth switch S5 is closed):

[0048]

[0049] (3) When the first switch S1 is open, the second switch S2 is open, and the third switch S3 is closed (the fourth switch S4 is closed, and the fifth switch S5 is open), VOUT is directly connected to the power supply:

[0050] VOUT=VDD33=3.3V

[0051] The LDO regulation circuit provided in this embodiment amplifies the reference voltage with different amplification factors by switching the closed and open states of each switch, or directly connects the output end to the power supply, thereby outputting voltages of different sizes at the output end, thereby achieving flexible adjustment of the output voltage, so that the requirements of different applications for communication voltage can be met, thereby improving the application range of the chip.

[0052] The utility model also provides an LDO regulation circuit, see Figure 2 and Figure 3 , which includes an amplifier EA, a first PMOS tube PM1, and two series-connected resistors R; the negative input terminal of the amplifier EA is connected to a reference voltage, the positive input terminal of the amplifier EA is connected to the middle node of the two series-connected resistors R, the head ends of the two series-connected resistors R are connected to the drain of the first PMOS tube PM1, and the ends of the two series-connected resistors R are grounded; the output end of the amplifier EA is connected to the gate of the first PMOS tube PM1, the source of the first PMOS tube PM1 is connected to a power supply, and the drain of the first PMOS tube PM1 serves as the output of the LDO regulation circuit.

[0053] Among them, the reference voltage is output by a voltage generating module; the voltage generating module includes: a current source I1, a plurality of resistors R connected in series and two switches; the current source I1 is connected to the plurality of resistors R connected in series and is arranged between a power supply and a ground; two nodes of the plurality of resistors R connected in series are respectively connected to the reference voltage through two switches; only one of the two switches is closed at a time; and the output voltage value of the regulating circuit is changed by controlling the closed and open states of the two switches.

[0054] In this embodiment, a reference voltage is input to the negative input terminal of the amplifier EA, and the reference voltage is output by the voltage generation module. Two fixed series resistors R are set between the output terminal and the positive input terminal of the amplifier EA, so that the amplifier EA maintains a fixed amplification factor for the reference voltage. In the voltage generation module, a plurality of series resistors R are set, and corresponding switches are respectively connected between two nodes of the plurality of resistors R and the reference voltage output terminal. The reference voltage is generated by an ICTAT current that is independent of temperature flowing through the resistor R. The working states of the two switches are controlled by registers to derive the corresponding reference voltage, and only one of the two switches is closed at the same time, so that when different switches are closed, the resistance value connected between the reference voltage output terminal and the ground can be adjusted, thereby adjusting the output value of the reference voltage. By switching the closed and open states of the two switches, different reference voltages are amplified with the same amplification factor, and voltages of different magnitudes can also be output at the output terminal of the LDO adjustment circuit, so as to meet the requirements of different applications for communication voltage, improve the application range of the chip and reduce the chip cost.

[0055] Furthermore, two nodes among the multiple resistors R connected in series are connected to the reference voltage through two switches, wherein the first node among the multiple resistors R connected in series is connected to the reference voltage through a first switch S1, and the second node is connected to the reference voltage through a second switch S2; the first node is closer to the ground than the second node.

[0056] In this embodiment, Figure 3 As shown, the reference voltage output terminal VREF is connected to a node A in a plurality of series resistors R through a first switch S1, and is also connected to a node B in a plurality of series resistors R through a second switch S2. When controlling the working state of the two switches, if the first switch S1 is closed and the second switch S2 is disconnected, it is recorded as the first state, and the first switch S1 is disconnected and the second switch S2 is closed, it is recorded as the second state. Since node A is closer to the ground than node B, there will be fewer resistors R connected between the reference voltage output terminal VREF and the ground in the first state compared to the second state, which reduces the voltage division size, thereby reducing the reference voltage output to the amplifier EA, that is, the reference voltage in the first state will be less than the reference voltage in the second state, so that the reference voltage is adjusted by switching the working state of the two switches when the amplification factor remains unchanged, and the effect of adjusting the LDO output voltage is also achieved. It should be understood that the number of multiple series resistors R and the node positions connected to the two switches can be flexibly set according to the actual voltage output requirements, and the utility model does not limit this.

[0057] Furthermore, the LDO regulating circuit further includes a third switch S3, and the third switch S3 is connected between the gate of the first PMOS tube PM1 and the ground. Whether the first PMOS tube PM1 is turned on can be controlled by controlling the working state of the third switch S3. Since the source of the first PMOS tube PM1 is connected to the power supply, when the third switch S3 is closed, the first PMOS tube PM1 is fully opened, so that the output terminal VOUT of the LDO regulating circuit is directly connected to the power supply, so that on the basis of amplifying the reference voltage by different multiples to achieve different voltage outputs, it can also meet the situation that the communication voltage is the chip power supply voltage, further broadening the application range of the chip and reducing the chip cost.

[0058] Specifically, only one of the first switch S1, the second switch S2, and the third switch S3 is turned on at a time. That is, the switches in the LDO regulation circuit are controlled by the register so that only one of the three switches is turned on at a time, and a voltage of a corresponding magnitude is output at the output end through the current path currently turned on, thereby obtaining three output voltages of different magnitudes.

[0059] Further, the LDO regulating circuit further includes a second PMOS tube PM2, a fourth switch S4, and a fifth switch S5, wherein the fourth switch S4 is connected between the gate of the second PMOS tube PM2 and the ground, and the fifth switch S5 is connected between the gate of the second PMOS tube PM2 and the power supply; the fourth switch S4 and the third switch S3 maintain the same closed and open states, while the fifth switch S5 and the third switch S3 maintain opposite closed and open states. By simultaneously setting the first PMOS tube PM1 and the second PMOS tube PM2, and making the fourth switch S4 and the third switch S3 always maintain the same working state, while the fifth switch S5 and the third switch S3 maintain opposite working states, when the third switch S3 is controlled to be closed, the fourth switch S4 is synchronously closed, and the fifth switch S5 is opened, so that the first PMOS tube PM1 and the second PMOS tube PM2 can be fully opened, ensuring that VOUT is directly connected to the power supply, and better ensuring the accuracy of voltage switching.

[0060] Preferably, in this embodiment, the two resistors R connected to the drain of the first PMOS transistor PM1 have the same resistance value, and the multiple series resistors R in the voltage generating module have the same resistance value to reduce the complexity of circuit elements and improve production efficiency.

[0061] For example, Figure 2 and 3As shown, when the two resistors R connected to the drain of the first PMOS tube PM1 and the resistance values ​​of the multiple series resistors R in the voltage generating module are the same, the closing and opening states of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4 and the fifth switch S5 are respectively controlled by the register, and the VOUT output can be adjusted to the following three voltage values:

[0062] (1) When the first switch S1 is closed, the second switch S2 is open, and the third switch S3 is open (the fourth switch S4 is open, and the fifth switch S5 is closed), VREF outputs a reference voltage of 0.6V:

[0063]

[0064] (2) When the first switch S1 is open, the second switch S2 is closed, and the third switch S3 is open (the fourth switch S4 is open, and the fifth switch S5 is closed), VREF outputs a reference voltage of 0.9 V:

[0065]

[0066] (3) When the first switch S1 is open, the second switch S2 is open, and the third switch S3 is closed (the fourth switch S4 is closed, and the fifth switch S5 is open), VOUT is directly connected to the power supply:

[0067] VOUT=VDD33=3.3V

[0068] The LDO regulation circuit provided in this embodiment can amplify reference voltages of different sizes by a fixed multiple by switching the closed and open states of each switch, or directly connect the output end to a power supply to output voltages of different sizes at the output end, thereby realizing flexible adjustment of the output voltage, so that the requirements of different applications for communication voltage can be met, thereby improving the application range of the chip.

[0069] The utility model also provides a distance measurement chip, such as Figure 4 As shown, it includes a controller 10, a register 20 and the LDO regulating circuit 10 as described above, wherein the controller 10, the register 20 and the LDO regulating circuit 30 are connected in sequence, and the controller 10 is used to control the value of the register 20, thereby changing the closed and open states of the switch. Since the LDO regulating circuit 30 has been introduced in detail above, it will not be repeated here.

[0070] In summary, the utility model provides an LDO regulating circuit, which includes an amplifier, a first PMOS tube, a plurality of resistors connected in series, and a plurality of switches; the negative input end of the amplifier is connected to a reference voltage, the positive input end of the amplifier is connected to two nodes of the plurality of resistors connected in series through two switches, the head ends of the plurality of resistors connected in series are connected to the first PMOS tube, the ends of the plurality of resistors connected in series are grounded, and only one of the two switches remains closed; the output end of the amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, and the drain of the first PMOS tube serves as the output of the LDO regulating circuit; the value of the output voltage is adjusted by switching the closed and open states of the two switches. By controlling the working states of the plurality of switches to switch the output corresponding voltage, the flexible adjustment of the output voltage value is achieved, so that the requirements of different applications for communication voltage can be met, and the application range of the chip is improved.

[0071] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For technicians in the technical field to which the present invention belongs, several equivalent substitutions or obvious variations can be made without departing from the concept of the present invention, and the performance or use is the same, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. An LDO regulation circuit, characterized in that: It includes an amplifier, a first PMOS tube, a plurality of resistors connected in series, and a plurality of switches; The negative input terminal of the amplifier is connected to a reference voltage, the positive input terminal of the amplifier is connected to two nodes of a plurality of resistors connected in series through two switches, the head ends of the plurality of resistors connected in series are connected to a first PMOS tube, the ends of the plurality of resistors connected in series are grounded, and only one of the two switches remains closed; The output end of the amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, and the drain of the first PMOS tube serves as the output of the LDO regulation circuit; the output voltage value is adjusted by switching the closed and open states of the two switches.

2. The LDO regulation circuit according to claim 1, characterized in that: The positive input terminal of the amplifier is connected to two nodes of a plurality of resistors connected in series through two switches, specifically comprising: The positive input terminal of the amplifier is connected to a first node among multiple resistors connected in series through a first switch; the positive input terminal of the amplifier is connected to a second node among multiple resistors connected in series through a second switch, and the second node is closer to the ground than the first node.

3. The LDO regulating circuit according to claim 2, characterized in that: The LDO regulating circuit further includes a third switch connected between the gate of the first PMOS tube and ground.

4. The LDO regulation circuit according to claim 3, characterized in that: Only one of the first switch, the second switch, and the third switch is turned on at a time.

5. An LDO regulation circuit, characterized in that: It includes an amplifier, a first PMOS tube, and two resistors connected in series; The negative input terminal of the amplifier is connected to a reference voltage, the positive input terminal of the amplifier is connected to the middle node of two series resistors, the head ends of the two series resistors are connected to the drain of the first PMOS tube, and the ends of the two series resistors are grounded; The output end of the amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, and the drain of the first PMOS tube serves as the output of the LDO regulating circuit; The reference voltage is output by a voltage generating module; The voltage generation module includes: a current source, a plurality of resistors connected in series and two switches; The current source is connected to a plurality of resistors connected in series and is arranged between a power source and a ground; Two nodes among the multiple resistors connected in series are connected to the reference voltage through two switches respectively; only one of the two switches is closed at a time; and the output voltage value of the regulating circuit is changed by controlling the closed and open states of the two switches.

6. The LDO regulating circuit according to claim 5, characterized in that: The resistance values ​​of the two resistors connected to the drain of the first PMOS tube are the same; the resistance values ​​of the multiple series resistors in the voltage generating module are the same.

7. The LDO regulating circuit according to claim 5, characterized in that: Two nodes among the multiple resistors connected in series are connected to the reference voltage through two switches, specifically: the first node among the multiple resistors connected in series is connected to the reference voltage through a first switch, and the second node is connected to the reference voltage through a second switch; the first node is closer to the ground than the second node.

8. The LDO regulation circuit according to claim 5, characterized in that: The LDO regulating circuit further includes a third switch connected between the gate of the first PMOS tube and ground.

9. The LDO regulating circuit according to claim 8, characterized in that: The LDO regulation circuit also includes a second PMOS tube, a fourth switch, and a fifth switch, wherein the fourth switch is connected between the gate of the second PMOS tube and the ground, and the fifth switch is connected between the gate of the second PMOS tube and the power supply; the fourth switch and the third switch maintain the same closed and open states, while the fifth switch and the third switch maintain opposite closed and open states.

10. A distance measurement chip, characterized in that: The LDO regulating circuit according to any one of claims 1 to 9 further comprises a controller and a register; The controller is used to control the value of the register, thereby changing the closed or open state of the switch.

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