Semiconductor structure and chip structure
By increasing the width of the cutting channel region in the semiconductor structure and reducing the number of chip regions, and transferring the test metal conductive structure to the chip region, the problems of regular collapse and back collapse during the semiconductor cutting process are solved, and the chip products are improved rate and productivity.
Patent Information
- Application Number
- CN202421066994.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-05-13
AI Technical Summary
During the semiconductor cutting process, the positive collapse and back collapse phenomenon leads to low yield of finished products, affecting the quality of chip products.
By increasing the width of the cutting channel region in the semiconductor structure, the number of chip regions on the wafer is reduced, and the test metal conductive structure is transferred to the chip region to avoid edge collapse during the cutting process.
It effectively improves the yield of chip products, reduces the impact of edge collapse on chip quality, and improves production efficiency.
Smart Images
Figure CN222483350U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor devices, in particular to a semiconductor structure and a chip structure. Background Art
[0002] In the preparation process of CSP products, when using semiconductor wafer cutting pieces to cut into single pieces, front and back collapse phenomena will occur, resulting in low overall finished product yield.
[0003] Therefore, how to avoid affecting the yield of finished products during the semiconductor cutting process has become a technical problem that technical personnel in this field need to solve urgently. Utility Model Content
[0004] The utility model provides a semiconductor structure and a chip structure to solve the problem of affecting the yield of finished products during the semiconductor cutting process.
[0005] According to a first aspect of the present invention, there is provided a semiconductor structure, comprising:
[0006] A wafer, wherein the wafer comprises a plurality of mutually discrete chip regions, a scribe line region is provided between adjacent chip regions, and a width of the scribe line region is greater than a first threshold;
[0007] Functional circuits located in the chip area;
[0008] A test metal conductive structure is located within the scribe line area.
[0009] Optionally, the first threshold is 75 μm.
[0010] Optionally, in the wafer, a ratio between a width of the chip region and a width of the dicing road region is 20% to 26.7%.
[0011] Optionally, the test metal conductive structure includes:
[0012] A test pad and a metal lead connected to the test pad.
[0013] Optionally, the semiconductor structure further includes: a test structure located in the cutting path area; and the test pad is connected to the test structure through the metal lead.
[0014] Optionally, the semiconductor structure further includes: a plurality of bonding bumps located in the chip area.
[0015] According to a second aspect of the present invention, a chip structure is provided, comprising:
[0016] The semiconductor structure described in any one of the first aspects of the utility model is cut in the cutting street area, so that a plurality of chip areas are separated from each other to form a plurality of independent chip structures.
[0017] According to a third aspect of the present invention, there is provided a semiconductor structure, comprising:
[0018] A wafer, wherein the wafer comprises a plurality of discrete chip regions, and a dicing road region is provided between adjacent chip regions;
[0019] Functional circuits and test metal conductive structures located within the chip area.
[0020] Optionally, the width of the cutting street area is greater than a second threshold.
[0021] Optionally, the second threshold is: 55μm.
[0022] Optionally, in the wafer, a ratio between a width of the chip region and a width of the dicing road region is 14.67%-20%.
[0023] Optionally, the test metal conductive structure includes:
[0024] A test pad and a metal lead connected to the test pad.
[0025] Optionally, the semiconductor structure further includes: a test structure located in the cutting path area; and the test pad is connected to the test structure through the metal lead.
[0026] Optionally, the semiconductor structure further includes: a plurality of bonding bumps located in the chip area.
[0027] According to a fourth aspect of the present invention, a chip structure is provided, comprising:
[0028] The semiconductor structure described in any one of the third aspects of the present invention is cut in the cutting street area to separate several chip areas from each other to form several independent chip structures.
[0029] Compared with the prior art, the technical solution of the utility model has the following advantages:
[0030] The utility model provides a semiconductor structure, which relatively increases the width of the cutting zone and relatively reduces the number of chip areas on the wafer to ensure that the width of the cutting zone is greater than a first threshold value, thereby accommodating a test conductive structure and avoiding serious edge collapse caused by a cutting knife directly cutting a metal test conductive structure, and providing a cutting width and edge collapse width for a blade cutting the cutting zone in a subsequent cutting process, thereby avoiding the influence of edge collapse caused by cutting non-metallic semiconductor materials in the cutting zone on chip area products. Therefore, the technical solution provided by the utility model avoids the problem of poor yield of chip products due to positive collapse or back collapse caused by a blade cutting the cutting zone, thereby achieving the technical effect of increasing the number of good chips and improving production efficiency.
[0031] Furthermore, the utility model sets the ratio of the width of the chip area to the width of the cutting road area to 20% to 26.7%, and further controls the upper limit of the proportion of the width of the cutting road area under the condition that the cutting road area meets the first threshold value, thereby achieving the goal of ensuring and increasing the total number of good chips on a single wafer while relatively reducing the number of chips in a single wafer.
[0032] The utility model provides a semiconductor structure which avoids the occurrence of positive collapse or back collapse caused by the blade cutting the test metal conductive structure located in the cutting path area by transferring the test metal conductive structure to the chip area; at the same time, it provides space for the blade cutting and edge collapse of the cutting path area in the subsequent cutting process, thereby avoiding the influence of the blade cutting the semiconductor material in the cutting path area on the product yield, thereby improving the yield of the chip product.
[0033] Furthermore, the utility model also sets the ratio of the width of the chip area to the width of the cutting road area to: 14.67%-20%. Under the condition of ensuring product yield, it further controls the upper limit of the width ratio of the cutting road area, thereby achieving the effect of increasing the total number of good chips on a single wafer while relatively reducing the number of chips in a single wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0035] Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment;
[0036] Figure 2It is a structural schematic diagram of a semiconductor structure provided by an embodiment of the utility model;
[0037] Figure 3 is a structural schematic diagram of a semiconductor structure provided by another embodiment of the utility model;
[0038] Description of the reference numerals;
[0039] 1, 2, 3-semiconductor structure;
[0040] 10- Chip area;
[0041] 11- cutting area;
[0042] 12-Test pad;
[0043] 13-metal lead;
[0044] 14-bonding bump;
[0045] 20-chip area;
[0046] 21- cutting road area;
[0047] 22-test pad;
[0048] 23-metal lead;
[0049] 24-bonding bump;
[0050] 30-chip area;
[0051] 31- cutting road area;
[0052] 32-test pad;
[0053] 33-metal lead;
[0054] 34-Bonding bump. DETAILED DESCRIPTION
[0055] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0056] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The terms "on" and "above" and any of their variations are intended to describe positional relationships and do not represent a relationship of direct contact between the described objects.
[0057] As described in the background art, the cutting of semiconductors will affect the yield of finished products, which will be described in detail below with reference to the accompanying drawings.
[0058] Please refer to Figure 1 , Figure 1 A semiconductor structure 1 includes: a wafer, wherein the wafer includes a plurality of discrete chip areas 10, a cutting path area 11 between adjacent chip areas 10, functional circuits and a plurality of bonding bumps 14 distributed in the chip areas 10, and test pads 12 distributed in the cutting path area 11 and metal leads 13 connecting the test pads 12.
[0059] In order to ensure the yield of chips in the wafer, Figure 1 It can be seen from the figure that a scribe line area 11 with a relatively small width is usually provided, and the scribe line area 11 is often covered with the test pads 12 and metal leads 13 provided thereon.
[0060] After further repeated experiments and demonstrations, the inventor found that directly cutting the metal test pad 12 and the metal lead 13 will lead to a relatively serious edge collapse phenomenon. In addition, in order to reduce process costs, a cutting blade is used for cutting when cutting the wafer. When this cutting method is used in the process of cutting the wafer, directly cutting the metal often leads to more serious wafer front collapse or back collapse, thereby affecting the yield of the chip product. Furthermore, when a cutting knife is used to cut the cutting area, the non-metallic materials on the cutting area will also affect the yield of the finished product.
[0061] In order to solve the above problems, the inventor of the present application provides a semiconductor structure, comprising: a wafer, wherein the wafer comprises a plurality of discrete chip regions, wherein the chip regions are provided with functional circuits and bonding bumps; a cutting road region is provided between adjacent chip regions, wherein the cutting road region is provided with test pads and metal leads connecting the test pads; wherein the width of the cutting road region is greater than a first threshold value; and the width of the cutting road region refers to Figure 1 The width of the middle cutting street area along the arrangement direction of the chip areas arranged in the array.
[0062] In this solution, a certain cutting path area is reserved by setting a cutting path area with a width greater than the first threshold value, which not only accommodates the test pads and metal leads, but also takes into account the maximum cutting edge extension width of the chip product and the cutting width of the cutting knife, thereby avoiding damage to the chips in the chip area during the cutting process and improving the chip yield.
[0063] In another embodiment, a semiconductor structure is provided, including a wafer, wherein the wafer includes a plurality of discrete chip regions, the chip regions are formed with metal leads of functional circuits and test pads, and there are cutting track regions between adjacent chip regions.
[0064] In this solution, by relatively increasing the area of the chip area and transferring the metal leads of the test pad to the chip area, a certain cutting path area is reserved, taking into account the maximum cutting edge extension width and the cutting width of the cutting knife. It also avoids damage to the chips in the chip area during the cutting process and improves the chip yield.
[0065] The following specific embodiments are used to describe the technical solution of the utility model in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
[0066] Figure 2 is a schematic diagram of a semiconductor structure 2 provided by an embodiment of the utility model;
[0067] Please refer to Figure 2 The utility model provides a semiconductor structure 22, comprising: a wafer, wherein the wafer comprises a plurality of discrete chip areas 20, wherein a cutting road area 21 is provided between adjacent chip areas 20, and wherein the width of the cutting road area 21 is greater than a first threshold; a functional circuit located in the chip area 20; and a test metal conductive structure located in the cutting road area 21.
[0068] The technical solution provided by the utility model relatively increases the width of the cutting zone and relatively reduces the number of chip areas on the wafer to ensure that the width of the cutting zone is greater than a first threshold value, thereby avoiding the cutting knife directly cutting the test metal conductive structure of the cutting zone and providing sufficient cutting width and edge collapse width for the blade cutting the cutting zone in the subsequent cutting process. Therefore, the problem of poor yield of chip products caused by positive collapse or back collapse occurring when the blade cuts the cutting zone is solved.
[0069] The embodiments of the pad structure of the semiconductor chip for copper wire bonding packaging will be described in detail below in conjunction with the above drawings.
[0070] The semiconductor structure 2 comprises:
[0071] The wafer includes a plurality of mutually separated chip areas 20 , and a sawing road area 21 is provided between adjacent chip areas 20 , and a width d1 of the sawing road area 21 is greater than a first threshold.
[0072] In one embodiment, the scribe line region 21 includes a semiconductor structure 2 made of a non-metallic material such as a polymer resin.
[0073] The width of the scribe line region 21 refers to the minimum distance between mutually separated chip regions 20 .
[0074] In one embodiment, a plurality of chip regions 20 are arranged in an array. In this embodiment, the width of the scribe line region 21 refers to the spacing between adjacent chip regions 20 along the arrangement direction of the array.
[0075] The functional circuits are located in the chip area 20 .
[0076] The test metal conductive structure is located in the scribe line area 21. In one embodiment, the test metal conductive structure includes: a test pad 22 and a metal lead 23 connected to the test pad 22.
[0077] In one embodiment, the semiconductor structure 2 further includes: a test structure located in the scribe line area 21 ; and the test pad 22 is connected to the test structure through the metal lead 23 .
[0078] In one embodiment, the semiconductor structure 2 further includes: a plurality of bonding bumps 24 located in the chip region 20 .
[0079] Since cutting the metal test pads 22 and metal leads 23 disposed in the cutting area 21 may cause serious edge collapse, a cutting area 21 with a sufficient width is provided to prevent the cutting area 21 from directly cutting the test pads 22 and metal leads 23 .
[0080] Furthermore, since the cutting knife may cause edge collapse to a certain extent during the process of cutting the cutting area 21, even if the metal material is not cut, which may affect the quality of the chip after cutting, the necessary cutting width of the cutting knife and the extension width of the cutting edge collapse of the material of the cutting area 21 are reserved when cutting the cutting area 21. It can be seen that this embodiment widens the width of the cutting area 21 and provides a cutting area 21 with a width greater than the first threshold, thereby greatly improving the yield of chip products.
[0081] In one embodiment, the first threshold is 75 μm.
[0082] Specifically, the inventors have found through numerous repeated experiments and demonstrations that the metal conductive structure in the cutting zone 21 is about 45 μm wide, the width after cutting is about 35 μm, and the maximum extension width of the cutting edge chipping is 20 μm. Therefore, the minimum safe value of the width of the cutting zone 21 is 75 μm.
[0083] Therefore, when the width of the cutting path area 21 is set to 75μm, it not only accommodates the metal test pad 22 and the metal lead 23, but also reserves space for the cutting width of the cutting knife and the extension width of the cutting edge collapse of the cutting path area 21 material, thereby avoiding the problem of poor yield of chip products caused by the positive collapse or back collapse phenomenon caused by the blade cutting the cutting path area 21.
[0084] In order to further ensure the number of good products of a single chip in a single wafer, in one embodiment, in the wafer, the ratio between the width d2 of the chip area 20 and the width d1 of the dicing road area 21 is 20% to 26.7%.
[0085] When the ratio between the width of the chip area 20 and the width of the cutting road area 21 is less than 20%, the edge collapse still extends to the chip area 20. Therefore, in this embodiment, the ratio between the width of the chip area 20 and the width of the cutting road area 21 is set to be not less than 20%, which can ensure the quality of the single chip after cutting. When the ratio between the width of the chip area 20 and the width of the cutting road area 21 is less than 26.7%, the number of good products of a single chip cannot be taken into account. Although the yield rate is improved, the overall process effect is not worth the loss.
[0086] Therefore, in this embodiment, the ratio between the width of the chip area 20 and the width of the cutting road area 21 is set to 20% to 26.7%, which ensures the chip yield in a single wafer while also ensuring or increasing the number of good chips.
[0087] It can be seen that in this embodiment, the area of the chip area 20 is relatively sacrificed and the width of the cutting road area 21 is increased, which relatively reduces the number of chips in a single wafer. However, from the perspective of the wafer as a whole, the total number of good chips is increased.
[0088] Correspondingly, in one embodiment, the width of the cutting street area 21 is between 75 μm and 100 μm.
[0089] Taking the preparation of CSP chips using 8-inch wafers as an example, the technical solution provided by the utility model and its beneficial effects are explained; wherein, the size of a traditional CSP chip is: 370μm*370μm, where the size refers to the size of each chip area.
[0090] By adopting the technical solution provided by the above embodiment of the utility model, the width of the cutting road area 21 is increased from 60 μm to 80 μm-100 μm, and the number of chip areas 20 is relatively reduced, so as to increase the number of good finished products of the chip structure and improve the yield rate.
[0091] In a specific embodiment, about 170K chip areas are set on the wafer. In terms of process, when cutting traditional wafers, 3DAOI (3D Automated Optical Inspection) is used to detect defects, and the overall yield is 70%, among which the number of good products of independent chip structures is about 119K, and the finished product yield is low; the cost is high; and the process cycle time takes 15 days, which is inefficient and not conducive to mass production on industrial production lines. By adopting the technical solution provided by the aforementioned embodiment of the utility model, taking the increase of the width of the cutting road area from 60μm to 80μm as an example: experiments have proved that: for the independent CSP chips formed after cutting, the approximately 170K chip areas set on the wafer are reduced to 155K, and the number of chip areas set on the wafer is reduced by 8.7%, but the number of finished good products of the chip structure is increased from 119K to 148K, which is 29K more than the traditional structural design; the yield is increased from the original 70% to 95.5%, the yield is greatly improved, and the yield of good products in a single wafer is greatly increased; the production cycle time is reduced by 3 days, and the production cost is reduced by 30%, which greatly improves the production efficiency and industry competitiveness.
[0092] In another specific example, the size of a traditional CSP chip in an 8-inch wafer is 370μm*370μm. In terms of process, when cutting traditional wafers, 3DAOI is used to detect defects, and the overall yield is 60%. Among them, there are about 157K chips set on the wafer, and the number of good products of the independent chip structure is about 94.2K, and the finished product yield is low; the cost is high, the efficiency is low, and it is not conducive to mass production on industrial production lines.
[0093] By adopting the technical solution provided by the above embodiment of the utility model, the width of the cutting road area is increased from 60μm to 75μm, and the approximately 157K chips area 20 set on the wafer is reduced to 147K chips, but the number of good finished products of the chip structure is increased to 139.65K chips, and the good product rate is 95%. The yield rate is greatly improved, and the output of good products in a single wafer is greatly increased, which greatly improves production efficiency and industry competitiveness.
[0094] It can be seen that by adopting the technical solution provided by the aforementioned embodiment of the present invention, the CSP chip is improved, the number of chip areas is relatively reduced, but the number of good finished products of the chip structure is increased, and the chip product yield is improved.
[0095] In summary, a semiconductor structure 2 provided in this embodiment sets a cutting path area with a width greater than a first threshold by relatively increasing the width of the cutting path area and relatively reducing the number of chip areas. At the same time, it avoids the cutting path area directly cutting the test pad and the metal lead, and the cutting knife causing a certain degree of edge collapse in the process of cutting the cutting path area, thereby affecting the quality of the chip after cutting. Therefore, the technical solution provided in this embodiment avoids the problem of poor chip product yield caused by edge collapse and improves the chip product yield.
[0096] Furthermore, in this embodiment, by further controlling the upper limit of the proportion of the width of the cutting road area, the width of the cutting road area is increased while the area of the chip area is relatively sacrificed, and the number of chips in a single wafer is relatively reduced, thereby ensuring and increasing the total number of good chips on a single wafer. Therefore, the technical solution provided by this embodiment achieves the technical effect of increasing the number of good chips while improving the yield of chip products, greatly improving production efficiency.
[0097] According to an embodiment of the present invention, a method for forming a chip structure is also provided, comprising: providing a semiconductor structure 2 as in the aforementioned embodiment of the present invention; cutting the semiconductor structure 2 in the cutting road area to separate several chip areas from each other to form several independent chip structures.
[0098] In one embodiment, in the semiconductor packaging process, it is necessary to cut the chip area. In order to save costs, scribe dicing or blade dicing (or sawing) is usually adopted.
[0099] In one embodiment, the width of the scribe line region of the semiconductor structure 2 according to any one of the aforementioned embodiments of the present invention is between 75 μm and 100 μm.
[0100] In one embodiment, in the wafer, a ratio between a width of the chip region and a width of the scribe line region is 20% to 26.7%.
[0101] The method for forming a semiconductor structure 2 provided in this embodiment avoids the problem of poor chip product yield caused by edge collapse, thereby improving the chip product yield.
[0102] Furthermore, when the ratio between the width of the prepared chip area and the width of the cutting road area is between 20% and 26.7%, the total number of good chips on a single wafer is increased while the area of the chip area is relatively sacrificed and the width ratio of the cutting road area is increased, thereby relatively reducing the number of chips in a single wafer.
[0103] Therefore, the chip structure forming method provided in this embodiment improves the chip product yield rate while increasing the number of good chips and production efficiency.
[0104] Figure 3 It is a schematic diagram of a semiconductor structure provided by another embodiment of the utility model.
[0105] Please refer to Figure 3 The utility model provides a semiconductor structure 3, comprising: a wafer, wherein the wafer comprises a plurality of discrete chip areas 30, and a cutting road area 31 is provided between adjacent chip areas 30; and a functional circuit and a test metal conductive structure located in the chip area 30.
[0106] The technical solution provided by the utility model avoids the occurrence of positive collapse or back collapse caused by the blade cutting the test metal conductive structure located in the cutting path area by transferring the test metal conductive structure to the chip area; at the same time, it provides space for the blade cutting and edge collapse in the cutting path area in the subsequent cutting process, thereby improving the yield of the chip product.
[0107] The embodiments of the pad structure of the semiconductor chip for copper wire bonding packaging will be described in detail below in conjunction with the above drawings.
[0108] The semiconductor structure 3 includes a wafer. The wafer includes a plurality of discrete chip regions 30 . A scribe line region 31 is provided between adjacent chip regions 30 .
[0109] In one embodiment, the scribe line region 31 includes a semiconductor structure 3 made of a non-metallic material such as a polymer resin.
[0110] Functional circuits and test metal conductive structures are located in the chip area 30 .
[0111] In one embodiment, the test metal conductive structure includes: a test pad 32 and a metal lead 33 connected to the test pad 32 .
[0112] In one embodiment, the semiconductor structure 3 further includes: a test structure located in the scribe line area 31 ; and the test pad 32 is connected to the test structure through the metal lead 33 .
[0113] In one embodiment, the semiconductor structure 3 further includes: a plurality of bonding bumps 34 located in the chip region 30 .
[0114] In a preferred embodiment, the width r1 of the cutting street area 31 is greater than a second threshold.
[0115] Although the test metal conductive structure is transferred to the chip area 30 in this embodiment, the serious edge collapse caused by the cutting knife directly cutting the metal is avoided; however, since the cutting knife will also have a certain degree of edge collapse in the process of cutting the cutting area 31, which affects the quality of the chip after cutting, it is necessary to reserve enough necessary cutting width of the cutting knife when cutting the cutting area 31 and the extension width of the cutting edge collapse of the cutting area 31 material. Therefore, in order to further ensure the yield, in this embodiment, the width of the cutting area 31 is greater than the second threshold.
[0116] In one embodiment, the second threshold is 55 μm.
[0117] After a lot of repeated experiments and demonstrations, the inventors found that after the metal conductive structure in the cutting zone 31 is removed, the cutting width of the cutting zone 31 is about 35μm, and the maximum extension width of the cutting edge is 20μm, so the minimum safe value of the width of the cutting zone 31 is: 55μm.
[0118] Therefore, when the width of the scribe line region 31 is greater than the second threshold value of 55 μm, the yield of chip products can be improved.
[0119] Correspondingly, in one embodiment, in the wafer, the ratio between the width of the chip region 30r2 and the width r1 of the dicing street region 31 is 14.67%-20%.
[0120] While ensuring the necessary cutting width of the cutting knife when cutting the cutting area 31 and the cutting edge extension width of the cutting area 31 material to avoid cutting affecting the quality of the chip product, since the test metal conductive structures are all formed in the chip area 30, the space of the functional circuits of the chip area 30 is relatively squeezed. Therefore, it is necessary to increase the area of the chip area 30 to accommodate the test metal conductive structure. Therefore, in order to ensure that more chip areas 30 can be set on a single wafer to increase the number of good chips on a single wafer, it is necessary to control the proportion of the width of the cutting area 31 relative to the width of the chip area 30. Therefore, the utility model sets the ratio between the width of the chip area 30 and the width of the cutting area 31 to: 14.67%-20%.
[0121] Correspondingly, in one embodiment, the second threshold is 55 μm to 75 μm.
[0122] When the second threshold of the width of the cutting street area 31 is lower than 55μm, there will be a phenomenon of edge collapse extending to the chip area 30 when the cutting knife cuts the cutting street area 31. When the second threshold of the width of the cutting street area 31 is higher than 75μm, the number of good products of a single chip cannot be taken into account. Although the yield is improved, the overall process effect does not make up for the loss.
[0123] Taking the use of 8-inch wafers to prepare CSP chips as an example, the technical solution and product yield and number of good products provided by this embodiment are described. The size of a traditional CSP chip is: 370 μm*370 μm.
[0124] In a specific example, when traditional wafers are cut, 3DAOI is used to detect defects, and the overall yield is 70%. Among them, the number of finished products is reduced to 170K, and the number of good products of independent chip structures is about 119K. The finished product yield is low; the cost is high; and the process cycle time takes 15 days, which is inefficient and not conducive to mass production on industrial production lines.
[0125] By adopting the technical solution provided in the aforementioned embodiment of the utility model, the test metal conductive structure is completely transferred to the chip area 30. When the width of the cutting road area 31 is set to 55μm, the experiment proves that: the number of finished chips is reduced to 161K, but the number of finished good chip structures is increased to 152.95K, and the yield rate reaches 95%.
[0126] In summary, a semiconductor structure 3 provided in this embodiment avoids the occurrence of serious positive collapse or back collapse caused by blade cutting of the test metal conductive structure located in the cutting area by transferring the test metal conductive structure to the chip area; at the same time, the width of the cutting area is set to be greater than the second threshold, which provides space for the cutting and edge collapse of the cutting area by the blade in the subsequent cutting process, thereby avoiding the influence of the semiconductor material in the cutting area by the blade on the product yield, thereby improving the yield of the chip product.
[0127] Furthermore, in this embodiment, by further controlling the upper limit of the proportion of the width of the cutting road area, the total number of good chips on a single wafer is increased while the area of the chip area is relatively sacrificed and the width of the cutting road area is increased, thereby relatively reducing the number of chips in a single wafer.
[0128] Therefore, the technical solution provided in this embodiment avoids the problem of poor chip product yield caused by edge collapse, achieves the technical effect of increasing the number of good chips while improving the chip product yield, and greatly improves production efficiency.
[0129] According to one embodiment of the present invention, a method for forming a chip structure is also provided, comprising: providing a semiconductor structure 3 as described in any one of the aforementioned embodiments of the present invention; cutting the semiconductor structure 3 in the cutting road area to separate several chip areas from each other to form several independent chip structures.
[0130] In one embodiment, in the semiconductor packaging process, it is necessary to cut the chip area. In order to save costs, scribe dicing or blade dicing (or sawing) is usually adopted.
[0131] The method for forming a semiconductor structure 3 provided in this embodiment avoids the problem of poor chip product yield caused by edge collapse, thereby improving the chip product yield.
[0132] Furthermore, when the width of the prepared cutting street area: the second threshold is 55μm to 75μm, the width of the cutting street area can be relatively reduced while the area of the chip area is relatively increased, and the total number of good chips on a single wafer is also increased.
[0133] Therefore, the chip structure forming method provided in this embodiment improves the chip product yield rate and the number of good chips, thereby greatly improving production efficiency.
[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.
Claims
1. A semiconductor structure, characterized in that: include: A wafer, wherein the wafer comprises a plurality of mutually discrete chip regions, a scribe line region is provided between adjacent chip regions, and a width of the scribe line region is greater than a first threshold; The first threshold is 75 μm; Functional circuits located in the chip area; A test metal conductive structure is located within the scribe line area.
2. The semiconductor structure according to claim 1, characterized in that: In the wafer, the ratio between the width of the chip area and the width of the scribe line area is 20% to 26.7%.
3. The semiconductor structure according to claim 1, characterized in that: The test metal conductive structure comprises: A test pad and a metal lead connected to the test pad.
4. The semiconductor structure according to claim 3, characterized in that: Also includes: a test structure located in the scribe line area; The test pad is connected to the test structure through the metal lead.
5. The semiconductor structure according to claim 4, characterized in that: Also includes: A plurality of bonding bumps are located in the chip area.
6. A chip structure, characterized in that: include: The semiconductor structure according to any one of claims 1 to 5 is cut in the cutting street area to separate a plurality of chip areas from each other to form a plurality of independent chip structures.
7. A semiconductor structure, characterized in that: include: A wafer, wherein the wafer comprises a plurality of discrete chip regions, and a dicing zone region is provided between adjacent chip regions; Functional circuits and test metal conductive structures located within the chip area.
8. The semiconductor structure according to claim 7, characterized in that: The width of the scribe line region is greater than a second threshold.
9. The semiconductor structure according to claim 8, characterized in that: The second threshold value is: 55 μm.
10. The semiconductor structure according to claim 9, characterized in that: In the wafer, the ratio between the width of the chip area and the width of the scribe line area is 14.67%-20%.
11. The semiconductor structure according to claim 7, characterized in that: The test metal conductive structure comprises: A test pad and a metal lead connected to the test pad.
12. The semiconductor structure according to claim 11, characterized in that: Also includes: a test structure located in the scribe line area; The test pad is connected to the test structure through the metal lead.
13. The semiconductor structure according to claim 12, characterized in that: Also includes: A plurality of bonding bumps are located in the chip area.
14. A chip structure, characterized in that: include: The semiconductor structure according to any one of claims 7 to 13 is cut in the cutting street area to separate several chip areas from each other to form several independent chip structures.