High-stability anti-interference POR circuit
By using an anti-interference sub-circuit with a field effect transistor plus a capacitor in the POR circuit, the error reset problem caused by power supply fluctuations is solved, and a POR circuit with high stability and strong anti-interference ability is realized.
Patent Information
- Application Number
- CN202421099120.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-05-20
AI Technical Summary
When high-frequency noise interference or load current changes instantaneously, existing POR circuits are prone to generate error reset signals, affecting the normal operation of the circuit system.
By adding a capacitor to the field effect tube, the power supply voltage detection sub-circuit, anti-interference sub-circuit, flip-flop T2, inverter I NV3 and inverter I NV4 are combined to achieve the combination of nat i ve NMOS tube and capacitor. Anti-interference of POR circuit.
When there are glitches on the power supply, the POR output state remains unchanged, which significantly improves the stability and anti-interference ability of the circuit.
Smart Images
Figure CN222484682U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of POR circuits, and more specifically to a high-stability and anti-interference POR circuit. Background Art
[0002] The POR (power-on reset) circuit is widely used to generate a POR enable signal when the power is powered on or restarted after power failure, and set the initial state of modules with memory functions such as latches, registers, and triggers to ensure that the circuit system enters a normal working state.
[0003] At present, when the circuit system is working, due to the interference of high-frequency noise or the instantaneous large change of load current, the power supply signal will generate an upward or downward spike, thereby generating a false reset signal, affecting the normal operation of the entire circuit system. Utility Model Content
[0004] This manual provides a high-stability and anti-interference POR circuit, which uses a field effect tube plus a capacitor to achieve POR anti-interference. When there is a glitch fluctuation on the power supply, the POR output state remains unchanged, and it has high stability and strong anti-interference ability.
[0005] The embodiments of the present specification disclose a high-stability and anti-interference POR circuit, comprising a power supply voltage detection subcircuit, an anti-interference subcircuit, a trigger T2, an inverter I NV3 and an inverter I NV4 connected in series in sequence; the anti-interference subcircuit comprises a native NMOS tube MN4 and a capacitor C2, a drain of the native NMOS tube MN4 is connected to the power supply voltage detection subcircuit, a gate of the native NMOS tube MN4 is externally connected to a voltage terminal VDD, a source of the native NMOS tube MN4 is connected to the trigger T2 and the grounded capacitor C2, and the power supply voltage detection subcircuit is connected to the voltage terminal VDD.
[0006] In some embodiments of the present specification, the power supply voltage detection subcircuit includes a field effect transistor MP1, a field effect transistor MP2, a field effect transistor MP3, a field effect transistor MP4, a field effect transistor MP5, a field effect transistor MP6, a field effect transistor MP7, a field effect transistor MP8, a field effect transistor MP9, a field effect transistor MP10, a field effect transistor MP11, a field effect transistor MP12, a field effect transistor MP13, a field effect transistor MN1, a field effect transistor MN2, a field effect transistor MN3, a trigger T1, a capacitor C1, an inverter INV1, and an inverter I NV2, the gate of the field effect tube MP1, the gate of the field effect tube MP2, the gate of the field effect tube MP3, the gate of the field effect tube MP4, the gate of the field effect tube MP5, the gate of the field effect tube MP6, the gate of the field effect tube MP7, the gate of the field effect tube MP10, the gate of the field effect tube MP11, the gate of the field effect tube MP12 and the gate of the field effect tube MP13 are all grounded, the source of the field effect tube MP1 is connected to the voltage terminal VDD, the drain of the field effect tube MP1 is connected to the source of the field effect tube MP2, the drain of the field effect tube MP2 is connected to the source of the field effect tube MP3, the drain of the field effect tube MP3 is connected to the source of the field effect tube MP4 and the drain of the field effect tube MP9, the drain of the field effect tube MP4 is connected The electrode is connected to the source of the field effect tube MP5, the drain of the field effect tube MP5 is connected to the source of the field effect tube MP6 and the gate of the field effect tube MP8, the drain of the field effect tube MP6 is connected to the source of the field effect tube MP7, the drain of the field effect tube MP7 is connected to the gate of the field effect tube MN2, the drain and the gate of the field effect tube MN1, the source of the field effect tube MN1 and the source of the field effect tube MN2 are both grounded, the drain of the field effect tube MN2 is connected to the drain of the field effect tube MP8, the input end of the trigger T1 and the grounded capacitor C1, the source of the field effect tube MP8 is connected to the voltage terminal VDD, the source of the field effect tube MP9 is connected to the voltage terminal VDD, the output end of the trigger T1 is connected to the inverter I The input end of the inverter INV1 is connected to the gate of the field effect tube MP9 and the input end of the inverter INV2, the output end of the inverter INV2 is connected to the gate of the field effect tube MN3, the source of the field effect tube MN3 is grounded, the drain of the field effect tube MN3 is connected to the drain of the field effect tube MP13 and the drain of the native NMOS tube MN4, the source of the field effect tube MP13 is connected to the drain of the field effect tube MP12, the source of the field effect tube MP12 is connected to the drain of the field effect tube MP11, the source of the field effect tube MP11 is connected to the drain of the field effect tube MP10, and the source of the field effect tube MP10 is connected to the voltage terminal VDD.
[0007] In some embodiments of the present specification, the field effect transistor MP1, field effect transistor MP2, field effect transistor MP3, field effect transistor MP4, field effect transistor MP5, field effect transistor MP6, field effect transistor MP7, field effect transistor MP8, field effect transistor MP9, field effect transistor MP10, field effect transistor MP11, field effect transistor MP12 and field effect transistor MP13 are P-type inverse ratio transistors.
[0008] In some embodiments of the present specification, the field effect transistor MN1, the field effect transistor MN2 and the field effect transistor MN3 are N-type enhancement field effect transistors.
[0009] In some embodiments of the present specification, the trigger T1 and the trigger T2 are Schmitt triggers.
[0010] This manual can at least achieve the following beneficial effects:
[0011] The method of field effect tube plus capacitor is used to realize POR anti-interference. When there is burr fluctuation on the power supply, the POR output state remains unchanged, which has high stability and strong anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 The present invention is a functional block diagram of a high-stability, anti-interference POR circuit according to some embodiments of the present invention.
[0013] Figure 2 It is a schematic diagram of a high-stability and anti-interference POR circuit involved in some embodiments of the present utility model.
[0014] Figure 3 This is a schematic diagram of the POR output waveform involved in some embodiments of the present utility model. DETAILED DESCRIPTION
[0015] The technical solution of the present utility model is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present utility model is not limited to the following.
[0016] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the utility model. Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the utility model for which protection is sought, but merely represents the selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the utility model.
[0017] In the description of the present invention, it is necessary to understand that the terms indicating orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0018] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0019] In the present utility model, unless otherwise clearly specified and limited, if a first feature exists above or below a second feature, it may include that the first and second features are in direct contact, or it may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature is above, above and above the second feature, including that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. If a first feature exists below, below and below the second feature, it includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0020] The present invention is further described below in conjunction with the embodiments, which are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in the field without creative work are all within the protection scope of the present invention.
[0021] Please refer to the attached drawings, which show the structure of the embodiment selected for the present invention, which is for illustration only, and the patent application is not limited to this structure.
[0022] like Figure 1 and Figure 2 As shown, the embodiment of this specification discloses a high-stability and anti-interference POR circuit, including a power supply voltage detection sub-circuit, an anti-interference sub-circuit, a trigger T2, an inverter I NV3 and an inverter I NV4 which are connected in series in sequence; the anti-interference sub-circuit includes a native NMOS tube MN4 and a capacitor C2, the drain of the native NMOS tube MN4 is connected to the power supply voltage detection sub-circuit, the gate of the native NMOS tube MN4 is externally connected to the voltage terminal VDD, the source of the native NMOS tube MN4 is connected to the trigger T2 and the grounded capacitor C2, and the power supply voltage detection sub-circuit is connected to the voltage terminal VDD.
[0023] In some embodiments, the power supply voltage detection subcircuit includes a field effect transistor MP1, a field effect transistor MP2, a field effect transistor MP3, a field effect transistor MP4, a field effect transistor MP5, a field effect transistor MP6, a field effect transistor MP7, a field effect transistor MP8, a field effect transistor MP9, a field effect transistor MP10, a field effect transistor MP11, a field effect transistor MP12, a field effect transistor MP13, a field effect transistor MN1, a field effect transistor MN2, a field effect transistor MN3, a trigger T1, a capacitor C1, an inverter INV1, and an inverter I NV2, the gate of the field effect tube MP1, the gate of the field effect tube MP2, the gate of the field effect tube MP3, the gate of the field effect tube MP4, the gate of the field effect tube MP5, the gate of the field effect tube MP6, the gate of the field effect tube MP7, the gate of the field effect tube MP10, the gate of the field effect tube MP11, the gate of the field effect tube MP12 and the gate of the field effect tube MP13 are all grounded, the source of the field effect tube MP1 is connected to the voltage terminal VDD, the drain of the field effect tube MP1 is connected to the source of the field effect tube MP2, the drain of the field effect tube MP2 is connected to the source of the field effect tube MP3, the drain of the field effect tube MP3 is connected to the source of the field effect tube MP4 and the drain of the field effect tube MP9, the drain of the field effect tube MP4 is connected The electrode is connected to the source of the field effect tube MP5, the drain of the field effect tube MP5 is connected to the source of the field effect tube MP6 and the gate of the field effect tube MP8, the drain of the field effect tube MP6 is connected to the source of the field effect tube MP7, the drain of the field effect tube MP7 is connected to the gate of the field effect tube MN2, the drain and the gate of the field effect tube MN1, the source of the field effect tube MN1 and the source of the field effect tube MN2 are both grounded, the drain of the field effect tube MN2 is connected to the drain of the field effect tube MP8, the input end of the trigger T1 and the grounded capacitor C1, the source of the field effect tube MP8 is connected to the voltage terminal VDD, the source of the field effect tube MP9 is connected to the voltage terminal VDD, the output end of the trigger T1 is connected to the inverter I The input end of the inverter I NV1 is connected, the output end of the inverter I NV1 is connected to the gate of the field effect tube MP9 and the input end of the inverter I NV2, the output end of the inverter I NV2 is connected to the gate of the field effect tube MN3, the source of the field effect tube MN3 is grounded, the drain of the field effect tube MN3 is connected to the drain of the field effect tube MP13 and the drain of the field effect tube MN4, the source of the field effect tube MP13 is connected to the drain of the field effect tube MP12, the source of the field effect tube MP12 is connected to the drain of the field effect tube MP11, the source of the field effect tube MP11 is connected to the drain of the field effect tube MP10, and the source of the field effect tube MP10 is connected to the voltage terminal VDD.
[0024] In some embodiments, the field effect transistor MP1, field effect transistor MP2, field effect transistor MP3, field effect transistor MP4, field effect transistor MP5, field effect transistor MP6, field effect transistor MP7, field effect transistor MP8, field effect transistor MP9, field effect transistor MP10, field effect transistor MP11, field effect transistor MP12 and field effect transistor MP13 are P-type inverse ratio transistors.
[0025] In some embodiments, the field effect transistor MN1 , the field effect transistor MN2 , and the field effect transistor MN3 are N-type enhancement mode field effect transistors.
[0026] In some embodiments, the trigger T1 and the trigger T2 are Schmitt triggers.
[0027] Figure 1 It is a functional block diagram. The function of the power supply voltage detection subcircuit is to detect whether the VDD voltage exceeds the POR output flip threshold. The field effect tube and the capacitor form a power supply voltage jitter interference source elimination circuit (anti-interference subcircuit).
[0028] The specific working principle of the circuit is as follows:
[0029] Field effect transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP10, MP11, MP12 and MP13 are used as resistors, and because of their large impedance, they occupy a small layout area. MN4 is a native NMOS tube, and its threshold voltage is close to 0V, so when working normally, native NMOS tube MN4 can be turned on and work normally.
[0030] When the circuit starts, the initial state of the voltage of all nodes (N1~N7) is 0. When 0<VDD≤vth (MOS tube threshold voltage), as the power supply voltage VDD starts to rise from 0, when VDD is less than the threshold voltage of the field effect tube MN1, the field effect tube MN1 is turned off, the voltage of the N1 node follows VDD, the field effect tube MP8 is turned off, the N3 and N4 nodes are low level, the field effect tube MP9, the field effect tube MN3, and the native NMOS tube MN4 are turned on, and the por output follows VDD;
[0031] VDD continues to rise, and the field effect tube MN1 gradually starts to work. Since a current path is formed between VDD and GND at this time, the voltage difference between the N1 node and VDD gradually increases. When it increases to be greater than the vth of the field effect tube MP8, the field effect tube MP8 is turned on. At this time, the N6 node changes from a low level to a high level, the native NMOS tube MN4 is turned on, N7 is high, and the por output is low.
[0032] The anti-interference principle is as follows:
[0033] When the power supply voltage fluctuates, the por output waveform is as follows Figure 3 As shown, when the power supply voltage is suddenly higher than the normal working voltage, due to the existence of capacitor C2, the source voltage of the native NMOS tube MN4 cannot change suddenly, the gate-source voltage difference of MN4 is greater than 0, the native NMOS tube MN4 is turned on, N7 is high, and the por output is low, that is, the output state remains unchanged; if the power supply voltage is suddenly lower than the normal working voltage, due to the existence of capacitor C2, the source voltage of the native NMOS tube MN4 cannot change suddenly, the gate-source voltage difference of MN4 is much less than 0, the native NMOS tube MN4 is in the cut-off state, the N7 node potential remains high, and the por output is low, that is, the output state remains unchanged. When the power supply voltage is normal, since MN4 is a native NMOS tube, the threshold voltage is close to 0V, and the gate voltage is equal to the source voltage, it can be turned on and work normally, that is, the gate does not need to provide a voltage higher than VDD (if MN4 is an ordinary NMOS tube, the source voltage is VDD, in order to ensure its normal operation, it is necessary to add, for example, a charge pump circuit or other circuits to make the gate voltage much larger than the source VDD voltage, which makes the circuit structure complicated and increases the layout area).
[0034] The utility model adopts a native NMOS tube plus a capacitor combination, and the capacitance value requirement is relatively small, its stability and anti-interference ability are greatly increased, and the required device size is relatively small, which can greatly save layout area and reduce chip cost.
[0035] The above embodiments are used to illustrate the present invention, not to limit the present invention, so changes in the exemplified values or replacement of equivalent components should still fall within the scope of the present invention.
[0036] From the above detailed description, it can be understood by those skilled in the art that the present invention can indeed achieve the aforementioned objectives and is in compliance with the provisions of the Patent Law.
[0037] Although the preferred embodiments of the utility model have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the utility model. The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. It should be pointed out that any modifications, equivalent substitutions and improvements made within the spirit and principles of the utility model should be included in the scope of protection of the utility model.
Claims
1. A high stability and anti-interference POR circuit, characterized in that: It includes a power supply voltage detection subcircuit, an anti-interference subcircuit, a trigger T2, an inverter INV3 and an inverter INV4 which are connected in series in sequence; The anti-interference subcircuit includes a native NMOS tube MN4 and a capacitor C2, the drain of the native NMOS tube MN4 is connected to the power supply voltage detection subcircuit, the gate of the native NMOS tube MN4 is externally connected to the voltage terminal VDD, the source of the native NMOS tube MN4 is connected to the trigger T2 and the grounded capacitor C2, and the power supply voltage detection subcircuit is connected to the voltage terminal VDD.
2. The high stability and anti-interference POR circuit as claimed in claim 1, characterized in that: The power supply voltage detection subcircuit includes a field effect transistor MP1, a field effect transistor MP2, a field effect transistor MP3, a field effect transistor MP4, a field effect transistor MP5, a field effect transistor MP6, a field effect transistor MP7, a field effect transistor MP8, a field effect transistor MP9, a field effect transistor MP10, a field effect transistor MP11, a field effect transistor MP12, a field effect transistor MP13, a field effect transistor MN1, a field effect transistor MN2, a field effect transistor MN3, a trigger T1, a capacitor C1, an inverter INV1 and an inverter INV2, and the gate of the field effect transistor MP1, the gate of the field effect transistor MP2, and the gate of the field effect transistor MP3 The gates of the field effect transistor MP4, the gates of the field effect transistor MP5, the gates of the field effect transistor MP6, the gates of the field effect transistor MP7, the gates of the field effect transistor MP10, the gates of the field effect transistor MP11, the gates of the field effect transistor MP12 and the gates of the field effect transistor MP13 are all grounded, the source of the field effect transistor MP1 is connected to the voltage terminal VDD, the drain of the field effect transistor MP1 is connected to the source of the field effect transistor MP2, the drain of the field effect transistor MP2 is connected to the source of the field effect transistor MP3, the drain of the field effect transistor MP3 is connected to the source of the field effect transistor MP4 and the field effect transistor The drain of the field effect transistor MP9 is connected, the drain of the field effect transistor MP4 is connected to the source of the field effect transistor MP5, the drain of the field effect transistor MP5 is connected to the source of the field effect transistor MP6 and the gate of the field effect transistor MP8, the drain of the field effect transistor MP6 is connected to the source of the field effect transistor MP7, the drain of the field effect transistor MP7 is connected to the gate of the field effect transistor MN2, the drain and gate of the field effect transistor MN1, the source of the field effect transistor MN1 and the source of the field effect transistor MN2 are both grounded, the drain of the field effect transistor MN2 is connected to the drain of the field effect transistor MP8, the input of the trigger T1 The input end is connected to the grounded capacitor C1, the source of the field effect transistor MP8 is connected to the voltage end VDD, the source of the field effect transistor MP9 is connected to the voltage end VDD, the output end of the trigger T1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the gate of the field effect transistor MP9 and the input end of the inverter INV2, the output end of the inverter INV2 is connected to the gate of the field effect transistor MN3, the source of the field effect transistor MN3 is grounded, the drain of the field effect transistor MN3 is connected to the drain of the field effect transistor MP13 and the drain of the native NMOS transistor MN4, the source of the field effect transistor MP13 is connected to the drain of the field effect transistor MP12, the source of the field effect transistor MP12 is connected to the drain of the field effect transistor MP11, the source of the field effect transistor MP11 is connected to the drain of the field effect transistor MP10, and the source of the field effect transistor MP10 is connected to the voltage end VDD.
3. The high stability and anti-interference POR circuit as claimed in claim 2, characterized in that: The field effect transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12 and MP13 are P-type inverse ratio transistors.
4. The high stability and anti-interference POR circuit as claimed in claim 2, characterized in that: The field effect transistor MN1, the field effect transistor MN2 and the field effect transistor MN3 are N-type enhancement field effect transistors.
5. The high stability and anti-interference POR circuit as claimed in claim 2, characterized in that: The trigger T1 and the trigger T2 are Schmitt triggers.