BMS port control circuit

Abstract

The utility model discloses a BMS port control circuit comprising an MCU control circuit (1), the MCU control circuit (1) is connected with a charging and discharging common circuit (2), and the charging and discharging common circuit (2) is connected with a discharging main loop (3) and a charging main loop (4); the charging and discharging common circuit (2) comprises an NMOS tube M1, an NMOS tube M3, a PMOS tube Q40, a voltage-regulator tube DZ7, a resistor R144, a resistor R146, a resistor R150, a resistor R159, a resistor R167, a resistor R170 and a capacitor C66, one end of the resistor R167 is connected with the MCU control circuit (1), the other end of the resistor R167 is connected with a grid electrode of the PMOS tube Q40 and one end of the resistor R170, and a source electrode of the PMOS tube Q40 is connected with the other end of the resistor R170 and the discharging main loop (3); according to the utility model, the discharging main loop and the charging main loop can be switched on and switched off through the charging and discharging common circuit, the circuit layout is simple, and the maintenance is facilitated.

Description

Technical Field

[0001] The utility model relates to the field of BMS circuits, in particular to a BMS sub-port control circuit. Background Art

[0002] BMS stands for Battery Management System. It is a device that monitors the status of energy storage batteries. It is mainly used for intelligent management and maintenance of each battery unit, preventing overcharging and over-discharging of the battery, extending the battery life, and monitoring the battery status. At present, the BMS battery management system performs charging and discharging through independent circuits, so it requires independent ports and circuits for control, resulting in many internal components and complex circuits in the system, which is not conducive to inspection and maintenance. Utility Model Content

[0003] The purpose of the utility model is to provide a BMS split-port control circuit. The utility model can turn on and off the discharge main circuit and the charging main circuit through the charge-discharge common circuit, and the circuit layout is simple and convenient for inspection and maintenance.

[0004] The technical solution of the utility model: a BMS split-port control circuit, including an MCU control circuit, the MCU control circuit is connected to a charge-discharge common circuit, the charge-discharge common circuit is connected to a discharge main circuit and a charge main circuit; the charge-discharge common circuit includes an NMOS tube M1, an NMOS tube M3, a PMOS tube Q40, a voltage regulator tube DZ7, a resistor R144, a resistor R146, a resistor R150, a resistor R159, a resistor R167, a resistor R170 and a capacitor C66, one end of the resistor R167 is connected to the MCU control circuit, the other end of the resistor R167 is connected to the gate of the PMOS tube Q40 and one end of the resistor R170, and the source of the PMOS tube Q40 is connected to the capacitor C66. The other end of the resistor R170 is connected to the discharge main circuit, the drain of the PMOS tube Q40 is connected to the negative electrode of the voltage regulator tube DZ7 and one end of the resistor R159, and the positive electrode of the voltage regulator tube DZ7 and the other end of the resistor R159 are connected to the battery pack; the source electrodes of the NMOS tubes M1 and M3 are both connected to the battery pack, the gate of the NMOS tube M1 is connected to the signal output ends of the charging main circuit and the discharging main circuit through the resistor R144, the gate of the NMOS tube M3 is connected to the signal output ends of the charging main circuit and the discharging main circuit through the resistor R146, the drain electrodes of the NMOS tubes M1 and M3 are both connected to the charging main circuit, the discharging main circuit and one end of the resistor R150, and the other end of the resistor R150 is grounded through the capacitor C66.

[0005] In the above-mentioned BMS split-port control circuit, the MCU control circuit includes an NMOS tube Q43, a resistor R177, a resistor R113 and a diode D23; the source of the NMOS tube Q43 is grounded, the gate of the NMOS tube Q43 is connected to one end of the resistor R113 and one end of the resistor R177, the other end of the resistor R113 is grounded, the other end of the resistor R177 is connected to the cathode of the diode D23, and the anode of the diode D23 is connected to the MCU signal control terminal.

[0006] In the above-mentioned BMS sub-port control circuit, the main discharge circuit includes resistor R13, resistor R14, resistor R145, resistor R147, resistor R161, resistor R163, resistor R166, resistor R172, diode D16, diode D17, diode D19, diode D20, NMOS tube Q3, NMOS tube M2, NMOS tube M4, capacitor C65, capacitor C67, capacitor C68, PNP transistor Q41, TVS tube TVS6, T VS tube TVS7 and TVS tube TVS8; one end of the resistor R172 is connected to the discharge control signal output end, the other end of the resistor R172 is connected to the cathode of the diode D19 and the emitter of the PNP transistor Q41, the anode of the diode D19 is connected to the anode of the diode D17, the base of the PNP transistor Q41 is connected to one end of the resistor R166, the other end of the resistor R166 is connected to the battery pack, the cathode of the diode D20 and one end of the capacitor C68, the anode of the diode and the base of the capacitor C68 The other end is grounded; the collector of the PNP transistor Q41 is connected to the positive electrode of the diode D17, one end of the resistor R147 and one end of the resistor R145, the other ends of the resistor R147 and the resistor R145 are respectively connected to the gates of the NMOS tube M2 and the NMOS tube M4, the source of the NMOS tube M2 and the NMOS tube M4 is connected to the positive output of the battery pack, and the drain of the NMOS tube M2 and the NMOS tube M4 is connected to the drain of the NMOS tube M1, the drain of the NMOS tube M3 and the charging main circuit; One end of the capacitor C65, one end of the TVS tube TVS6 and one end of the TVS tube TVS7 are connected to the drain of the NMOS tube M1, the drain of the NMOS tube M3 and the main charging circuit, and the other end of the capacitor C65, the other end of the TVS tube TVS6 and the other end of the TVS tube TVS7 are connected to the positive output electrode of the battery pack; one end of the capacitor C67, the TVS tube TVS8 and the resistor R161 are connected to the positive output electrode of the battery pack, and the other ends of the capacitor C67, the TVS tube TVS8 and the resistor R161 are grounded.

[0007] The aforementioned BMS split-port control circuit also includes a voltage regulator DZ6 and a resistor R162. The negative electrode of the voltage regulator DZ6 and one end of the resistor R162 are connected to the collector of the PNP transistor Q41, and the positive electrode of the voltage regulator DZ6 and the other end of the resistor R162 are connected to the positive output electrode of the battery pack.

[0008] The aforementioned BMS split-port control circuit also includes a resistor R13, a resistor R14, a resistor R15, a diode D16, a voltage regulator DZ11 and an NMOS tube Q3; one end of the resistor R13 is connected to the negative output electrode of the battery pack. The other end of the resistor R13 is connected to the positive electrode of the diode D16, the negative electrode of the diode D16 is connected to the gate of the NMOS tube Q3, one end of the resistor R15 and the negative electrode of the voltage regulator DZ11, the source of the NMOS tube Q3, the other end of the resistor R15 and the positive electrode of the voltage regulator DZ11 are connected to the positive output electrode of the battery pack; the drain of the NMOS tube Q3 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the resistor R145 and the resistor R147.

[0009] In the above-mentioned BMS split-port control circuit, the charging main circuit includes a resistor R20, a resistor R74, a resistor R178, a resistor R181, a resistor R182, a resistor R183, a resistor R184, a capacitor C69, a capacitor C71, a PNP transistor Q44, an NPN transistor Q45, an NMOS tube M10, a diode D25, a diode D26, a diode D27, a voltage regulator tube DZ10, a TVS tube TVS9 and a TVS tube TVS10; one end of the resistor R20 is connected to The other end of the resistor R20 is connected to the emitter of the PNP transistor Q44, the anode of the diode D25, the anode of the diode D26, one end of the resistor R178 and the emitter of the NPN transistor Q45. The collector of the PNP transistor Q44 is connected to one end of the resistor R182. The other end of the resistor R182 is connected to the gate of the NMOS tube M10. The base of the NPN transistor Q44 is connected to one end of the resistor R185. The cathode of the diode D25 is connected to the resistor R144 and The resistor R146 and the cathode of the diode D26 are connected to one end of the capacitor C69 and one end of the resistor R184, the other end of the capacitor C69 is connected to the other end of the resistor R185 and the battery pack, the other end of the resistor R178 is connected to the base of the NPN transistor Q45 and the other end of the resistor R184, the collector of the NPN transistor Q45 is connected to the cathode of the diode D27, the anode of the diode D27 is connected to one end of the resistor R183, and the other end of the resistor R183 is connected to the resistor R182; the NMOS tube M1 The drain of NMOS tube M0 is connected to one end of TVS tube TVS9 and the main discharge circuit, the source of NMOS tube M10 is connected to the other end of TVS tube TVS9, the positive electrode of voltage regulator tube DZ10, one end of resistor R181, one end of capacitor C71, one end of TVS tube TVS10, one end of resistor R74 and the input end of the charger, the negative electrode of voltage regulator tube DZ10 and the other end of resistor R181 are connected to resistor R182, and the other end of capacitor C71, the other end of TVS tube TVS10 and the other end of resistor R74 are grounded.

[0010] In the aforementioned BMS port control circuit, the collector of the PNP transistor Q44 is connected to the anode of the diode D24, and the PNP transistor Q44 is connected to the resistor R182 via the diode D25.

[0011] Compared with the prior art, when the signal output end of the discharge main circuit of the utility model outputs a high-level discharge signal, the MCU control circuit outputs a high-level signal to control the PMOS tube Q40 to be turned on, and the high-level discharge signal reaches the gates of the NMOS tubes M1 and M3 through the PMOS tube Q40, the resistor R144 and the resistor R146, and the NMOS tubes M1 and M3 are turned on. The current of the battery pack enters the discharge main circuit through the NMOS tubes M1 and M3 to realize discharge. When the signal output end of the discharge main circuit outputs a low-level discharge stop signal, the NMOS tubes M1 and M3 are turned off, and the discharge is completed. When the signal output end of the charging main circuit outputs a high-level charging signal, the high-level discharge signal reaches the gates of the NMOS tubes M1 and M3 through the resistors R144 and R146, and the NMOS tubes M1 and M3 are turned on. The current of the charging main circuit enters the battery pack through the NMOS tubes M1 and M3 to realize charging. When the signal output end of the charging main circuit outputs a low-level charging stop signal, the NMOS tubes M1 and M3 are turned off, and the charging stops. The discharge main circuit and the charging main circuit are turned on and off by the charge-discharge common circuit, and the circuit layout is simple and convenient for inspection and maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of the utility model;

[0013] Figure 2 It is a structural schematic diagram of the charging and discharging common circuit of the utility model;

[0014] Figure 3 It is a structural schematic diagram of the MCU control circuit of the utility model;

[0015] Figure 4 It is a structural schematic diagram of the main discharge circuit of the utility model;

[0016] Figure 5 It is a structural schematic diagram of the main charging circuit of the utility model.

[0017] The markings in the attached figure are: 1-MCU control circuit; 2-charging and discharging common circuit; 3-discharging main circuit; 4-charging main circuit. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with the accompanying drawings and embodiments, but they are not intended to limit the present invention.

[0019] Embodiment: A BMS port control circuit, as shown in the attached Figure 1 As shown, it includes an MCU control circuit 1, the MCU control circuit 1 is connected to a charge and discharge common circuit 2, and the charge and discharge common circuit 2 is connected to a discharge main circuit 3 and a charge main circuit 4; as shown in the attached Figure 1 As shown, the charge and discharge common circuit 2 includes an NMOS tube M1, an NMOS tube M3, a PMOS tube Q40, a voltage regulator tube DZ7, a resistor R144, a resistor R146, a resistor R150, a resistor R159, a resistor R167, a resistor R170 and a capacitor C66, one end of the resistor R167 is connected to the MCU control circuit 1, the other end of the resistor R167 is connected to the gate of the PMOS tube Q40 and one end of the resistor R170, the source of the PMOS tube Q40 is connected to the other end of the resistor R170 and the discharge main loop 3, the drain of the PMOS tube Q40 is connected to the negative electrode of the voltage regulator tube DZ7 and one end of the resistor R159, the positive electrode of the PMOS tube Q40 and the voltage regulator tube DZ7 are connected. The source of the NMOS tube M1 and the source of the NMOS tube M3 are connected to the battery pack, the gate of the NMOS tube M1 is connected to the signal output end of the charging main circuit 4 and the discharging main circuit 3 through the resistor R144, the gate of the NMOS tube M3 is connected to the signal output end of the charging main circuit 4 and the discharging main circuit 3 through the resistor R146, the drain of the NMOS tube M1 and the drain of the NMOS tube M3 are connected to the charging main circuit 4, the discharging main circuit 3 and one end of the resistor R150, and the other end of the resistor R150 is grounded through the capacitor C66; as shown in the attached figure Figure 3 As shown, the MCU control circuit 1 includes an NMOS tube Q43, a resistor R177, a resistor R113 and a diode D23; the source of the NMOS tube Q43 is grounded, the gate of the NMOS tube Q43 is connected to one end of the resistor R113 and one end of the resistor R177, the other end of the resistor R113 is grounded, the other end of the resistor R177 is connected to the cathode of the diode D23, and the anode of the diode D23 is connected to the MCU signal control terminal. When there is a backwash current entering the charge and discharge common circuit from the discharge main circuit, the MCU signal control terminal outputs a high level at this time to turn off the NMOS tube Q43, thereby disconnecting the PMOS tube Q40, thereby disconnecting the NMOS tube M1 and the NMOS tube M, and effectively preventing current backcharging; as shown in the attached Figure 4As shown, the discharge main circuit 3 includes a resistor R13, a resistor R14, a resistor R145, a resistor R147, a resistor R161, a resistor R163, a resistor R166, a resistor R172, a diode D16, a diode D17, a diode D19, a diode D20, an NMOS tube Q3, an NMOS tube M2, an NMOS tube M4, a capacitor C65, a capacitor C67, a capacitor C68, a PNP-type triode Q41, a TVS tube TVS6, a TVS tube TVS7 and a TVS tube TVS8; one end of the resistor R172 is connected to the discharge control signal output end, and the The other end is connected to the cathode of the diode D19 and the emitter of the PNP transistor Q41, the anode of the diode D19 is connected to the anode of the diode D17, the base of the PNP transistor Q41 is connected to one end of the resistor R166, the other end of the resistor R166 is connected to the battery pack, the cathode of the diode D20 and one end of the capacitor C68, the anode of the diode and the other end of the capacitor C68 are grounded; the collector of the PNP transistor Q41 is connected to the anode of the diode D17, one end of the resistor R147 and one end of the resistor R145, the other ends of the resistor R147 and the resistor R145 are respectively connected to the NMOS transistor M 2 and the gate of the NMOS tube M4, the source of the NMOS tube M2 and the NMOS tube M4 are connected to the positive output of the battery pack, and the drain of the NMOS tube M2 and the NMOS tube M4 are connected to the drain of the NMOS tube M1, the drain of the NMOS tube M3 and the main charging circuit 4; one end of the capacitor C65, one end of the TVS tube TVS6 and one end of the TVS tube TVS7 are connected to the drain of the NMOS tube M1, the drain of the NMOS tube M3 and the main charging circuit 4, and the other end of the capacitor C65, the other end of the TVS tube TVS6 and the other end of the TVS tube TVS7 are connected to the positive output of the battery pack; the capacitor C 67, one end of the TVS tube TVS8 and the resistor R161 are connected to the positive output electrode of the battery pack, and the other ends of the capacitor C67, the TVS tube TVS8 and the resistor R161 are grounded; it also includes a voltage regulator tube DZ6 and a resistor R162, the negative electrode of the voltage regulator tube DZ6 and one end of the resistor R162 are connected to the collector of the PNP type transistor Q41, and the positive electrode of the voltage regulator tube DZ6 and the other end of the resistor R162 are connected to the positive output electrode of the battery pack; it also includes a resistor R13, a resistor R14, a resistor R15, a diode D16, a voltage regulator tube DZ11 and an NMOS tube Q3; one end of the resistor R13 is connected to the negative output electrode of the battery pack.The other end of the resistor R13 is connected to the positive electrode of the diode D16, the negative electrode of the diode D16 is connected to the gate of the NMOS tube Q3, one end of the resistor R15 and the negative electrode of the voltage regulator tube DZ11, the source of the NMOS tube Q3, the other end of the resistor R15 and the positive electrode of the voltage regulator tube DZ11 are connected to the positive electrode output of the battery pack; the drain of the NMOS tube Q3 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the resistor R145 and the resistor R147. When there is a negative voltage on the positive electrode output of the battery pack, the negative electrode voltage of the battery pack output is higher than the positive electrode voltage of the battery pack output, the NMOS tube Q3 is turned on, and the gate and source of the NMOS tube M2 and the NMOS tube M4 are short-circuited through the resistor R14, the resistor R147 and the resistor R145 to eliminate the negative voltage; as shown in the attached. Figure 5As shown, the charging main circuit 4 includes a resistor R20, a resistor R74, a resistor R178, a resistor R181, a resistor R182, a resistor R183, a resistor R184, a capacitor C69, a capacitor C71, a PNP transistor Q44, an NPN transistor Q45, an NMOS transistor M10, a diode D25, a diode D26, a diode D27, a voltage regulator DZ10, a TVS transistor TVS9 and a TVS transistor TVS10; one end of the resistor R20 is connected to the charging control signal output end, and the other end of the resistor R20 is connected to the generating end of the PNP transistor Q44. The emitter, the anode of the diode D25, the anode of the diode D26, one end of the resistor R178 and the emitter of the NPN transistor Q45, the collector of the PNP transistor Q44 is connected to one end of the resistor R182, the other end of the resistor R182 is connected to the gate of the NMOS tube M10, the base of the NPN transistor Q44 is connected to one end of the resistor R185, the cathode of the diode D25 is connected to the resistor R144 and the resistor R146, the cathode of the diode D26 is connected to one end of the capacitor C69 and one end of the resistor R184, the other end of the capacitor C69 is connected to the The other end of the NMOS tube M10 is connected to the battery pack, the other end of the resistor R178 is connected to the base of the NPN transistor Q45 and the other end of the resistor R184, the collector of the NPN transistor Q45 is connected to the cathode of the diode D27, the anode of the diode D27 is connected to one end of the resistor R183, and the other end of the resistor R183 is connected to the resistor R182; the drain of the NMOS tube M10 is connected to one end of the TVS tube TVS9 and the main discharge circuit 3, the source of the NMOS tube M10 is connected to the other end of the TVS tube TVS9, the anode of the voltage regulator tube DZ10, one end of the resistor R181, and the capacitor C7 1, one end of the TVS tube TVS10, one end of the resistor R74 and the charger input end, the cathode of the voltage regulator tube DZ10 and the other end of the resistor R181 are connected to the resistor R182, the other end of the capacitor C71, the other end of the TVS tube TVS10 and the other end of the resistor R74 are grounded; the collector of the PNP transistor Q44 is connected to the anode of the diode D24, the PNP transistor Q44 is connected to the resistor R182 via the diode D25, when a high voltage is input to the charger input end, the diode D24 can play a cut-off role to protect each MOS tube and the battery pack.

[0020] Working principle: When the discharge control signal output terminal outputs a high-level signal, the MCU control circuit outputs a high-level signal to control the PMOS tube Q40 to turn on. The high-level signal is connected to the emitter of the PNP transistor Q41 through the resistor R172. At this time, the emitter level is higher than the base level, and the PNP transistor Q41 is turned on. The high-level signal is connected to the gates of the NMOS tubes M2 and M4 through the resistors R147 and R145. The NMOS tubes M2 and M4 are turned on. The high-level signal reaches the gates of the NMOS tubes M1 and M3 through the PMOS tube Q40, the resistors R144 and R146. The NMOS tubes M1 and M3 are turned on. The current of the battery pack enters the discharge main circuit through the NMOS tubes M2, M4, M1 and M3 to realize discharge. When the signal output terminal of the discharge main circuit outputs a low-level signal, the NMOS tubes M2, M4, M1 and M3 The S transistor M3 is turned off, and the discharge stops; when the charging control signal output terminal of the charging main circuit outputs a high-level signal, the PNP transistor Q44 is turned on, and the high-level signal is connected to the gate of the NMOS transistor M10 through the resistor R20, the PNP transistor Q44, the diode D24 and the resistor R182, and the NMOS transistor M10 is turned on. At the same time, the high-level signal reaches the gates of the NMOS transistors M1 and M3 through the diode D25, the resistor R144 and the resistor R146, and the NMOS transistors M When the charging control signal output terminal outputs a low-level signal, the NPN transistor Q45 is turned on, and the low-level signal passes through the resistor R20, the NPN transistor Q45, the diode D27 and the resistor R182 to the gate of the NMOS tube M10, and the NMOS tube M10 is turned off. At the same time, the NMOS tube M1 and the NMOS tube M3 are also turned off, and the charging stops.

[0021] The above embodiments only express the implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. In this embodiment, up, down, left, right, front, and back only represent their relative positions and do not represent their absolute positions. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A BMS port control circuit, characterized in that: The invention comprises an MCU control circuit (1), the MCU control circuit (1) is connected to a charge-discharge common circuit (2), the charge-discharge common circuit (2) is connected to a discharge main circuit (3) and a charge main circuit (4); the charge-discharge common circuit (2) comprises an NMOS tube M1, an NMOS tube M3, a PMOS tube Q40, a voltage regulator tube DZ7, a resistor R144, a resistor R146, a resistor R150, a resistor R159, a resistor R167, a resistor R170 and a capacitor C66, one end of the resistor R167 is connected to the MCU control circuit (1), the other end of the resistor R167 is connected to the gate of the PMOS tube Q40 and one end of the resistor R170, the source of the PMOS tube Q40 is connected to the other end of the resistor R170 and the discharge main circuit (4), and the charge-discharge common circuit (2) comprises an NMOS tube M1, an NMOS tube M3, a PMOS tube Q40, a voltage regulator tube DZ7, a resistor R144, a resistor R146, a resistor R150, a resistor R159, a resistor R167, a resistor R170 and a capacitor C66, one end of the resistor R167 is connected to the MCU control circuit (1), the other end of the resistor R167 is connected to the gate of the PMOS tube Q40 and one end of the resistor R170, and the source of the PMOS tube Q40 is connected to the other end of the resistor R170 and the discharge main circuit (4). The main electric circuit (3) has a drain of the PMOS tube Q40 connected to the negative electrode of the voltage regulator tube DZ7 and one end of the resistor R159, and the positive electrode of the voltage regulator tube DZ7 and the other end of the resistor R159 are connected to a battery pack; the source electrodes of the NMOS tube M1 and the NMOS tube M3 are both connected to the battery pack, the gate electrode of the NMOS tube M1 is connected to the signal output ends of the charging main circuit (4) and the discharging main circuit (3) via the resistor R144, the gate electrode of the NMOS tube M3 is connected to the signal output ends of the charging main circuit (4) and the discharging main circuit (3) via the resistor R146, the drain electrodes of the NMOS tube M1 and the NMOS tube M3 are both connected to the charging main circuit (4), the discharging main circuit (3) and one end of the resistor R150, and the other end of the resistor R150 is grounded via the capacitor C66.

2. The BMS port control circuit according to claim 1, characterized in that: The MCU control circuit (1) comprises an NMOS tube Q43, a resistor R177, a resistor R113 and a diode D23; the source of the NMOS tube Q43 is grounded, the gate of the NMOS tube Q43 is connected to one end of the resistor R113 and one end of the resistor R177, the other end of the resistor R113 is grounded, the other end of the resistor R177 is connected to the cathode of the diode D23, and the anode of the diode D23 is connected to the MCU signal control terminal.

3. The BMS port control circuit according to claim 1, characterized in that: The main discharge circuit (3) comprises a resistor R13, a resistor R14, a resistor R145, a resistor R147, a resistor R161, a resistor R163, a resistor R166, a resistor R172, a diode D16, a diode D17, a diode D19, a diode D20, an NMOS transistor Q3, an NMOS transistor M2, an NMOS transistor M4, a capacitor C65, a capacitor C67, a capacitor C68, a PNP transistor Q41, a TVS transistor TVS6, a TVS transistor TVS7 and a TVS transistor TVS8; one end of the resistor R172 is connected to the discharge control signal output end, the other end of the resistor R172 is connected to the cathode of the diode D19 and the emitter of the PNP transistor Q41, the anode of the diode D19 is connected to the anode of the diode D17, the base of the PNP transistor Q41 is connected to one end of the resistor R166, the other end of the resistor R166 is connected to the battery pack, the cathode of the diode D20 and one end of the capacitor C68, the anode of the diode and the other end of the capacitor C68 are grounded; the PN The collector of the P-type transistor Q41 is connected to the positive electrode of the diode D17, one end of the resistor R147 and one end of the resistor R145; the other ends of the resistor R147 and the resistor R145 are respectively connected to the gates of the NMOS transistors M2 and M4; the sources of the NMOS transistors M2 and M4 are connected to the positive output of the battery pack; the drains of the NMOS transistors M2 and M4 are connected to the drain of the NMOS transistor M1, the drain of the NMOS transistor M3 and the main charging circuit (4); the capacitor C6 One end of the capacitor C5, one end of the TVS tube TVS6 and one end of the TVS tube TVS7 are connected to the drain of the NMOS tube M1, the drain of the NMOS tube M3 and the charging main circuit (4); the other end of the capacitor C65, the other end of the TVS tube TVS6 and the other end of the TVS tube TVS7 are connected to the positive output electrode of the battery pack; one end of the capacitor C67, the TVS tube TVS8 and the resistor R161 are connected to the positive output electrode of the battery pack, and the other ends of the capacitor C67, the TVS tube TVS8 and the resistor R161 are grounded.

4. The BMS port control circuit according to claim 3, characterized in that: It also includes a voltage regulator tube DZ6 and a resistor R162. The cathode of the voltage regulator tube DZ6 and one end of the resistor R162 are connected to the collector of the PNP transistor Q41, and the anode of the voltage regulator tube DZ6 and the other end of the resistor R162 are connected to the positive output electrode of the battery pack.

5. The BMS port control circuit according to claim 3, characterized in that: It also includes a resistor R13, a resistor R14, a resistor R15, a diode D16, a voltage regulator DZ11 and an NMOS tube Q3; one end of the resistor R13 is connected to the negative electrode of the battery pack output, the other end of the resistor R13 is connected to the positive electrode of the diode D16, the negative electrode of the diode D16 is connected to the gate of the NMOS tube Q3, one end of the resistor R15 and the negative electrode of the voltage regulator DZ11, the source of the NMOS tube Q3, the other end of the resistor R15 and the positive electrode of the voltage regulator DZ11 are connected to the positive electrode of the battery pack output; the drain of the NMOS tube Q3 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the resistor R145 and the resistor R147.

6. The BMS port control circuit according to claim 1, characterized in that: The charging main circuit (4) comprises a resistor R20, a resistor R74, a resistor R178, a resistor R181, a resistor R182, a resistor R183, a resistor R184, a capacitor C69, a capacitor C71, a PNP transistor Q44, an NPN transistor Q45, an NMOS transistor M10, a diode D25, a diode D26, a diode D27, a voltage regulator DZ10, a TVS transistor TVS9 and a TVS transistor TVS10; one end of the resistor R20 is connected to the charging control signal output end, The other end of the resistor R20 is connected to the emitter of the PNP transistor Q44, the anode of the diode D25, the anode of the diode D26, one end of the resistor R178 and the emitter of the NPN transistor Q45. The collector of the PNP transistor Q44 is connected to one end of the resistor R182. The other end of the resistor R182 is connected to the gate of the NMOS tube M10. The base of the NPN transistor Q44 is connected to one end of the resistor R185. The cathode of the diode D25 is connected to the resistor R144 and the resistor R146. The cathode of the tube D26 is connected to one end of the capacitor C69 and one end of the resistor R184, the other end of the capacitor C69 is connected to the other end of the resistor R185 and the battery pack, the other end of the resistor R178 is connected to the base of the NPN transistor Q45 and the other end of the resistor R184, the collector of the NPN transistor Q45 is connected to the cathode of the diode D27, the anode of the diode D27 is connected to one end of the resistor R183, and the other end of the resistor R183 is connected to the resistor R182; the drain of the NMOS tube M10 is connected to One end of the TVS tube TVS9 is connected to the main discharge circuit (3); the source of the NMOS tube M10 is connected to the other end of the TVS tube TVS9, the positive electrode of the voltage regulator tube DZ10, one end of the resistor R181, one end of the capacitor C71, one end of the TVS tube TVS10, one end of the resistor R74 and the charger input end; the negative electrode of the voltage regulator tube DZ10 and the other end of the resistor R181 are connected to the resistor R182; the other end of the capacitor C71, the other end of the TVS tube TVS10 and the other end of the resistor R74 are grounded.

7. The BMS port control circuit according to claim 6, characterized in that: The collector of the PNP transistor Q44 is connected to the anode of the diode D24, and the PNP transistor Q44 is connected to the resistor R182 via the diode D25.

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