Semiconductor element

Abstract

A semiconductor device includes a semiconductor region, a gate stack, and a fin isolation region. The gate stack is on the semiconductor region, wherein the gate stack includes a first gate stack portion and a second gate stack portion. The fin isolation region separates the first gate stack portion and the second gate stack portion, wherein the fin isolation region includes a first portion and a plurality of second portions. The first portion is higher than a bottom surface of the gate stack. The plurality of second portions are under and connected to the first portion, where a first outermost portion of the plurality of second portions has a first depth equal to or greater than a second depth of an inner portion of the plurality of second portions.

Description

Technical Field

[0001] The present application relates to a semiconductor device. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generations. Over the course of the evolution of integrated circuits, functional density (e.g., the number of interconnected elements per wafer area) has generally increased while geometry size has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction has also increased the complexity of processing and manufacturing integrated circuits. In order to achieve these advances, similar developments in integrated circuit processing and manufacturing are needed. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structure of FinFETs and methods for manufacturing FinFETs are under development.

[0004] The formation of a FinFET typically includes forming a long semiconductor fin and a long gate stack, and then forming an isolation region to cut the long semiconductor fin and the long gate stack into shorter portions that serve as the fins and gate stacks of the FinFET. Utility Model Content

[0005] The present application provides a semiconductor element to solve the problem in the prior art that the capability of leakage current is adversely affected.

[0006] According to some embodiments, a semiconductor element includes a semiconductor region, a gate stack, and a fin isolation region. The gate stack is on the semiconductor region, wherein the gate stack includes a first gate stack portion and a second gate stack portion. The fin isolation region separates the first gate stack portion and the second gate stack portion, wherein the fin isolation region includes a first portion and a plurality of second portions. The first portion is higher than the bottom surface of the gate stack. The plurality of second portions are located below the first portion and connected to the first portion, wherein a first outermost portion of the plurality of second portions has a first depth, and the first depth is equal to or greater than a second depth of an inner portion of the plurality of second portions.

[0007] According to some embodiments, a semiconductor element includes a semiconductor substrate, a first dielectric insulating region, a plurality of semiconductor fins, a gate stack, and a second dielectric insulating region. The first dielectric insulating region extends into the semiconductor substrate. A plurality of semiconductor fins protrude above the first dielectric insulating region and are parallel to each other. A gate stack is above the plurality of semiconductor fins. A plurality of source / drain regions extend into the plurality of semiconductor fins. The second dielectric insulating region contacts the sidewalls of the plurality of semiconductor fins. The gate stack and the second dielectric insulating region are located on opposite sides of the plurality of source / drain regions. The second dielectric insulating region includes an upper portion and a plurality of lower portions. The plurality of lower portions are located below the upper portion and connected to the upper portion, wherein the outer portions of the plurality of lower portions are deeper than the inner portions of the plurality of lower portions.

[0008] According to some embodiments, a semiconductor device includes a semiconductor substrate, a first dielectric insulating region, a plurality of semiconductor fins, a plurality of first source / drain regions, a plurality of second source / drain regions, and a second dielectric insulating region. The first dielectric insulating region extends into the semiconductor substrate. The plurality of semiconductor fins protrude higher than the first dielectric insulating region and are parallel to each other. The plurality of first source / drain regions extend into the plurality of semiconductor fins. The plurality of second source / drain regions extend into the plurality of semiconductor fins. The second dielectric insulating region contacts the sidewalls of the plurality of semiconductor fins. The plurality of first source / drain regions and the plurality of second source / drain regions are located on opposite sides of the second dielectric insulating region. The second dielectric insulating region includes. an upper portion and a plurality of lower portions. The lower portion is located below the upper portion and connected to the upper portion. The outer portion of the plurality of lower portions is deeper than the inner portion of the plurality of lower portions.

[0009] Through the above-mentioned semiconductor element, the fin isolation region can have a deeper outermost isolation region, thereby improving its ability to block leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When with Figure 1 When read together, the various aspects of the present application can be best understood from the following detailed description. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity, the size of various features can be increased or reduced arbitrarily.

[0011] Figures 1 to 8 , Fig. 9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B and Fig. 16C depicts perspective, cross-sectional, and top views of intermediate stages of formation of isolation regions and fin field effect transistors (FinFETs) according to some embodiments;

[0012] Figures 17 to 19 depicts an enlarged view of some portions of a cross-sectional view during the formation of a fin isolation region according to some embodiments;

[0013] Fig. 20 schematically illustrates an etching tool used in a fin cutting process according to some embodiments;

[0014] Fig.21 A process flow for forming isolation regions and FinFETs according to some embodiments is schematically depicted.

[0015]

Explanation of symbols

[0016] 10: Wafer

[0017] 20: Base material

[0018] 22: Shallow trench isolation area

[0019] 22T: Top

[0020] 22B: Bottom

[0021] 24: Semiconductor Strip

[0022] 25: Dielectric dummy strip

[0023] 24':Semiconductor fins

[0024] 25': dummy fin

[0025] 30: Gate stack

[0026] 32: Dummy gate dielectric

[0027] 34: Virtual gate electrode

[0028] 36: Hard Mask Layer

[0029] 38: Gate spacer

[0030] 42: Epitaxial area

[0031] 46: Contact Etch Stop Layer

[0032] 48: Interlayer dielectric

[0033] 50: Hard Mask

[0034] 52: Gate dielectric

[0035] 54: Gate electrode

[0036] 56: Gate stack

[0037] 60: Depression

[0038] 64: Hard Mask

[0039] 66: Groove

[0040] 9B-9B: Cross section

[0041] 68: Dielectric materials

[0042] 70: Gate isolation area

[0043] 72: Etching mask

[0044] 72T: Top layer

[0045] 72M: Middle layer

[0046] 72B: Bottom layer

[0047] 74: Opening

[0048] 76: Groove

[0049] 78: Groove

[0050] 78R: Outermost groove

[0051] 78L: Outermost groove

[0052] 78C: Center groove

[0053] 78I: medial groove

[0054] Dom,Dce:Depth

[0055] 80: Location

[0056] 81: Byproduct

[0057] 84: Dielectric materials

[0058] 86: Fin isolation area

[0059] 86A: Lower part

[0060] 86B: Upper part

[0061] 90: Dielectric area

[0062] 92: Etching stop layer

[0063] 94: Interlayer dielectric

[0064] 96: Gate contact plug

[0065] 100: FinFET

[0066] 110: Etching tools

[0067] 112: Top electrode

[0068] 114: Plasma

[0069] 116: Bottom electrode

[0070] 120: Chamber

[0071] 124:Export

[0072] 126: Pump

[0073] 130,132,134: Line

[0074] 200:Process flow

[0075] 202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232: Technology DETAILED DESCRIPTION

[0076] The following disclosure provides many different embodiments or examples for implementing different features of the present application. In order to simplify the content of the present application, specific examples of components and arrangements are described below. Of course, these are just examples and are not meant to be restrictive. For example, in the following description, the formation of a first feature on or above a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the content of the present application may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0077] Additionally, spatially relative terms, such as "below," "lower," "beneath," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature(s), as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0078] The present application provides a method for forming an isolation region of an isolation transistor. A profile of an isolation structure is also provided. According to some embodiments, the gate stack is etched to expose the protruding semiconductor fins of the bottom layer. The semiconductor fins and the bottom semiconductor substrate block are etched so that the recess generated extends to the bottom semiconductor substrate block. In the etching process, the gas conductivity is increased to adjust the profile of the depth of the recess generated. The sputtering effect can also be increased in the etching process to adjust the profile. It is understood that although the formation of the isolation of FinFET is taken as an example, the above method can also be applied to the isolation of other transistors, such as planar transistors, gate-around (GAA) transistors, etc. The embodiments discussed here are to provide examples so that the subject matter of the present application can be manufactured or used, and those skilled in the art will easily understand the modifications that can be made within the intended scope of maintaining different embodiments. In various views and illustrative embodiments, similar reference numbers are used to designate similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0079] Figures 1 to 8 , Fig. 9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B and Fig. 16C 3D, cross-sectional and top views are shown of intermediate stages of formation of isolation regions and FinFETs according to some embodiments. The corresponding process is also schematically shown in FIG. Fig.21 In the process flow shown in .

[0080] Figure 1 A perspective view of the initial structure is shown. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22, such as a shallow trench isolation (STI) region, may be formed extending from the top surface of the substrate 20 into the substrate 20. Fig.21 As shown, in the process flow 200 , the corresponding process is depicted as process 202 . A portion of the substrate 20 between adjacent shallow trench isolation regions 22 is referred to as a semiconductor strip 24 .

[0081] According to some embodiments, semiconductor strip 24 is a portion of original substrate 20, and the material of semiconductor strip 24 is the same as the material of the underlying bulk portion of substrate 20. According to alternative embodiments, semiconductor strip 24 is a replacement strip formed by etching a portion of substrate 20 between shallow trench isolation regions 22 to form a recess, and performing an epitaxy process to re-grow another semiconductor material in the recess. Therefore, semiconductor strip 24 is formed of a semiconductor material different from substrate 20. According to some embodiments, semiconductor strip 24 is formed of Si, SiP, carbon-doped silicon, SiPC, SiGe, SiGeB, Ge, III-V compound semiconductors such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.

[0082] The shallow trench isolation region 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or the like. The shallow trench isolation region 22 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0083] Figure 1 The formation of the dielectric dummy strip 25 is further illustrated. According to some embodiments, the dielectric dummy strip 25 is formed by etching one of the semiconductor strips 24 to form a recess, and then filling the recess with a dielectric material. Therefore, the bottom of the dielectric dummy strip 25 contacts the top surface of the underlying bulk portion of the semiconductor substrate 20. According to other embodiments, the dielectric dummy strip 25 and some portions of the shallow trench isolation region 22 surrounding it are formed in a combined process. The resulting dielectric dummy strip 25 can fall on the underlying dielectric material, and the dotted line represents the bottom surface of the dielectric dummy strip 25. The dielectric dummy strip 25 can be formed of or include a high dielectric constant material, such as silicon nitride.

[0084] The semiconductor strips 24 between the two dielectric dummy strips 25 together form a semiconductor strip group. The semiconductor strips 24 in the same semiconductor strip group may have a uniform spacing or a substantially uniform spacing (eg, a variation of less than about 20%). Figure 1 As shown, the semiconductor strip group may include two semiconductor strips 24 (and Figure 2 ). According to other embodiments, the semiconductor strip group may be a single strip group including one semiconductor strip 24. According to another embodiment, the semiconductor strip group may include a plurality of (more than two) semiconductor strips 24. For example, Fig. 16C An example semiconductor strip group including a plurality of closely positioned semiconductor strips 24 is depicted.

[0085] Please refer to Figure 2 , the shallow trench isolation region 22 is recessed. The top portions of the semiconductor strip 24 and the dielectric dummy strip 25 protrude above the top surface 22T of the remaining portion of the shallow trench isolation region 22 to form a protruding fin 24' and a dummy fin 25', respectively. The corresponding process is Fig.21 The process flow 200 is shown as process 204. Etching can be performed using a dry etching process, where an etching gas such as a mixture of HF and NH3 can be used. According to an alternative embodiment, the recessing of the shallow trench isolation region 22 is performed using a wet etching process. The etching chemistry can include, for example, an HF solution.

[0086] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns, for example, with smaller pitches than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fins.

[0087] Please refer to Figure 3 , forming a dummy gate stack 30 and a gate spacer 38 on the top surface and sidewalls of the (protruding) fin 24' and the dummy fin 25'. The corresponding process is Fig.21The process flow 200 is shown as process 206. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 may be formed using materials such as polysilicon or amorphous silicon, or other materials. Each dummy gate stack 30 may also include a hard mask layer 36 above one (or more) dummy gate electrodes 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride or a multilayer thereof. The dummy gate stack 30 may pass over a single or multiple protruding fins 24' and dummy fins 25' and the shallow trench isolation region 22. The length direction of the dummy gate stack 30 is also perpendicular to the length direction of the protruding fins 24' and the dummy fins 25'.

[0088] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments, the gate spacer 38 is formed of, for example, silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0089] Figure 4 The formation of epitaxial region 42 is shown, which serves as the source / drain region of the resulting FinFET and is therefore alternatively referred to as source / drain region 42. The corresponding process is Fig.21 The process flow 200 is shown as process 208. The source / drain region may refer to the source or drain, individually or collectively depending on the context. According to some embodiments, an etching process (hereinafter referred to as source / drain recess) is performed to etch some portions of the protruding fin 24' that are not covered by the dummy gate stack 30 and the gate spacer 38 to form a recess. The recess may be anisotropic, so that some portions of the protruding fin 24' directly below the dummy gate stack 30 and the gate spacer 38 are protected from being etched. During the etching process, the dielectric dummy fin 25' is not etched. For example, the protruding fin 24' may be etched using a mixture of NF3 and NH3, a mixture of HF and NH3, or the like.

[0090] Next, an epitaxial region 42 is formed by selectively growing a semiconductor material from the recess. According to some embodiments, the epitaxial region 42 contains silicon germanium, silicon, silicon carbon, or the like. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped with the epitaxial. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), SiB, GeB, or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. After the epitaxial region 42 completely fills the recess, the epitaxial region 42 begins to expand horizontally, and facets may be formed.

[0091] Figure 5 A three-dimensional diagram of the structure after forming a contact etch stop layer (CESL) 46 and an inter-layer dielectric (ILD) 48 is shown. Fig.21 In the process flow 200 shown, the corresponding process is illustrated as process 210. The contact etch stop layer 46 can be formed of silicon nitride, silicon carbonitride, or the like. The contact etch stop layer 46 can be formed using a conformal deposition method, such as ALD or CVD. The interlayer dielectric 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The interlayer dielectric 48 can also be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or the like. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, is performed to make the top surfaces of the interlayer dielectric 48, the dummy gate stack 30, and the gate spacer 38 flat with each other.

[0092] Figure 5 Also shown is the formation of a hard mask 50 for protecting the interlayer dielectric 48 in subsequent processes. According to some embodiments, the formation of the hard mask 50 includes recessing the interlayer dielectric 48 (and possibly the contact etch stop layer 46) to form recesses between adjacent gate spacers 38, filling a dielectric layer to fill the recesses, and performing a planarization process (e.g., a chemical mechanical polishing process or a mechanical polishing process) to remove excess portions of the dielectric material. The remaining portion of the dielectric material is the hard mask 50. According to some embodiments, the hard mask 50 is formed of or includes silicon nitride, silicon oxide, or a similar material.

[0093] Figure 6The formation of the replacement gate stack 56 is shown. The corresponding process is Fig.21 The process flow 200 is shown as process 212. The formation process includes removing the dummy gate stack 30 to form a trench and forming a replacement gate stack 56 in the formed trench. The gate stack 56 includes a gate dielectric 52 and a gate electrode 54. The gate dielectric 52 may include an interface layer and a high-k dielectric layer above the interface layer. The interface layer may include silicon oxide. The high-k dielectric layer may include hafnium oxide, zirconium oxide, lanthanum oxide and / or the like. The gate electrode 54 may include a work function layer composed of TiN, TiSiN, TaN, TiAlN, TiAl and / or the like, and may or may not include a fill metal formed of cobalt, tungsten and / or the like. Accordingly, the gate electrode 54 is also referred to as a metal gate 54.

[0094] Next, the formation process proceeds to cutting the gate stack 56 and cutting the protruding fins 24' to isolate the transistor. The cutting of the gate stack 56 is called the Cut Metal Gate (CMG) process. The cutting of the protruding semiconductor fins 24' is called the Continuous Metal On-Diffusion Edge (CMODE) process, or sometimes referred to as the Cut Metal on-Diffusion Edge (CMODE) process. It will be understood that in the illustrated embodiment, a CMODE process is performed, in which the cutting of the protruding semiconductor fins 24' is performed after the replacement gate stack 56 is formed. According to an alternative embodiment, the cutting of the protruding semiconductor fins 24' can be performed before the replacement gate stack 56 is formed, and the dummy gate stack 30 ( Figure 5 ). Therefore, the corresponding process is called a continuous poly at diffusion edge (CPODE) process or a cutting poly at diffusion edge (CPODE) process.

[0095] Please refer to Figure 7 , the replacement gate stack 56 is recessed by an etching process to form a recess 60, thereby reducing the height of the replacement gate stack 56. Fig.21 In the process flow 200 shown, the corresponding process is depicted as process 214. During the etching process, the hard mask 50 protects the underlying interlayer dielectric 48. According to some embodiments, Figure 7 As shown, the gate spacers 38 are also recessed. According to an alternative embodiment, the gate spacers 38 are not recessed.

[0096] Please refer to Figure 8 , forming a hard mask 64. Fig.21 In the process flow 200 shown, the corresponding process is depicted as process 216. The formation process may include depositing a hard mask layer and performing a planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, to planarize the top surface of the hard mask 64. The hard mask 64 extends into the recess 60 ( Figure 7 ). According to some embodiments, the hard mask 64 is formed of a uniform material, such as amorphous silicon. According to other embodiments, the hard mask 64 can be a composite layer including multiple layers. For example, the hard mask layer 64 can include a first layer (which can be a conformal layer) and a second layer above the first layer. For example, the dotted line represents the interface between the first layer and the second layer, as an example. The first layer can be formed of or include silicon nitride, and according to some embodiments, the second layer can include amorphous silicon. The hard mask 64 may or may not include a third layer, such as a silicon nitride layer deposited on the planarized second layer.

[0097] Fig. 9A , Fig. 9B and Fig.10 The metal gate cutting process according to some embodiments is shown. Fig. 9A The etching process may include forming an etching mask (such as a photoresist or a three-layer etching mask, not shown), patterning the etching mask, and etching hard masks 64 and 50, interlayer dielectric 48, contact etch stop layer 46, and replacement gate stack 56 to form trench 66.

[0098] Fig. 9B Draw Fig. 9A The replacement gate stack 56 is cut into some independent parts. The top surface of the dielectric dummy fin 25' can be exposed in the groove 66. The corresponding process is Fig.21 The process flow 200 is shown as process 218 .

[0099] Please refer to Fig.10 , dielectric material 68 is deposited. The corresponding process is Fig.21 The process flow 200 is shown as process 220. According to some embodiments, the dielectric material 68 is formed of a uniform dielectric material, such as silicon nitride, silicon oxide, or the like. According to alternative embodiments, the dielectric material 68 includes multiple dielectric layers. For example, the dielectric material 68 may include a dielectric liner formed of a first dielectric material, and a second dielectric material on the dielectric liner. The second dielectric material is different from the first dielectric material. For example, the first dielectric material may include silicon oxide, and the second dielectric material may include silicon nitride. Alternatively, the first dielectric material may include silicon nitride, and the second dielectric material may include silicon oxide.

[0100] The formation of dielectric material 68 includes depositing the dielectric material and performing a planarization process to planarize the top surface of the dielectric material. According to some embodiments, after the planarization process, a portion of dielectric material 68 may remain on the overlying hard mask 64 as a hard mask layer. According to alternative embodiments, the planarization process is performed until the top surface of hard mask 64 is exposed, and another hard mask may be deposited on the remaining hard mask 64. Grooves 66 ( Fig. 9A and Fig. 9B The portion of the dielectric material 68 in the ) is hereinafter referred to as the gate isolation region 70, which is also referred to as the cut metal gate region 70. Some exemplary gate isolation regions 70 are Fig. 16C Pictured in the middle, Fig. 16C This is a top view.

[0101] Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A and Fig. 15B An intermediate stage in the CMODE process is shown, where fin isolation regions are formed to cut through the semiconductor strips and underlying bulk portions of the semiconductor substrate.

[0102] Fig. 11C FIG. 1 is a perspective view showing the formation of an etching mask 72 according to some embodiments. The corresponding process is shown in FIG. Fig.21 The process flow 200 shown in FIG. 2 is depicted as process 222. The etch mask 72 may be three layers, which may include a bottom layer 72B, an intermediate layer 72M on the bottom layer 72B, and a top layer 72T on the intermediate layer 72M. According to some embodiments, the bottom layer 72B may include a carbon-containing dielectric material, a cross-linked photoresist, or the like. The intermediate layer 72M may include an inorganic material such as silicon oxide. The top layer 72T may include a photoresist, and the top layer 72T is patterned to form an opening 74. The intermediate layer 72M and the bottom layer 72B are then patterned using the patterned top layer 72T as an etch mask.

[0103] Fig.11A and Fig. 11B Draw separately Fig. 11C The cross-sectional views of the cross sections 11A-11A and 11B-11B are shown. Fig.11A As shown, the opening 74 overlaps a portion of each of the two dummy fins 25' and also overlaps the middle protruding semiconductor fin 24'. Fig. 11BAs shown, opening 74 overlaps one of replacement gate stacks 56. According to some embodiments, Fig. 11B As shown, a single opening 74 is formed, and on one or both sides of the opening 74, there are multiple replacement gate stacks 56, and no opening 74 overlaps with it. According to alternative embodiments, multiple openings 74 (shown in dotted lines) can be formed, each opening 74 overlaps with one of the multiple adjacent replacement gate stacks 56.

[0104] In the following process, numbers may be referred to using numbers containing the letter "A" or "B". Numbers whose numbering contains the letter "A" are derived from the same Fig.11A The same cross-section as the cross-section obtained, the number containing the letter "B" is the number from the Fig. 11B The cross section is the same as the cross section obtained.

[0105] Next, the underlying dielectric material 68, hard mask 64, gate isolation region 70, and replacement gate stack 56 are etched using etch mask 72 to form trench 76 extending to replacement gate stack 56. Fig.21 The process flow 200 is shown as process 224. The resulting structure is as shown in FIG. Fig. 12A and Fig. 12B In the etching process, the top layer 72T and the middle layer 72M ( Fig.11A and Fig. 11B ) may be consumed. The protruding semiconductor fin 24' is exposed. The etching may include multiple etching processes. For example, the etching of the dielectric material 68 and the hard mask layer 64 may be performed using CF4, CH2F2, CH3F, HF, O2, Ar, or a combination thereof, depending on the respective materials. The etching of the replacement gate stack 56 may be performed using HCl, H2O2, H2O, etc., or a combination thereof. After the etching process, the protruding semiconductor fin 24' is exposed.

[0106] Next, the protruding fins 24' are etched. After the protruding fins 24' are removed, the underlying semiconductor strips 24 between the shallow trench isolation regions 22 are also etched to form trenches 78. The corresponding process is Fig.21 The process flow 200 is shown as process 226. The resulting structure is Fig.13A and Fig. 13B The etching process is performed until the bottom of the generated trench 78 is lower than the bottom surface 22B of the shallow trench isolation region 22. Therefore, the trench 78 further extends to the bulk portion of the substrate 20 below the shallow trench isolation region 22. The details of the etching process will be referred to Fig.17 and Fig.18 According to some embodiments, as shown in reference Fig.17 and Fig.18As discussed in detail, the etching process and / or etching tool is selected so that the outermost trenches 78L and 78R have the same depth or are the same depth as the inner trenches 78 .

[0107] Fig. 13B Draw Fig.13A A cross-sectional view of the structure shown. According to some embodiments, there is a single opening 74, and thus there can be a single trench 78. According to alternative embodiments, multiple openings 74 are formed to overlap adjacent replacement gate stacks 56, thereby forming multiple trenches 78 (shown as dashed lines) to be parallel to each other in the illustrated cross-section.

[0108] Then, if Fig.14A and Fig. 14B As shown, dielectric material 84 is filled in trenches 78 and 76. The corresponding process is Fig.21 This is depicted as process 228 in the illustrated process flow 200. According to some embodiments, dielectric material 84 is formed of a uniform dielectric material, such as silicon nitride, silicon oxide, or the like. According to alternative embodiments, dielectric material 84 includes a plurality of dielectric layers, which may be selected from the same set of candidate materials used to form dielectric material 68, and the details are therefore not discussed herein.

[0109] Fig.15A and Fig. 15B A planarization process is shown for removing excess portions of dielectric material 84. The corresponding process is Fig.21 The process flow 200 is shown as process 230. Therefore, the remaining portion of the dielectric material 84 is referred to as the fin isolation region 86, also referred to as the CMODE region 86. The fin isolation region 86 includes a lower isolation region (some portions) 86A, which extends to the shallow trench isolation region 22 and the bulk portion of the semiconductor substrate 20, and an upper region (some portions) 86B, which extends to the gate stack 56.

[0110] According to some embodiments, Fig.15A and Fig. 15B As shown, the planarization process is performed using the hard mask 64 as a chemical mechanical polishing stop layer, so the top surface of the hard mask 64 is exposed. According to an alternative embodiment, as shown in FIG. Fig. 15B As shown, the planarization process may stop at one of the possible layers 88. As shown by the dashed line 86, a plurality of fin isolation regions 86 may also be formed as a group adjacent to each other.

[0111] In a subsequent process, the hard mask 64 is replaced with a dielectric material to form a dielectric region 90, such as Fig.16A and Fig. 16BNext, some upper features are formed, including an etch stop layer 92, an interlayer dielectric 94, and a gate contact plug 96. Source / drain silicide regions (not shown) and source / drain contact plugs (not shown) are also formed on top of the source / drain regions 42. Fig.21 In the process flow 200 shown, the corresponding process is illustrated as process 232. Thus, the FinFET 100 is formed.

[0112] Fig. 16C Draw Fig.16A and Fig. 16B Top view of the structure shown. Fig.16A Draw Fig. 16C The cross section 16A-16A in FIG. Fig.16A Two isolation regions 86A are shown, and Fig. 16C Six isolation regions 86A are shown. Fig. 16B Draw Fig. 16C The cross section 16B-16B in FIG. 16B-16B is shown in FIG. 16B-16B. It can be understood that Fig. 16C A simplified layout is shown showing how the fin isolation regions 86 and gate isolation regions 70 cut the fins and gate stacks, respectively. The actual layout of the fin isolation regions 86 and gate isolation regions 70 may be different from the illustration and may be more complex than the illustration.

[0113] Fig.17 and Fig.18 Draw Fig.13A An enlarged view of the portion 80 in which the protruding semiconductor fins 24', the semiconductor strips 24 and the underlying block portion of the semiconductor substrate 20 are etched to form grooves 76 and 78. According to some embodiments, the etching process can be performed using HBr, O2 and Ar as process gases. According to other embodiments, other process gases such as bromine (Br2), C2F6, CF4, SO2, CH2F2, etc. can be used or can be added to HBr, O2 and Ar as process gases. HBr and O2 (and possibly other gases when used) are used for chemical etching. Ar can be used as a carrier gas, and semiconductor material can also be mechanically removed by sputtering.

[0114] During the etching process, byproducts 81 are generated. The byproducts 81 have the function of passivating and protecting the sidewalls of the bulk portion of the semiconductor substrate 20, thereby making the grooves 78 more vertical. However, the byproducts 81 have some side effects. The byproducts 81 cause a slowdown in the etching process. In addition, the byproducts 81 cause pattern loading in the etching process. For example, it has been found that in areas where the grooves 78 have a higher density, the byproducts 81 are thinner (due to the byproducts 81 being more diffused to a larger surface area), thus resulting in a higher etching rate, where the etching rate is the increase in the depth of the inner grooves 78 per unit time. On the contrary, in areas where the density of the grooves 78 is lower, the byproducts 81 are thicker (due to the byproducts 81 being less diffused to a smaller surface area), so the etching rate is lower. In addition, when the grooves 78 are longer (in a top view), the etching rate is also higher.

[0115] It is understood that the sidewall portion of the byproduct 81 on the sidewall of the substrate 20 cannot be too thin. Otherwise, the protection from the byproduct 81 is too low and the side etching may be severe. This may cause the epitaxial region 42 ( Fig. 13B ) is damaged. Therefore, according to an embodiment of the present application, the byproduct 81 is maintained to have a more uniform thickness in all different trenches 78 to reduce lateral etching.

[0116] Please refer to Fig.17 , the groove group formed by the grooves 78 has a uniform spacing, or a substantially uniform spacing, and its spacing variation is less than, for example, 20%. The groove group includes a leftmost groove 78L and a rightmost groove 78R. Throughout the description, the groove between the outermost grooves 78L and 78R is referred to as the inner groove 78I. The groove between the outermost grooves 78L and 78R is referred to as the center groove 78C, and the center groove 78C is also the inner groove 78I. When the total number of grooves 78 is an odd number, there is one center groove 78C, and when the total number of grooves 78 is an even number, there are two center grooves 78C.

[0117] The leftmost groove 78L and the rightmost groove 78R are in a semi-dense region because no groove is formed on one side of each groove 78L and 78R, while a groove is formed on the other side. The inner groove 78I is in a higher groove density region than the outermost grooves 78L and 78R. Therefore, in conventional applications, it is found that the grooves have the deepest central groove and the shallowest outermost grooves. From the central groove to the outermost groove, the depth of the groove gradually decreases in conventional applications. This results in the outermost grooves and the isolation regions formed thereby having the smallest depth. Since the isolation regions are used to block leakage current, their ability to block leakage current is adversely affected.

[0118] According to an embodiment of the present application, etching tools and etching process conditions are selected and adjusted to achieve deeper outermost trenches 78L and 78R (relative to central trench 78C). Fig. 20 A schematic diagram of an etching tool 110 according to some embodiments is shown. The etching tool 110 has a wafer 10 therein and is configured to etch the wafer 10 to form the trench 78. The etching tool 110 includes a top electrode 112 and a bottom electrode 116, with the wafer 10 located therebetween. A plasma 114 is generated by a process gas therein to etch the protruding semiconductor fins 24' ( Fig.13A and Fig. 13B ), semiconductor strip 24 and substrate 20.

[0119] The etching tool 110 includes a chamber 120 and an inlet 118 through which a process gas is introduced into the chamber 120. The process gas is pumped out of the chamber 120 through an outlet 124, which is connected to a pump 126. Experiments have shown that increasing the gas conductance of the chamber 120 can result in an increase in the depth of the outer trench relative to the depth of the inner trench. The effect of gas conductance may be related to the increased removal efficiency of the byproduct 81 ( Fig.17 and Fig.18 ), so the byproduct 81 is thinner and has a more uniform thickness in different grooves with different depths, lengths and densities.

[0120] Several experiments have been conducted to form trenches 78 on different wafers with the same layout, using different conductivity values ​​in the etching process performed on the different wafers. It has been found that as the gas conductivity increases, the depth ratio Dom / Dce also increases, where Dom( Fig.18 ) is the depth of the outermost grooves 78L and 78R, and Dce is the depth of the center groove 78C. It is also found that for wafers etched using low gas conductivity, the corresponding depth ratio Dom / Dce of the grooves in the corresponding wafer is less than 1.0. When the gas conductivity of the etching wafer is equal to the threshold, the depth ratio Dom / Dce increases to equal 1.0. Further increasing the gas conductivity, the depth ratio Dom / Dce of the corresponding wafer further increases to greater than 1.0. For example, the depth ratio Dom / Dce of some wafers can be increased to a value greater than about 1.1, and can range between about 1.0 and about 1.2.

[0121] According to some embodiments, a threshold gas conductivity corresponding to a depth ratio Dom / Dce equal to 1.0 (which is estimated using a flow rate / pressure ratio) is greater than about 20 sccm / mT and may range between about 15 sccm / mT and about 25 sccm / mT. Through experiments, an ideal gas conductivity corresponding to an ideal profile of the trench (having an ideal Dom / Dce equal to or greater than 1.0) may be determined and used for mass production of wafer 10.

[0122] It is understood that increasing the gas conductivity also results in a decrease in the pressure in the chamber 120. According to some embodiments, when the threshold gas conductivity is used, the threshold pressure of the chamber in the etching process is about 30 mTorr. Accordingly, the chamber pressure in the etching process is less than about 30 mTorr and can be between about 5 mTorr and about 30 mTorr.

[0123] To achieve the desired gas conduction, the pump of the existing etching tool can be replaced with a more powerful pump. For example, Fig. 20 The pump 126 shown in the figure can be a turbo pump. According to some embodiments, as the gas conductance increases and the chamber pressure decreases, it is more difficult to generate plasma from the etching gas. Accordingly, the etching tool 110 can also use a more powerful mechanism in generating plasma. For example, electron cyclotron resonance (ECR) can be used to generate plasma instead of inductively coupled plasma (ICP).

[0124] In addition to gas conductivity, other process conditions can also be adjusted to achieve a higher depth ratio Dom / Dce. For example, the sputtering effect can also be increased to achieve a more uniform depth of the groove 78. According to some embodiments, in the etching process, a bias power supply is provided to increase the sputtering effect. The bias power supply can be turned on and off periodically, and there can be multiple off cycles in the process of forming the groove. For example, in an off-on cycle, no bias power supply is provided in the first time period T1. During this time, the sputtering effect is very low. During the on period of the off-on cycle, a bias power supply is provided in the second time period T2, so that the sputtering effect is high. In the off-on cycle, etching gases such as HBr, O2 and Ar can be continuously applied. In order to improve the sputtering effect, the off / on ratio T2 / T1 is increased to make the depth ratio Dom / Dce closer to 1.0.

[0125] It is understood that the off / on ratio T2 / T1 cannot be too high or too low. When the off / on ratio T2 / T1 is too low, the effect of improving the depth uniformity by the sputtering effect is low. When the off / on ratio T2 / T1 is too high, a bowing effect may occur, in which the middle portion of the trench 78 adjacent to the shallow trench isolation region 22 is wider than the upper and lower portions, which may increase unfavorably. According to some embodiments, the off / on ratio T2 / T1 may be between about 0.25 and about 4.

[0126] The sputtering effect can also be increased by increasing the bias power. Similarly, the bias power cannot be too low or too high. Otherwise, either the sputtering effect is too low or the bow effect is too severe. According to some embodiments, the bias power can be between about 20 watts and about 700 watts.

[0127] like Fig.17 and Fig.18 As shown, as the etching of the semiconductor substrate 20 proceeds, the depth of the trench 78 further increases until a desired depth is reached. Fig.18 Trench 78 is shown at the end of the etching process. For example, when the etching process is complete, the depth of trench 78 can be between about 130 nanometers and about 170 nanometers.

[0128] It is also necessary to understand that the etching of different portions of the semiconductor can be adjusted to have adjusted process conditions. For example, in the initial stages of etching, such as etching the protruding semiconductor fins 24' and the semiconductor strips 24, the grooves are wider and the non-uniformity of the thickness of the byproduct 81 is not obvious. Therefore, the etching of the protruding semiconductor fins 24' and the semiconductor strips 24 can be performed using the first process conditions. However, the subsequent etching of the bulk portion of the semiconductor substrate 20 is more affected by the non-uniformity of the thickness of the byproduct 81. Therefore, the etching process conditions need to be carefully controlled to improve the thickness uniformity of the byproduct 81, and the bulk portion of the semiconductor substrate 20 can be etched using a second process condition different from the first process condition.

[0129] According to some embodiments, the first process condition comprises a first off / on ratio T2 / T1, a first bias power, a first gas conductivity value, and a first chamber pressure. The second process condition comprises a second off / on ratio T2 / T1, a second bias power, a second gas conductivity value, and a second chamber pressure. According to some embodiments, the second off / on ratio T2 / T1 is greater than the first off / on ratio T2 / T1 and / or the second bias power is greater than the first bias power. The first gas conductivity value may be less than the second gas conductivity value. The first chamber pressure may be higher than the second chamber pressure.

[0130] Fig.18The bottom of the groove 78 is shown in accordance with some embodiments. The depth Dom of the outermost grooves 78L and 78R is equal to or greater than the depth of at least one inner groove. According to some embodiments, the bottom of the groove 78 can be aligned with the horizontal straight line 130. According to alternative embodiments, the bottom of the groove 78 can also be substantially aligned with the straight line 130, for example, the maximum average depth difference between the grooves 78 is less than about 5 nanometers. According to another embodiment, as represented by the dashed line 132, from the outermost groove 78R to the central groove 78C, the bottom of some of the grooves 78 is aligned with the straight line and the oblique straight line. There may also be some variations, where one of the outermost grooves 78L and 78R is deeper than the first inner groove 78I (78), but shallower than the second inner groove 78I (78). Dashed line 134 shows another profile, in which the outermost grooves 78L and 78R are the deepest and the central groove 78C is the shallowest. The depth of the grooves 78 may gradually decrease from the outermost grooves 78L and 78R to the central groove 78C.

[0131] Fig.19 Draw Fig.16A 80 ', where the total number of isolated regions 86 is greater than 2. Likewise, dashed lines 130, 132, and 134 are drawn to show different possible contours of the bottom of the isolated region 86. The isolated region 86 includes an upper region 86B and a lower region 86A. The lower region 86A includes outermost portions 86AL and 86AR, an inner portion 86AI, and a center portion 86AC, which fill the outermost portions 78L and 78R, the inner portion 78I, and the center portion 78C, respectively.

[0132] Embodiments of the present application have some advantageous features. By selecting etching tools and process conditions for etching the semiconductor fins and the underlying body of the semiconductor substrate, the fin isolation region (used to cut the semiconductor fins) can have a deeper outermost isolation region, thereby improving its ability to block leakage current.

[0133] According to some embodiments, a method includes: forming a gate stack on a semiconductor region, wherein the semiconductor region is above a semiconductor substrate block; etching the gate stack to form a first trench, wherein the first trench exposes a plurality of protruding semiconductor fins; etching the plurality of protruding semiconductor fins to form a plurality of second trenches extending into the semiconductor substrate block; and forming a fin isolation region filling the first trench and a plurality of second trenches. The plurality of second trenches are located below the first trench and connected to the first trench. The plurality of second trenches include a first outermost trench, a second outermost trench, and an inner trench. The first outermost trench has a first depth. The inner trench is located between the first outermost trench and the second outermost trench. The inner trench has a second depth that is equal to or less than the first depth.

[0134] In some embodiments, before etching the gate stack to form a plurality of second trenches, etching the gate stack to form a third trench, wherein a dummy fin is below and exposed by the third trench, and forming a gate isolation structure to fill the third trench. In some embodiments, when etching a plurality of protruding semiconductor fins, the gas conductivity in each etching chamber is higher than about 20 sccm / mT. In some embodiments, when etching a plurality of protruding semiconductor fins, the gas pressure in each etching chamber is lower than about 30 mTorr. In some embodiments, when etching a plurality of protruding semiconductor fins, plasma is generated by each etching gas using electron cyclotron resonance (ECR). In some embodiments, the second depth is equal to the first depth. In some embodiments, the second depth is less than the first depth.

[0135] In some embodiments, etching the gate stack to form the first trench comprises: forming a hard mask layer, wherein the first trench and the plurality of second trenches are formed using the hard mask layer as part of an etch mask. In some embodiments, the hard mask layer comprises amorphous silicon. In some embodiments, the plurality of second trenches comprises a plurality of inner trenches between the first outermost trench and the second outermost trench, and wherein the first outermost trench and the second outermost trench are deeper than all of the inner trenches in the plurality of inner trenches. In some embodiments, the plurality of inner trenches comprises a center trench between the first outermost trench and the second outermost trench, and wherein the trenches from the center trench to the first outermost trench have increasingly deeper depths.

[0136] According to some embodiments, a structure includes a semiconductor region, a gate stack, and a fin isolation region. The gate stack is on the semiconductor region, wherein the gate stack includes a first gate stack portion and a second gate stack portion. The fin isolation region separates the first gate stack portion and the second gate stack portion, wherein the fin isolation region includes a first portion and a plurality of second portions. The first portion is higher than a bottom surface of the gate stack. The plurality of second portions are located below the first portion and connected to the first portion, wherein a first outermost portion of the plurality of second portions has a first depth, and the first depth is equal to or greater than a second depth of an inner portion of the plurality of second portions.

[0137] In some embodiments, the first depth is equal to the second depth. In some embodiments, the first depth is greater than the second depth. In some embodiments, the plurality of second portions further include a second outermost portion and a center portion. The center portion is located between the first outermost portion and the second outermost portion, wherein the height of the plurality of second portions gradually increases from the center portion to the first outermost portion. In some embodiments, the structure further includes a gate isolation region extending through the gate stack, wherein the fin isolation region contacts the gate isolation region. In some embodiments, the fin isolation region extends into the gate isolation region.

[0138] According to some embodiments, a structure includes a semiconductor substrate, a first dielectric insulating region, a plurality of semiconductor fins, a gate stack, and a second dielectric insulating region. The first dielectric insulating region extends into the semiconductor substrate. A plurality of semiconductor fins protrude above the first dielectric insulating region and are parallel to each other. A gate stack is above the plurality of semiconductor fins. A plurality of source / drain regions extend into the plurality of semiconductor fins. The second dielectric insulating region contacts the sidewalls of the plurality of semiconductor fins. The gate stack and the second dielectric insulating region are located on opposite sides of the plurality of source / drain regions. The second dielectric insulating region includes an upper portion and a plurality of lower portions. The plurality of lower portions are located below the upper portion and connected to the upper portion, wherein the outer portions of the plurality of lower portions are deeper than the inner portions of the plurality of lower portions. In some embodiments, the outermost portions of the plurality of lower portions are the deepest of the plurality of lower portions. In some embodiments, the center portion of the plurality of lower portions is the shallowest of the plurality of lower portions.

[0139] According to some embodiments, a semiconductor device includes a semiconductor substrate, a first dielectric insulating region, a plurality of semiconductor fins, a plurality of first source / drain regions, a plurality of second source / drain regions, and a second dielectric insulating region. The first dielectric insulating region extends into the semiconductor substrate. The plurality of semiconductor fins protrude higher than the first dielectric insulating region and are parallel to each other. The plurality of first source / drain regions extend into the plurality of semiconductor fins. The plurality of second source / drain regions extend into the plurality of semiconductor fins. The second dielectric insulating region contacts the sidewalls of the plurality of semiconductor fins. The plurality of first source / drain regions and the plurality of second source / drain regions are located on opposite sides of the second dielectric insulating region. The second dielectric insulating region includes. an upper portion and a plurality of lower portions. The lower portion is located below the upper portion and connected to the upper portion. The outer portion of the plurality of lower portions is deeper than the inner portion of the plurality of lower portions.

[0140] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present application. Those skilled in the art should understand that they can easily use the content of this application as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present application, and they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present application.

Claims

1. A semiconductor element, characterized in that: Include: a semiconductor region; a gate stack on the semiconductor region, wherein the gate stack includes a first gate stack portion and a second gate stack portion; and A fin isolation region is provided to separate the first gate stack portion and the second gate stack portion, wherein the fin isolation region comprises: a first portion higher than a bottom surface of the gate stack; and A plurality of second parts are located below the first part and connected to the first part, wherein a first outermost part among the plurality of second parts has a first depth that is equal to or greater than a second depth of an inner part among the plurality of second parts.

2. The semiconductor device according to claim 1, wherein: The first depth is equal to the second depth.

3. The semiconductor device according to claim 1, wherein: The first depth is greater than the second depth.

4. The semiconductor device according to claim 1, wherein: The plurality of second parts further comprises: a second outermost portion; and A central portion is located between the first outermost portion and the second outermost portion, wherein the heights of the plurality of second portions gradually increase from the central portion to the first outermost portion.

5. The semiconductor device according to claim 1, wherein: The invention further comprises a gate isolation region penetrating the gate stack, wherein the fin isolation region contacts the gate isolation region.

6. The semiconductor device according to claim 5, wherein: The fin isolation region extends into the gate isolation region.

7. A semiconductor element, characterized in that: Include: a semiconductor substrate; A first dielectric insulating region extending into the semiconductor substrate; A plurality of semiconductor fins protruding above the first dielectric insulating region and parallel to each other; a gate stack above the plurality of semiconductor fins; a plurality of source / drain regions extending into the plurality of semiconductor fins; as well as a second dielectric insulating region contacting sidewalls of the plurality of semiconductor fins, wherein the gate stack and the second dielectric insulating region are located on opposite sides of the plurality of source / drain regions, wherein the second dielectric insulating region comprises: an upper portion; and A plurality of lower parts are located below the upper part and connected to the upper part, wherein outer parts of the plurality of lower parts are deeper than inner parts of the plurality of lower parts.

8. The semiconductor device according to claim 7, wherein: An outermost portion of the plurality of lower portions is the deepest of the plurality of lower portions.

9. The semiconductor device according to claim 8, wherein: A central portion among the plurality of lower portions is the shallowest among the plurality of lower portions.

10. A semiconductor element, characterized in that: Include: a semiconductor substrate; a first dielectric insulating region extending into the semiconductor substrate; A plurality of semiconductor fins protruding above the first dielectric insulating region and parallel to each other; a plurality of first source / drain regions extending into the plurality of semiconductor fins; a plurality of second source / drain regions extending into the plurality of semiconductor fins; as well as a second dielectric insulating region contacting sidewalls of the plurality of semiconductor fins, wherein the plurality of first source / drain regions and the plurality of second source / drain regions are located on opposite sides of the second dielectric insulating region, wherein the second dielectric insulating region comprises: an upper portion; and A plurality of lower parts are located below the upper part and connected to the upper part, wherein outer parts of the plurality of lower parts are deeper than inner parts of the plurality of lower parts.

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