Asymmetric silicon carbide trench gate VDMOS

Abstract

The utility model provides an asymmetric silicon carbide trench gate VDMOS, comprising a drift layer connected to a silicon carbide substrate, and the drift layer is provided with a groove; the first well region is connected to the drift layer; the second well region is arranged on the groove; the gate dielectric layer is connected to the drift layer, the gate dielectric layer is connected with the first well region, and a groove is formed in the gate dielectric layer; the first N-type source region is connected to the first well region, and the first N-type source region is connected to the gate dielectric layer; the second N-type source region is connected to the second well region, and the second N-type source region is connected to the gate dielectric layer; the first P-type source region is connected to the first well region, and the first P-type source region is connected to the first N-type source region; the second P-type source region is connected to the second well region, and the second P-type source region is connected to the second N-type source region; the source metal layer is respectively connected with the first well region, the first N-type source region, the second N-type source region, the first P-type source region and the second P-type source region; the gate metal layer is arranged in the groove; and the drain metal layer is connected to the silicon carbide substrate, so that the device with low follow current loss is realized.

Description

Technical Field

[0001] The utility model relates to an asymmetric silicon carbide trench gate VDMOS. Background Art

[0002] As a representative device among SiC power devices, SiC VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. Among them, trench gate SiC VDMOS has attracted much attention due to its advantages such as low on-resistance and low drive charge, but it has gate reliability issues caused by electric field concentration at the gate corner, weak body diode freewheeling capability and large on-state voltage drop. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide an asymmetric silicon carbide trench gate VDMOS to realize a device with both high-reliability gate and low freewheeling loss.

[0004] The utility model is implemented as follows: an asymmetric silicon carbide trench gate VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a groove is provided on the drift layer;

[0007] A first well region, wherein a lower side of the first well region is connected to an upper side of the drift layer;

[0008] a second well region, wherein the second well region is disposed on the groove;

[0009] a gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the drift layer, the left side of the gate dielectric layer is connected to the right side of the first well region, and a groove is provided in the gate dielectric layer;

[0010] A first N-type source region, wherein a lower side surface of the first N-type source region is connected to an upper side surface of the first well region, and a right side surface of the first N-type source region is connected to a left side surface of the gate dielectric layer;

[0011] a second N-type source region, wherein the lower side of the second N-type source region is connected to the upper side of the second well region, and the left side of the second N-type source region is connected to the right side of the gate dielectric layer;

[0012] A first P-type source region, wherein a lower side surface of the first P-type source region is connected to an upper side surface of the first well region, and a right side surface of the first P-type source region is connected to a left side surface of the first N-type source region;

[0013] a second P-type source region, wherein a lower side surface of the second P-type source region is connected to an upper side surface of the second well region, and a left side surface of the second P-type source region is connected to a right side surface of the second N-type source region;

[0014] A source metal layer, the source metal layer is respectively connected to the first well region, the first N-type source region, the second N-type source region, the first P-type source region and the second P-type source region;

[0015] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0016] and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0017] The utility model has the following advantages: the utility model is an asymmetric silicon carbide trench gate VDMOS, the device adopts an asymmetric device structure, and a high source voltage, a low drain voltage, and an internal NPN device structure when the device is not turned on are constructed on one side of the device, so that the large current can be continued before the device gate is controlled to be turned on; after the device is turned on, the second p-type well region below the second n+ source region is inverted to n-type under the control of the gate, and the npn structure becomes a full electronic conductive type, presenting a normal conduction and continued current state of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0019] Figure 1 The utility model is a schematic diagram of an asymmetric silicon carbide trench gate VDMOS.

[0020] Figure 2 The utility model is a flow chart of a method for preparing an asymmetric silicon carbide trench gate VDMOS.

[0021] Figure 3 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 1 .

[0022] Figure 4 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 2 .

[0023] Figure 5 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 3 .

[0024] Figure 6 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 4 .

[0025] Figure 7 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 5 .

[0026] Figure 8 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 6 .

[0027] Fig. 9 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 7 .

[0028] Fig.10 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 8 .

[0029] Fig.11 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 9 .

[0030] Fig.12 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 10 .

[0031] Fig.13 This is a cross-sectional view of the process of an asymmetric silicon carbide trench gate VDMOS of the utility model. Figure 10 one. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figure 1 As shown, the embodiment of the present application provides an asymmetric silicon carbide trench gate VDMOS, including:

[0038] Silicon carbide substrate 101,

[0039] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a groove 1021 is provided on the drift layer 102;

[0040] A first well region 103, wherein the lower side of the first well region 103 is connected to the upper side of the drift layer 102;

[0041] A second well region 104, wherein the second well region 104 is disposed on the groove 1021;

[0042] A gate dielectric layer 105, wherein the lower side of the gate dielectric layer 105 is connected to the upper side of the drift layer 102, the left side of the gate dielectric layer 105 is connected to the right side of the first well region 103, and a groove 1051 is provided in the gate dielectric layer 105;

[0043] A first N-type source region 106 , wherein the lower side of the first N-type source region 106 is connected to the upper side of the first well region 103 , and the right side of the first N-type source region 106 is connected to the left side of the gate dielectric layer 105 ;

[0044] A second N-type source region 107 , wherein the lower side of the second N-type source region 107 is connected to the upper side of the second well region 104 , and the left side of the second N-type source region 107 is connected to the right side of the gate dielectric layer 105 ;

[0045] A first P-type source region 108 , wherein the lower side of the first P-type source region 108 is connected to the upper side of the first well region 103 , and the right side of the first P-type source region 108 is connected to the left side of the first N-type source region 106 ;

[0046] A second P-type source region 109 , wherein the lower side of the second P-type source region 109 is connected to the upper side of the second well region 104 , and the left side of the second P-type source region 109 is connected to the right side of the second N-type source region 107 ;

[0047] A source metal layer 110 , wherein the source metal layer 110 is respectively connected to the first well region 103 , the first N-type source region 106 , the second N-type source region 107 , the first P-type source region 108 , and the second P-type source region 109 ;

[0048] A gate metal layer 111, wherein the gate metal layer 111 is disposed in the groove 1051;

[0049] And, a drain metal layer 112 , wherein the upper side of the drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101 .

[0050] In this embodiment, preferably, the depth of the groove 1021 is 300 nm; the thickness of the first well region 103 and the second well region 104 are both 300 nm.

[0051] In this embodiment, preferably, the thickness of the first N-type source region 106 and the first P-type source region 108 are both 300 nm.

[0052] In this embodiment, preferably, the thickness of the second N-type source region 107 and the second P-type source region 109 are both 600 nm.

[0053] In this embodiment, preferably, the width of the first N-type source region 106 is equal to the width of the first P-type source region 108 .

[0054] In this embodiment, preferably, the width of the second N-type source region 107 is equal to 1 / 6 to 1 / 3 of the width of the second P-type source region 109 .

[0055] In this embodiment, preferably, the doping concentration of the first P-type source region 108 is equal to the doping concentration of the second P-type source region 109 .

[0056] In this embodiment, preferably, the doping concentration of the first well region 103 is greater than the doping concentration of the second well region 104 .

[0057] In this embodiment, preferably, the doping concentration of the first N-type source region 106 is less than the doping concentration of the second N-type source region 107 .

[0058] The device adopts an asymmetric device structure. On one side of the device, a high source voltage and a low drain voltage are constructed. When the device is not turned on, the internal NPN device structure can complete the freewheeling of large current before the device gate control is turned on (i.e., the second N-type source region (with the source metal Schottky) - the p-type region controlled by the second P-type source region (source metal ohm) - the n-type region of the drift layer);

[0059] After the device is turned on, the second well region 104 below the second N-type source region 107 is inverted to n-type under the control of the gate, and the npn structure becomes a full electronic conductivity type, presenting a normal on-state of the device;

[0060] The depth of the second N-type source region 107 and the second P-type source region 109 is 600nm, the depth of the first N-type source region 106 and the first P-type source region 108 is 300nm, the depth of the first well region 103 is 600nm, and the depth of the second well region 104 is 900nm. When the depth of the first N-type source region 106 is consistent with the depth of the gate dielectric layer 105, this is to ensure the reliability of the gate corner while reducing the device resistance. The depth of the second N-type source region 107 is deeper in order to form a potential difference between the second N-type source region 107 and the source metal layer 110 through the second P-type source region 109 to the second well region 104, ensuring that the potential of the second well region 104 is higher than that of the second N-type source region 107, forming a conductive npn structure. In order to protect the reliability of the gate corner while forming an npn conductive structure under specific circumstances, the depth of the second well region 104 is 900nm.

[0061] like Figures 2 to 13 As shown, the preparation method of the above VDMOS includes the following steps:

[0062] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; depositing and growing on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0063] Step 2: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 102 to form a second well region 104, wherein the ion implantation energy is 10-300kev and the depth is 900nm;

[0064] Step 3, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the drift layer 102, form the first well region 103, the ion implantation energy is 10-200kev, and the depth is 600nm;

[0065] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the second well region 104, form a second P-type source region 109, the implantation energy is 10-200kev, and the depth is 600nm;

[0066] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the second well region 104, form a second N-type source region 107, the implantation energy is 10-200kev, and the depth is 600nm;

[0067] Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the first well region 103, form the first P-type source region 108, the implantation energy is 10-100kev, and the depth is 300nm;

[0068] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the first well region 103, form the first N-type source region 106, the implantation energy is 10-100kev, and the depth is 300nm;

[0069] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing metal deposition on the through hole to form a source metal layer 110;

[0070] Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the drift layer 102, the etching depth of the drift layer 102 is 900nm, and performing dry oxygen oxidation after etching to form a gate dielectric layer 105;

[0071] Step 10, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a and the gate dielectric layer 105 to form a groove 1051, deposit metal to form a gate metal layer 111, remove the barrier layer a, and complete the preparation.

[0072] The doping concentration of the silicon carbide substrate 101 is 2e18cm -3 The doping concentration of the drift layer 102 is 6e17cm -3 The doping concentration of the first well region 103 is 5e17 cm -3 , the doping concentration of the second well region 104 is 3e17 cm -3 The doping concentration of the first N-type source region 106 is 2e18cm -3 The doping concentration of the second N-type source region 107 is 5e18cm -3 The doping concentration of the first P-type source region 108 is 5e18cm -3 The doping concentration of the second P-type source region 109 is 5e18cm -3 The first well region 103 and the second well region 104 are both P-type, and the silicon carbide substrate 101 and the drift layer 102 are both N-type.

[0073] The gate dielectric layer 105 is silicon dioxide. The doping concentration of the silicon carbide substrate 101 is to form an ohmic contact with the drain metal layer while reducing the drain contact resistance. The doping concentration of the drift layer 102 is a compromise between reducing the on-resistance of the device and ensuring the withstand voltage. The doping concentration of the first well region 103 is higher than that of the second p-type well region 104 because the bottom of the first well region 103 is at the same height as the gate dielectric, which suppresses the breakdown caused by the electric field concentration at the gate corner; the second well region 104 is a compromise between the control of the device switching characteristics and the on-resistance. The first N-type source region 106 is to reduce the source contact resistance, thereby reducing the on-resistance of the device. The second N-type source region 107 is to ensure that the second N-type source region 107 with a resistance lower than the second P-type source region 109 is formed on the basis of reducing the source contact resistance. For the normal operation of the parasitic npn transistor, since the p-type doping resistance is larger under the same doping concentration condition, in order to ensure that its resistivity is close to that of the first N-type source region 106, the first P-type source region 108 and the second P-type source region 109 with the above doping concentration are selected.

[0074] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. An asymmetric silicon carbide trench gate VDMOS, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a groove is provided on the drift layer; A first well region, wherein a lower side of the first well region is connected to an upper side of the drift layer; a second well region, wherein the second well region is disposed on the groove; a gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the drift layer, the left side of the gate dielectric layer is connected to the right side of the first well region, and a groove is provided in the gate dielectric layer; A first N-type source region, wherein a lower side surface of the first N-type source region is connected to an upper side surface of the first well region, and a right side surface of the first N-type source region is connected to a left side surface of the gate dielectric layer; a second N-type source region, wherein the lower side of the second N-type source region is connected to the upper side of the second well region, and the left side of the second N-type source region is connected to the right side of the gate dielectric layer; A first P-type source region, wherein a lower side surface of the first P-type source region is connected to an upper side surface of the first well region, and a right side surface of the first P-type source region is connected to a left side surface of the first N-type source region; a second P-type source region, wherein a lower side surface of the second P-type source region is connected to an upper side surface of the second well region, and a left side surface of the second P-type source region is connected to a right side surface of the second N-type source region; A source metal layer, the source metal layer is respectively connected to the first well region, the first N-type source region, the second N-type source region, the first P-type source region and the second P-type source region; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

2. An asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The depth of the groove is 300 nm; the thickness of the first well region and the second well region are both 300 nm.

3. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The thickness of the first N-type source region and the first P-type source region are both 300 nm.

4. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The thickness of the second N-type source region and the second P-type source region are both 600 nm.

5. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The width of the first N-type source region is equal to the width of the first P-type source region.

6. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The width of the second N-type source region is equal to 1 / 6 to 1 / 3 of the width of the second P-type source region.

7. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region.

8. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The doping concentration of the first well region is greater than the doping concentration of the second well region.

9. The asymmetric silicon carbide trench gate VDMOS according to claim 1, characterized in that: The doping concentration of the first N-type source region is less than the doping concentration of the second N-type source region.

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