ESD (Electro-Static Discharge) circuit for full-chip protection, ESD circuit device and micro-processing chip

Abstract

The utility model provides an ESD circuit for full-chip protection, an ESD circuit device and a microprocessing chip, the ESD circuit comprises a first DCSCR device, the first end of the first DCSCR device is used for connecting a first level port, the second end of the first DCSCR device is used for connecting an I / O port, the first DCSCR device is used for connecting the I / O port when an ESD event exists in the first level port, and the second end of the first DCSCR device is used for connecting the I / O port when the ESD event exists in the I / O port. When the ESD event exists in the I-O port, discharging the current of the first level port to the I-O port, or when the ESD event exists in the I-O port, discharging the current of the I-O port to the first level port; the first end of the second DCSCR device is used for being connected with a first level port, the second end of the second DCSCR device is used for being connected with an I port, and the second DCSCR device is used for discharging the current of the second level port to the I port when the ESD event exists in the second level port, or discharging the current of the I port to the second level port when the ESD event exists in the I port. In the embodiment of the invention, bidirectional ESD protection between the two ports is realized, and the ESD protection circuit is suitable for a whole chip.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an ESD circuit, an ESD circuit device and a microprocessor chip for full chip protection. Background Art

[0002] Electrostatic discharge (ESD) refers to the charge transfer phenomenon that occurs when objects with different electric potentials are close to or in contact with each other. Since the discharge time is extremely short, a large current will be generated during the discharge process. For integrated circuits, modern chips are more susceptible to damage caused by ESD. This large current can damage or even burn internal devices, causing chip failure. Electrostatic discharge may occur in every link of chip production, transportation and use, so ESD protection measures for chips are indispensable to their reliability.

[0003] A diode directly connected thyristor (DCSCR) is an SCR device triggered by a diode string. It has many advantages such as low resistance and high robustness. At the same time, DCSCR can also adjust the trigger voltage through device stacking to meet different design window requirements. It is widely used in ESD protection under advanced processes.

[0004] However, the DCSCR devices in the prior art have at least the following problems when used for ESD protection: 1. The layout is not compact enough, resulting in a large layout area; 2. It can only be used for electrostatic protection in one direction (from anode to cathode) between two ports and is not suitable for the entire chip.

[0005] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0006] The present application provides an ESD circuit, an ESD circuit device and a microprocessor chip for full chip protection, so as to solve the problem that the ESD protection device in the prior art can only be used for electrostatic protection in one direction between two ports and is not suitable for the whole chip.

[0007] In a first aspect, an embodiment of the present application provides an ESD circuit for full chip protection, including:

[0008] a first DCSCR device, wherein a first end of the first DCSCR device is used to connect to a first level port, a second end of the first DCSCR device is used to connect to an IO port, and the first DCSCR device is used to discharge a current of the first level port to the IO port when an ESD event occurs at the first level port, or discharge a current of the IO port to the first level port when an ESD event occurs at the IO port;

[0009] A second DCSCR device, wherein the first end of the second DCSCR device is used to connect to a second level port, the second end of the second DCSCR device is used to connect to an IO port, and the second DCSCR device is used to discharge the current of the second level port to the IO port when an ESD event occurs at the second level port, or discharge the current of the IO port to the second level port when an ESD event occurs at the IO port.

[0010] In the embodiment of the present application, bidirectional ESD protection is implemented between two ports, which is applicable to the whole chip.

[0011] In a possible implementation, an RC detection module is further included, and the RC detection module includes:

[0012] a first transistor, wherein a drain of the first transistor is used to connect to the first level port, and a source of the first transistor is used to connect to the second level port;

[0013] A control circuit, wherein the first end of the control circuit is used to connect to the first level port, the second end of the control circuit is used to connect to the second level port, and the third end of the control circuit is electrically connected to the gate of the first transistor, and the control circuit is configured to: when an ESD event occurs at the first level port or the second level port, control the first transistor to be turned on; when no ESD event occurs at the first level port and the second level port, control the first transistor to be turned off.

[0014] In the embodiment of the present application, when an ESD event occurs at the first level port or the second level port, current discharge can be performed simultaneously through the ESD protection device and the RC detection module, thereby improving current discharge efficiency.

[0015] In a possible implementation manner, the first transistor is a PMOS transistor or an NMOS transistor.

[0016] In a possible implementation, the control circuit includes:

[0017] An RC circuit, wherein the RC circuit comprises a first resistor and a first capacitor connected in series, wherein a first end of the RC circuit is used to connect to the first level port, and a second end of the RC circuit is used to connect to the second level port;

[0018] a second transistor, wherein a gate of the first transistor is electrically connected to a node between the first resistor and the first capacitor, a source of the second transistor is used to connect to the first level port, and a drain of the second transistor is electrically connected to the gate of the first transistor;

[0019] a third transistor, wherein a gate of the third transistor is electrically connected to a node between the first resistor and the first capacitor, a source of the third transistor is used to connect to the second level port, and a drain of the third transistor is electrically connected to the gate of the first transistor.

[0020] In a possible implementation, the first end of the first resistor is used to connect to the first level port, the second end of the first resistor is electrically connected to the first end of the first capacitor, and the second end of the first capacitor is used to connect to the second level port;

[0021] or,

[0022] The first end of the first capacitor is used to connect to the first level port, the second end of the first capacitor is electrically connected to the first end of the first resistor, and the second end of the first resistor is used to connect to the second level port.

[0023] In a possible implementation, the method further includes:

[0024] A second resistor is connected in series between the first level port and the drain of the first transistor, or the second resistor is connected in series between the second level port and the source of the first transistor.

[0025] In a possible implementation manner, the second transistor is a PMOS transistor, and the third transistor is an NMOS transistor.

[0026] In a possible implementation, the first DCSCR device includes:

[0027] a fourth transistor, wherein a source of the fourth transistor is used to connect to the first level port;

[0028] a fifth transistor, wherein a drain of the fifth transistor is electrically connected to the gate of the fourth transistor, a gate of the fifth transistor is electrically connected to the drain of the fourth transistor, and a source of the fifth transistor is used to connect to the IO port;

[0029] a third resistor, a first end of the third resistor being connected to a node between the gate of the fourth transistor and the drain of the fifth transistor;

[0030] A fourth resistor, wherein a first end of the fourth resistor is electrically connected to the second end of the third resistor, and a second end of the fourth resistor is connected to a node between the drain of the fourth transistor and the gate of the fifth transistor.

[0031] In a possible implementation manner, the fourth transistor is an NMOS transistor, and the fifth transistor is a PMOS transistor.

[0032] In a possible implementation, the second DCSCR device includes:

[0033] a sixth transistor, wherein a source of the sixth transistor is used to connect to the IO port;

[0034] a seventh transistor, wherein a drain of the seventh transistor is electrically connected to the gate of the sixth transistor, a gate of the seventh transistor is electrically connected to the drain of the sixth transistor, and a source of the seventh transistor is used to connect to the second level port;

[0035] a fifth resistor, a first end of the fifth resistor being connected to a node between the gate of the sixth transistor and the drain of the seventh transistor;

[0036] A sixth resistor, wherein a first end of the sixth resistor is electrically connected to a second end of the fifth resistor, and a second end of the sixth resistor is connected to a node between a drain of the sixth transistor and a gate of the seventh transistor.

[0037] In a possible implementation manner, the sixth transistor is an NMOS transistor, and the seventh transistor is a PMOS transistor.

[0038] In a second aspect, an embodiment of the present application provides an ESD circuit device for full chip protection, including the ESD circuit for full chip protection as described in any one of the first aspect.

[0039] In a third aspect, an embodiment of the present application provides a microprocessor chip, comprising the ESD circuit for full chip protection as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0041] Figure 1A cross-sectional view of a DCSCR device provided for related technology;

[0042] Figure 2 A layout of a DCSCR device provided for related technology;

[0043] Figure 3 A cross-sectional view of an ESD protection device provided in an embodiment of the present application;

[0044] Figure 4 A layout of an ESD protection device provided in an embodiment of the present application;

[0045] Figure 5 A layout of another ESD protection device provided in an embodiment of the present application;

[0046] Figure 6 A layout of another ESD protection device provided in an embodiment of the present application;

[0047] Figure 7 A layout of another ESD protection device provided in an embodiment of the present application;

[0048] Fig. 8A A schematic diagram of the structure of an ESD protection circuit provided in an embodiment of the present application;

[0049] Figure 8B A schematic diagram of the structure of another ESD protection circuit provided in an embodiment of the present application;

[0050] Figure 8C A schematic diagram of the structure of another ESD protection circuit provided in an embodiment of the present application;

[0051] Fig. 9 A schematic diagram of the structure of an ESD circuit device provided in an embodiment of the present application;

[0052] Fig.10 A schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application;

[0053] Fig.11 A schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0055] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0056] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0057] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0058] To facilitate understanding, the abbreviations involved in this application are first explained below.

[0059] ESD: Electro Static Discharge, electrostatic discharge;

[0060] DCSCR: Di rect Connected Si l icon Controlled Rect ifier, diode directly connected triggered silicon controlled rectifier;

[0061] N-type: Donor impurities are added to the semiconductor to obtain an N-type semiconductor, in which there are more electrons than holes;

[0062] P-type: When acceptor impurities are added to a semiconductor, a P-type semiconductor is obtained. There are more holes than electrons in a P-type semiconductor.

[0063] A conductivity type: N type or P type, and different from B conductivity type;

[0064] B conductivity type: N type or P type, and different from A conductivity type;

[0065] Psub: P-type substrate;

[0066] NWe ll / NW: N-type well region, may also be referred to as "N well" for short;

[0067] PWe ll / PW: P-type well region, may also be referred to as "P well" for short;

[0068] DNWell / DNW: N-type deep well region, may also be referred to as "deep N well";

[0069] N+ / NPLUS: N-type doping region;

[0070] P+ / PPLUS: P-type doped region.

[0071] The ESD phenomenon refers to the charge transfer phenomenon that occurs when objects with different electric potentials are close to or in contact with each other. Since the discharge time is extremely short, a large current will be generated during the discharge process. For integrated circuits, modern chips are more susceptible to damage caused by ESD. This large current can damage or even burn internal devices, causing chip failure. Electrostatic discharge may occur in every link of chip production, transportation and use, so ESD protection measures for chips are indispensable to their reliability.

[0072] DCSCR is a SCR device triggered by a diode string. It has many advantages such as low resistance and high robustness. At the same time, DCSCR can also adjust the trigger voltage by stacking devices to meet the requirements of different design windows, and is widely used in ESD protection under advanced processes. The DCSCR device is equivalent to two diodes in series, and can replace diodes in ESD protection networks. The trigger voltage of DCSCR is only about 1.4V, which is the lowest turn-on voltage that SCR-type devices can achieve in silicon process, and is very suitable for the most advanced low-voltage ESD window (such as 0.8V circuit under 14nmFinFET process); for the relatively high operating voltage in traditional planar CMOS process, DCSCR can be flexibly met by stacking, and can also replace the diode device of I / O port in the full-chip ESD protection architecture based on power rail to achieve better parasitic capacitance characteristics; on the other hand, in DCSCR, since the emitter junctions of the two transistors parasitic to the SCR structure are just in the auxiliary trigger path, their charging time (i.e., Tcharge) is very fast, which makes DCSCR have the advantage of fast turn-on speed.

[0073] See also Figure 1 , a cross-sectional view of a DCSCR device provided in the related art; see Figure 2 , a layout of a DCSCR device provided in the related art. For the convenience of explanation, a first direction X and a second direction Y perpendicular to each other are defined on the layout, wherein the first direction X and the second direction Y are perpendicular to each other.

[0074] like Figure 1 Combined with Figure 2As shown, the DCSCR device includes a P-type substrate Psub, an N-type deep well region DNW is provided on the P-type substrate Psub, and an N-type well region NWe ll (may also be referred to as "N-well" in other parts of this article) and a P-type well region PWe ll (may also be referred to as "P-well" in other parts of this article) are provided in the N-type deep well region DNW. Among them, an N-type doping region 111 and a P-type doping region 121 are provided in the N-type well region NWe ll, and an N-type doping region 112 and a P-type doping region 122 are provided in the P-type well region PWe ll. Among them, the N-type doping region 111, the P-type doping region 121, the N-type doping region 112 and the P-type doping region 122 are arranged in sequence along the first direction X, and extend along the second direction Y respectively. In addition, the N-type doping region 111 in the N-type well region NWe ll and the P-type doping region 122 in the P-type well region PWe ll are connected by metal. The P-type doping region 121 is used to connect to the anode, and the N-type doping region 112 is used to connect to the cathode.

[0075] Based on the above structure of the DCSCR device, a diode D11 is formed between the N-type doping region 111 and the P-type doping region 121, and a diode D12 is formed between the N-type doping region 112 and the P-type doping region 122. When the voltage between the anode and the cathode meets the preset conditions, the current can be discharged from the anode to the cathode along the current discharge path, thereby achieving ESD protection.

[0076] However, the above DCSCR device has at least the following problems: 1. The layout is not compact enough, resulting in a large layout area; 2. It can only be used for electrostatic protection in one direction between two ports (current can only be discharged from the anode to the cathode, not from the cathode to the anode), and is not suitable for the whole chip.

[0077] Based on the above problems, the embodiment of the present application provides an ESD protection device, which adopts a simple and compact layout method to achieve bidirectional ESD protection between two ports, and is applicable to the whole chip. The specific implementation method is described in detail below.

[0078] See also Figure 3 , is a cross-sectional view of an ESD protection device provided in an embodiment of the present application; see Figure 4 , is a layout of an ESD protection device provided in an embodiment of the present application. For the convenience of explanation, a first direction X and a second direction Y perpendicular to each other are defined on the layout, wherein the first direction X and the second direction Y are perpendicular to each other.

[0079] like Figure 3 Combined with Figure 4As shown, the ESD protection device includes a P-type substrate Psub, an N-type deep well region DNW is provided on the P-type substrate Psub, and a P-type well region PWe ll and an N-type well region NWe ll are provided in the N-type deep well region DNW. A first N-type doping region 211, a second N-type doping region 212 and a third P-type doping region 223 are provided in the P-type well region NWe ll; a first P-type doping region 221, a second P-type doping region 222 and a third N-type doping region 213 are provided in the N-type well region NWe ll. Among them, the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222 and the second N-type doping region 212 are arranged in sequence along the first direction and extend along the second direction respectively. The third P-type doping region 223 and the third N-type doping region 213 extend along the first direction, respectively, and are located at the two ends of “the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222, and the second N-type doping region 212”. Specifically, the third P-type doping region 223 is located at the first end ( Figure 4 The third N-type doping region 213 is located at the second end of “the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222 and the second N-type doping region 212” ( Figure 4 upper end in the orientation shown).

[0080] In addition, the third P-type doping region 223 and the third N-type doping region 213 are connected by metal. The first N-type doping region 211 and the second P-type doping region 222 are used to connect the IO port, the first P-type doping region 221 is used to connect the second level port VSS, and the second N-type doping region 212 is used to connect the first level port VDD.

[0081] Based on the above structure of the ESD device, a first diode D21 and a second diode D22 are formed between the first N-type doping region 211 and the first P-type doping region 221, that is, a current discharge path between the first N-type doping region 211 and the first P-type doping region 221. A third diode D23 and a fourth diode D24 are formed between the second P-type doping region 222 and the second N-type doping region 212, that is, a current discharge path between the second P-type doping region 222 and the second N-type doping region 212. When there is no ESD event on the IO port, the voltage of the IO port is usually less than the voltage of the first level port VDD and greater than the voltage of the second level port VSS. In this state, the first diode D21, the second diode D22, the third diode D23 and the fourth diode D24 are all in a reverse cut-off state, so that the ESD protection device does not generate leakage current, thereby not interfering with the normally operating circuit. When there is a positive ESD event on the IO port (which may be due to static charge accumulation caused by external contact or coupling), the voltage of the IO port is usually greater than the voltage of the first level port VDD and the second level port VSS. In this state, the first diode D21 and the second diode D22 will be reversely broken down, and the third diode D23 and the fourth diode D24 are in a forward biased state, so that the current caused by the positive ESD event can pass through Figure 3 The current discharge path shown is discharged to the first level port VDD and / or the second level port VSS. When there is a negative ESD event on the IO port, the voltage of the IO port is usually less than the voltage of the first level port VDD and the second level port VSS. In this state, the first diode D21 and the second diode D22 are in a forward biased state, and the third diode D23 and the fourth diode D24 are reversely broken down, so that the current caused by the negative ESD event can pass through Figure 3 The current discharge path shown is discharged to the first level port VDD and / or the second level port VSS. Based on the same principle, when an ESD event occurs at the first level VSS port or the second level VDD port, the current can also be discharged to the first level port VDD and / or the second level port VSS. Figure 3 The current discharge path shown discharges the current to the IO port. That is, the ESD protection device provided in the embodiment of the present application can realize bidirectional ESD protection between two ports.

[0082] Please continue reading Figure 4 In the present application, in addition to the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222 and the second N-type doping region 212 extending along the second direction, there are also the third P-type doping region 223 and the third N-type doping region 213 extending along the first direction. Therefore, the overall layout of the ESD protection device is more compact, thereby reducing the area of ​​the layout.

[0083] See also Figure 5, is a layout diagram of another ESD protection device provided in an embodiment of the present application. Figure 4 The difference of the illustrated embodiment is that the third P-type doping region 223 further includes a first branch region 2231 and a second branch region 2232. The first branch region 2231 extends along the second direction and is disposed on a side of the first N-type doping region 211 away from the first P-type doping region 221, that is, the first branch region 2231 is disposed on the left side of the first N-type doping region 211. The second branch region 2232 extends along the second direction and is disposed on a side of the second N-type doping region 212 away from the second P-type doping region 222, that is, the second branch region 2232 is disposed on the right side of the second N-type doping region 212. The third N-type doping region 213 further includes a third branch region 2131, which extends along the second direction and is disposed between the first P-type doping region 221 and the second P-type doping region 222.

[0084] It can be understood that when the third P-type doping region 223 further includes the first branch region 2231 and the second branch region 2232, the free ends ( Figure 5 The upper end in the orientation shown in the figure is closer to the third N-type doping region 213. Therefore, the side of the third N-type doping region 213 close to the first branch region 2231 can be connected to the free end of the first branch region 2231 through metal, and the side of the third N-type doping region 213 close to the second branch region 2232 can be connected to the free end of the second branch region 2232 through metal to achieve the connection between the third N-type doping region 213 and the third P-type doping region 223. It should be noted that Figure 5 The layout shown is only an exemplary description provided by the embodiment of the present application. Those skilled in the art may also set only one or two branch regions among the first branch region 2231, the second branch region 2232 and the third branch region 2131 according to actual needs, and the embodiment of the present application does not specifically limit this.

[0085] In the embodiment of the present application, the layout of the ESD protection device is more compact, there are more contact points between components, the connection is tighter, and the triggering ability of the diode is stronger, thereby enhancing the ability to withstand reverse breakdown voltage.

[0086] Understandably, Figure 4 and Figure 5In the implementation shown, the third N-type doping region 213 and the third P-type doping region 223 both extend along the first direction. In a possible implementation, one of the third N-type doping region 213 and the third P-type doping region 223 may be set to extend along the first direction, and the other may be set to extend along the second direction. Exemplarily, the third N-type doping region 213 extends along the first direction, and the third P-type doping region 223 extends along the second direction; or, the third P-type doping region 223 extends along the first direction, and the third N-type doping region 213 extends along the second direction. This will be described in detail below in conjunction with specific embodiments.

[0087] See also Figure 6 , is a layout diagram of another ESD protection device provided in an embodiment of the present application. Figure 4 The difference of the illustrated embodiment is that the third P-type doping region 223 includes a first P-type doping sub-region 2233 and a second P-type doping sub-region 2234, and the first P-type doping sub-region 2233 and the second P-type doping sub-region 2234 extend along the second direction respectively. The first P-type doping sub-region 2233 is arranged on a side of the first N-type doping region 211 away from the first P-type doping region 221, that is, the first P-type doping sub-region 2233 is arranged on the left side of the first N-type doping region 211. The second P-type doping sub-region 2234 is arranged on a side of the second N-type doping region 212 away from the second P-type doping region 222, that is, the second P-type doping sub-region 2234 is arranged on the right side of the second N-type doping region 212.

[0088] The third N-type doping region 213 includes a first N-type doping sub-region 2132 and a second N-type doping sub-region 2133, the first N-type doping sub-region 2132 and the second N-type doping sub-region 2133 respectively extend along the first direction and are respectively located at both ends of “the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222 and the second N-type doping region 212”. Specifically, the first N-type doping sub-region 2132 is located at the first end ( Figure 6 The second N-type doping sub-region 2133 is located at the second end of “the first N-type doping region 211, the first P-type doping region 221, the second P-type doping region 222 and the second N-type doping region 212” ( Figure 6 upper end in the orientation shown).

[0089] Further, two ends of the first N-type doped sub-region 2132 are respectively connected to the first ends of the first P-type doped sub-region 2233 and the second P-type doped sub-region 2234 ( Figure 6The two ends of the second N-type doped sub-region 2133 are respectively connected to the second ends ( Figure 6 The upper end in the orientation shown) is connected by metal to achieve electrical connection between the third N-type doping region 213 and the third P-type doping region 223.

[0090] It should be pointed out that in some possible implementations, the first P-type doped sub-region 2233 and the second P-type doped sub-region 2234 can be set to extend along the first direction, and the first N-type doped sub-region 2132 and the second N-type doped sub-region 2133 can be set to extend along the second direction, and the embodiments of the present application are not limited to this.

[0091] In the embodiment of the present application, the layout of the ESD protection device can achieve simultaneous upper and lower triggering and discharge. When subjected to an ESD event impact, it can respond quickly and improve the discharge efficiency.

[0092] See also Figure 7 , is a layout diagram of another ESD protection device provided in an embodiment of the present application. Figure 6 The difference of the illustrated embodiment is that the ESD protection device further includes a third N-type doping sub-region 2134, which is connected between the first N-type doping sub-region 2132 and the second N-type doping sub-region 2133, extending along the second direction, and the third N-type doping sub-region 2134 is disposed between the first P-type doping region 221 and the second P-type doping region 222. It can be understood that after the third N-type doping sub-region 2134 is disposed, the shape of the third N-type doping region 213 composed of the first N-type doping sub-region 2132, the second N-type doping sub-region 2133 and the third N-type doping sub-region 2134 is an "I" shape.

[0093] It should be pointed out that, relative to Figure 4 The layout design scheme in Figure 5-Figure 7 The layout design scheme in the present invention can make the diode in the ESD protection device have a lower trigger voltage and a faster response speed, thereby improving the ESD protection performance of the ESD protection device.

[0094] In addition, the P-type and N-type in each part of the ESD protection device in the above embodiment can be interchanged. In general, the ESD protection device includes: an A conductive type substrate; a B conductive type deep well region, the B conductive type deep well region is arranged in the A conductive type substrate; an A conductive type well region, the A conductive type well region is arranged in the B conductive type deep well region, and the A conductive type well region is provided with a first B conductive type doping region, a second B conductive type doping region and a third A conductive type doping region; a B conductive type well region, the B conductive type well region is arranged in the B conductive type deep well region, and the B conductive type well region is provided with a first A conductive type doping region, a second A conductive type doping region and a third B conductive type doping region; the first B conductive type doping region, the first A conductive type doping region, the second A conductive type doping region and the second B conductive type doping region are arranged in sequence along the first direction and extend along the second direction respectively, and the first direction and the second direction are perpendicular; the third A conductive type doping region and / or the third B conductive type doping region extend along the first direction, and the third A conductive type doping region and the third B conductive type doping region are connected by a metal wire.

[0095] In the above embodiment, the conductivity type of A is P type, and the conductivity type of B is N type. In specific implementation, the conductivity type of A can also be N type, and the conductivity type of B can be P type. For the specific content, please refer to the description of the above embodiment. For the sake of brevity, it will not be repeated here.

[0096] Corresponding to the above-mentioned embodiment, the embodiment of the present application further provides an ESD circuit for full chip protection.

[0097] See also Fig. 8A , is a schematic diagram of the structure of an ESD circuit for full chip protection provided in an embodiment of the present application. Fig. 8AAs shown, the ESD circuit includes an ESD protection device and an RC detection module. Among them, the ESD protection device includes a first DCSCR device and a second DCSCR device. The first end of the first DCSCR device is used to connect the first level port VDD, the second end of the first DCSCR device is used to connect the IO port, and the first DCSCR device is used to discharge the current of the first level port VDD to the IO port when an ESD event occurs at the first level port VDD, or when an ESD event occurs at the IO port, discharge the current of the IO port to the first level port VDD. In other words, the first DCSCR device can realize bidirectional ESD protection between the first level port VDD and the IO port, thereby realizing protection of the internal circuit. The first end of the second DCSCR device is used to connect the second level port VSS, the second end of the second DCSCR device is used to connect the IO port, and the second DCSCR device is used to discharge the current of the second level port VSS to the IO port when an ESD event occurs at the second level port VSS, or when an ESD event occurs at the IO port, discharge the current of the IO port to the second level port VSS. That is to say, the second DCSCR device can realize bidirectional ESD protection between the second level port VSS and the IO port, thereby realizing protection of the internal circuit.

[0098] The RC detection module includes a first transistor Mesd and a control circuit. Among them, the drain of the first transistor Mesd is used to connect to the first level port VDD, and the source of the first transistor Mesd is used to connect to the second level port VSS; the first end of the control circuit is used to connect to the first level port VDD, the second end of the control circuit is used to connect to the second level port VSS, and the third end of the control circuit is electrically connected to the gate of the first transistor Mesd. The control circuit is configured to: when there is an ESD event at the first level port VDD or the second level port VSS, control the first transistor Mesd to turn on; when there is no ESD event at the first level port VDD and the second level port VSS, control the first transistor Mesd to turn off. In a specific implementation, the first transistor Mesd is a PMOS tube or an NMOS tube. It can be understood that when there is an ESD event, the first transistor Mesd is turned on, and then the current of the first level port VDD can be discharged to the second level port VSS or the current of the second level port VSS can be discharged to the first level port VDD, so as to realize bidirectional ESD protection between the first level port VDD and the second level port VSS, so as to realize protection of the internal circuit. In addition, when there is no ESD event, the first transistor Mesd is disconnected, and the RC detection module does not generate leakage current, thereby not interfering with the normally operating internal circuit.

[0099] In summary, in the embodiments of the present application, when an ESD event occurs, the current between different ports can be discharged simultaneously through the ESD protection device and the RC detection module, thereby increasing the current discharge speed and thus improving the protection effect of the internal circuit. It should be noted that in some possible implementations, the ESD circuit may only include an ESD protection device but not an RC detection module, and the embodiments of the present application do not specifically limit this.

[0100] Please continue reading Fig. 8A In a possible implementation, the control circuit includes an RC circuit, a second transistor Mp and a third transistor Mn. The RC circuit includes a first resistor R1 and a first capacitor C1 connected in series, the first end of the RC circuit is used to connect to the first level port VDD, and the second end of the RC circuit is used to connect to the second level port VSS. Specifically, the first end of the first resistor R1 is used to connect to the first level port VDD, the second end of the first resistor R1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is used to connect to the second level port VSS. The gate of the second transistor Mp is electrically connected to the node between the first resistor R1 and the first capacitor C1, the source of the second transistor Mp is used to connect to the first level port VDD, and the drain of the second transistor Mp is electrically connected to the gate of the first transistor Mesd; the gate of the third transistor Mn is electrically connected to the node between the first resistor R1 and the first capacitor C1, the source of the third transistor Mn is used to connect to the second level port VSS, and the drain of the third transistor Mn is electrically connected to the gate of the first transistor Mesd. In a specific implementation, the second transistor Mp is a PMOS tube, and the third transistor Mn is an NMOS tube.

[0101] In the embodiment of the present application, when there is no ESD event, the first capacitor C1 is equivalent to an open circuit, and the gates of the second transistor Mp and the third transistor Mn receive a high level passing through the first resistor R1, so that the second transistor Mp is turned off and the third transistor Mn is turned on. Further, since the second transistor Mp is turned off and the third transistor Mn is turned on, the first transistor Mesd receives a low level and the first transistor Mesd is turned off. It can be understood that when the first transistor Mesd is turned off, the RC detection module will not generate leakage current, thereby not interfering with the normal working circuit. When an ESD event occurs at the first level port VDD or the second level port VSS, the RC circuit composed of the first resistor R1 and the first capacitor C1 is equivalent to receiving a high-frequency alternating current, the first capacitor C1 is regarded as a path, and the gates of the second transistor Mp and the third transistor Mn receive a low level, so that the second transistor Mp is turned on and the third transistor Mn is turned off. Further, since the second transistor Mp is turned on and the third transistor Mn is turned off, the first transistor Mesd receives a high level and the first transistor Mesd is turned on. It can be understood that when the first transistor Mesd is turned on, the current of the first level port VDD can be discharged to the second level port VSS through the RC detection module, or the current of the second level port VSS can be discharged to the first level port VDD through the RC detection module to achieve ESD protection.

[0102] Please continue reading Fig. 8A In a possible implementation, the first DCSCR device includes a fourth transistor M4, a fifth transistor M5, a third resistor R3 (P well resistor R PW ) and the fourth resistor R4 (N-well resistor R NW ). Among them, the source of the fourth transistor M4 is used to connect to the first level port VDD; the drain of the fifth transistor M5 is electrically connected to the gate of the fourth transistor M4, the gate of the fifth transistor M5 is electrically connected to the drain of the fourth transistor M4, and the source of the fifth transistor M5 is used to connect to the IO port; the first end of the third resistor R3 is connected to the node between the gate of the fourth transistor M4 and the drain of the fifth transistor M5; the first end of the fourth resistor R4 is electrically connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is connected to the node between the drain of the fourth transistor M4 and the gate of the fifth transistor M5. In a specific implementation, the fourth transistor M4 is an NMOS tube, and the fifth transistor M5 is a PMOS tube.

[0103] In a possible implementation, the second DCSCR device includes a sixth transistor M6, a seventh transistor M7, a fifth resistor R5 (P-well resistor R PW ) and the sixth resistor R6 (N-well resistor R NW). Among them, the source of the sixth transistor M6 is used to connect to the IO port; the drain of the seventh transistor M7 is electrically connected to the gate of the sixth transistor M6, the gate of the seventh transistor M7 is electrically connected to the drain of the sixth transistor M6, and the source of the seventh transistor M7 is used to connect to the second level port VSS; the first end of the fifth resistor R5 is connected to the node between the gate of the sixth transistor M6 and the drain of the seventh transistor M7; the first end of the sixth resistor R6 is electrically connected to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is connected to the node between the drain of the sixth transistor M6 and the gate of the seventh transistor M7. In a specific implementation, the sixth transistor M6 is an NMOS tube, and the seventh transistor M7 is a PMOS tube.

[0104] It should be pointed out that Fig. 8A This is only an exemplary description of the ESD circuit in the embodiment of the present application. Those skilled in the art can Fig. 8A Adding devices or adjusting the connection relationship between devices to achieve the same or similar functions should fall within the protection scope of this application.

[0105] Exemplarily, the connection sequence of the first resistor R1 and the first capacitor C1 can be adjusted, that is, the first end of the first capacitor C1 is used to connect to the first level port VDD, the second end of the first capacitor C1 is electrically connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to connect to the second level port VSS, such as Figure 8B shown.

[0106] Exemplarily, a resistor is added in series with the first transistor Mesd. Specifically, the second resistor R2 is connected in series between the second level port VSS and the source of the first transistor Mesd, such as Figure 8C Of course, the second resistor R2 can also be connected in series between the first level port VDD and the drain of the first transistor Mesd, and the embodiment of the present application does not impose any specific limitation on this.

[0107] It should be noted that the layout design of ESD protection devices in the ESD circuit can refer to the above description. For the sake of brevity, it will not be repeated in the ESD circuit part.

[0108] Corresponding to the above-mentioned embodiment, the embodiment of the present application also provides an ESD circuit device for full chip protection.

[0109] See also Fig. 9 , is a schematic diagram of the structure of an ESD circuit device for full chip protection provided by an embodiment of the present application. Fig. 9As shown, the ESD circuit device includes an ESD circuit, and the ESD circuit is the ESD circuit described in the above embodiment. The specific content of the ESD circuit can be found in the above description, and will not be repeated here for the sake of simplicity.

[0110] Corresponding to the above embodiment, the embodiment of the present application also provides a microprocessor chip.

[0111] See also Fig.10 , is a schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application. Fig.10 As shown, the microprocessor chip includes an ESD protection device, which is the ESD protection device described in the above embodiment. The ESD protection device can be used to implement ESD protection for the entire microprocessor chip.

[0112] It should be noted that the microprocessor chip can be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions.

[0113] For details about the ESD protection device, please refer to the description of the above embodiments. For the sake of brevity, it will not be repeated here.

[0114] Corresponding to the above embodiment, the embodiment of the present application also provides another microprocessor chip.

[0115] See also Fig.11 , is a schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. Fig.11 As shown, the microprocessor chip includes an ESD circuit, which is the ESD circuit described in the above embodiment. The ESD circuit can be used to implement ESD protection for the entire microprocessor chip.

[0116] It should be noted that the microprocessor chip can be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions.

[0117] For the specific content of the ESD circuit, please refer to the description of the above embodiment. For the sake of brevity, it will not be repeated here.

[0118] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0119] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0121] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0122] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An ESD circuit for full chip protection, characterized in that: include: a first DCSCR device, wherein a first end of the first DCSCR device is used to connect to a first level port, a second end of the first DCSCR device is used to connect to an IO port, and the first DCSCR device is used to discharge a current of the first level port to the IO port when an ESD event occurs at the first level port, or discharge a current of the IO port to the first level port when an ESD event occurs at the IO port; A second DCSCR device, wherein the first end of the second DCSCR device is used to connect to a second level port, the second end of the second DCSCR device is used to connect to an IO port, and the second DCSCR device is used to discharge the current of the second level port to the IO port when an ESD event occurs at the second level port, or discharge the current of the IO port to the second level port when an ESD event occurs at the IO port.

2. The ESD circuit according to claim 1, characterized in that: It also includes an RC detection module, the RC detection module includes: a first transistor, wherein a drain of the first transistor is used to connect to the first level port, and a source of the first transistor is used to connect to the second level port; A control circuit, wherein the first end of the control circuit is used to connect to the first level port, the second end of the control circuit is used to connect to the second level port, and the third end of the control circuit is electrically connected to the gate of the first transistor, and the control circuit is configured to: when an ESD event occurs at the first level port or the second level port, control the first transistor to be turned on; when no ESD event occurs at the first level port and the second level port, control the first transistor to be turned off.

3. The ESD circuit according to claim 2, characterized in that: The first transistor is a PMOS transistor or an NMOS transistor.

4. The ESD circuit according to claim 2, characterized in that: The control circuit comprises: An RC circuit, wherein the RC circuit comprises a first resistor and a first capacitor connected in series, wherein a first end of the RC circuit is used to connect to the first level port, and a second end of the RC circuit is used to connect to the second level port; a second transistor, wherein a gate of the second transistor is electrically connected to a node between the first resistor and the first capacitor, a source of the second transistor is used to connect to the first level port, and a drain of the second transistor is electrically connected to the gate of the first transistor; a third transistor, wherein a gate of the third transistor is electrically connected to a node between the first resistor and the first capacitor, a source of the third transistor is used to connect to the second level port, and a drain of the third transistor is electrically connected to the gate of the first transistor.

5. The ESD circuit according to claim 4, characterized in that: The first end of the first resistor is used to connect to the first level port, the second end of the first resistor is electrically connected to the first end of the first capacitor, and the second end of the first capacitor is used to connect to the second level port; or, The first end of the first capacitor is used to connect to the first level port, the second end of the first capacitor is electrically connected to the first end of the first resistor, and the second end of the first resistor is used to connect to the second level port.

6. The ESD circuit according to claim 4, characterized in that: Also includes: A second resistor is connected in series between the first level port and the drain of the first transistor, or the second resistor is connected in series between the second level port and the source of the first transistor.

7. The ESD circuit according to claim 4, characterized in that: The second transistor is a PMOS transistor, and the third transistor is an NMOS transistor.

8. The ESD circuit according to claim 1, characterized in that: The first DCSCR device comprises: a fourth transistor, wherein a source of the fourth transistor is used to connect to the first level port; a fifth transistor, wherein a drain of the fifth transistor is electrically connected to the gate of the fourth transistor, a gate of the fifth transistor is electrically connected to the drain of the fourth transistor, and a source of the fifth transistor is used to connect to the IO port; a third resistor, a first end of the third resistor being connected to a node between the gate of the fourth transistor and the drain of the fifth transistor; A fourth resistor, wherein a first end of the fourth resistor is electrically connected to the second end of the third resistor, and a second end of the fourth resistor is connected to a node between the drain of the fourth transistor and the gate of the fifth transistor.

9. The ESD circuit according to claim 8, characterized in that: The fourth transistor is an NMOS transistor, and the fifth transistor is a PMOS transistor.

10. The ESD circuit according to claim 1, characterized in that: The second DCSCR device comprises: a sixth transistor, wherein a source of the sixth transistor is used to connect to the IO port; a seventh transistor, wherein a drain of the seventh transistor is electrically connected to the gate of the sixth transistor, a gate of the seventh transistor is electrically connected to the drain of the sixth transistor, and a source of the seventh transistor is used to connect to the second level port; a fifth resistor, a first end of the fifth resistor being connected to a node between the gate of the sixth transistor and the drain of the seventh transistor; A sixth resistor, wherein a first end of the sixth resistor is electrically connected to a second end of the fifth resistor, and a second end of the sixth resistor is connected to a node between a drain of the sixth transistor and a gate of the seventh transistor.

11. The ESD circuit according to claim 10, characterized in that: The sixth transistor is an NMOS transistor, and the seventh transistor is a PMOS transistor.

12. An ESD circuit device for full chip protection, characterized in that: An ESD circuit for full chip protection comprising the ESD circuit described in any one of claims 1-11.

13. A microprocessor chip, characterized in that: An ESD circuit for full chip protection comprising the ESD circuit described in any one of claims 1-11.

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