Stacked image sensor chip and electronic equipment

Abstract

The utility model describes a stack type image sensor chip, which comprises a first semiconductor substrate and a second semiconductor substrate which are oppositely stacked, the first semiconductor substrate comprises a pixel substrate layer and a first bonding layer, the pixel substrate layer comprises a logic area and a pixel area, and the pixel area comprises a plurality of pixel units arranged in an array; the second semiconductor substrate at least comprises a second bonding layer and a functional element layer; the first bonding layer comprises a plurality of first complementary parts which are projected in the first direction and located in the pixel area, the second bonding layer comprises a plurality of second complementary parts which are projected in the first direction and located in the pixel area, and the first complementary parts and the second complementary parts are arranged in a staggered mode. By designing the metal block complementary structure of the pixel wafer and the logic wafer, a light-blocking shielding layer is formed, and the influence of heat and light emitting of the logic wafer on the performance of the pixel wafer in the working process is reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductors, in particular to an electronic device comprising a stacked image sensor chip. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As semiconductor technology enters the post-Moore era, in order to meet the needs of high integration and high performance, the chip structure is developing towards a three-dimensional direction, and wafer-level bonding technology has been widely used. Traditional image sensor chips use a two-dimensional architecture, in which the pixel area and the logic area are arranged in a two-dimensional plane, and a considerable part of the chip area is a non-pixel area, resulting in a limit on the number of pixels that can be set, thereby affecting the image quality. Stacked image sensor chips were thus born. In stacked image sensor chips, the hybrid bonding process, which is a key technology for wafer three-dimensional integration, is applied, and how to bond the bonding layers on multiple wafers becomes the key. Utility Model Content

[0003] In view of this, the utility model provides a stacked image sensor chip, which comprises at least a first semiconductor substrate and a second semiconductor substrate stacked opposite to each other, wherein: the first semiconductor substrate comprises a pixel substrate layer arranged away from a side of the second semiconductor substrate and a first bonding layer arranged close to a side of the second semiconductor substrate, the pixel substrate layer comprises a logic area and a pixel area, the pixel area comprises a plurality of pixel units arranged in an array; the second semiconductor substrate comprises at least a second bonding layer arranged close to a side of the first semiconductor substrate and a functional element layer arranged away from a side of the first semiconductor substrate; the first bonding layer comprises a plurality of first complementary portions whose projections along a first direction are located in the pixel area, the second bonding layer comprises a plurality of second complementary portions whose projections along the first direction are located in the pixel area, the first direction is a direction from the second semiconductor substrate to the first semiconductor substrate, wherein the first complementary portion and the second complementary portion are staggered.

[0004] Optionally, the first complementary portion is located on a side away from the second semiconductor substrate.

[0005] Optionally, the second complementary portion is located on a side away from the first semiconductor substrate.

[0006] Optionally, projections of the first complementary portion and the second complementary portion along the first direction cover the pixel area.

[0007] Optionally, the first bonding layer also includes a plurality of first interface bonding blocks located close to the second semiconductor substrate and whose projections along the first direction are located at the pixel area, and the second bonding layer also includes a plurality of second interface bonding blocks located close to the first semiconductor substrate and whose projections along the first direction are located at the pixel area, and the first interface bonding blocks are in contact and bonded with the second interface bonding blocks.

[0008] Optionally, the first bonding layer also includes a first metal routing and a first interface bonding block, and the first complementary part is connected to the first interface bonding block through the first metal routing; the second bonding layer also includes a second metal routing and a second interface bonding block, and the second complementary part is connected to the second interface bonding block through the second metal routing; the first interface bonding block and the second interface bonding block are in contact and bonded with each other to achieve electrical connection between the first complementary part and the second complementary part.

[0009] Optionally, the second complementary portion is located on a side close to the first semiconductor substrate.

[0010] Optionally, the first bonding layer further includes a first interface bonding block located on a side close to the second semiconductor substrate, and the second complementary portion is in contact and bonded with the first interface bonding block.

[0011] Optionally, the first bonding layer further includes a first bonding portion whose projection along the first direction is located in the logic area, and the second bonding layer further includes a second bonding portion whose projection along the first direction is located in the logic area, and the first bonding portion and the second bonding portion are bonded to each other.

[0012] The present application also provides an electronic device, comprising the above-mentioned stacked image sensor chip.

[0013] Compared with the prior art, the utility model has at least one of the following outstanding advantages:

[0014] In the present application, by staggering the first complementary portion on the first semiconductor substrate and the second complementary portion on the second semiconductor substrate, the complementary structure formed by the first complementary portion and the second complementary portion can shield the light or heat generated during the operation of the second semiconductor substrate, thereby reducing the impact on the pixel unit in the first semiconductor substrate, and improving the performance of the image sensor chip on the basis of the existing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a partial cross-sectional schematic diagram of a stacked image sensor chip in the prior art;

[0016] Figure 2is a schematic diagram of a film layer structure of a stacked image sensor chip provided in an embodiment of the present application;

[0017] Figure 3 It is a schematic diagram of the positions of a logic area and a pixel area on a first semiconductor substrate provided by an embodiment of the present application;

[0018] Figure 4 is another schematic diagram of the positions of a logic area and a pixel area on a first semiconductor substrate provided by an embodiment of the present application;

[0019] Figure 5 This is another schematic diagram of the positions of the logic area and the pixel area on the first semiconductor substrate provided by an embodiment of the present application;

[0020] Figure 6 is a partial cross-sectional schematic diagram of a stacked image sensor chip provided in an embodiment of the present application;

[0021] Figure 7 is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application;

[0022] Figure 8 is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application;

[0023] Fig. 9 is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application;

[0024] Fig.10 is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application;

[0025] Fig.11 It is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application.

[0026] Component number description

[0027] 10. First semiconductor substrate

[0028] 20. Second semiconductor substrate

[0029] 110 First bonding layer

[0030] 120 pixel substrate layer

[0031] 210 Second bonding layer

[0032] 220 Functional Component Layer

[0033] 111 First bonding part

[0034] 113 First Top Metal

[0035] 115 first interface bonding block

[0036] 212 Second bonding portion

[0037] 214 Second top metal

[0038] 216 Second interface bonding block

[0039] 218 Second metal routing

[0040] M1 The first complementary part

[0041] M2 Second complementary part

[0042] LA Logical Area

[0043] PA pixel area DETAILED DESCRIPTION

[0044] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0046] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0047] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0049] like Figure 1 As shown, in the prior art, stacked image sensor chips are made by hybrid bonding of logic wafers and pixel wafers. Since the logic wafer will generate heat and light during operation, it will affect the photosensitive area of ​​the pixel wafer, thereby affecting the image quality. Therefore, it is urgent to achieve performance improvement through existing processes. This application designs a complementary structure of metal blocks of the logic wafer and the pixel wafer to form a light-blocking shielding layer, thereby reducing the impact of heat and light generated by the logic wafer during operation on the performance of the pixel wafer.

[0050] In the embodiments of the present application, Figure 2 The schematic diagram of the film layer structure of the stacked image sensor chip shown in the figure, the stacked image sensor chip at least includes a first semiconductor substrate 10 and a second semiconductor substrate 20 stacked opposite to each other; it can be understood that the first semiconductor substrate is a semiconductor chip provided with a pixel area, and some functional modules are arranged on the second semiconductor substrate, and the functional modules include some logic areas, memories and processor circuits, etc., so as to increase the usable area of ​​the pixel unit on a single semiconductor substrate, improve the image quality and optimize the performance of the logic elements in the logic area; in some embodiments, the second semiconductor substrate can be a chip with specific functions, such as an application-specific integrated circuit chip (ASIC), a field programmable gate array (FPGA), a dynamic random access memory (DRAM) or a static random access memory (SRAM), etc.

[0051] The first semiconductor substrate 10 includes a pixel substrate layer 120 disposed away from the second semiconductor substrate 20 and a first bonding layer 110 disposed close to the second semiconductor substrate 20. The pixel substrate layer 120 includes a logic area LA and a pixel area PA, wherein the pixel area PA includes a plurality of pixel units disposed in an array, and the plurality of pixel units in the pixel area PA may be arranged in a two-dimensional array structure, and each pixel unit may include a photodiode and a plurality of pixel transistors. Optionally, the pixel transistors include a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor; the logic area LA may be provided with a logic element for processing a pixel signal from the pixel area. For example, Figure 3 As shown, the logic area LA is located on one side of the first semiconductor substrate, and the pixel area PA is located on the other side of the first semiconductor substrate; illustratively, as Figure 4 As shown, the logic area LA is located on both sides of the pixel area PA; illustratively, as Figure 5 As shown, the logic area LA is arranged around the pixel area PA. The positional relationship between the logic area LA and the pixel area PA is designed according to actual needs and is not limited here.

[0052] Continue to refer Figure 2 The second semiconductor substrate 20 at least includes a second bonding layer 210 disposed close to a side of the first semiconductor substrate 10 and a functional element layer 220 disposed away from a side of the first semiconductor substrate 10, wherein the functional element layer 220 may include a portion of a logic area, a memory, a processor circuit, etc.;

[0053] The first bonding layer 110 includes a plurality of first complementary parts M1 projected along the first direction and located in the pixel area PA, and the second bonding layer 210 includes a plurality of second complementary parts M2 projected along the first direction and located in the pixel area PA, wherein the first direction is the direction from the second semiconductor substrate 20 to the first semiconductor substrate 10, wherein the first complementary parts M1 and the second complementary parts M2 are staggered. It can be understood that the staggered arrangement means that along the first direction, the second complementary parts M2 make up for the gap between adjacent first complementary parts M1, so that the light or heat generated during the operation of the second semiconductor substrate 20 is shielded by the complementary structure formed by the first complementary parts M1 and the second complementary parts M2, thereby reducing the impact on the pixel unit in the first semiconductor substrate 10.

[0054] Furthermore, the first bonding layer 110 also includes a first bonding portion 111 whose projection along the first direction is located in the logic area LA, and the second bonding layer 210 also includes a second bonding portion 212 whose projection along the first direction is located in the logic area LA. The first bonding portion 111 and the second bonding portion 212 are bonded to achieve electrical connection between the first semiconductor substrate 10 and the second semiconductor substrate 20.

[0055] In the embodiment of the present application, the first complementary portion M1 on the first semiconductor substrate 10 and the second complementary portion M2 on the second semiconductor substrate 20 are staggered so that the complementary structure formed by the first complementary portion M1 and the second complementary portion M2 can shield the light or heat generated during the operation of the second semiconductor substrate 20, thereby reducing the impact on the pixel unit in the first semiconductor substrate 10, thereby improving the performance of the image sensor chip on the basis of the existing process.

[0056] In some embodiments, in conjunction with reference Figure 2 and Figure 6 The first complementary portion M1 is located at a side away from the second semiconductor substrate 20, and the second complementary portion M2 is located at a side away from the first semiconductor substrate 10. That is, the first complementary portion M1 is the first top metal 113 in the first semiconductor substrate 10, and the second complementary portion 214 is the second top metal 214 in the second semiconductor substrate 20.

[0057] Optionally, the first complementary portion M1 and the second complementary portion M2 have the same size, which improves process simplicity.

[0058] Optionally, the projections of the first complementary portion M1 and the second complementary portion M2 along the first direction cover the pixel area PA. This design allows the heat and light generated during the operation of the second semiconductor substrate 20 to be shielded as much as possible by the complementary structure formed by the first complementary portion M1 and the second complementary portion M2.

[0059] In the embodiment of the present application, a complementary structure is formed between two top-layer metals to shield the heat and light generated by the working process of the second semiconductor substrate, so that the pixel unit in the first semiconductor substrate is not affected by crosstalk, thereby improving the performance of the image sensor chip based on the existing process.

[0060] In some embodiments, Figure 7 As shown, the first complementary portion M1 is located on the side away from the second semiconductor substrate 20, and the second complementary portion M2 is located on the side away from the first semiconductor substrate 10, that is, the first complementary portion M1 is the first top metal 113 in the first semiconductor substrate 10, and the second complementary portion 214 is the second top metal 214 in the second semiconductor substrate 20; and the first bonding layer 110 also includes a plurality of first interface bonding blocks 115 located on the side close to the second semiconductor substrate 20 and whose projections along the first direction are located on the pixel area PA, and the second bonding layer 210 also includes a plurality of second interface bonding blocks 216 located on the side close to the first semiconductor substrate 10 and whose projections along the first direction are located on the pixel area PA, and the first interface bonding blocks 115 are in contact and bonded with the second interface bonding blocks 216.

[0061] In existing stacked image sensor chips, it is usually necessary to form an interface bonding block by grinding the entire wafer after depositing metal in the non-pixel area. The pixel area without an interface bonding block will produce loss during the grinding process, which will lead to an uneven bonding surface and reduce the bonding strength of the two facing wafers. At the same time, the loss of the wafer surface in the pixel area of ​​the image sensor chip during the grinding process will also affect the effect of the image sensor in receiving light, thereby affecting the yield and stability of the product.

[0062] Therefore, in this embodiment, a complementary structure is formed between the two top-layer metals to shield the heat and light generated by the working process of the second semiconductor substrate, so that the pixel unit in the first semiconductor substrate is not affected by crosstalk, thereby improving the performance of the image sensor chip on the basis of the existing process. At the same time, by setting relative interface bonding blocks and bonding in the areas of the first bonding layer and the second bonding layer corresponding to the pixel area, while ensuring the bonding strength, it is also possible to avoid the splitting of the wafer surface due to excessive stress during the polishing process, thereby affecting the effect of the pixel unit receiving light.

[0063] On the basis that the first complementary portion M1 is located at a side away from the second semiconductor substrate 20 and the second complementary portion M2 is located at a side away from the first semiconductor substrate 10, in some embodiments, such as Figure 8 As shown, the first bonding layer 110 further includes a first metal wiring 117 and a first interface bonding block 115, and the first complementary portion M1 is connected to the first interface bonding block 115 through the first metal wiring 117;

[0064] The second bonding layer 210 further includes a second metal wiring 218 and a second interface bonding block 216, and the second complementary portion M2 is connected to the second interface bonding block 216 through the second metal wiring 218;

[0065] The first interface bonding block 115 and the second interface bonding block 216 are in contact and bonded with each other, so that the first complementary portion 113 and the second complementary portion 214 are electrically connected.

[0066] In the embodiment of the present application, a complementary structure is formed by a group of top-layer metals, metal routings and interface bonding blocks, so that the heat and light generated by the working process of the second semiconductor substrate are shielded, so that the pixel unit in the first semiconductor substrate is not affected by crosstalk, thereby improving the performance of the image sensor chip on the basis of the existing process. At the same time, by setting the top-layer metal, metal routing and interface bonding blocks in the first bonding layer corresponding to the pixel area PA, the signal of the pixel unit in the first semiconductor substrate can be output to the functional element in the second semiconductor substrate through the top-layer metal, metal routing and interface bonding blocks for subsequent image processing.

[0067] In some embodiments, Fig. 9 As shown, the first complementary part M1 is located on the side away from the second semiconductor substrate 20, and the second complementary part M2 is located on the side close to the first semiconductor substrate 10, that is, the first complementary part is the first top metal 113 in the first bonding layer 110, and the second complementary part M2 is the second interface bonding block 216 in the second bonding layer 210.

[0068] Optional, such as Fig.10 As shown, the first bonding layer 110 further includes a first interface bonding block 115 located on a side close to the second semiconductor substrate 20, and the second complementary portion M2 is in contact and bonding with the first interface bonding block 115, that is, the first interface bonding block 115 is in contact and bonding with the second interface bonding block 216. Optionally, the first complementary portion M1, the first interface bonding block 115, and the second interface bonding block 216 have the same size.

[0069] Further optional, such as Fig.11As shown, the second bonding layer 210 further includes a second top metal 214 located at a side away from the first semiconductor substrate 10, and the projections of the second top metal 214 and the first complementary portion 113 along the first direction completely overlap. The second top metal 214, the second interface bonding block 216, the first interface bonding block 115 and the first complementary portion 113 form a complementary structure for shielding the heat and light generated during the operation of the second semiconductor substrate.

[0070] In an embodiment of the present application, the second complementary portion is configured as a second interface bonding block of the second bonding layer close to the interface, so that at least the second interface bonding block and the first top metal layer form a complementary structure, shielding the heat and light generated by the working process of the second semiconductor substrate, so that the pixel unit in the first semiconductor substrate is not affected by crosstalk, thereby improving the performance of the image sensor chip on the basis of the existing process. At the same time, when the first bonding layer also includes a first interface bonding block located on the side close to the second semiconductor substrate, the first interface bonding block is contacted and bonded with the second interface bonding block, which ensures the bonding strength while avoiding the splitting of the wafer surface due to excessive stress during the polishing process, thereby affecting the effect of the pixel unit receiving light.

[0071] The present application also provides an electronic device, comprising the above-mentioned stacked image sensor chip.

[0072] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A stacked image sensor chip, characterized in that: The stacked image sensor chip comprises at least a first semiconductor substrate and a second semiconductor substrate which are stacked facing each other, wherein: The first semiconductor substrate comprises a pixel substrate layer disposed away from a side of the second semiconductor substrate and a first bonding layer disposed close to a side of the second semiconductor substrate, the pixel substrate layer comprises a logic area and a pixel area, and the pixel area comprises a plurality of pixel units arranged in an array; The second semiconductor substrate at least comprises a second bonding layer disposed close to a side of the first semiconductor substrate and a functional element layer disposed away from a side of the first semiconductor substrate; The first bonding layer includes a plurality of first complementary portions whose projections along a first direction are located in the pixel area, and the second bonding layer includes a plurality of second complementary portions whose projections along the first direction are located in the pixel area, the first direction is a direction from the second semiconductor substrate to the first semiconductor substrate, wherein the first complementary portion and the second complementary portion are staggered.

2. The stacked image sensor chip according to claim 1, wherein: The first complementary portion is located at a side away from the second semiconductor substrate.

3. The stacked image sensor chip according to claim 2, wherein: The second complementary portion is located at a side away from the first semiconductor substrate.

4. The stacked image sensor chip according to claim 3, wherein: Projections of the first complementary portion and the second complementary portion along the first direction cover the pixel area.

5. The stacked image sensor chip according to claim 3, wherein: The first bonding layer also includes a plurality of first interface bonding blocks located near the second semiconductor substrate and whose projections along the first direction are located at the pixel area. The second bonding layer also includes a plurality of second interface bonding blocks located near the first semiconductor substrate and whose projections along the first direction are located at the pixel area. The first interface bonding blocks are in contact and bonded with the second interface bonding blocks.

6. The stacked image sensor chip according to claim 3, wherein: The first bonding layer further includes a first metal wiring and a first interface bonding block, and the first complementary portion is connected to the first interface bonding block through the first metal wiring; The second bonding layer further includes a second metal wiring and a second interface bonding block, and the second complementary portion is connected to the second interface bonding block through the second metal wiring; The first interface bonding block and the second interface bonding block are in contact and bonded with each other, so that the first complementary portion and the second complementary portion are electrically connected.

7. The stacked image sensor chip according to claim 2, wherein: The second complementary portion is located close to the first semiconductor substrate.

8. The stacked image sensor chip according to claim 7, wherein: The first bonding layer further includes a first interface bonding block located on a side close to the second semiconductor substrate, and the second complementary portion is in contact and bonded with the first interface bonding block.

9. The stacked image sensor chip according to claim 1, wherein: The first bonding layer further includes a first bonding portion whose projection along the first direction is located in the logic area, and the second bonding layer further includes a second bonding portion whose projection along the first direction is located in the logic area, and the first bonding portion and the second bonding portion are bonded to each other.

10. An electronic device, characterized in that: The electronic device comprises the stacked image sensor chip as described in any one of claims 1-9.

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