Testing device and system

Abstract

The utility model provides a test device and system. The test device comprises a vector unit, a switching controller, a first clock controller and a plurality of logic gates, the vector unit is used for being connected to test vector generation equipment to obtain a test vector and outputting an enable vector based on the test vector; the switching controller is connected to the vector unit, and the switching controller is configured to provide a switching signal to the vector unit; the input ends of the logic gates are connected to the vector unit and the first clock controller, and the output ends of the logic gates are respectively connected to a plurality of partitions of a to-be-tested element; and the plurality of logic gates provide second clock signals for the plurality of partitions of the to-be-tested element based on the enable vector and a first clock signal output by the first clock controller, so that a register in the to-be-tested element is selectively overturned based on the second clock signal. According to the scheme, the effects of reducing the test power consumption and improving the coverage rate and the test efficiency are achieved.

Description

Technical Field

[0001] The disclosed embodiments of the present application relate to the field of electronic technology, and more specifically, to a testing device and system. Background Art

[0002] During the manufacturing and packaging process of chips, it is inevitable that there will be defects in the chips due to various reasons (such as process, materials, etc.), and such defects will cause the chips to fail to work properly. The main task of chip testing is to pick out defective chips. Because the cost of such defective chips entering the market will be far greater than the cost of chip testing, chip testing is a crucial part of the chip manufacturing process. Specifically, the automatic test pattern generation (ATPG) tool can be used to generate multiple test patterns for various chip failures, and the automatic test equipment (ATE) can be used to input the test vectors for the chip to be tested. By comparing whether the response of the chip under test is consistent with the expected response, quality inspection can be performed immediately after production is completed.

[0003] As the complexity and scale of chip design continue to rise, chip power consumption has also risen sharply. Modern chip designs based on scan chains will cause the chip to enter a state that it would not enter in functional mode during testing, which also brings additional power consumption. For example, during testing, the flipping of the logic value of the register in the scan chain generates power consumption during the test. Excessive test power consumption may cause damage such as breakdown to the chip, greatly affecting the reliability of the chip, or causing a loss in chip yield. In some conventional schemes, in order to reduce power consumption, only after the final test vector is generated, it is verified whether the power consumption of the generated test vector meets the low power consumption requirements, which will result in a large number of test vectors that do not meet the test power consumption requirements, thereby affecting the test coverage for various faults. At the same time, in order to improve the test coverage, more test vectors need to be generated, resulting in reduced test efficiency.

[0004] Therefore, how to improve coverage and test efficiency while reducing test power consumption has become a problem that needs to be solved urgently. Utility Model Content

[0005] According to an embodiment of the present application, the present application proposes a testing device and system to improve coverage and testing efficiency while reducing test power consumption.

[0006] According to one aspect of the present application, an exemplary test device is disclosed, including: a vector unit, a switching controller, a first clock controller and a plurality of logic gates; the vector unit is used to connect to a test vector generation device to obtain a test vector, and output an enable vector based on the test vector, the number of preset vector values ​​in the enable vector does not exceed a preset threshold, and the preset vector value is used to control the register in the element under test to flip; the switching controller is connected to the vector unit, and the switching controller is configured to provide a switching signal to the vector unit; the input ends of the plurality of logic gates are connected to the vector unit and the first clock controller, and the output ends are used to be respectively connected to a plurality of partitions of the element under test; the plurality of logic gates provide a second clock signal to the plurality of partitions of the element under test based on the enable vector and the first clock signal output by the first clock controller, so that the register in the element under test selectively flips based on the second clock signal; wherein the vector unit generates at least two enable vectors based on the same test vector, and switches the output enable vector based on the switching signal provided by the switching controller, so that the registers in different partitions flip.

[0007] Another aspect of the present application provides a test system, which includes a test vector generation device, a component to be tested, and the test apparatus of the first aspect described above.

[0008] The above scheme provides a test vector for the vector unit through a test vector generation device, and controls the number of preset vector values ​​output by the vector unit to not exceed a preset threshold value, so that the vector unit controls some registers in the component under test to flip, so as to meet the power consumption requirement; and the switching controller controls the enable vector output by the vector unit to switch, so that the vector unit can output different enable vectors based on the same test vector to control the register flipping of different partitions of the component under test, thereby improving the coverage without increasing the number of test vectors. Therefore, the effect of reducing the test power consumption while improving the coverage and test efficiency is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application will be further described below in conjunction with the accompanying drawings and implementation methods, in which:

[0010] Figure 1 It is a schematic diagram of the framework of an embodiment of a test system of the present application;

[0011] Figure 2 It is a schematic diagram of the framework of an embodiment of the testing device of the present application;

[0012] Figure 3 is a schematic diagram of a framework of another embodiment of the testing device of the present application;

[0013] Figure 4It is a schematic diagram of output waveforms of a logic gate of an embodiment of the test device of the present application. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0015] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0016] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0017] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0018] During the chip testing process, it is necessary to test various possible faults. To this end, it is necessary to generate test packages (test cubs) for each fault. Through a series of calculation, analysis and verification operations, the test packages for each fault can generate a final test package set. The final test package set is provided to ATE, and ATE uses the final test package set to verify whether the circuit design has a fault. Specifically, ATE will perform ATPG on each target fault in the target fault list to generate multiple test packages. After a certain amount of test packages are generated, the entire process will enter the test package fusion (cube merging) and other steps to make the final test package set as compact as possible. In the last step of the process, the final test package set will be simulated, and the logic value flip rate of each test vector will be calculated. If the logic value flip rate does not meet the requirements set by the user, the test vector will be discarded. In this type of conventional solution, the test process only adds a verification step after the final test package set is generated. Although this method can ensure that the final generated test vector meets the low-power test requirements, a large number of test vectors will be discarded, which greatly affects the test coverage. For example, some faults may not be detected because the test vectors corresponding to them are discarded.

[0019] To this end, the present application proposes a test system 1000, please refer to Figure 1 , Figure 1It is a framework diagram of an embodiment of a test system 1000 of the present application; specifically, the test system 1000 includes a test vector generation device 1100, a component under test 1300 and a test device 1200; in some embodiments, the test device 1200 may include a vector unit 1210, a switching controller 1220, a first clock controller 1230 and a plurality of logic gates 1240; the vector unit 1210 is used to connect to the test vector generation device 1100 to obtain a test vector, and output an enable vector based on the test vector, the number of preset vector values ​​in the enable vector does not exceed a preset threshold, and the preset vector value is used to control the register in the component under test 1300 to flip; the switching controller 1220 is connected to the vector unit 1210, and the switching controller 1220 is configured to provide a switching signal to the vector unit 1210; the input ends of the plurality of logic gates 1240 are connected to the vector Unit 1210 and the first clock controller 1230, the output ends are used to be connected to several partitions of the component under test 1300 respectively; several logic gates 1240 provide second clock signals to several partitions of the component under test 1300 based on the enable vector and the first clock signal output by the first clock controller 1230, so that the registers in the component under test 1300 are selectively flipped based on the second clock signal; wherein, the vector unit 1210 generates at least two enable vectors based on the same test vector, and switches the output enable vector based on the switching signal provided by the switching controller 1220, so that the registers in different partitions are flipped. Other specific structures of the test device 1200 will be described in detail in the following embodiments and will not be repeated here; the test vector generation device 1100 can be an ATPG tool, ATE or a combination of the above two; the component under test 1300 can be a chip.

[0020] In the above scheme, the test vector generation device 1100 provides a test vector for the vector unit 1210, and the number of preset vector values ​​output by the vector unit 1210 is controlled not to exceed a preset threshold value, so that the vector unit 1210 controls some registers in the component under test 1300 to flip, so as to meet the power consumption requirement; and the switching controller 1220 controls the enable vector output by the vector unit 1210 to switch, so that the vector unit 1210 can output different enable vectors based on the same test vector to control the register flipping of different partitions of the component under test 1300, thereby improving the coverage without increasing the number of test vectors. Therefore, the effect of reducing the test power consumption while improving the coverage and test efficiency is achieved.

[0021] In some embodiments of the present application, a testing device 1200 is also provided. Please continue to refer to Figure 1Specifically, the test device 1200 includes a vector unit 1210, a switching controller 1220, a first clock controller 1230, and a plurality of logic gates 1240; the vector unit 1210 is used to connect to the test vector generation device 1100 to obtain a test vector, and output an enable vector based on the test vector, the number of preset vector values ​​in the enable vector does not exceed a preset threshold, and the preset vector value is used to control the register in the element under test 1300 to flip; the switching controller 1220 is connected to the vector unit 1210, and the switching controller 1220 is configured to provide a switching signal to the vector unit 1210; the input of the plurality of logic gates 1240 The first clock controller 1230 is used to connect the first clock signal output by the first clock controller 1230 to the plurality of partitions of the component under test 1300; the first clock signal output by the first clock controller 1230 is used to connect the second clock signal to the plurality of partitions of the component under test 1300; the first clock signal output by the first clock controller 1230 is used to connect the second clock signal to the plurality of partitions of the component under test 1300, so that the registers in the component under test 1300 are selectively flipped based on the second clock signal; wherein the first clock signal output by the first clock controller 1230 is used to connect the second clock signal to the plurality of partitions of the component under test 1300; the second ...

[0022] In this embodiment, the preset vector value may be, for example, a logic value "0" or "1"; specifically, when the logic gate 1240 includes an AND gate, the preset vector value may be a logic value "1", and the logic value "1" is used as an input of the AND gate, and the first clock signal of the first clock controller 1230 that flips from a low level to a high level is used as another input of the AND gate, thereby obtaining a second clock signal that flips from a low level to a high level, thereby causing the register of the corresponding partition of the element under test 1300 to flip after receiving the rising edge of the second clock signal; when the logic gate 1240 includes an OR gate, the preset vector value may be "0", and the logic value "0" is used as an input of the OR gate, and the first clock signal of the first clock controller 1230 that flips from a high level to a low level is used as another input of the OR gate, thereby obtaining a second clock signal that flips from a high level to a low level, thereby causing the register of the corresponding partition of the element under test 1300 to flip after receiving the falling edge of the second clock signal.

[0023] In this embodiment, the enable vector may be composed of a plurality of vector values, and the number of vector values ​​in the enable vector may be the same as the number of partitions of the DUT 1300; for example, please continue to refer to Figure 1, the element under test 1300 may include 4 partitions, then the enable vector may include 4 vector values, for example, one enable vector may be "1100". It should be noted that, corresponding to different numbers of partitions of the element under test 1300, the preset threshold of the number of preset vector values ​​in the enable vector may also be different. For example, when the element under test 1300 includes 4 partitions, the preset threshold of the number of preset vector values ​​in the enable vector may be 2, even if the enable vector cannot include 3 or more preset vector values; when the element under test 1300 includes 8 partitions, the preset threshold of the number of preset vector values ​​in the enable vector may be 4, even if the enable vector cannot include 5 or more preset vector values, and so on. Of course, corresponding to different numbers of partitions of the element under test 1300, the preset threshold of the number of preset vector values ​​in the enable vector may be flexibly set according to power consumption requirements. For example, when the element under test 1300 includes 8 partitions, the preset threshold may also be 5, 6, etc., and the present application does not limit this.

[0024] The loads of different partitions of the unit under test are substantially the same, that is, the numbers of registers included in different partitions of the unit under test are substantially the same.

[0025] In this embodiment, the vector unit 1210 generates at least two enable vectors based on the same test vector, that is, the test vector generation device 1100 can continuously provide different test vectors to the vector unit 1210. After the test vector generation device 1100 provides a test vector to the vector unit 1210, the vector unit 1210 can generate at least two enable vectors based on the test vector. The number of enable vectors generated specifically needs to be determined according to a preset threshold value of the number of preset vector values ​​and the received test vector. For example, when the test vector provided by the test vector generation device 1100 is is "1111", and the preset threshold is 2, then the vector unit 1210 can generate two enable vectors: "0011" and "1100" (or "1001" and "0110", etc., the specific enable vector generated can be determined according to the test vector generation device 1100), the vector unit 1210 can first output the enable vector "0011", and after receiving the switching signal provided by the switching controller 1220, it outputs the enable vector "1100". During the test, although the registers in each partition of the component under test 1300 are flipped, the peak toggle rate is only half of the original, thereby reducing the test power consumption. Therefore, by adjusting the test vector through the vector unit 1210, not only the test coverage is improved and the power consumption is reduced, but also a larger number of test vectors are not needed. In some embodiments, when the test vector provided by the test vector generation device 1100 is "0011" and the preset threshold is 2, although the number of preset vector values ​​in the test vector does not exceed the preset threshold, the vector unit 1210 can still generate two enable vectors according to the test vector: "0011" and "1100", respectively. The vector unit 1210 can first output the enable vector "0011", and then output the enable vector "1100" after receiving the switching signal provided by the switching controller 1220. Therefore, in the above embodiment, by generating at least two enable vectors based on the same test vector through the vector unit 1210, the amount of test vectors used can be reduced, thereby improving the test efficiency.

[0026] In the above scheme, the test vector generation device 1100 provides a test vector for the vector unit 1210, and the number of preset vector values ​​output by the vector unit 1210 is controlled not to exceed a preset threshold value, so that the vector unit 1210 controls some registers in the component under test 1300 to flip, so as to meet the power consumption requirement; and the switching controller 1220 controls the enable vector output by the vector unit 1210 to switch, so that the vector unit 1210 can output different enable vectors based on the same test vector to control the register flipping of different partitions of the component under test 1300, thereby improving the coverage without increasing the number of test vectors. Therefore, the effect of reducing the test power consumption while improving the coverage and test efficiency is achieved.

[0027] In some embodiments of this application, please refer to Figure 2 , Figure 2 1 is a schematic diagram of a framework of an embodiment of the test device of the present application; the test device 1200 may also include an enable vector configuration unit 1250, which is connected to the vector unit 1210 and provides a configuration signal to the vector unit 1210, and the configuration signal is used to indicate a preset threshold. Therefore, by enabling the vector configuration unit 1250, different preset thresholds can be flexibly set to adapt to the required peak flip rate, thereby improving the adaptability of the test device 1200.

[0028] In some embodiments, the logic gate 1240 may include an integrated clock gate (ICG); specifically, the ICG may include a latch and an AND gate, or a latch and an OR gate. The specific structure of the ICG may adopt the ICG structure commonly used in the prior art, which will not be described in detail here. Different ICGs may be selected corresponding to different trigger types of registers, such as rising edge trigger or falling edge trigger type. In this embodiment, the logic gate 1240 includes an ICG, which can prevent the second clock signal from carrying a glitch signal compared to other embodiments in which the logic gate 1240 only includes an AND gate or an OR gate.

[0029] In some embodiments, please refer to Figure 3 , Figure 3 It is a framework diagram of another embodiment of the test device of the present application; specifically, the vector unit 1210 may include an input unit 1211 and a decoding unit 1212; one end of the input unit 1211 is connected to the test vector generation device 1100 to generate an enable vector group, which includes at least two enable vectors; the decoding unit 1212 is connected to the input unit 1211, the switching controller 1220 and a plurality of logic gates 1240, the decoding unit 1212 obtains the enable vector from the input unit 1211, and outputs the enable vector to the plurality of logic gates 1240; wherein the decoding unit 1212 switches the output enable vector based on the switching signal to flip the registers in different partitions.

[0030] Exemplarily, the input unit 1211 can generate an enable vector group based on the test vector, and the enable vector group includes at least two enable vectors, that is, the test vector generation device 1100 can continuously provide different test vectors for the input unit 1211. After the test vector generation device 1100 provides a test vector to the vector unit 1210, the vector unit 1210 can generate at least two enable vectors based on the test vector. The number of enable vectors generated specifically needs to be determined according to a preset threshold of the number of preset vector values ​​and the received test vector; for example, when the test vector provided by the test vector generation device 1100 is "1111" and the preset threshold is 2, the enable vector group generated by the input unit 1211 may include two Enable vectors: “0011” and “1100” (or “1001” and “0110”, etc., the specific generated enable vector can be determined according to the test vector generating device 1100), the decoding unit 1212 can first output the enable vector “0011”, and then output the enable vector “1100” after receiving the switching signal provided by the switching controller 1220. Since the ICG including the AND gate will output the second clock signal only when the received enable signal is “1”, thereby controlling the register of the corresponding partition in the component under test 1300 to flip, therefore, in the above test process, although the registers in each partition in the component under test 1300 are flipped successively under the control of the two enable vectors, the peak toggle rate is only half of the original one, thereby reducing the test power consumption. Therefore, by adjusting the test vector through the vector unit 1210, not only the test coverage is improved and the power consumption is reduced, but also a larger number of test vectors are not needed. In some embodiments, when the test vector provided by the test vector generation device 1100 is "0011" and the preset threshold is 2, although the number of preset vector values ​​in the test vector does not exceed the preset threshold, the input unit 1211 can still generate two enable vectors according to the test vector: "0011" and "1100", respectively. The decoding unit 1212 can first output the enable vector "0011", and then output the enable vector "1100" after receiving the switching signal provided by the switching controller 1220. Therefore, in the above embodiment, by generating at least two enable vectors based on the same test vector through the input unit 1211, the amount of test vectors used can be reduced, thereby improving the test efficiency.

[0031] In some embodiments, the input unit 1211 may include at least two input blocks, each of which is used to store an enable vector in the enable vector group. For example, in an implementation scenario where the input unit 1211 includes two input blocks, the enable vector group generated by the input unit 1211 may include two enable vectors, which are respectively stored in the two input blocks, and the decoding unit 1212 provides the enable vectors in the two input blocks to the logic gate 1240. In other embodiments, the input unit 1211 may also include other numbers of input blocks, such as 4, 8, etc.

[0032] In some embodiments, the input block may include a plurality of storage units, each storage unit storing a vector value in the enable vector, and the number of storage units is configured to be the same as the number of partitions of the element under test 1300. Specifically, the storage unit may be a register, a trigger, etc., which is not limited in the present application. Exemplarily, the element under test 1300 may include 4 partitions, then each input block may include 4 storage units, and the enable vector values ​​stored in the 4 storage units are respectively used to control the registers in the 4 partitions to flip; when the preset threshold of the preset vector value in the enable vector is 2, and the input test vector is "1111", the input unit 1211 may generate "0011" and "1100" respectively, which are respectively stored in the 4 storage units of the 2 input blocks, and the decoding unit 1212 successively selects the enable vectors stored in the 4 storage units of the 2 input blocks for output.

[0033] In some embodiments, the switching controller 1220 may include a second clock controller (not shown in the figure), which is connected to the first clock controller 1230 and the vector unit 1210 and synchronized with the clock of the first clock controller 1230; the second clock controller is configured to generate a switching signal at a preset switching cycle, and provide a clock cycle for the vector unit 1210, and the vector unit 1210 outputs an enable vector at a preset transmission cycle of the second clock controller.

[0034] Still taking the example that the element under test 1300 includes 4 partitions and the preset threshold of the preset vector value in the enable vector is 2; if the second clock controller can support up to 8 cycle pulses, then two clock cycles among the 8 clock cycles can be defined as the first preset transmission cycle and the second preset transmission cycle, that is, two enable vectors are respectively transmitted at these clock cycles; between the first preset transmission cycle and the second preset transmission cycle, a preset switching cycle is defined, for example, the first and second clock cycles are defined as the first preset transmission cycle, and the seventh and eighth clock cycles are defined as the second preset transmission cycle, then any cycle among the third to sixth clock cycles can be defined as the preset switching cycle, and a switching signal is provided to the vector unit 1210 in the preset switching cycle. Assuming that the two enable vectors generated by the vector unit 1210 are "0011" and "1100" respectively, the vector unit 1210 can output the first enable vector, that is, output "0011" at the first two cycles of the second clock controller; then a switching signal can be provided to the vector unit 1210 at the fifth clock cycle, and then the vector unit 1210 switches to output "1100" at the seventh and eighth clock cycles.

[0035] The configuration of the preset switching cycle and the preset transmission cycle may not be limited to the configuration in the above example. For example, the 1st, 2nd, 4th, 5th, 7th, and 8th clock cycles may be configured as preset transmission cycles, and the 3rd and 6th clock cycles may be configured as preset switching cycles, so that the vector unit 1210 can output 3 different enable vectors respectively.

[0036] It should be noted that the above examples are only for illustrative purposes and do not represent the actual testing behavior of the testing device 1200 .

[0037] In some embodiments, the switching controller 1220 may include a second clock controller and a counter (not shown in the figure); specifically, two clock cycles of the second clock controller can be configured as preset transmission cycles. After the vector unit 1210 outputs an enable vector in the preset transmission cycle according to the clock provided by the second clock controller, the counter starts counting, resets the second clock controller after a preset time, and outputs a second enable vector in the preset transmission cycle of the second clock controller.

[0038] In some embodiments, the first clock controller 1230 may have 4 control bits. Figure 4 , Figure 4 is a schematic diagram of output waveforms of a logic gate 1240 of an embodiment of the test device 1200 of the present application; Figure 4The waveform timing change diagram of logic gates 1 to 4 is shown. In the capture phase, the first clock controller 1230 can output 4 clock pulse signals to control the registers of the element under test 1300 to launch and capture respectively. In other embodiments, the first clock controller 1230 can have 8 control bits. Compared with the capture phase of basic scan which only includes a single capture clock pulse, for fast-sequential, after the shift phase, there may be multiple capture clock pulses, for example, there are 3 capture clock pulses, then at least 8 control bits are required to enable the registers in the partition of the element under test 1300 corresponding to the two enable vectors to complete launch-capture.

[0039] It should be noted that, when the vector unit 1210 outputs different numbers of enable vectors corresponding to the same test vector, the control bits required by the first clock controller 1230 will also change, and are not limited to those described in the above embodiments; for example, when the vector unit 1210 outputs 4 different enable vectors based on the same test vector, that is, it is necessary to control different partitions of the element under test 1300 to complete launch-capture four times in succession, then for basic scan, the first clock controller 1230 needs 8 control bits, and for fast-sequential, the first clock controller 1230 needs 16 control bits.

[0040] Combine the following Figure 1 to Figure 4 , the working process of the testing device 1200 is further described: Figure 1 As shown, the DUT 1300 is divided into 4 different partitions; assuming that the preset threshold is configured as 2, when the test vector generation device 1100 provides the test vector "1111" to the vector unit 1210, the vector unit 1210 can generate enable vectors "1001" and "0110" respectively according to the test vector, and provide the two enable vectors to the logic gate 1240 (in this example, the logic gate 1240 is an ICG including an AND gate) twice; within the preset transmission cycle provided by the second clock controller, the vector unit 1210 sends the enable vector "1001" to the logic gate 1240, and the first clock controller 1230 also sends two high-level first clock signals to the logic gate 1240, then the output end of the logic gate 1240 outputs two high-level second clock signals, as shown in FIG. Figure 4As shown, the first pulse in the second clock signal is used to control the registers in the corresponding partitions (i.e., the first partition and the fourth partition) of the DUT 1300 to launch, and the second pulse is used to control the registers in the corresponding partitions (i.e., the first partition and the fourth partition) of the DUT 1300 to capture; then the second clock controller outputs a switching signal to the vector unit 1210, so that the vector unit 1210 is then switched to the output enable vector "0110", and the first clock controller 1230 also sends two high-level first clock signals to the logic gate 1240, then the output end of the logic gate 1240 outputs two high-level second clock signals for the second time, as shown in FIG. Figure 4 As shown, the first pulse in the second clock signal output for the second time is used to control the registers in the corresponding partitions (i.e., the second partition and the third partition) of the component under test 1300 to launch, and the second pulse is used to control the registers in the corresponding partitions (i.e., the second partition and the third partition) of the component under test 1300 to capture, and the fault is captured during the two captures respectively.

[0041] Therefore, in the above scheme, the test vector generation device 1100 provides a test vector for the vector unit 1210, and the number of preset vector values ​​output by the vector unit 1210 is controlled not to exceed the preset threshold value, so that the vector unit 1210 controls some registers in the component under test 1300 to flip, so as to meet the power consumption requirement; and the switching controller 1220 controls the enable vector output by the vector unit 1210 to switch, so that the vector unit 1210 can output different enable vectors based on the same test vector, and control the register flipping of different partitions of the component under test 1300, thereby improving the coverage without increasing the number of test vectors. Therefore, the effect of reducing the test power consumption while improving the coverage and test efficiency is achieved.

[0042] It is easy for a person skilled in the art to know that many modifications and changes can be made to the device and method while maintaining the teaching content of the present application. Therefore, the above disclosure should be considered as limited only by the scope of the appended claims.

Claims

1. A testing device, characterized in that: include: A vector unit, configured to be connected to a test vector generating device to obtain a test vector, and to output an enable vector based on the test vector, wherein the number of preset vector values ​​in the enable vector does not exceed a preset threshold, and the preset vector value is used to control a register in the element under test to flip; a switching controller connected to the vector unit, the switching controller being configured to provide a switching signal to the vector unit; a first clock controller; a plurality of logic gates, whose input ends are connected to the vector unit and the first clock controller, and whose output ends are respectively connected to the plurality of partitions of the element under test; the plurality of logic gates provide a second clock signal to the plurality of partitions of the element under test based on the enable vector and the first clock signal output by the first clock controller, so that the registers in the element under test are selectively flipped based on the second clock signal; The vector unit generates at least two enable vectors based on the same test vector, and switches the output enable vectors based on the switching signal provided by the switching controller, so as to flip the registers in different partitions.

2. The testing device according to claim 1, characterized in that: The logic gates include integrated clock gates.

3. The testing device according to claim 1, characterized in that: Also includes: An enabling vector configuration unit is connected to the vector unit and provides a configuration signal for the vector unit, wherein the configuration signal is used to indicate the preset threshold.

4. The testing device according to claim 1, characterized in that: The vector unit comprises: An input unit, one end of which is connected to the test vector generating device, generating an enable vector group, wherein the enable vector group includes at least two of the enable vectors; A decoding unit connected to the input unit, the switching controller and the plurality of logic gates, the decoding unit acquiring the enable vector from the input unit and outputting the enable vector to the plurality of logic gates; The decoding unit switches the output enable vector based on the switching signal to flip the registers in different partitions.

5. The testing device according to claim 4, characterized in that: The input unit comprises: At least two input blocks, each input block is used to store one of the enable vectors in the enable vector group.

6. The testing device according to claim 5, characterized in that: The input block includes: A plurality of storage units, each of which stores a vector value in the enable vector, and the number of the storage units is configured to be the same as the number of partitions of the DUT.

7. The testing device according to claim 1, characterized in that: The number of registers included in different partitions of the device under test is substantially the same.

8. The testing device according to claim 1, characterized in that: The switching controller comprises: A second clock controller is connected to the first clock controller and the vector unit and is synchronized with the clock of the first clock controller; the second clock controller is configured to generate the switching signal at a preset switching cycle and provide a clock cycle for the vector unit, and the vector unit outputs the enable vector at a preset transmission cycle of the second clock controller.

9. The testing device according to claim 1, characterized in that: The number of partitions of the device under test is the same as the number of logic gates.

10. A test system, comprising a test vector generating device and a component to be tested, characterized in that: It also comprises the testing device according to any one of claims 1 to 9.

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