Package structure including guide pattern

Abstract

The utility model provides a packaging structure which comprises a wiring substrate, a semiconductor crystal grain and a dielectric layer. The wiring substrate includes die bonding regions and a guide pattern (auxiliary pattern or pseudo pattern) distributed between the die bonding regions. The semiconductor die is disposed on the die bonding region and electrically connected to the wiring substrate, in which the guide pattern is electrically insulated from the semiconductor die. The dielectric layer is disposed between the semiconductor die and the wiring substrate, wherein the dielectric layer covers the guide pattern and is in contact with the guide pattern.

Description

Technical Field

[0001] An embodiment of the utility model relates to a packaging structure including a guiding pattern. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. With the recent demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for smaller and more innovative semiconductor die packaging technologies has also increased. Utility Model Content

[0003] According to some embodiments of the present disclosure, a packaging structure including a wiring substrate, a semiconductor die and a dielectric layer is provided. The wiring substrate includes a die bonding region and a guide pattern distributed between the die bonding regions. The semiconductor die is disposed on the die bonding region and electrically connected to the wiring substrate, wherein the guide pattern is electrically insulated from the semiconductor die. The dielectric layer is disposed between the semiconductor die and the wiring substrate, wherein the dielectric layer covers the guide pattern and contacts the guide pattern.

[0004] According to some other embodiments of the present disclosure, a packaging structure including a wiring substrate, a first semiconductor grain and a dielectric layer is provided. The wiring substrate includes a plurality of grain bonding areas, and the grain bonding areas are laterally spaced apart from each other by separation areas. The wiring substrate further includes auxiliary patterns distributed in the separation areas. The first semiconductor grain is configured in the first grain bonding area in the grain bonding area and is electrically connected to the wiring substrate. The first semiconductor grain includes a first group of conductive terminals and a second group of conductive terminals, wherein the first arrangement spacing of the first group of conductive terminals is greater than the second arrangement spacing of the second group of conductive terminals. The auxiliary pattern is electrically insulated from the first group of conductive terminals, the second group of conductive terminals, the third group of conductive terminals and the fourth group of conductive terminals. The dielectric layer is configured in a first gap between the first semiconductor grain and the wiring substrate and in a second gap between the second semiconductor grain and the wiring substrate. The dielectric layer covers the auxiliary pattern and contacts the auxiliary pattern.

[0005] According to some other embodiments of the present disclosure, a packaging structure including a wiring substrate, a first semiconductor grain, a second semiconductor grain and a dielectric layer is provided. The wiring substrate includes a conductive wiring and a dummy pattern, wherein the dummy pattern is distributed on the surface of the wiring substrate, and the dummy pattern is electrically floating. The first semiconductor grain is arranged on the surface of the wiring substrate and is electrically connected to the conductive wiring of the wiring substrate. The second semiconductor grain is arranged on the surface of the wiring substrate and is electrically connected to the conductive wiring of the wiring substrate. The dielectric layer includes a first portion, a second portion and a connecting portion located between the first portion and the second portion. The first portion is arranged between the first semiconductor grain and the wiring substrate, the second portion is arranged between the second semiconductor grain and the wiring substrate, and the connecting portion of the dielectric layer covers the dummy pattern and contacts the dummy pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 4 A cross-sectional view schematically illustrates a manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0008] FIG. 5A to FIG. 5E The diagram schematically illustrates a manufacturing process of a dielectric layer on an interposer wiring substrate of a CoWoS packaging structure according to some embodiments of the present disclosure.

[0009] Figure 6 An enlarged top view of a guide pattern according to some embodiments of the present disclosure is schematically depicted.

[0010] Fig. 7A and Figure 7B Schematically depicts Figure 6 A cross-sectional view of the guide pattern shown in FIG.

[0011] Figure 8 An enlarged top view of a guide pattern according to some embodiments of the present disclosure is schematically depicted.

[0012] Fig.9A and Fig. 9B Schematically depicts Figure 8 A cross-sectional view of the guide pattern shown in FIG.

[0013] Figures 10 to 12 An enlarged top view of a guide pattern in some alternative embodiments according to the present disclosure is schematically depicted. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which other features are formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, in various examples, the disclosure will repeat reference numbers and / or letters. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and / or architectures discussed.

[0015] Additionally, for ease of description, spatially relative terms, such as "benefit", "below", "lower", "above", "upper", etc., may be used herein to indicate the relationship of one component or feature to another component or feature. The spatially relative terms are intended to encompass different orientations of the component in use, or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0016] Embodiments of the utility model may further include other features and processes. For example, the device may include a test structure to assist in verification testing of a 3D package or 3DIC component. For example, the test structure may include a test pad formed in a redistribution layer or formed on a substrate, and the test pad allows verification testing such as testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. to be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0017] Figures 1 to 4 A cross-sectional view schematically illustrates a manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0018] refer to Figure 1 , providing a package structure 100 including a package substrate 110, a semiconductor die 120 and an insulating encapsulation body 130. The semiconductor die 120 is disposed on the package substrate 110 and electrically connected to the package substrate 110, and the insulating encapsulation body 130 laterally encapsulates the semiconductor die 120. In some embodiments, as Figure 1As shown in the figure, a chip-on-wafer-on-substrate (CoWoS) packaging structure 100 is provided. The CoWoS packaging structure 100 may include a packaging substrate 110, a semiconductor die 120, an insulating encapsulation body 130, an interposer wiring substrate 140, a conductive terminal 150, a dielectric layer 160, a conductive terminal 170, and a dielectric layer 180. In some embodiments, the interposer wiring substrate 140 includes a silicon interposer, an organic interposer, or other suitable interposer substrates. The interposer wiring substrate 140 may include conductive wiring formed thereon. The interposer wiring substrate 140 may include conductive through-holes formed therein.

[0019] The package substrate 110 may be a printed circuit board or other suitable type of wiring substrate. The semiconductor die 120 may be or include at least one first semiconductor die 120a and at least one second semiconductor die 120b. The at least one first semiconductor die 120a and the at least one second semiconductor die 120b are arranged side by side on the interposer wiring substrate 140. In some embodiments, the first semiconductor die 120a includes a high bandwidth memory (HBM) cube, which includes a stacked HBM memory die and a controller die for controlling the operation of the stacked HBM memory die, and the second semiconductor die 120b includes a system on chip (SoC) die. In some other embodiments, the first semiconductor die 120a and the second semiconductor die 120b may be system on integrated chip (SoIC) die with various functions. The first semiconductor die 120a and the second semiconductor die 120b are disposed on the interposer wiring substrate 140 and are electrically connected to the interposer wiring substrate 140 through the conductive terminals 150. The semiconductor die 120 can be bonded to the interposer wiring substrate 140 through the conductive terminals 150 through a chip-on-wafer (CoW) bonding process. The conductive terminals 150 are disposed between the semiconductor die 120 and the interposer wiring substrate 140. The conductive terminals 150 may be or include micro-bumps for electrically connecting the semiconductor die 120 and the interposer wiring substrate 140. The dielectric layer 160 is disposed on the interposer wiring substrate 140. The dielectric layer 160 is disposed between the semiconductor die 120 and the interposer wiring substrate 140 to laterally encapsulate the conductive terminals 150. In some embodiments, the dielectric layer 160 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Therefore, the shear stress on the conductive terminal 150 can be minimized by the dielectric layer 160, and the reliability of the conductive terminal 150 can be enhanced by the dielectric layer 160. The material of the dielectric layer 160 can be or include epoxy resin or other suitable dielectric materials.

[0020] The following will be combined FIG. 5A to FIG. 5E A detailed description related to the dielectric layer 160 will be described.

[0021] like Figure 1 As shown, the insulating encapsulation body 130 is disposed on the interposer wiring substrate 140 to laterally encapsulate the semiconductor die 120 and the dielectric layer 160. The insulating encapsulation body 130 does not contact the base portion 214 of the cover body 210. Figure 1As shown, the top surface (e.g., back surface) of the semiconductor die 120 is substantially flush with the top surface of the insulating encapsulation body 130, and the sidewall of the insulating encapsulation body 130 is substantially aligned with the sidewall of the interposer wiring substrate 140. The conductive terminal 170 is disposed on the bottom surface of the interposer wiring substrate 140, and the interposer wiring substrate 140 is electrically connected to the package substrate 110 through the conductive terminal 170. The conductive terminal 170 may be or include a controlled collapse chip connection (Controlled Collapse Chip Connection bumps, C4) bump for electrically connecting the interposer wiring substrate 140 and the package substrate 110. The dielectric layer 180 is disposed on the package substrate 110. The dielectric layer 180 is disposed between the interposer wiring substrate 140 and the package substrate 110 to laterally encapsulate the conductive terminal 170. In some embodiments, the dielectric layer 180 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Furthermore, the dielectric layer 180 covers the sidewalls of the interposer wiring substrate 140 and lower portions of the sidewalls of the insulating encapsulant 130 .

[0022] like Figure 1 As shown, the semiconductor die 120 is electrically connected to the package substrate 110 through the interposer wiring substrate 140, the conductive terminal 150 and the conductive terminal 170. The interposer wiring substrate 140 can be a silicon interposer wiring substrate with a fine line pitch (e.g., sub-micron pitch), an organic interposer wiring substrate with a larger fine line pitch (e.g., 4 micron pitch), or an interposer wiring substrate with a local silicon interconnect (LSI) die. In an embodiment where the interposer wiring substrate 140 is a silicon interposer wiring substrate, the CoWoS package structure 100 is a so-called CoWoS-S package. In an embodiment where the interposer wiring substrate 140 is an organic interposer wiring substrate, the CoWoS package structure 100 is a so-called CoWoS-R package. In an embodiment where the interposer wiring substrate 140 is an interposer wiring substrate with a local silicon interconnect (LSI) die, the CoWoS package structure 100 is a so-called CoWoS-L package.

[0023] Although for the sake of illustration Figure 1 A CoWoS packaging structure 100 is shown in FIG. 1 , but the architecture of the packaging structure 100 is not limited to CoWoS packaging. In the embodiments of the present invention, an integrated fan-out on substrate (InFO-oS) package may be used.

[0024] refer to Figure 2, an adhesive layer 190 is provided on the packaging substrate 110, and a thermal interface material (TIM) 200 is provided on the top surface (e.g., the back surface) of the semiconductor die 120 and the top surface of the insulating encapsulation body 130. The material in the adhesive layer 190 may be or include a thermally conductive adhesive, a silicon based resin adhesive, or an epoxy resin based adhesive. The material of the adhesive layer 190 may be or include a rubber based material with a curing promoting material. The thermal interface material 200 may be or include a silicon based thermal interface material, a metal thermal interface material, a combination of the foregoing materials, or similar materials. In the present embodiment, a thin film type thermal interface material 200 is provided and attached to the top surface (e.g., the back surface) of the semiconductor die 120 and the top surface of the insulating encapsulation body 130.

[0025] Reference Figure 3 , after providing the adhesive layer 190 and the thermal interface material 200, a cover 210 is provided and attached to the CoWoS packaging structure 100. The cover 210 is mounted on the packaging substrate 110 to cover the semiconductor die 120 encapsulated by the insulating encapsulant 130. The cover 210 includes a cover portion 212 and a base portion 214 extending from the cover portion 212 to the packaging substrate 110. The cover portion 212 covers the semiconductor die 120 and the insulating encapsulant 130. The bottom surface of the base portion 214 is attached to the packaging substrate 110 through the adhesive layer 190, and the cover portion 212 of the cover 210 is attached to the packaging structure 100 through the thermal interface material 200. The cover 210 may further include an alignment cutout 216 formed at a corner of the cover 10 so that the cover 210 can be correctly and quickly assembled with the packaging substrate 110. The details of the cover 210 will be described in conjunction with FIG. 5 and Figure 6 Give a description.

[0026] Reference Figure 4 , the conductive terminals 220 are formed on the bottom surface of the package substrate 110. The conductive terminals 112 formed on the bottom surface of the package substrate 110 may be solder balls arranged in an array, and the solder balls may be formed by a ball mounting process and a subsequent reflow process. The package substrate 110 may be a ball grid array (BGA) circuit board. After the conductive terminals 220 are formed on the bottom surface of the package substrate 110, a singulation process may be performed to cut the package substrate 110, thereby obtaining Figure 4 The individualized semiconductor components shown.

[0027] FIG. 5A to FIG. 5E The diagram schematically illustrates a manufacturing process of a dielectric layer 160 on an interposer wiring substrate 140 of a CoWoS packaging structure 100 according to some embodiments of the present disclosure.

[0028] refer to Figure 5A , Figure 5A The upper portion of is an enlarged cross-sectional view, which schematically illustrates a semiconductor die 120, an interposer wiring substrate 140, and a conductive terminal 150; Figure 5A The lower portion of FIG. 1 is a top view schematically illustrating the distribution of the dummy patterns 144 formed on the interposer wiring substrate 140 .

[0029] like Figure 5A As shown in the upper part of FIG. 1 , the interposer wiring substrate 140 may include a conductive wiring 142 and a guide pattern 144. The conductive wiring 142 is embedded in the interposer wiring substrate 140 and / or distributed on the top surface 140A of the interposer wiring substrate 140, so that the interposer wiring substrate 140 can provide a signal transmission function. In addition, the guide pattern 144 is distributed on the top surface 140A of the interposer wiring substrate 140 to provide a guiding function. In other words, the guide pattern 144 can be a dummy pattern or an auxiliary pattern for guiding or adjusting the subsequently applied underfill material (such as Figure 5D , flow (e.g., flow rate, flow direction, flow front, or a combination thereof).

[0030] In some embodiments, the interposer wiring substrate 140 includes a first die bonding region 140B1 and a second die bonding region 140B2 laterally spaced apart from the first die bonding region 140B1. The first die bonding region 140B1 is laterally spaced apart from the second die bonding region 140B2 by a separation region 140C. The separation region 140C is laterally distributed between the first die bonding region 140B1 and the second die bonding region 140B2. The first semiconductor die 120a and the second semiconductor die 120b are both mounted on the top surface 140A of the interposer wiring substrate 140. The first semiconductor die 120a and the second semiconductor die 120b are electrically connected to the conductive wiring 142 of the interposer wiring substrate 140. The first semiconductor die 120a can be mounted on the first die bonding region 140B1 through a first set of conductive terminals 150a and a second set of conductive terminals 150b, and electrically connected to the interposer wiring substrate 140. In addition, the second semiconductor die 120b can be mounted on the second die bonding region 140B2 through the third group of conductive terminals 150c and the fourth group of conductive terminals 150d, and electrically connected to the interposer wiring substrate 140. The above-mentioned multiple groups of conductive terminals 150a, 150b, 150c and 150d are collectively referred to as conductive terminals 150 (e.g., micro bumps).

[0031] The first group of conductive terminals 150a is distributed on the high density area HD1 of the first die bonding area 140B1, and the second group of conductive terminals 150b is distributed on the low density area LD1 of the first die bonding area 140B1. The third group of conductive terminals 150c is distributed on the high density area HD2 of the second die bonding area 140B2, and the fourth group of conductive terminals 150d is distributed on the low density area LD2 of the second die bonding area 140B2. Figure 5A As shown in the lower part of FIG. 1 , the partition area 140C is defined by the high-density area HD1 and the high-density area HD2. Figure 5A As shown in the lower part of FIG. 1 , the partition area 140C is a T-shaped area defined by two L-shaped high-density areas HD1 and one long strip-shaped high-density area HD2 . However, the partition area 140C is not limited to being a T-shaped area.

[0032] In some embodiments, the first arrangement pitch of the first group of conductive terminals 150a is smaller than the second arrangement pitch of the second group of conductive terminals 150b, and the third arrangement pitch of the third group of conductive terminals 150c is smaller than the fourth arrangement pitch of the fourth group of conductive terminals 150d. The first arrangement pitch may be equal to the third arrangement pitch, and the second arrangement pitch may be equal to the fourth arrangement pitch. In some other embodiments, the first arrangement pitch is different from the third arrangement pitch, and the second arrangement pitch is different from the fourth arrangement pitch.

[0033] like Figure 5A As shown in FIG. 1 , the guide pattern 144 is distributed in the separation area 140C between the first die bonding area 140B1 and the second die bonding area 140B2. The guide pattern 144 of the interposer wiring substrate 140 is electrically floating. The guide pattern 144 of the interposer wiring substrate 140 is electrically insulated from the conductive wiring 142 of the interposer wiring substrate 140. The guide pattern 144 of the interposer wiring substrate 140 is electrically insulated from the first semiconductor die 120a and the second semiconductor die 120b. The guide pattern 144 of the interposer wiring substrate 140 is electrically insulated from the first group of conductive terminals 150a, the second group of conductive terminals 150b, the third group of conductive terminals 150c, and the fourth group of conductive terminals 150d. In addition, the first group of conductive terminals 150a are laterally disposed between the guiding pattern 144 and the second group of conductive terminals 150b, and the third group of conductive terminals 150c are laterally disposed between the guiding pattern 144 and the fourth group of conductive terminals 150d.

[0034] After the first semiconductor die 120a and the second semiconductor die 120b are mounted on the top surface of the interposer wiring substrate 140, a first gap is maintained between the first semiconductor die 120a and the interposer wiring substrate 140, and a second gap is maintained between the second semiconductor die 120b and the interposer wiring substrate 140. The guide pattern 144 of the interposer wiring substrate 140 is spaced apart from the first semiconductor die 120a and the second semiconductor die 120b. In other words, the guide pattern 144 of the interposer wiring substrate 140 does not physically contact the first semiconductor die 120a and the second semiconductor die 120b.

[0035] Reference FIG. 5B to FIG. 5E After the first semiconductor die 120a and the second semiconductor die 120b are mounted on the top surface of the interposer wiring substrate 140, a dielectric material, such as an underfill material UF, is applied to the top surface 140A of the interposer wiring substrate 140. Figure 5B As shown. The capillary underfill process can be performed by, for example, a dispensing injector to apply the underfill material UF to the edge (e.g., the left edge) of the interposer wiring substrate 140. The flowable underfill material UF without voids can be injected by the dispensing injector. Through the capillary phenomenon, such as Figure 5C As shown, the non-voided flowable underfill material UF can flow laterally into the first gap between the first semiconductor die 120a and the interposer wiring substrate 140. Then, as shown in FIG. Figure 5D and Figure 5E As shown in FIG. 1 , the underfill material UF may flow into the region between the first semiconductor die 120a and the interposer wiring substrate 140, pass through the separation region 140C, and then flow into the region between the second semiconductor die 120b and the interposer wiring substrate 140. After the underfill material UF is applied, a curing process may be performed to form a Figure 1 The dielectric layer 160 shown in FIG. 1 covers the guide pattern 144 and physically contacts the guide pattern 144. In addition, the dielectric layer 160 is disposed in a first gap between the first semiconductor die 120a and the interposer wiring substrate 140 and in a second gap between the second semiconductor die 120b and the interposer wiring substrate 140.

[0036] Since the arrangement pitch of the first group of conductive terminals 150a is smaller than the arrangement pitch of the second group of conductive terminals 150b, the portion of the underfill material UF flowing on the high-density region HD1 may move slower (i.e., have a lower flow rate) than the other portion of the underfill material UF flowing on the low-density region LD1. In other words, when the underfill material UF flows on the high-density region HD1, the first group of conductive terminals 150a distributed on the high-density region HD1 provides less flow resistance, and when the underfill material UF flows on the low-density region LD1, the second group of conductive terminals 150b distributed on the high-density region HD1 provides more flow resistance. The above-mentioned difference in flow resistance and flow rate caused by the high-density region HD1 and the low-density region LD1 may cause voids to be trapped in the underfill material UF. In order to improve the encysted void issue of the underfill material UF, a guide pattern 144 distributed in the separation area 140C (e.g., a T-shaped separation area) may be provided. Since the guide pattern 144 provides sufficient capillary guiding force for the under-fill material UF, when the under-fill material UF passes through the separation area 140C, the guide pattern 144 reduces the flow resistance of the under-fill material UF and accelerates the flow rate of the under-fill material UF.

[0037] Since the guide pattern 144 provides sufficient capillary guiding force for the underfill material UF, the underfill material UF can flow from the high-density area HD1 to the high-density area HD2 with lower flow resistance. Therefore, the flow front and flow path of the underfill material UF can be well controlled, and the hole embedding problem of the underfill material UF can be easily solved.

[0038] Figure 6 An enlarged top view of a guide pattern according to some embodiments of the present disclosure is schematically depicted.

[0039] Reference Figure 6 In the present embodiment, the partition 140C is a T-shaped partition, and the guide pattern 144 includes a dot pattern distributed between the die bonding area 140B1 and the die bonding area 140B2. In some embodiments, the dot guide pattern 144 may be uniformly distributed in the T-shaped partition 140C, and the arrangement spacing of the dot guide pattern 144 may be fixed. In some alternative embodiments, the dot guide pattern 144 may be distributed only around the T-bonding area of ​​the T-shaped partition 140C, and the arrangement spacing of the dot guide pattern 144 may be fixed. In addition, the dot guide pattern 144 may be or include a circular guide pattern, an elliptical guide pattern, a triangular guide pattern, a rectangular guide pattern, a combination of the foregoing patterns, or a dot pattern of other suitable shapes.

[0040] like Figure 6As shown, in some embodiments, the lateral size of the dot-shaped guide pattern 144 may be greater than the lateral size of the pads distributed in the high-density area HD1 (e.g., the conductive pads covered by the conductive terminal 150a). In some alternative embodiments, not shown in the figure, the lateral size of the dot-shaped guide pattern 144 may be substantially equal to the lateral size of the pads distributed in the high-density area HD1 (e.g., the conductive pads covered by the conductive terminal 150a). Similarly, in some embodiments, the lateral size of the dot-shaped guide pattern 144 may be greater than the lateral size of the pads distributed in the high-density area HD2 (e.g., the conductive pads covered by the conductive terminal 150c). In some alternative embodiments, not shown in the figure, the lateral size of the dot-shaped guide pattern 144 may be substantially equal to the lateral size of the pads distributed in the high-density area HD2 (e.g., the conductive pads covered by the conductive terminal 150c).

[0041] To provide sufficient capillary guiding force between the high-density area HD1 and the high-density area HD2 , the arrangement pitch of the dot guide patterns 144 may be in the range of about 10 microns to about 40 microns, and the lateral dimension of the dot guide patterns 144 may be in the range of about 6 microns to about 20 microns.

[0042] Fig. 7A and Figure 7B Schematically depicts Figure 6 A cross-sectional view of the guide pattern shown in FIG.

[0043] Reference Figure 1 and Fig. 7A , the guide pattern 144 is covered by the dielectric layer 160. Figure 1 and Fig. 7A As shown, the dielectric layer 160 includes a first portion 160a, a second portion 160b, and a connecting portion 160c between the first portion 160a and the second portion 160b. The first portion 160a of the dielectric layer 160 is covered by the first semiconductor die 120a, and the first portion 160a is disposed between the first semiconductor die 120a and the interposer wiring substrate 140. The second portion 160b of the dielectric layer 160 is covered by the second semiconductor die 120b, and the second portion 160b is disposed between the second semiconductor die 120b and the interposer wiring substrate 140. The connecting portion 160c of the dielectric layer 160 covers the guide pattern 144 and contacts the guide pattern 144. In some embodiments, the guide pattern 144 is separated from the first semiconductor die 120a and the second semiconductor die 120b by the dielectric layer 160. In some embodiments, the connecting portion 160 c of the dielectric layer 160 is thicker than the first portion 160 a and the second portion 160 b of the dielectric layer 160 .

[0044] like Fig. 7AAs shown in FIG. 1 , due to the capillary phenomenon, the connection portion 160c of the dielectric layer 160 may have a concave top surface. The connection portion 160c of the dielectric layer 160 may cover the sidewalls of the first semiconductor grain 120a and the second semiconductor grain 120b. The upper portion of the sidewalls of the first semiconductor grain 120a and the second semiconductor grain 120b is not laterally enclosed by the connection portion 160c of the dielectric layer 160. In addition, the connection portion 160c of the dielectric layer 160 is formed by the insulating encapsulation body 130 (such as Figure 1 As shown), and the connecting portion 160c of the dielectric layer 160 is in physical contact with the insulating enclosure 130.

[0045] Reference Figure 7B , Figure 7B The guide pattern 144′ shown in FIG. Fig. 7A The illustrated guide pattern 144 is similar, except that each guide pattern in the guide pattern 144' includes a conductive pattern 144a and a solder 144b, the conductive pattern 144a is disposed on the top surface of the wiring substrate 140, and the solder 144b covers the conductive pattern 144a. The conductive pattern 144a of the guide pattern 144' may be or include a circular guide pattern, an elliptical guide pattern, a triangular guide pattern, a rectangular guide pattern, or a dot pattern of other suitable shapes. In addition, the solder 144b of the guide pattern 144' may be or include a circular solder cap, an elliptical solder cap, a triangular solder cap, a rectangular solder cap, or other suitable types of solder caps.

[0046] like Figure 7B As shown, the connection portion 160 c of the dielectric layer 160 covers the conductive pattern 144 a and the solder 144 b , and the connection portion 160 c of the dielectric layer 160 is in physical contact with the conductive pattern 144 a and the solder 144 b .

[0047] Figure 8 An enlarged top view of a guide pattern according to some embodiments of the present disclosure is schematically depicted.

[0048] refer to Figure 8 , Figure 8 The guide pattern 244 shown in FIG. Fig. 7A, except that the guide pattern 244 includes a strip pattern 244a and a strip pattern 244 extending through the partition 140C. In the present embodiment, the guide pattern 244 includes at least one strip pattern 244a and at least one strip pattern 244b. At least one strip pattern 244a extends from one of the first die bonding areas 140B1 to the second die bonding area 140B2, and at least one strip pattern 244b extends from the other of the first die bonding areas 140B1 to the second die bonding area 140B2. In addition, a portion of the partition 140C sandwiched between adjacent high-density areas HD1 is not occupied by the guide pattern 244. The guide pattern 244 is mainly distributed on another portion of the partition 140C sandwiched between the high-density area HD1 and the high-density area HD2. In other words, the guide pattern 244 is not uniformly distributed on the partition 140C. In some alternative embodiments, the guide pattern 244 may be distributed only around the T-joining region of the T-shaped partition region 140C.

[0049] Fig.9A and Fig. 9B Schematically depicts Figure 8 A cross-sectional view of the guide pattern shown in FIG.

[0050] Reference Figure 1 and Fig.9A , the guide pattern 244 is covered by the dielectric layer 160. Figure 1 and Fig.9A As shown, the dielectric layer 160 includes a first portion 160a, a second portion 160b, and a connecting portion 160c located between the first portion 160a and the second portion 160b. The first portion 160a of the dielectric layer 160 is covered by the first semiconductor die 120a, and the first portion 160a is disposed between the first semiconductor die 120a and the interposer wiring substrate. The second portion 160b of the dielectric layer 160 is covered by the second semiconductor die 120b, and the second portion 160b is disposed between the second semiconductor die 120b and the interposer wiring substrate. The connecting portion 160c of the dielectric layer 160 covers the guide pattern 244 and contacts the guide pattern 244. In some embodiments, the guide pattern 244 is separated from the first semiconductor die 120a and the second semiconductor die 120b by the dielectric layer 160. In some embodiments, the connecting portion 160c of the dielectric layer 160 is thicker than the first portion 160a and the second portion 160b of the dielectric layer 160.

[0051] like Fig.9AAs shown in FIG. 1 , due to the capillary phenomenon, the connection portion 160c of the dielectric layer 160 may have a concave top surface. The connection portion 160c of the dielectric layer 160 may cover the sidewalls of the first semiconductor grain 120a and the second semiconductor grain 120b. The upper portion of the sidewalls of the first semiconductor grain 120a and the second semiconductor grain 120b is not laterally enclosed by the connection portion 160c of the dielectric layer 160. In addition, the connection portion 160c of the dielectric layer 160 is formed by the insulating encapsulation body 130 (such as Figure 1 As shown), and the connecting portion 160c of the dielectric layer 160 is in physical contact with the insulating enclosure 130.

[0052] Reference Fig. 9B , Fig. 9B The guide pattern 244' is shown Fig.9A The illustrated guide pattern 244 is similar, except that each guide pattern in the guide pattern 244' includes a conductive pattern 244a and a solder 244b, the conductive pattern 244a is disposed on the top surface of the wiring substrate 140, and the solder 244b covers the conductive pattern 244a. The conductive pattern 244a of the guide pattern 244' may be or include a circular guide pattern, an elliptical guide pattern, a triangular guide pattern, a rectangular guide pattern, or a dot pattern of other suitable shapes. In addition, the solder 244b of the guide pattern 244' may be or include a circular solder cap, an elliptical solder cap, a triangular solder cap, a rectangular solder cap, or other suitable types of solder caps.

[0053] like Fig. 9B As shown, the connection portion 160 c of the dielectric layer 160 covers the conductive pattern 244 a and the solder 244 b , and the connection portion 160 c of the dielectric layer 160 is in physical contact with the conductive pattern 244 a and the solder 244 b .

[0054] Figures 10 to 12 An enlarged top view of a guide pattern in some alternative embodiments according to the present disclosure is schematically depicted.

[0055] Reference Figure 6 and Fig.10 , Fig.10 The guide pattern 144" shown in FIG. Figure 6 The guide pattern 144 is similar to the guide pattern 144 shown in , except that the distribution density and number of the guide pattern 144 ″ are less than the distribution density and number of the guide pattern 144 .

[0056] Reference Figure 6 and Fig.11 , Fig.11 The guide pattern 144'' is shown with Figure 6The guide pattern 144 shown is similar, except that the lateral size of each dot-shaped guide pattern in the guide pattern 144'" is reduced. The lateral size of the dot-shaped guide pattern 144'" is smaller than the lateral size of the pads distributed in the high-density area HD1 (e.g., the conductive pads covered by the conductive terminal 150a). Similarly, in some embodiments, the lateral size of the dot-shaped guide pattern 144'" is smaller than the lateral size of the pads distributed in the high-density area HD2 (e.g., the conductive pads covered by the conductive terminal 150c).

[0057] Reference Figure 8 and Fig.12 , Fig.12 The guide pattern 244" is shown with Figure 6 The illustrated guide pattern 244 is similar, with the difference that the guide pattern 244" is distributed only around the T-joining area of ​​the T-shaped separation area 140C. In addition, some of the conductive wirings 142 may extend through the separation area 140C. For example, the conductive wirings 142 are distributed on opposite sides (e.g., the upper side and the lower side) of the guide pattern 244".

[0058] In the above embodiments, various guide patterns are provided between adjacent semiconductor dies, so that the flow front and flow path of the underfill material applied between the semiconductor die and the interposer wiring substrate can be effectively controlled. Therefore, the possibility of void embedding in the flowable underfill material can be minimized.

[0059] According to some embodiments of the present disclosure, a packaging structure including a wiring substrate, a semiconductor die and a dielectric layer is provided. The wiring substrate includes a die bonding area and a guide pattern distributed between the die bonding areas. The semiconductor die is configured on the die bonding area and electrically connected to the wiring substrate, wherein the guide pattern is electrically insulated from the semiconductor die. The dielectric layer is configured between the semiconductor die and the wiring substrate, wherein the dielectric layer covers the guide pattern and contacts the guide pattern. In some embodiments, the guide pattern is electrically floating. In some embodiments, the guide pattern is electrically insulated from the conductive wiring of the wiring substrate, and the conductive wiring of the wiring substrate is electrically connected to the semiconductor die. In some embodiments, the guide pattern includes a plurality of long strip patterns extending from a first die bonding area in the die bonding area to a second die bonding area in the die bonding area. In some embodiments, the guide pattern includes a dot pattern distribution between the die bonding areas. In some embodiments, the guide pattern includes a conductive pattern and a solder, respectively, the conductive pattern is configured on the wiring substrate, and the solder covers the conductive pattern. In some embodiments, the guide pattern is spaced apart from the semiconductor die by a dielectric layer. In some embodiments, the package structure further includes an insulating encapsulation body disposed on the wiring substrate, and the insulating encapsulation body laterally encapsulates the semiconductor die.

[0060] According to some other embodiments of the present disclosure, a packaging structure including a wiring substrate, a first semiconductor grain and a dielectric layer is provided. The wiring substrate includes a plurality of grain bonding areas, and the grain bonding areas are laterally spaced apart from each other by separation areas. The wiring substrate further includes auxiliary patterns distributed in the separation areas. The first semiconductor grain is configured in the first grain bonding area in the grain bonding area and is electrically connected to the wiring substrate. The first semiconductor grain includes a first group of conductive terminals and a second group of conductive terminals, wherein the first arrangement spacing of the first group of conductive terminals is greater than the second arrangement spacing of the second group of conductive terminals. The auxiliary pattern is electrically insulated from the first group of conductive terminals, the second group of conductive terminals, the third group of conductive terminals and the fourth group of conductive terminals. The dielectric layer is configured in a first gap between the first semiconductor grain and the wiring substrate and in a second gap between the second semiconductor grain and the wiring substrate. The dielectric layer covers the auxiliary pattern and contacts the auxiliary pattern. In some embodiments, the package structure further includes a second semiconductor grain, the second semiconductor grain is configured on a second grain bonding area in the grain bonding area, and is electrically connected to the wiring substrate, wherein the second semiconductor grain includes a third group of conductive terminals and a fourth group of conductive terminals, and the third arrangement spacing of the third group of conductive terminals is greater than the fourth arrangement spacing of the fourth group of conductive terminals. In some embodiments, the auxiliary pattern is electrically floating. In some embodiments, the auxiliary pattern is electrically insulated from the semiconductor grain. In some embodiments, the auxiliary pattern includes a plurality of long strip patterns extending through the separation area. In some embodiments, the auxiliary pattern includes a plurality of dot patterns distributed in the separation area. In some embodiments, the auxiliary pattern includes a conductive pattern and a solder, respectively, the conductive pattern is configured on the wiring substrate, and the solder covers the conductive pattern. In some embodiments, the first group of conductive terminals is laterally configured between the auxiliary pattern and the second group of conductive terminals, and the third group of conductive terminals is laterally configured between the auxiliary pattern and the fourth group of conductive terminals.

[0061] According to some other embodiments of the present disclosure, a packaging structure including a wiring substrate, a first semiconductor grain, a second semiconductor grain and a dielectric layer is provided. The wiring substrate includes a conductive wiring and a dummy pattern, wherein the dummy pattern is distributed on the surface of the wiring substrate, and the dummy pattern is electrically floating. The first semiconductor grain is configured on the surface of the wiring substrate and is electrically connected to the conductive wiring of the wiring substrate. The second semiconductor grain is configured on the surface of the wiring substrate and is electrically connected to the conductive wiring of the wiring substrate. The dielectric layer includes a first portion, a second portion and a connecting portion located between the first portion and the second portion. The first portion is configured between the first semiconductor grain and the wiring substrate, the second portion is configured between the second semiconductor grain and the wiring substrate, and the connecting portion of the dielectric layer covers the dummy pattern and contacts the dummy pattern. In some embodiments, the dummy pattern is spaced apart from the semiconductor grain by the dielectric layer. In some embodiments, the connecting portion is thicker than the first portion and the second portion. In some embodiments, the packaging structure further includes a first conductive terminal and a second conductive terminal, wherein the first semiconductor grain is electrically connected to the conductive wiring of the wiring substrate through the first conductive terminal, and the second semiconductor grain is electrically connected to the conductive wiring of the wiring substrate through the second conductive terminal. In some embodiments, the dummy patterns include a conductive pattern and solder, respectively. The conductive pattern is disposed on the wiring substrate, and the solder covers the conductive pattern.

[0062] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: A wiring substrate including a plurality of die bonding areas and a plurality of guide patterns distributed between the plurality of die bonding areas; a plurality of semiconductor dies disposed on the plurality of die bonding regions and electrically connected to the wiring substrate, wherein the plurality of guide patterns are electrically insulated from the plurality of semiconductor dies; as well as A dielectric layer is located between the plurality of semiconductor dies and the wiring substrate, wherein the dielectric layer covers the plurality of guide patterns and contacts the plurality of guide patterns.

2. The packaging structure according to claim 1, characterized in that: The plurality of guide patterns are electrically floating.

3. The packaging structure according to claim 1, characterized in that: The plurality of guide patterns are electrically insulated from the conductive wiring of the wiring substrate, and the conductive wiring of the wiring substrate is electrically connected to the plurality of semiconductor dies.

4. The packaging structure according to claim 1, characterized in that: The plurality of guide patterns include a plurality of long stripe patterns extending from a first die bonding region among the plurality of die bonding regions to a second die bonding region among the plurality of die bonding regions.

5. The packaging structure according to claim 1, characterized in that: The plurality of guide patterns include a plurality of dot patterns distributed between the plurality of die bonding areas.

6. A packaging structure, characterized in that: include: a wiring substrate comprising a plurality of die bonding regions laterally spaced apart from each other by separation regions, wherein the wiring substrate further comprises a plurality of auxiliary patterns distributed in the separation regions; A first semiconductor die is disposed in a first die bonding region among the plurality of die bonding regions and is electrically connected to the wiring substrate, wherein the first semiconductor die comprises a first group of conductive terminals and a second group of conductive terminals, and a first arrangement pitch of the first group of conductive terminals is greater than a second arrangement pitch of the second group of conductive terminals; as well as A dielectric layer is disposed between the first semiconductor die and the wiring substrate, wherein the dielectric layer covers and contacts the plurality of auxiliary patterns.

7. The packaging structure according to claim 6, characterized in that: Also includes: a second semiconductor die disposed in a second die bonding region among the plurality of die bonding regions and electrically connected to the wiring substrate, the second semiconductor die comprising a third group of conductive terminals and a fourth group of conductive terminals, a third arrangement pitch of the third group of conductive terminals being greater than a fourth arrangement pitch of the fourth group of conductive terminals, wherein the plurality of auxiliary patterns are electrically insulated from the first group of conductive terminals, the second group of conductive terminals, the third group of conductive terminals, and the fourth group of conductive terminals, and The dielectric layer is further disposed between the second semiconductor die and the wiring substrate.

8. The packaging structure according to claim 6, characterized in that: The plurality of auxiliary patterns are electrically floating or electrically insulated from the plurality of semiconductor grains.

9. A packaging structure, characterized in that: include: A wiring substrate, comprising a plurality of conductive wirings and a plurality of dummy patterns, wherein the plurality of dummy patterns are distributed on a surface of the wiring substrate and electrically floated; A first semiconductor crystal grain is disposed on the surface of the wiring substrate and is electrically connected to the plurality of conductive wirings of the wiring substrate; a second semiconductor crystal grain disposed on the surface of the wiring substrate and electrically connected to the plurality of conductive wirings of the wiring substrate; as well as A dielectric layer includes a first portion, a second portion, and a connecting portion between the first portion and the second portion, wherein the first portion is configured between the first semiconductor grain and the wiring substrate, the second portion is configured between the second semiconductor grain and the wiring substrate, and the connecting portion of the dielectric layer covers the multiple dummy patterns and contacts the multiple dummy patterns.

10. The packaging structure according to claim 9, characterized in that: The dielectric layer includes an underfill material, and the plurality of dummy patterns are separated from the plurality of semiconductor grains by the underfill material.

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