Semiconductor device

Abstract

A semiconductor device. A semiconductor die includes a lower die separated by a dielectric region; a cross die vertically stacked on the lower die and the dielectric region; the molding structure fills the dielectric region and surrounds side surfaces of the lower die and the cross-die. A bond ring connecting the cross-die to the lower die, and including: an upper metal ring formed in a bottom surface of the cross-die; and a lower metal ring formed in the top surface of the lower die and extending through the molded structure in the dielectric region. A lower metal ring is bonded to the upper metal ring.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly, to semiconductor devices. Background Art

[0002] The semiconductor industry continues to grow due to the ever-increasing packing density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, these improvements in packing density come from the continued shrinking of minimum feature sizes, which allows more components to be packed into a given area.

[0003] In addition to smaller electronic components, improvements in component packaging also seek to provide smaller packages that take up less area than previous packages. Examples of semiconductor packaging types include plastic quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer level packages (WLPs), package on package (PoP), system on chip (SoC) or system on integrated circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are prepared by placing chips on chips at the semiconductor wafer level. These three-dimensional devices provide improved packing density and other advantages, such as faster speeds and higher bandwidths, due to the reduced interconnect length between stacked chips. However, there are many challenges associated with three-dimensional devices. Utility Model Content

[0004] The present disclosure provides a semiconductor device, comprising: at least two lower dies separated by a dielectric region; a cross die vertically stacked on the at least two lower dies and the dielectric region; a molding structure filling the dielectric region and laterally surrounding the side surfaces of the at least two lower dies and the cross die; and a bonding ring connecting the cross die to the at least two lower dies, the bonding ring comprising: an upper metal ring formed on the bottom surface of the cross die; and a lower metal ring formed in the top surfaces of the at least two lower dies and extending through the molding structure in the dielectric region, wherein the lower metal ring is bonded to the upper metal ring.

[0005] In some embodiments, a bottom surface of the upper metal ring contacts at least 10% of a top surface of the lower metal ring; or a top surface of the lower metal ring contacts at least 10% of a bottom surface of the upper metal ring.

[0006] In some embodiments, the bottom surface of the upper metal ring is larger than the top surface of the upper metal ring; or the top surface of the lower metal ring is larger than the bottom surface of the lower metal ring.

[0007] In some embodiments, with respect to a vertical direction, a thickness of the upper metal ring is at least 10% of a thickness across the die; and with respect to the vertical direction, a thickness of the lower metal ring is at least 10% of a thickness of the lower die.

[0008] In some embodiments, the engagement ring is discontinuous.

[0009] In some embodiments, the cross-die includes a memory chip, a logic chip, an analog chip, a radio frequency chip, or an integrated passive device chip; at least one of the lower dies includes an interposer or a dummy die; the lower metal ring and the upper metal ring include copper or a copper alloy; and the cross-die is fusion-bonded or hybrid-bonded to the lower die.

[0010] The present disclosure provides a semiconductor device, comprising: two lower dies separated by a dielectric region; a cross-die vertically stacked on the two lower dies and the dielectric region; a lower dielectric layer filling the dielectric region and laterally surrounding the side surfaces of the two lower dies; an upper dielectric layer laterally surrounding the side surfaces of the cross-die; a bonding ring formed in the dielectric region on the bottom surface of the cross-die, the top surface of the lower die, and the top surface of the lower dielectric layer to connect the cross-die to the two lower dies; and a plurality of bonding wires disposed inside the bonding ring and connecting the cross-die to the two lower dies, wherein a portion of the bonding ring is disposed in the lower dielectric layer and extends across the dielectric region.

[0011] In some embodiments, the semiconductor device further includes a plurality of bonding wires disposed inside the bonding ring and connecting the cross-die to the two lower dies, the bonding wires including: a plurality of upper metal wires formed on the bottom surface of the cross-die; and a plurality of lower metal wires formed in the top surface of the lower dies, wherein each lower metal wire is bonded to a corresponding upper metal wire.

[0012] In some embodiments, the bonding ring includes: an upper metal ring formed on a bottom surface of the cross-die; and a lower metal ring formed in a top surface of the lower die and extending through the dielectric region, wherein the lower metal ring is bonded to the upper metal ring; and at least one of the upper metal ring and the lower metal ring has a width in a horizontal direction that is greater than 25% of a height of the cross-die in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The embodiments of the present disclosure are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various elements may be arbitrarily enlarged or reduced to clearly represent the components of the embodiments of the present disclosure.

[0014] Figure 1A is a vertical cross-sectional view of a semiconductor die according to various embodiments of the present disclosure.

[0015] Figure 1B is a vertical cross-sectional view of an interposer according to various embodiments of the present disclosure.

[0016] Figure 2A is a top view of a multi-layer, multi-die semiconductor device according to various embodiments of the present disclosure.

[0017] Figure 2B is along Figure 2A A cross-sectional view taken along line L1.

[0018] Figure 2C yes Figure 2B Magnified view of the P1 section.

[0019] Figure 3A-Figure 3F yes Figure 2A and Figure 2B Vertical cross-sectional views of alternative configurations of upper and lower metal rings having different sizes and overlapping configurations.

[0020] Figure 3G and Figure 3H yes Figure 2A and Figure 2B A top view of different size configurations of the upper metal ring and the lower metal ring.

[0021] Figure 4A-4D According to various embodiments of the present disclosure Figure 2A and 2B Top view of a semiconductor device showing a possible horizontal offset of the upper and lower metal rings.

[0022] Figure 5A is a top view of a semiconductor device according to various embodiments of the present disclosure.

[0023] Figure 5B is along Figure 5A A cross-sectional view taken along line L1.

[0024] Figure 6A-6D is a top view of a semiconductor device having an alternative metal ring configuration according to various embodiments of the present disclosure.

[0025] Figure 7A-7Eis a top view of a semiconductor device having an alternative metal ring configuration according to various embodiments of the present disclosure.

[0026] Figure 8A-8D is a top view of a semiconductor device having an alternative metal ring configuration according to various embodiments of the present disclosure.

[0027] Figure 9A-9F is a vertical cross-sectional view depicting alternative minimum distances MD1 and MD2 according to various embodiments of the present disclosure.

[0028] Figures 10A-10D is a top view of a semiconductor device having an alternative metal ring configuration according to various embodiments of the present disclosure.

[0029] Fig.10E yes Fig. 10D Magnified view of the P1 section.

[0030] Figure 10F-10H yes Fig. 10D Alternative enlarged view of section P1.

[0031] Fig.11 is a flow chart of a method of forming a semiconductor device according to various embodiments of the present disclosure.

[0032] Figures 12A-12F It is shown Fig.11 Vertical cross-section of an intermediate stage of operation of the method.

[0033] The reference numerals are described as follows:

[0034] 10: Grain

[0035] 50: Carrier

[0036] 100: Cross-die

[0037] 102: Semiconductor substrate

[0038] 104: Dielectric Structure

[0039] 104A: Substrate oxide layer

[0040] 104B: Inter-Layer Dielectric (ILD) layer

[0041] 104C: Inter-Layer Dielectric (ILD) layer

[0042] 104D: Inter-Layer Dielectric (ILD) layer

[0043] 104E: Inter-Layer Dielectric (ILD) layer

[0044] 104F: Inter-Layer Dielectric (ILD) layer

[0045] 104G: Passivation layer

[0046] 106: Metal parts

[0047] 108: Substrate electrode

[0048] 110: Interconnection Structure

[0049] 130: Sealing ring

[0050] 150: Bonding layer

[0051] 152: Bonding pad

[0052] 153: Bonding layer

[0053] 162: TSV (Through-Silicon Via) structure

[0054] 200: Lower grain

[0055] 224: Redistribution Layer

[0056] 225: Substrate

[0057] 226: Protective layer

[0058] 227: Metal parts

[0059] 228: Bonding layer

[0060] 230: Conductive via structure

[0061] 252: Bonding pad

[0062] 300: Semiconductor devices

[0063] 302: Grain gap (dielectric region)

[0064] 305: Mating ring

[0065] 310: Molded structure

[0066] 310a: Lower dielectric layer

[0067] 310b: Upper dielectric layer

[0068] 320: Solder bump

[0069] 350: Mating ring

[0070] 351: Rounded Corners

[0071] 352: Upper metal ring

[0072] 354: Lower metal ring

[0073] 355: Engagement groove

[0074] 356: Metal Wire

[0075] 358: Lower metal wire

[0076] 360: Joining line

[0077] 370: Passive components

[0078] 500: Semiconductor devices

[0079] L1: Line

[0080] MD1: Distance

[0081] MD2: Distance

[0082] T1: Thickness

[0083] T2: thickness.

[0084] T3: Thickness

[0085] W1: Width

[0086] W2: Width

[0087] DT1: Thickness

[0088] DT2: Thickness

[0089] DT3: Thickness

[0090] P1: Local DETAILED DESCRIPTION

[0091] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments of the present disclosure. Of course, the above are merely examples and are not intended to define the embodiments of the present disclosure. For example, if the description mentions that a first element is formed above a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0092] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "higher" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0093] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range that takes into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances for manufacturing components to which the number is related, the number or range of numbers covers a reasonable range including the number, such as within + / -10% of the number. For example, a material layer having a thickness of "about 5 nanometers" may cover a size range of 4.25 nanometers to 5.75 nanometers, given that the manufacturing tolerance associated with deposited material layers is + / -15% by those of ordinary skill in the art.

[0094] In a three-dimensional (3D) semiconductor package, a bonding pad formed in each of the upper die and the lower die can be used to bond the upper die and the lower die so as to physically and electrically connect the upper die and the lower die. Typically, a bonding pad is a structure with a relatively small horizontal cross-sectional surface area. Therefore, precise alignment of the die is required to ensure that the bonding pad on the upper die is aligned with the bonding pad formed on the lower die. In addition, the relatively small cross-sectional area of ​​the bonding pad provides a relatively weak bond between the die. In the case where the upper die (e.g., a cross die) is bonded to more than one lower die, the gap between the lower die may cause the bonding pad pattern density to change. Due to the copper chemical mechanical planarization (CMP) loading effect reduces the flatness of the copper-copper bonding interface, this change in the bonding pad pattern density may cause the grain stress to increase. In this way, the relatively small contact area between the bonding pads on the lower die and the upper die may be further reduced. In addition, the difference in coefficient of thermal expansion (CTE) between the upper and lower dies and the inter-die gap filled with dielectric material may increase cross-die stress. As a result, high wafer bonding failure rate may reduce manufacturing yield.

[0095] The present disclosure relates to fused and / or hybrid bonded stacked semiconductor devices. Fusion may include fusion of metal elements such as metal bonding rings, wires and / or pads. Hybrid bonding may include bonding of dielectric layers such as SiOx layers and fusion bonding of metal elements. Specifically, the present disclosure relates to cross-grain semiconductor devices (devices including semiconductor grains extending through more than one semiconductor grain and bonded to more than one semiconductor grain), which include bonding structures designed to provide improved bonding strength. Specifically, various embodiments provide bonding structures, which may include bonding rings and / or bonding wires, which are configured to provide increased bonding strength when the cross-grain is bonded to any number of bottom grains. Such structures may have an enhanced surface area to ensure better alignment and overlap and an increased surface area to form a bond. For example, at least a portion of the bonding structure may be located adjacent to one or more edges of the cross-grain. In some embodiments, at least a portion of the bonding structure may be located adjacent to one or more edges of the bottom grain, and specifically, adjacent to the grain gap between the bottom grains spanned by the cross-grain. In yet another embodiment, the shape of the bonding structure can be designed to account for variations in the size and / or shape of the upper die and one or more lower (bottom) dies.

[0096] In various embodiments, a bonding structure can be formed by bonding an upper metal ring formed in a cross-die (upper die) to a lower metal ring formed in a lower (bottom) die. The width (and corresponding surface area) of the upper and lower metal rings can be designed and configured to ensure sufficient bonding strength even when semiconductor die misalignment occurs. In other words, the width and / or surface area of ​​the upper and lower metal rings can be designed to provide a minimum amount of overlap even when semiconductor die misalignment occurs. In addition, the size of the upper and lower metal rings can be designed to provide sufficient bonding strength when taking into account the thickness variation of the cross-die and / or bottom die.

[0097] Figure 1A is a vertical cross-sectional view of a semiconductor die 10 according to various embodiments of the present disclosure. Figure 1B is a vertical cross-sectional view of the interposer 20 according to various embodiments of the present disclosure.

[0098] refer to Figure 1AThe semiconductor die 10 may be, for example, an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulation chip, or a memory chip. In some embodiments, the semiconductor die 10 may be an active component or a passive component. In some embodiments, the semiconductor die 10 includes a semiconductor substrate 102, a dielectric structure 104, an interconnect structure 110 embedded in the dielectric structure 104, a seal ring 130, and a TSV (Through-Silicon Via) structure 162.

[0099] In some embodiments, the semiconductor substrate 102 may include an elemental semiconductor such as silicon or germanium and / or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride, or indium phosphide. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate. In various embodiments, the semiconductor substrate 102 may be a planar substrate, a substrate with a plurality of fins, a nanowire, or other forms known to those of ordinary skill in the art. Depending on the design requirements, the semiconductor substrate 102 may be a P-type substrate or an N-type substrate, and may have a doped region therein. The doped region may be configured for an N-type device or a P-type device.

[0100] In some embodiments, the semiconductor substrate 102 includes an isolation structure defining at least one active region, and the first device layer can be disposed on / in the active region. The first device layer can include a variety of devices. In some embodiments, the device can include active components, passive components, or a combination thereof. In some embodiments, the device can include an integrated circuit device. The device can be, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In some embodiments, the first device layer includes a gate structure, a source / drain region, a spacer, etc.

[0101] The dielectric structure 104 may be disposed on the front side of the semiconductor substrate 102. In some embodiments, the dielectric structure 104 may include silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. Other suitable dielectric materials may be within the contemplated scope of the present disclosure. The dielectric structure 104 may be a single layer or a multi-layer dielectric structure. For example, Figure 1BAs shown, the dielectric structure 104 may include a plurality of dielectric layers 104A-104F, which may include a substrate oxide layer 104A, inter-layer dielectric (ILD) layers 104B-104F, and a passivation layer 104G. However, the present disclosure is not limited to any particular number of layers. Fewer or additional dielectric layers may be included in the dielectric structure 104.

[0102] The dielectric structure 104 may be formed by any suitable deposition process. Herein, "suitable deposition process" may include chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, high density plasma chemical vapor deposition (HDPCVD) process, metal organic chemical vapor deposition (MOCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, sputtering process, laser ablation, etc.

[0103] The interconnect structure 110 may be formed in the dielectric structure 104. The interconnect structure 110 may include a metal feature 106 disposed in the dielectric structure 104. The metal feature 106 may be any of a variety of metal line and via structures that electrically connect metal lines of adjacent ILD layers 104B-104F. The metal feature 106 may be electrically connected to a substrate electrode 108 disposed on the semiconductor substrate 102, so that the interconnect structure 110 may electrically interconnect semiconductor devices formed on the semiconductor substrate 102. In some embodiments, the substrate electrode 108 may include a metal gate of a transistor formed in a device layer of the semiconductor substrate 102.

[0104] The interconnect structure 110 may be formed of any suitable conductive material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, silver (Ag), combinations thereof, etc. For example, the interconnect structure 110 may preferably include copper having an atomic percentage greater than 80% (such as greater than 90% and / or greater than 95%), but greater or lesser percentages of copper may be used. Other suitable conductive materials are within the contemplated scope of the present disclosure.

[0105] In some embodiments, a barrier layer (not shown) may be disposed between the metal feature 106 and the dielectric layer of the dielectric structure 104 to prevent material of the metal feature 106 from migrating to the semiconductor substrate 102. The barrier layer may include, for example, Ta, TaN, Ti, TiN, CoW, or a combination thereof. Other suitable barrier layer materials may be within the contemplated scope of the present disclosure.

[0106] The sealing ring 130 may extend around the periphery of the die 10. For example, the sealing ring 130 may be disposed in the dielectric structure 104 and may laterally surround the interconnect structure 110. The sealing ring 130 may be configured to protect the interconnect structure 110 from contaminant diffusion and / or physical damage during device fabrication processes, such as plasma etching and / or deposition processes.

[0107] The seal ring 130 may include greater than 80 atomic percent copper, such as greater than 90 atomic percent and / or greater than 95 atomic percent, although greater or lesser percentages may be used. The seal ring 130 may include conductive lines and via structures connected to each other, and may be formed simultaneously with conductive lines and via structures of the metal features 106 of the interconnect structure 110. The seal ring 130 may be electrically isolated from the metal features 106. Other suitable seal ring materials may be within the contemplated scope of the present disclosure.

[0108] In some embodiments, the metal feature 106 and / or the seal ring 130 can be formed by a dual damascene process or by multiple damascene processes. A damascene process typically forms and fills a single feature with copper at each damascene stage. A dual damascene process typically forms two features at the same time and fills both features with copper, for example, both a trench and an overlapping via can be filled with a single copper deposition using a dual damascene process. In an alternative embodiment, the metal feature 106 and / or the seal ring 130 can be formed by an electroplating process.

[0109] For example, the damascene process may include patterning the dielectric structure 104 to form openings, such as trenches and / or through-holes (e.g., vias). A deposition process may be performed to deposit a conductive metal (e.g., copper) in the openings. A planarization process such as chemical mechanical planarization (CMP) may then be performed to remove excess copper (e.g., overburden) disposed on top of the dielectric structure 104.

[0110] Specifically, patterning, metal deposition, and planarization processes may be performed on each of the ILD layers 104B-104F to form the interconnect structure 110 and / or the seal ring 130. For example, the ILD layer 104B may be deposited and patterned to form an opening in the ILD layer. A deposition process may then be performed to fill the opening in the ILD layer 104B. A planarization process may then be performed to remove the cap layer and form the metal feature 106 in the ILD layer 104B. These process steps may be repeated to form the ILD layers 104C-104F and the corresponding metal features 106, thereby completing the interconnect structure 110 and / or the seal ring 130.

[0111] The bonding layer 150 may be disposed above the dielectric structure 104. The bonding layer 150 may be formed of a dielectric material. The bonding layer 150 may be formed by depositing a dielectric material (e.g., silicon oxide, silicon nitride, polymer, or a combination thereof) using any suitable deposition process. Other suitable dielectric materials may be within the intended scope of the present disclosure. The bonding layer 150 may include a bonding pad 152, which may be made of a conductive metal. For example, the bonding pad 152 may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or a combination thereof.

[0112] The upper metal ring 352 may be formed in the bonding layer 150. The upper metal ring 352 may be disposed in a bonding groove formed in the bonding layer 150. In some embodiments, the upper metal ring 352 may be alternatively or additionally formed on the bottom of the semiconductor substrate 102. For example, the upper metal ring 352 may be formed in a bonding layer 153 disposed on the bottom of the semiconductor layer 102. The upper metal ring 352 may be referred to as an upper metal ring 352 because it may be formed in a bonding layer 153 disposed on the bottom of the semiconductor layer 102 of the upper semiconductor die 10, which may then be placed above and fused and / or hybrid-bonded to the lower semiconductor die 200.

[0113] Preferably, the upper metal ring 352 may be formed of a low melting point metal such as tin, lead, copper, or a copper alloy. Preferably, the upper metal ring 352 may include copper having an atomic percentage greater than 80%, for example greater than 90% and / or greater than 95%, but a greater or lesser percentage of copper may be used. However, the present disclosure is not limited to any particular material. As described above, the upper metal ring 352 may be formed by a dual damascene process or by one or more single damascene processes. In an alternative embodiment, the upper metal ring 352 may be formed by an electroplating process.

[0114] In some embodiments, the die 10 may optionally include an upper metal line 356 formed in the bonding layer 150 or the replacement bonding layer 153. The upper metal line 356 may be formed of the same material as the upper metal ring 352 and / or by the same deposition process.

[0115] The TSV structure 162 may extend through a trench formed in the semiconductor substrate 102. The TSV structure 162 may be formed during a middle-end-of-line (MEOL) process and may be formed of a suitable conductive material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, silver (Ag), tungsten (W), combinations thereof, etc. For example, the TSV structure 162 may preferably include copper having an atomic percentage greater than 80% (such as greater than 90% and / or greater than 95%), although a greater or lesser percentage of copper may be used.

[0116] In some embodiments, a barrier layer may be disposed between the TSV structure 162 and the semiconductor substrate 102 and the dielectric structure 104. The barrier layer may include, for example, Ta, TaN, Ti, TiN, CoW, or a combination thereof. Other suitable barrier layer materials may be within the contemplated scope of the present disclosure.

[0117] refer to Figure 1B , the interposer 20 may be a multi-layer structure including a substrate 225 such as a silicon substrate, at least one redistribution layer 224, a protective layer 226, and a bonding layer 228. In some embodiments, the interposer 20 may be configured to be mounted to a supporting substrate, such as a printed circuit board (PCB). The electrical connection between the supporting substrate (e.g., PCB) and the interposer 20 may be achieved via the redistribution structure 224 within the interposer 20. Other suitable configurations for the interposer 20 are within the intended scope of the present disclosure.

[0118] For example, the interposer 20 may include a pair of redistribution layers 224 located above and below a substrate 225. The substrate 225 may be a plate-like member made of a suitable material other than silicon, such as epoxy, glass and / or ceramic materials. The substrate 225 may include a plurality of conductive via structures 230 extending through the substrate 225. The redistribution layer 224 may include metal features 227 embedded in the dielectric material array, such as metal lines, via structures, and bonding areas. In some embodiments, the dielectric material matrix may include multiple layers of dielectric material, such as a photosensitive epoxy material. Each layer of dielectric material may be lithographically patterned to form open areas (e.g., trenches and via openings) within the corresponding dielectric material layer. A metallization process may be used to fill the open areas within each layer of dielectric material with a suitable conductive material (e.g., copper or copper alloy) to form metal features 227 embedded in the dielectric material array.

[0119] Protection layer 226 and bonding layer 228 may be formed over corresponding redistribution layer 224. Protection layer 226 and bonding layer 228 may include bonding pads 252, which may be made of a conductive metal such as copper, copper alloy, etc. In some embodiments, protection layer 226 may include a solder resist material layer that may serve as a protective coating for interposer 20 and underlying metal features 227.

[0120] The bonding layer 228 may be formed by depositing a dielectric material (eg, silicon oxide, silicon nitride, polymer, or a combination thereof) using any suitable deposition process. Other suitable dielectric materials may be within the contemplated scope of the present disclosure.

[0121] At least a portion of the lower metal ring 354 may be formed in the bonding layer 228. In some embodiments, the lower metal ring 354 may be disposed in a trench formed in the bonding layer 228. The lower metal ring 354 may be formed of a low melting point metal such as tin, lead, copper, or a copper alloy. However, the present disclosure is not limited to any particular material. The lower metal ring 354 may preferably include copper having an atomic percentage greater than 80%, for example greater than 90% and / or greater than 95%, but a greater or lesser percentage of copper may be used. As described above, the lower metal ring 354 may be formed by a dual damascene process or by one or more single damascene processes. In an alternative embodiment, the lower metal ring 354 may be formed by an electroplating process.

[0122] In some embodiments, the interposer 20 may optionally include a lower metal line 358 disposed in the bonding layer 228. The lower metal line 358 may be formed by the same process and of the same material as the lower metal ring 354.

[0123] refer to Figure 1A and Figure 1B It should be noted that the bonding layer 152 of the die 10 includes two portions of the upper metal ring 352 and two portions of the upper metal line 356, while the interposer 20 includes only a portion of the lower metal ring 354. This is because the upper die 10 is configured as a cross-die, which is designed to be bonded to at least two interposers 20 (e.g., the bottom die), while the interposer 20 is configured to be bonded to one cross-die. However, the interposer 20 may include additional bottom metal rings and bottom metal line segments for bonding to additional cross-dies.

[0124] Figure 2A is a top view of a semiconductor device 300 according to various embodiments of the present disclosure. Figure 2B is along Figure 2A A cross-sectional view taken along line L1. Figure 2C yes Figure 2B An enlarged view of the P1 section. Figure 2A-2C, the semiconductor device 300 may include at least one cross-die 100 vertically stacked and bonded to at least two lower dies 200. In some embodiments, the cross-die 100 may be disposed on a carrier 50. In some embodiments, the semiconductor device 300 may include a plurality of dies stacked on and bonded to the cross-die 100.

[0125] The semiconductor device 300 may include a molding structure 310 surrounding the cross-die 100 and the lower die 200. The molding structure 310 may be a dielectric material, such as a metal oxide, such as silicon oxide, silicon nitride, silicon oxynitride, a polymer material, a molding material, a resin, etc. The molding structure 310 may include a lower dielectric layer 310a and an upper dielectric layer 310b. The lower dielectric layer 310 may laterally surround the lower die 200 (e.g., may contact the side surface of the lower die 200) and may fill the die gap 302 separating the lower die 200. Therefore, the die gap 302 may be referred to as a dielectric region 302. The upper dielectric layer 310b may laterally surround the cross-die 100 and cover at least a portion of the lower die 200.

[0126] In some embodiments, semiconductor device 300 may include solder bumps on the bottom of lower die 200. Solder bumps 320 may be micro bumps formed of a solder material such as tin, lead, alloys thereof, etc., and may be configured to electrically connect the semiconductor device to other components such as a PCB.

[0127] In some embodiments, the semiconductor device 300 may include one or more passive components 370 disposed within the molding structure 310. The passive components 370 may include transistors, fuses, resistors, inductors, etc., which may be electrically connected to any one of the bottom die 200 and / or the cross die 100.

[0128] Each of the cross die 100 and / or the lower die 200 can be an active die or a passive die. For example, an active chip, such as a memory chip, a logic chip, an analog chip, a radio frequency chip, an integrated passive device chip, etc. For example, the cross die 100 can be such as Figure 1A The semiconductor die 10 shown. A passive die may be a non-computing die configured to communicate signals generated by one or more active die. For example, a passive die may include an interposer, a dummy die, etc. For example, in some embodiments, at least one of the lower die 200 may be as shown. Figure 1B The interposer 20 is shown.

[0129] The semiconductor device 300 may include a bonding ring 350 configured to strengthen the bonding of the cross-die 100 with the lower die 200. The bonding ring 350 may be a continuous or discontinuous feature, line, ring, or circuit formed in the semiconductor device 300. The bonding ring 350 may be formed by bonding an upper metal ring 352 of the cross-die 100 and a lower metal ring 354 of the lower die 200. For example, the upper metal ring 352 may be formed in the lower surface of the cross-die. A portion 354p of the lower metal ring 354 may be formed in the molding structure 310 (e.g., the lower dielectric layer 310a) and may extend through the dielectric region 302, which is adjacent to a corresponding portion of the upper metal ring 352.

[0130] With respect to the vertical direction (e.g., the stacking direction of the cross die 100 and the lower die 200), the upper metal ring 352 may have a first line thickness T1, the lower metal ring 354 may have a second line thickness T2, the cross die 100 may have a first die thickness DT1, and the lower die 200 may have a second die thickness DT2. The first line thickness T1 may be at least 10% of the first die thickness DT1, and the second line thickness T2 may be at least 10% of the first die thickness DT1 or the second die thickness DT2. For example, in some embodiments, the first line thickness T1 and the second line thickness T2 may each be ≥ For example, the first line thickness T1 and the second line thickness T2 may be in the range of about to approximately In various embodiments, the first die thickness DT1 and the second die thickness DT2 may be the same or different, and the first line thickness T1 and the second line thickness T2 may also be substantially the same thickness. In other embodiments, the first line thickness T1 and the second line thickness T2 may be different thicknesses. In various embodiments, the bus thickness T3 (T1+T2) may be at least 10% of the total die thickness DT3 (DT1+DT2).

[0131] With respect to the horizontal direction perpendicular to the vertical direction, the upper metal ring 352 may have a first width W1, and the lower metal ring 354 may have a second width W2. The first width W1 and / or the second width W2 may be ≥ For example ≥ And in some embodiments, it can be in the range of 0.5μm to 100μm, for example, 1μm to about 40μm. In various embodiments, the first width W1 and / or the second width W2 can be greater than 25% of the first die thickness DT1. In some embodiments, the first width W1 can be greater than the second width W2. In other embodiments, the second width W2 can be greater than the first width W1. In some other embodiments, the first width W1 and the second width W2 can be substantially the same.

[0132] In plan view, the bonding ring 350 may have a generally rectangular structure with rounded corners 351. In plan view, the bonding ring 350 may be disclosed as being adjacent to the peripheral edge of the cross-die 100 so as to provide higher bonding strength in areas where high bonding stresses typically occur. For example, the minimum distance MD1 between the linear portion of the bonding ring 350 and the edge of the cross-die 100 taken in a horizontal direction perpendicular to the vertical stacking direction may range from 0 μm to 30 μm, such as from 1 μm to 20 μm, 2 μm to 15 μm, or 3 μm to 10 μm. For example, the minimum distance may be 0.5 μm, 1 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 17 μm, or 20 μm. In this document, "minimum distance" refers to the shortest distance between two points.

[0133] In some embodiments, rounded corners 351 of bonding ring 350 may be disposed greater than a minimum distance MD1 from an edge of cross-die 100. Specifically, the corner portion of bonding ring 350 is positioned farther from the corner of cross-die 100. Die 100 may reduce the accumulation of bonding stress under the corner of cross-die 100.

[0134] Figures 3A-3E yes Figure 2A and Figure 2B A vertical cross-sectional view of alternative configurations of upper metal ring 352 and lower metal ring 354 having different sizes and overlapping configurations. Figure 3G and Figure 3H yes Figure 2A and Figure 2B A top view of the upper metal ring 352 and the lower metal ring 354 of different size configurations.

[0135] Reference FIG. 3A to FIG. 3F , with respect to the horizontal direction perpendicular to the vertical direction, the upper metal ring 352 may have a first width W1, and the lower metal ring 352 may have a second width W2. The first width W1 and / or the second width W2 may be greater than ≥ For example ≥ And in some embodiments, each width may be in the range from 0.05 μm to 100 μm, for example, from 1 μm to 40 μm. In various embodiments, the first width W1 and / or the second width W2 may be greater than 25% of the first die thickness DT1 (see Figure 2B In some embodiments, the first width W1 may be greater than the second width W2. Figure 3A and Figure 3B In other embodiments, the second width W2 may be greater than the first width W1, such as Figure 3C and Figure 3D In other embodiments, the first width W1 and the second width W2 may be substantially the same, such as Figure 3E and Figure 3F In other words, the surface area of ​​the upper metal ring 352 may be greater than the surface area of ​​the lower metal ring 354, the surface area of ​​the lower metal ring 354 may be greater than the surface area of ​​the upper metal ring 352, or the surface areas of the upper metal ring 352 and the lower metal ring 354 may be substantially the same.

[0136] The vertical overlap between the upper metal ring 352 and the lower metal ring 354 may be at least 10% of the area of ​​the smaller of the upper metal ring 352 and the lower metal ring 354. For example, Figure 3A As shown Figure 3B As shown, the larger upper metal ring 352 may overlap at least 10% of the area of ​​the smaller lower metal ring 354. Figure 3B As shown, the larger upper metal ring 352 may overlap 100% of the area of ​​the smaller lower metal ring. Figure 3C As shown, the larger lower metal ring 354 can overlap 100% of the area of ​​the smaller upper metal ring 352. Figure 3D As shown, the larger lower metal ring 354 may overlap with 10% of the area of ​​the smaller upper metal ring 352. Figure 3E As shown, the upper metal ring 352 and the lower metal ring 354 having the same width may have an area overlap of at least 10%. Figure 3F As shown, the upper metal ring 352 and the lower metal ring 354 having the same width may have a 100% area overlap.

[0137] like Figure 3G As shown, the lower metal ring 354 can have a larger surface area than the upper metal ring 352. The bottom surface of the upper metal ring 352 can contact at least 10%, such as at least 25%, or at least 50% of the top surface of the lower metal ring 354. For example, the bottom surface of the upper metal ring 352 can contact from 10% to 100%, such as from 20% to 90%, from 30% to 80%, from 40% to 70%, or 50% to 60% of the top surface of the lower metal ring 354.

[0138] like Figure 3H As shown, the upper metal ring 352 may have a larger area than the lower metal ring 354. The top surface of the lower metal ring 354 may contact at least 10%, such as at least 25%, or at least 50% of the bottom surface of the upper metal ring 352. For example, the top surface of the lower metal ring 354 may contact from 10% to 100% of the bottom surface of the upper metal ring 352, such as from 20% to 90%, from 30% to 80%, from 40% to 70%, or 50% to 60%.

[0139] Figure 4A-4Dis a top view of semiconductor device 300 according to various embodiments of the present disclosure, illustrating possible horizontal offsets of upper metal ring 352 and lower metal ring 354. Various offsets may be caused by misalignment of cross die 100 over lower die 200 during pick and place operations.

[0140] During the manufacturing process, wafer misalignment may occur. For example, Figure 4A As shown, the cross die 100 can be rotated relative to the desired position on the lower die 200. Figure 4B As shown, the cross-die 100 may be misaligned in the Y direction relative to the ideal position. Figure 4C As shown, the cross die 100 may be misaligned in the X direction relative to the ideal position on the lower die 200. Figure 4D As shown, the cross-die 100 may be misaligned in the X and Y directions relative to an ideal position on the lower die 200 such that the cross-die is diagonally misaligned.

[0141] Various embodiments disclosed herein can accommodate various misalignments across the die 100 and the lower die 200 by providing a bonding ring 350 that can be configured to provide sufficient overlapping surface area between the upper metal ring 352 and the lower metal ring 354. Thus, even though the upper metal ring 352 is not precisely aligned with the lower metal ring 354, the widths of the upper metal ring 352 and the lower metal ring 354 can be designed to provide a minimum overlapping area of ​​at least 10%, even when the die is misaligned as described above. Figure 4A-4D In this manner, for example, the width of the upper metal ring 352 and / or the lower metal ring 354 can be designed to provide sufficient bonding area and corresponding bonding strength even with a typical amount of die misalignment.

[0142] Figure 5A is a top view of a semiconductor device 500 according to various embodiments of the present disclosure. Figure 5B is along Figure 5A The semiconductor device 500 may be similar to the semiconductor device 300. Therefore, only the differences therebetween will be discussed in detail.

[0143] Reference Figure 5A and Figure 5B , semiconductor device 500 may include bonding ring 350 and bonding wire 360. Bonding ring 350 and bonding wire 360 ​​may each be a continuous or discontinuous metal element formed in semiconductor device 300. In a plan view, bonding ring 350 may be a rectangular ring having rounded corners and extending along at least a portion of the perimeter across die 100. Bonding wire 360 ​​may be disposed within bonding ring 350 and may extend along an edge of lower die 200 adjacent dielectric region 302.

[0144] Bonding ring 350 may be formed by bonding upper metal ring 352 and lower metal ring 354. Bonding wire 360 ​​may be formed by bonding upper metal wire 356 formed in cross die 100 and lower metal wire 358 formed in lower die. Bonding wire 360 ​​provides additional structure for cross die 100 to bond to lower die 200 to create a stronger bond and additional alignment points.

[0145] According to various embodiments, portions of the bonding ring 350 and / or the bonding wire 360 ​​may be disposed adjacent to one or more edges of the cross-die 100 and / or one or more edges of the lower die 200 in order to provide greater bonding along the wafer edge, where the highest bonding stresses typically occur. For example, the linear portion of the bonding ring 350 may be disposed at a minimum distance MD1 from the corresponding edge of the cross-die 100, the distance being taken in a horizontal direction perpendicular to the vertical stacking direction of the cross-die 100 and the lower die 200. Additionally, the bonding wire 360 ​​may be disposed within a minimum distance MD2 from the corresponding edge of the lower die 200, which may be an edge of the dielectric region 302. The minimum distances MD1 and MD2 may be the same or different and may be in the range of 0 μm to 30 μm, for example from 1 μm to 20 μm, from 2 μm to 15 μm, or from 3 μm to 10 μm. For example, the minimum distance may be 0.5 μm, 1 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 17 μm or 20 μm.

[0146] The sizes and overlap amounts of the upper metal ring 352, the lower metal ring 354, the upper metal line 356, and the lower metal line 358 may be as described above with respect to Figure 2A-2C The grain thicknesses D1, D2 and D3 may also be as described above.

[0147] Figure 6A-6D 6 is a top view of semiconductor devices 600a-600d according to various embodiments of the present disclosure. The semiconductor devices 600a-600d may be similar to the semiconductor device 300. Therefore, only the differences therebetween will be discussed in detail.

[0148] refer to Fig. 6A , the semiconductor device 600a may include a square cross-die 100 disposed on four square lower dies 200. The cross-die 100 may be located at the center of the lower die 200. In some embodiments, the lower dies 200 may have the same size and shape.

[0149] Reference Figure 6B , the semiconductor device 600b may include a rectangular cross-die 100 disposed on four rectangular lower dies 200. The cross-die 100 may be located at the center of the lower die 200. As shown in FIG. 6B , the lower dies 200 may be of the same size.

[0150] refer to Figure 6C , the semiconductor device 600c may include a square cross-die 100 disposed on four rectangular lower dies 200. The cross-die 100 may be disposed off-center (e.g., offset) relative to the lower die 200. The lower die 200 may have different sizes. In this way, the cross-die 100 may be securely bonded to the lower die 200 having a variety of shapes.

[0151] refer to Fig.6D , the semiconductor device 600d may include a rectangular cross-die 100 disposed on four square lower dies 200. The cross-die 100 may be centered with respect to the lower dies 200. The lower dies 200 may have the same size.

[0152] Therefore, if Figure 6A-6D As shown, the cross-die 100 can be disposed on the lower die 200 having various configurations. For example, the cross-die 100 can be located at the center of one or more lower dies 200 and / or can be offset relative to one or more lower dies 200. In addition, the bonding ring 350 can be designed to firmly bond the cross-die 100 to the corresponding lower die 200. Specifically, the bonding ring 350 can be configured to increase the bonding strength at the edge area of ​​the cross-die 100. In various embodiments, the shape and size of the cross-die 100 can affect the shape and size of the connecting ring. The position of the bonding ring 350 can be determined by the edge of the cross-die. Therefore, for example, the shape and size and placement of the cross-die 100 can determine the position of the bonding ring 350. In some embodiments, as Figure 6C As shown, the bonding ring 350 can be offset from the position of the lower die 200. In some embodiments, the cross-die 100 can be offset from the lower die 200 by any distance as long as the guidelines of metal ring connection area and minimum distance across the die edge are followed.

[0153] Figure 7A-7E is a top view of semiconductor devices 700a-700e according to various embodiments of the present disclosure. The semiconductor devices 700a-700e may be similar to the semiconductor device 300. Therefore, only the differences therebetween will be discussed in detail.

[0154] Reference Fig. 7A , the semiconductor device 700a may include a cross-die 100 disposed on two lower dies 200. The cross-die 100 may include a pentagonal bonding ring 350. The internal angles of the bonding ring 350 may be in the range of less than 180° to 90°. At least one internal angle (e.g., internal angle θ) may be in the range of less than 180° to greater than 90°. The lower dies 200 may have the same or different sizes and / or shapes.

[0155] Reference Figure 7B, the semiconductor device 700b may include a cross-die 100 disposed on two lower dies 200. The cross-die 100 may include an octagonal bonding ring 350. The inner angle (eg, inner angle θ) of the bonding ring 350 may be from less than 180° to greater than 90°. The lower dies 200 may have the same or different sizes and / or shapes.

[0156] Reference Figure 7C , the semiconductor device 700c may include a cross-die 100 disposed on two lower dies 200. The cross-die 100 may include a rectangular bonding ring 350. The inner angle of the bonding ring 350 may be 90°. The lower dies 200 may have the same or different sizes and / or shapes.

[0157] Reference Fig.7D , the semiconductor device 700d may include a cross-die 100 disposed on three lower dies 200. The cross-die 100 may include a polygonal bonding ring 350. The inner angle of the bonding ring 350 may be, for example, 90°. The lower dies 200 may have different sizes and / or shapes. The bonding ring 350 may extend along the gaps between the lower dies 200 to provide increased bonding strength for the gaps between adjacent dies 200, where high bonding stress and / or weak bonding typically occurs.

[0158] Reference Fig. 7E , the semiconductor device 700e may include a cross-die 100 disposed on two lower dies 200. The cross-die 100 may include a rectangular bonding ring 350 with rounded corners. Each rounded corner may have a radius of curvature r greater than 0 and less than half the length of the adjacent shortest linear portion of the bonding ring 350. The lower dies 200 may have the same or different sizes and / or shapes.

[0159] Figure 7A-7E The bonding ring shape shown can provide a wide process window. For example, the shape of the bonding ring can be configured to allow the bonding ring to be routed around existing die elements, such as bonding pads, TSV structures, sealing rings, etc. In addition, the bonding ring can be routed around areas that may affect wafer edge pattern density, bonding ring deposition, or CMP thickness uniformity. In some embodiments, the bonding ring can be designed to provide a strong bond even when the cross-die 100 or the lower die includes manufacturing defects such as chipping or cracks due to, for example, die cutting, by including a routed bonding ring around the damaged area. Thus, a bonding ring can be formed. Figure 7A-7E The various angles and shapes of the bonding ring 350 are shown to avoid manufacturing defects, thereby ensuring a stable bonding connection between the cross die 100 and the lower die 200 .

[0160] Figure 8A-8D8 is a top view of semiconductor devices 800a-800d according to various embodiments of the present disclosure. The semiconductor devices 800a-800d may be similar to the semiconductor device 300. Therefore, only the differences therebetween will be discussed in detail. The semiconductor devices 800a-800d may include bonding rings and / or wires disposed at various locations where high bonding stress may occur.

[0161] Reference Fig. 8A , the semiconductor device 800a may include a cross-die 100 disposed on four lower dies 200. The cross-die 100 may include a rectangular bonding ring 350 with rounded corners, a first bonding wire 360a, and a second bonding wire 360b. The bonding ring 350 may extend along the periphery of the cross-die 100. The first bonding wire 360a may be a line extending along the opposite side of the first portion 302a of the die gap, and the second bonding wire 360b may extend along the opposite side of the second portion 302b of the die gap. In some embodiments, the first bonding wire 360a and the second bonding wire 360b may extend in a vertical direction.

[0162] refer to Figure 8B , the semiconductor device 800b may include a cross-die 100 disposed on six lower dies 200a-200f. The cross-die 100 may include a bonding ring 350, a first bonding wire 360a, a second bonding wire 360b, and a third bonding wire 360c. The bonding ring 350 is a rectangular ring having rounded corners and extending along the periphery of the cross-die 100. The first bonding wire 360a, the second bonding wire 360b, and the third bonding wire 360c may extend along one or more edges of adjacent lower dies 200b, 200c, and 200e. Specifically, the edges of the lower dies 200b, 200c, and 200e that overlap with the cross-die 100 may be farther away from the corresponding edges of the cross-die 100 than the overlapping edges of the lower dies 200a, 200d, and 200f. As such, the first bonding wire 360a, the second bonding wire 360b, and the third bonding wire 360c may provide enhanced bonding strength along the corresponding portions of the dielectric region 302 formed between the lower dies 200. Specifically, the first bonding wire 360a, the second bonding wire 360b, and the third bonding wire 360c may be disposed over the lower dies 200b, 200c, and 200e having edges farther than the minimum distance MD2 from the bonding ring 350 to improve the bonding strength at the edges of the lower dies 200b, 200c, and 200e.

[0163] Reference Figure 8C, the semiconductor device 800c may include a cross-die 100a, a second die 100b, and a third die 100c disposed on four lower dies 200. The cross-die 100a may include a bonding ring 350 and a bonding wire 360. The bonding ring 350 may be a rectangular ring having rounded corners and extending along the periphery of the cross-die 100. The linear segment of the bonding ring 350 may be disposed within a minimum distance MD1 of the edge of the cross-die 100a.

[0164] The second die 100b may include a rectangular bonding ring 350 with rounded corners. The linear segment of the bonding ring 350 may be disposed within a minimum distance MD1 of an edge of the second die 100b and may also be disposed within a minimum distance MD2 of an edge of the corresponding lower die 200.

[0165] The third die 100c may include a rectangular bonding ring 350 with rounded corners. The bonding ring 350 may vertically overlap the dielectric region 302. The linear segment of the bonding ring 350 may be disposed at a minimum distance MD1 from the edge of the third die 100c, or may be disposed at a minimum distance MD2 from the edge of the corresponding lower die 200.

[0166] Reference Fig.8D , the semiconductor device 800d may include a cross-die 100a and a second die 100b disposed on three lower dies 200. The cross-die 100a may include a first bonding ring 350a and a second bonding ring 350b. The first bonding ring 350a and the second bonding ring 350b may be disposed on opposite sides of the dielectric region 302. The linear segments of the first bonding ring 350a and the second bonding ring 350b may be disposed within a minimum distance MD1 of an edge of the cross-die 100a, or within a minimum distance MD2 of an edge of the corresponding lower die 200.

[0167] The second die 100b may include a first bonding ring 350a and a second bonding ring 350b, which may vertically overlap the dielectric region 302. The linear segments of the first bonding ring 350a and the second bonding ring 350b may be disposed within a minimum distance MD1, within a minimum distance MD2 across the edge of the die 100a, or within a minimum distance MD2 of the edge of the corresponding lower die 200.

[0168] Reference Figure 8A-8D The bonding ring can have various configurations and can be designed to enhance bonding strength in areas where bonding problems typically occur, such as areas of high bonding stress and / or areas where the lowest bonding strength typically occurs, such as across the edge regions of the die. For example, the bonding ring can be flexibly designed to provide enhanced bonding strength in areas that are most likely to experience bonding stress and / or weak bonding due to die stacking structure, differences in die thickness, area of ​​dielectric regions, die metal density, etc. In some embodiments, see e.g. Fig.8D , the flexibility of the shape, size and configuration of the bonding ring 350 can position the bonding ring 350 completely within the die gap region. Such an embodiment can improve the bonding of the cross-die 100 to the die gap. In other embodiments, adding a bonding wire 360 ​​together with the bonding ring 350 can provide an enhanced bonding between the cross-die 100 and the lower die 200.

[0169] Figure 9A-9F is a cross-sectional view showing how the minimum distances MD1 and MD2 may be measured according to various embodiments of the present disclosure. Fig. 9A and Fig. 9B , a minimum distance MD1 may be measured between the nearest portion of the bonding ring 350 and the edge across the die 100. For example, the minimum distance MD1 may be measured between the upper metal ring 352 and the adjacent edge across the die 100, or between the lower metal ring 354 and the adjacent edge across the die 100.

[0170] like Fig. 9C and Fig.9D As shown, a minimum distance MD2 may similarly be measured between a nearest portion of the bond wire 360 ​​and an edge of an adjacent edge of the lower die 200 (eg, an edge of the dielectric region 302 ). Fig.9E 3 shows a measurement of the minimum distance MD2 in an embodiment where the joining ring 350 is disposed above the dielectric region 302, for example with respect to Figure 8C and Fig.8D The die 100 c and the die 100 e are bonded to the ring 350 . Fig.9F The same portion of the distance engagement ring 350 is shown (such as relative to Figure 8C The minimum distances MD1 and MD2 of the bonding ring 350 of the second die 100 b are measured.

[0171] According to various embodiments, the minimum distance MD2 may also be measured in a similar manner with respect to the bonding wire 360. For example, the minimum distance MD2 may be measured from the closer one of the upper metal line 356 and / or the lower metal line 358 to the corresponding edge of the adjacent lower die 200.

[0172] Figures 10A-10D are top views of semiconductor devices 1000 a - 1000 d according to various embodiments of the present disclosure. Fig.10E yes Fig. 10D Magnified view of the P1 section. Fig.10F -H shows Fig.10EThe semiconductor device 1000a may be similar to the semiconductor device 800a, the semiconductor device 1000b may be similar to the semiconductor device 700d, the semiconductor device 1000c may be similar to the semiconductor device 800b, and the semiconductor device 1000d may be similar to the semiconductor device 600a. Therefore, only the differences therebetween will be discussed in detail.

[0173] Reference Fig. 10A , the semiconductor device 1000a may include a cross-die 100 disposed on four lower dies 200. The semiconductor device 1000a may also include a bonding ring 350, a first bonding wire 360a, and a second bonding wire 360b. The bonding ring 350 is a continuous rectangular ring extending along the periphery of the cross-die 100. The first bonding wire 360a and the second bonding wire 360b may be discontinuous lines extending along the edge of the lower die 200 adjacent to the gap between the lower dies 200.

[0174] refer to Fig. 10B , the semiconductor device 1000 b may include a cross-die 100 disposed on four lower dies 200 . The semiconductor device 1000 b may also include a discontinuous polygonal bonding ring 350 extending along an edge of the lower die 200 adjacent to one or more gaps between the lower dies 200 .

[0175] Reference Fig. 10C , the semiconductor device 1000c may include a cross-die 100 disposed on six lower dies 200. The semiconductor device 1000b may also include a bonding ring 350, a first bonding wire 360a, a second bonding wire 360b, and a third bonding wire 360c. The bonding ring 350 is a continuous rectangular ring extending along the periphery of the cross-die 100. The first bonding wire 360a and the second bonding wire 360b may be discontinuous lines extending along the edge of the lower die 200 adjacent to one or more gaps between the lower dies 200.

[0176] Reference Fig. 10D , the semiconductor device 1000d may include a square cross-die 100 disposed on four square lower dies 200. The cross-die 200 may include a discontinuous bonding ring 350 having rounded corners.

[0177] like Fig.10E As shown, the discontinuous joint ring 350 may include a discontinuous upper metal ring 352 and a discontinuous lower metal ring 354. The segments of the upper metal ring 352 and the lower metal ring 354 may be aligned to completely or almost completely overlap each other and may have the same segment pattern.

[0178] like Figure 10F-10HAs shown, the segments of the upper metal ring 352 and the lower metal ring 354 may be misaligned and / or may have different patterns, so that the overlapping area can be reduced compared to the precisely aligned die. However, as long as the overlapping area is at least 10%, sufficient bonding strength can be obtained, as described above with respect to Figure 3A-Figure 3F As discussed. In addition, the discontinuous bonding ring structure can advantageously reduce the local metal density of the die, which may otherwise complicate metal plating and / or CMP. In some embodiments, the discontinuous bonding ring structure can provide improved bonding strength compared to fusion bonding alone. Dense metal areas may affect copper plating and CMP performance, which may result in poor U% of the bonding surface. Therefore, the discontinuous bonding ring can reduce the local metal density on the edge of the die and can also provide stronger die bonding force than pure fusion bonding.

[0179] Fig.11 is a flow chart of a method of forming a semiconductor device according to various embodiments of the present disclosure. Figures 12A-12F It is shown Fig.11 A cross-sectional diagram of the method's operation.

[0180] Reference Fig.11 and Fig. 12A In operation 1, a lower die 200 may be disposed on a carrier 52. A lower dielectric layer 310a may be deposited on the lower die 200. For example, the resulting structure may be planarized by CMP to remove excess dielectric material.

[0181] Reference Fig.11 and Fig. 12B , in operation 2, you can etch Fig. 12A The bonding trench 355 may be formed by patterning the structure of the lower dielectric layer 310a to form the bonding trench 355. For example, the structure may be etched using a patterned photoresist layer and a wet or dry etching process. The bonding trench 355 may extend through the lower dielectric layer 310a in the grain gap between the lower grains 200.

[0182] Reference Fig.11 and Fig. 12C , in operation 3, a lower metal ring 354 may be formed in the bonding trench 355. In some embodiments, a lower metal line 358 may also be formed in the corresponding bonding trench 355. Specifically, a metal such as copper or a copper alloy may be deposited in the bonding trench 355 using any suitable deposition method. Excess metal may be removed by CMP or a similar process to planarize the structure and form the lower metal ring 354 and / or the lower metal line 358.

[0183] Reference Fig.11 and Fig.12DIn operation 4, an upper metal ring 352 may be formed in the cross-die 100 disposed on the carrier 50. An upper metal line 356 may also be optionally formed in the cross-die 100. The upper metal ring 352 and the upper metal line 356 may be formed by etching, deposition, and planarization processes as discussed above with respect to the lower metal ring 354. An upper dielectric layer 310b may be deposited around the cross-die 100 using any suitable deposition process. Operation 4 may also include planarizing the upper dielectric layer 310b using, for example, CMP. Referring to FIG. Fig.11 and Fig.12E Operation 5 may include aligning the cross die 100 and the lower die 200 such that the upper metal ring 352 and the upper metal line 356 are aligned with the lower metal ring 354 and the lower metal line 358 .

[0184] Reference Fig.11 and Fig.12E In operation 6, the cross die 100 is bonded to the lower die 200. For example, the bonding may include a hybrid bonding process, in which the upper metal ring 352 and the lower metal ring 354 are fused to form the bonding ring 350 and / or the upper metal line 356 and the lower metal line 358 are fused to form the bonding line 360. The bonding process may also include bonding the lower dielectric layer 310a and the upper dielectric layer 310b to form the molding structure 310.

[0185] Reference Fig.11 and Fig.12F In operation 7 , the carrier 52 may be removed, and a protection layer 226 may be formed on the lower die 200 , and a solder bump 320 may be formed on the protection layer 226 to complete the semiconductor device 300 .

[0186] With reference to all the drawings and according to various embodiments of the present disclosure, a semiconductor device 300 is provided, which includes: at least two lower dies 200 separated by a dielectric region 302; a cross-die 100 vertically stacked on the lower dies 200 and the dielectric region 302; a molding structure 310 filling the dielectric region 302 and laterally surrounding the side surfaces of the lower dies 200 and the cross-die 100; and a bonding ring 350 connecting the cross-die 100 to the lower die 200, the bonding ring including: an upper metal ring 352 formed in the bottom surface of the cross-die 100; and a lower metal ring 354 formed in the top surface of the lower die 200 and extending through the molding structure 310 in the dielectric region 302, wherein the lower metal ring 354 is bonded to the upper metal ring 352.

[0187] In one embodiment, the minimum distance between at least a linear portion of the bonding ring 350 and an adjacent edge of the cross-die 100 may be greater than 0 micrometers (μm) and may be less than 20 μm. In one embodiment, the bottom surface of the upper metal ring 352 contacts at least 10% of the top surface of the lower metal ring 354; or the top surface of the lower metal ring 354 contacts at least 10% of the bottom surface of the upper metal ring 352. In one embodiment, the bottom surface of the upper metal ring 352 may be greater than the top surface of the upper metal ring 352; or the top surface of the lower metal ring 354 may be greater than the bottom surface of the lower metal ring 354. In one embodiment, the minimum distance between at least a portion of the bonding ring 350 and an edge of the dielectric region 302 may be greater than 0 micrometers (μm) and less than 20 μm. In one embodiment, the thickness of the upper metal ring 352 may be at least 10% of the thickness of the cross-die 100 relative to the vertical direction; and the thickness of the lower metal ring 354 may be at least 10% of the thickness of the lower die 200 relative to the vertical direction. In one embodiment, the thickness of the upper metal ring 352 may be at least And the thickness of the lower metal ring 354 can be at least In one embodiment, the bonding ring 350 may be discontinuous. In one embodiment, the bonding ring 350 may be rectangular, square or polygonal. In one embodiment, the cross-die 100 includes a memory chip, a logic chip, an analog chip, a radio frequency chip or an integrated passive device chip; at least one of the at least two lower dies 200 includes an interposer 20 or a dummy die; the lower metal ring 354 and the upper metal ring 352 are made of copper or copper alloy; the cross-die 100 is fused or hybrid-bonded to the at least two lower dies 200.

[0188] According to another aspect of the present invention, a semiconductor device is provided, which includes: two lower dies 200 separated by a dielectric region 302; a cross-die 100 vertically stacked on the two lower dies 200 and the dielectric region 302; a lower dielectric layer 310a filling the dielectric region 302 and surrounding the side surface of the lower dies 200; an upper dielectric layer 310b laterally surrounding the side surface of the cross-die 100; a bonding ring 350 formed on the bottom surface of the cross-die 100, the top surface of the two lower dies 200, and the top surface of the lower dielectric layer 310a in the dielectric region to connect the cross-die 100 to the two lower dies 200; and a bonding wire 360, which is arranged inside the bonding ring 350 and connects the cross-die 100 to the two lower dies 200, wherein a portion of the bonding ring 350 is arranged in the lower dielectric layer 310a and extends through the dielectric region 302. The bonding ring 350 connects the cross-die 100 to the lower die 200, and the bonding ring 350 includes: an upper metal ring 352 formed on the bottom surface of the cross-die 100; and a lower metal ring 354 formed in the top surface of the lower die 200 and extending through the dielectric region 302, wherein the lower metal ring 354 is bonded to the upper metal ring 352; wherein the width of at least one of the upper metal ring 352 and the lower metal ring 354 in the horizontal direction is greater than 25% of the height H1 of the cross-die 100 in the vertical direction.

[0189] In one embodiment, the semiconductor device may further include a bonding wire 360 ​​disposed inside the bonding ring 305 and connecting the cross-die 100 to at least two lower dies 200, the bonding wire 360 ​​including: a metal wire 356 formed on the bottom surface of the cross-die 100; and a lower metal wire 358 formed in the top surface of the lower die 200, wherein each lower metal wire 358 may be bonded to a corresponding upper metal wire 356. In one embodiment, the bonding wire 360 ​​may include: a first bonding wire 360a extending in a first direction along opposite sides of the first portion of the dielectric region 302; and a second bonding wire 360b extending in a second direction perpendicular to the first direction along opposite sides of the second portion of the dielectric region 302. In one embodiment, the minimum distance between at least a portion of the bonding ring 350 and the edge of the cross-die 100 may be greater than 0 micrometers (μm) and less than 20 μm; and the minimum distance between at least a portion of each bonding wire 360 ​​and the dielectric region 302 may be greater than 0 micrometers (μm) and less than 20 μm. In one embodiment, the bottom surface of the upper metal line 356 contacts at least 10% of the top surface of at least two lower metal lines 358; or the top surface of the lower metal line 358 contacts at least 10% of the bottom surface of the upper metal line 356. In one embodiment, each bonding wire 360 ​​overlaps a single lower die 100 and does not extend through the dielectric region 302. In one embodiment, the bonding ring 350 may include: an upper metal ring 352 formed in the bottom surface of the cross-die 100; and a lower metal ring 354 formed in the top surface of the lower die 200 and extending through the dielectric region 302, wherein the lower metal ring 354 is bonded to the upper metal ring 352; and at least one of the upper metal ring 352 and the lower metal ring 354 has a width in the horizontal direction greater than 25% of the height of the lower die 100 in the vertical direction.

[0190] According to another aspect of the present invention, a semiconductor device 500 is provided, which includes: a lower die 200 separated by a dielectric region 302; a cross-die 100 vertically stacked on the lower die 200 and the dielectric region 302; a lower dielectric layer 310a filling the dielectric region and laterally surrounding the side surfaces of at least two lower die 200; an upper dielectric layer 310b laterally surrounding the side surfaces of the cross-die 100; a molding structure 310 filling the dielectric region 302 and surrounding the side surfaces of the lower die 200 and the cross-die 100; a first bonding ring 350a connecting the cross-die 100 to the lower die 200, and a second bonding ring 350b connecting the cross-die 100 to the lower die 200, wherein: the first bonding ring 350a and the second bonding ring 350b can be set at opposite positions; or, the first bonding ring 350a and the second bonding ring 350b can be set in the dielectric region 302 and do not vertically overlap with the lower die 200. In some embodiments, the first bonding ring 350a includes: an upper metal ring 352 formed in the bottom surface of the cross-die 100; and a lower metal ring 354 formed in the top surface of the lower die 200 or in the die gap, wherein the lower metal ring 354 is bonded to the upper metal ring 350. In some embodiments, a minimum distance MD2 between at least a portion of the first bonding ring 350a and / or the second bonding ring 350B and an edge of the cross-die 100 is greater than 0 micrometers (μm) and less than 20 μm.

[0191] In one embodiment, the first bonding ring 350a may be disposed above the dielectric region 302, and the lower metal ring 354 may be formed only in the dielectric region 302. In one embodiment, the semiconductor device 500 may further include a second bonding ring 350b connecting the cross-die 100 to the lower die 200, wherein: In one embodiment, the semiconductor device 500 may further include an upper dielectric layer 310b disposed on the lower dielectric layer 310a and laterally surrounding the cross-die 100.

[0192] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: at least two lower dies separated by a dielectric region; a cross die, vertically stacked on at least the at least two lower dies and the dielectric region; a molding structure filling the dielectric region and laterally surrounding the side surfaces of the at least two lower dies and the cross-die; as well as a bonding ring, connecting the cross die to the at least two lower dies, the bonding ring comprising: an upper metal ring formed on a bottom surface of the cross-die; as well as A lower metal ring is formed in the top surfaces of the at least two lower dies and extends through the molding structure in the dielectric region, wherein the lower metal ring is bonded to the upper metal ring.

2. The semiconductor device according to claim 1, wherein: A bottom surface of the upper metal ring contacts at least 10% of a top surface of the lower metal ring; or A top surface of the lower metal ring contacts at least 10% of a bottom surface of the upper metal ring.

3. The semiconductor device according to claim 1, wherein: The bottom surface of the upper metal ring is larger than the top surface of the upper metal ring; or The top surface of the lower metal ring is larger than the bottom surface of the lower metal ring.

4. The semiconductor device according to claim 1 or 2, wherein: With respect to a vertical direction, a thickness of the upper metal ring is at least 10% of a thickness of the cross-die; and With respect to the vertical direction, a thickness of the lower metal ring is at least 10% of a thickness of the lower die.

5. The semiconductor device according to claim 1, wherein The engagement ring is discontinuous.

6. The semiconductor device according to claim 1, wherein: The cross-die includes a memory chip, a logic chip, an analog chip, a radio frequency chip or an integrated passive device chip; At least one of the lower dies includes an interposer or a dummy die; The lower metal ring and the upper metal ring include copper or a copper alloy; and The cross-die is fusion-bonded or hybrid-bonded to the lower die.

7. A semiconductor device, characterized in that: include: two lower dies separated by a dielectric region; a cross die, vertically stacked on the two lower dies and the dielectric region; a lower dielectric layer filling the dielectric region and laterally surrounding the side surfaces of the two lower dies; an upper dielectric layer laterally surrounding the side surface of the cross-die; a bonding ring formed on a bottom surface of the cross-die, a top surface of the lower die, and a top surface of the lower dielectric layer in the dielectric region to connect the cross-die to the two lower dies; as well as A plurality of bonding wires are disposed inside the bonding ring and connect the cross-die to the two lower dies, wherein a portion of the bonding ring is disposed in the lower dielectric layer and extends across the dielectric region.

8. The semiconductor device according to claim 7, wherein: Further comprising a plurality of bonding wires disposed inside the bonding ring and connecting the cross die to the two lower dies, the bonding wires comprising: a plurality of upper metal lines formed on the bottom surface of the cross-die; and A plurality of lower metal lines are formed in the top surface of the lower die, wherein each lower metal line is bonded to a corresponding one of the upper metal lines.

9. The semiconductor device according to claim 7, wherein: The mating ring comprises: an upper metal ring formed on a bottom surface of the cross-die; and a lower metal ring formed in a top surface of the lower die and extending through the dielectric region, wherein the lower metal ring is bonded to the upper metal ring; and A width of at least one of the upper metal ring and the lower metal ring in a horizontal direction is greater than 25% of a height of the cross-die in a vertical direction.

10. A semiconductor device, characterized in that: include: a plurality of lower dies separated by a dielectric region; a cross die vertically stacked on the lower die and the dielectric region; a molding structure filling the dielectric region and surrounding the side surfaces of the lower die and the cross die; a first bonding ring connecting the cross-die to the lower die; and a second bonding ring connecting the cross die to the lower die, in: The first joining ring and the second joining ring are disposed on both sides of the dielectric region; or The first bonding ring and the second bonding ring are disposed in the dielectric region and do not vertically overlap with the lower die.

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