Gallium nitride semiconductor device

Abstract

The utility model discloses a gallium nitride semiconductor device which comprises a semiconductor stack, a gate electrode, a source electrode contact, a drain electrode contact, a dielectric layer and a passivation layer. Wherein the gate electrode, the source electrode and the drain electrode are arranged on the semiconductor laminated layer; the dielectric layer is arranged on the semiconductor laminated layer in a filling manner and is respectively in contact with the gate electrode, the source electrode and the drain electrode in an abutting manner, and one side, far away from the semiconductor laminated layer, of the dielectric layer is lower than one side, far away from the semiconductor laminated layer, of the source electrode and / or the drain electrode; the passivation layer comprises a first passivation layer and a second passivation layer which are sequentially arranged in a stacked mode in the direction from the semiconductor stack to the dielectric layer, and the first passivation layer is arranged in a containing groove formed by the dielectric layer, the source electrode contact and / or the drain electrode contact in a filling mode. And the second passivation layer covers the first passivation layer, the source electrode contact and the drain electrode contact and is far away from one side of the semiconductor lamination layer. The gallium nitride semiconductor device is relatively high in water vapor erosion resistance, reliability and service life.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, in particular to gallium nitride semiconductor devices. Background Art

[0002] Power semiconductor devices involve high voltage, high current and high power, and are the core and foundation of energy conservation and emission reduction. Gallium nitride is a typical representative of the third-generation semiconductor materials, with excellent characteristics such as large bandgap width, high breakdown electric field and high saturation electron drift rate. It can be used in high frequency, high voltage, high power, low power consumption and miniaturization occasions, and has broad application prospects in electric vehicles, laser radars, general power equipment and data centers.

[0003] During the packaging process, reliability testing and actual operation, GaN semiconductor devices are often placed in harsh environments such as high temperature and high pressure or high and low temperature cycles. Water vapor will gradually invade the device, and the invasion rate is affected by the ambient temperature. After the water vapor diffuses to the surface of the device, it is electrolyzed under the action of a high electric field to form hydroxide ions and hydrogen ions. The ions move toward the two poles under the action of the electric field to form acid or alkaline solutions with different pH values, thereby promoting the electrochemical migration of metal ions and device failure.

[0004] In related technologies, in order to reduce the risk of water vapor erosion of devices, a passivation layer is usually set on the surface of the dielectric layer and metal layer on the top of the device to improve the stability of the device. In the high temperature and high pressure test environment, the thermal expansion coefficients of GaN semiconductor devices are mismatched between the plastic packaging material, the dielectric layer and the metal layer, which will lead to large tensile stress, resulting in cracks or metal deformation in the passivation layer structure, thereby reducing the device's ability to resist water vapor erosion during packaging or application, affecting its life and reliability. Utility Model Content

[0005] The present application provides a gallium nitride semiconductor device, which can alleviate the diffusion of tensile stress generated by the gallium nitride semiconductor device in a high temperature and high pressure environment, improve the gallium nitride semiconductor device's ability to resist water vapor erosion, and thus improve reliability and service life.

[0006] In order to solve the above technical problems, the present application provides a gallium nitride semiconductor device on one hand, which includes a semiconductor stack, a gate electrode, a source electrode, a drain electrode, a dielectric layer and a passivation layer. In which, a two-dimensional electron gas is generated in the semiconductor stack; the gate electrode, the source electrode contact and the drain electrode contact are arranged on the semiconductor stack; the dielectric layer is filled and arranged on the semiconductor stack, and is in contact with the gate electrode, the source electrode contact and the drain electrode contact, and the side of the dielectric layer away from the semiconductor stack is lower than the side of the source electrode contact and / or the drain electrode contact away from the semiconductor stack; the passivation layer includes a first passivation layer and a second passivation layer stacked in sequence along the direction from the semiconductor stack to the dielectric layer, the first passivation layer is filled and arranged in the receiving groove formed by the dielectric layer, the source electrode contact and / or the drain electrode contact, and the second passivation layer is covered and arranged on the first passivation layer, the source electrode contact and the drain electrode contact away from the semiconductor stack.

[0007] In some embodiments of the present application, the gallium nitride semiconductor device is provided with a first passivation layer filled in a receiving groove formed by a dielectric layer, a source electrode contact and / or a drain electrode contact, so that a second passivation layer can relatively flatly cover the first passivation layer, the source contact and the drain contact, thereby alleviating the diffusion of tensile stress generated in the gallium nitride semiconductor device under a high temperature and high pressure environment, improving the gallium nitride semiconductor device's ability to resist water vapor erosion, and improving reliability and service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0009] Figure 1 is a schematic diagram of a gallium nitride semiconductor device in some embodiments of the present application;

[0010] Figure 2 is a schematic diagram of a semiconductor stack in some embodiments of the present application;

[0011] Figure 3 is a schematic diagram of a semiconductor stack in some embodiments of the present application;

[0012] Figure 4 is a schematic diagram of a receiving tank in some embodiments of the present application;

[0013] Figure 5 is a schematic diagram of a gallium nitride semiconductor device in some embodiments of the present application;

[0014] Figure 6is a schematic diagram of a receiving tank in some embodiments of the present application;

[0015] Figure 7 is a schematic diagram of a gallium nitride semiconductor device in some embodiments of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0017] See also Figure 1 , Figure 1 Schematic diagram of a gallium nitride semiconductor device in some embodiments of the present application. The gallium nitride semiconductor device 10 of the present application is an enhanced gallium nitride chip, including a semiconductor stack 101, a gate electrode 102, a source electrode contact 103, a drain electrode contact 104, a dielectric layer 105 and a passivation layer 106.

[0018] In some embodiments, see Figure 1 , a two-dimensional electron gas (Two-Dimensional Electron Gas, 2DEG); a gate electrode 102, a source electrode contact 103 and a drain electrode contact 104 are arranged on the semiconductor stack 101; a dielectric layer 105 is filled and arranged on the semiconductor stack 101, and is respectively in contact with the gate electrode 102, the source electrode contact 103 and the drain electrode contact 104, and a side of the dielectric layer 105 away from the semiconductor stack 101 is lower than a side of the source electrode 103 and / or the drain electrode 104 away from the semiconductor stack 101; the passivation layer 106 includes a first passivation layer 1061 and a second passivation layer 1062 which are sequentially stacked in a direction from the semiconductor stack 101 to the dielectric layer 105, the first passivation layer 1061 is filled and arranged in a receiving groove formed by the dielectric layer 105, the source electrode contact 103 and / or the drain electrode contact 104, and the second passivation layer 1062 is covered and arranged on the first passivation layer 1061, the source electrode contact 103 and the drain electrode contact 104 on a side away from the semiconductor stack 101.

[0019] In some embodiments, the semiconductor stack 101 is also referred to as an epitaxial structure of the gallium nitride semiconductor device 10 .

[0020] See also Figure 2 , Figure 2Schematic diagram of a semiconductor stack 101 in some embodiments of the present application. The semiconductor stack 101 includes a substrate 201 and an epitaxial layer 202 disposed on the substrate 201, wherein the epitaxial layer 202 includes a semiconductor composite structure that generates a two-dimensional electron gas, and the semiconductor composite structure includes at least a nucleation layer 2021, a buffer layer 2022, a channel layer 2023, and a potential stack 2024 stacked in sequence.

[0021] In some embodiments, the substrate 201 is made of, but not limited to, silicon (Si), doped silicon (doped Si), silicon carbide (SiC), silicon germanium (SiGe), gallium arsenide (GaAs), sapphire and other materials.

[0022] In some embodiments, the nucleation layer 2021 may be made of materials including but not limited to aluminum nitride or any alloy thereof. The nucleation layer 2021 is disposed between the substrate 201 and the buffer layer 2024 , and the nucleation layer 2021 may be configured as a transition layer to avoid mismatching between the substrate 201 and the buffer layer 2022 .

[0023] In some embodiments, the buffer layer 2022 includes but is not limited to nitrides, such as aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN) or a combination thereof. The buffer layer 2022 can be disposed between the substrate 201 and the channel layer 2023. The buffer layer 2022 can reduce the lattice mismatch and thermal mismatch between the substrate 201 and the channel layer 2023, thereby reducing defects caused by the mismatch.

[0024] In some embodiments, the channel layer 2023 is a gallium nitride channel layer, and the barrier stack 2024 is a gallium nitride aluminum barrier stack.

[0025] In one application scenario, the thickness of the GaN channel layer can be in the range of 50 to 300 nm, and the doping concentration of the nitride is in the range of 1017 to 1021 cm -3 range; the thickness of the gallium nitride aluminum barrier layer can be in the range of 1 to 50 nm, and the concentration of the aluminum element is in the range of 1 to 100%.

[0026] A heterojunction structure is formed at the contact surface between the channel layer 2023 and the barrier stack 2024. The heterojunction structure is a gallium nitride heterojunction field effect transistor composed of gallium nitride and gallium aluminum nitride.

[0027] In addition, the material of the potential stack 2024 has a wider band gap than the material of the channel layer 2023. When reaching equilibrium, the interface of the heterojunction will bend, resulting in discontinuity of the conduction band and the valence band, and a triangular potential well will be formed at the heterojunction interface. Since the electrons in the conduction band on the side of the channel layer 2023 are lower than the Fermi level, a large number of electrons accumulate in the triangular potential well. At the same time, one side of the potential stack 2024 is a high potential barrier, making it difficult for electrons to cross the potential well, and the lateral movement of electrons is limited to the two-dimensional electron gas at this interface.

[0028] That is, the heterojunction structure between the channel layer 2023 and the barrier stack 2024 includes a layer of high-mobility electrons, namely, a two-dimensional electron gas. The two-dimensional electron gas can form a channel between the drain electrode contact 104 and the source electrode contact 103, and the two-dimensional electron gas has a high electron mobility and conductivity. When a voltage is applied to the drain electrode contact 104 and the source electrode contact 103, the two-dimensional electron gas can effectively conduct electrons, so that the gallium nitride semiconductor device 10 can have excellent performance. Specifically, for a normally-on gallium nitride semiconductor device, when the voltage between the gate and the source is zero, a 2DEG channel already exists between the drain and the source, and the normally-on gallium nitride semiconductor device is turned on. When the voltage between the gate and the source is less than zero, the 2DEG channel between the drain and the source is disconnected, and the normally-on gallium nitride semiconductor device is turned off. For a normally-off gallium nitride semiconductor device, when the voltage between the gate and the source is greater than zero, a 2DEG channel between the drain and the source is formed, and the normally-off gallium nitride semiconductor device is turned on.

[0029] In some embodiments, the buffer layer 2022 , the channel layer 2023 , and the barrier stack 2024 may be formed by metal organic chemical vapor deposition (MOCVD) epitaxial growth or other appropriate deposition steps.

[0030] In some embodiments, see Figure 1 The passivation layer 106 includes but is not limited to materials such as Si, O, and N. The passivation layer 106 can be formed by atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), high density plasma (HDP) CVD, spin coating, and sputtering.

[0031] In some embodiments, after the passivation layer 106 is formed, a surface of the passivation layer 106 may be processed by chemical-mechanical planarization (CMP).

[0032] In some embodiments, before disposing the gate electrode 102 , the source electrode contact 103 , and the drain electrode contact 104 on the semiconductor stack 101 , a P-type nitride gate layer needs to be disposed on the semiconductor stack 101 .

[0033] In one application scenario, the P-type nitride gate layer is a P-GaN gate. Specifically, a gate pattern can be formed by processes such as silicon nitride masking, photoresist coating, photolithography development, and inductively coupled plasma etching (ICP), thereby forming a P-GaN gate.

[0034] In some embodiments, the gate electrode 102 includes a gate metal and a P-GaN gate, wherein the gate metal includes but is not limited to elements such as titanium, aluminum, nickel, gold, tantalum, palladium, and alloys and / or compounds thereof. The gate metal can be prepared by vacuum metal evaporation, sputtering, and other preparation processes after forming a gate pattern through photoresist coating, photolithography, and development processes.

[0035] In some embodiments, the source electrode contact 103 corresponds to a source metal, and the source metal includes but is not limited to elements such as titanium, aluminum, nickel, gold, tantalum, and alloys and / or compounds containing the above metal systems. The source pattern can be formed by photoresist coating, photolithography, and development processes, and then the source metal can be prepared by vacuum metal evaporation, sputtering, and other preparation processes.

[0036] In some embodiments, the drain electrode contact 104 corresponds to a drain metal, and the drain metal includes but is not limited to elements such as titanium, aluminum, nickel, gold, tantalum, and alloys and / or compounds containing the above metal systems. The drain pattern can be formed by photoresist coating, photolithography, and development processes, and then the drain metal can be prepared by vacuum metal evaporation, sputtering, and other preparation processes.

[0037] In some embodiments, source metal deposition and drain metal deposition are performed simultaneously and after gate metal deposition is completed. That is, the source electrode contact 103 and the drain electrode contact 104 are provided simultaneously and after the gate electrode 102 is provided.

[0038] It is worth noting that in the embodiment of the present application, the source electrode contact 103, the drain electrode contact 104 and the gate electrode 102 are respectively formed by interconnecting multiple metal layers. Figure 1As shown, the source electrode contact 103 and the drain electrode contact 104 are heterogeneous patterns connected by multiple layers of metal. That is, after the source metal / drain metal is prepared, multiple layers of metal are deposited by evaporation after tempering to form an interconnection structure.

[0039] In some embodiments, Figure 1 As shown, the source electrode contact 103 and the drain electrode contact 104 are respectively disposed on opposite sides of the semiconductor stack 101 , and the gate electrode 102 is disposed on the semiconductor stack 101 and between the source electrode contact 103 and the drain electrode contact 104 .

[0040] See also Figure 3 , Figure 3 1 is a schematic diagram of a semiconductor stack 101 in some embodiments of the present application. In addition to a substrate 201 and an epitaxial layer 202 stacked in sequence, the semiconductor stack 101 also includes an isolation region 203. The isolation region 203 is disposed in the epitaxial layer 202, and the isolation region 203 extends along the surface of the epitaxial layer 202 toward the substrate 201 and extends to below the two-dimensional electron gas.

[0041] Specifically, at the same time, before or after the gate electrode 102 / source electrode contact 103 / drain electrode contact 104 is provided, a dielectric layer 105 is provided on the semiconductor stack 101 using processes such as atomic layer deposition and chemical vapor deposition for multiple times, and isolation is formed by processes such as ion implantation and etching to generate 2DEG. After the isolation step is completed, the 2DEG is retained in the portion blocked by the mask, and the 2DEG disappears in the portion not blocked by the mask.

[0042] The ions involved in ion implantation include but are not limited to hydrogen ions and helium ions; the etching gases involved in etching include but are not limited to BCl 3 , Cl 2 .

[0043] In some embodiments, the passivation layer 106 includes, but is not limited to, oxides or nitrides, such as silicon nitride (SiN), silicon oxide (SiO 2 ). The passivation layer 106 includes but is not limited to a composite layer of oxide and nitride, such as Al 2 O 3 / SiN、Al 2 O 3 / SiO 2 、AlN / SiN、AlN / SiO 2 The passivation layer 106 may be formed by CVD, high density plasma (HDP) CVD, spin coating, sputtering, and other processes.

[0044] The gallium nitride semiconductor device 10 provided in some embodiments of the present application can alleviate the diffusion of tensile stress generated by the gallium nitride semiconductor device 10 by disposing a passivation layer 106 on the electrode and covering the electrode / electrode contact with the passivation layer 106, thereby improving the water vapor corrosion resistance of the gallium nitride semiconductor device 10 and enhancing the reliability and service life of the gallium nitride semiconductor device 10.

[0045] In some embodiments, a portion of the first passivation layer 1061 in the receiving groove abuts against the source electrode contact 104 and the dielectric layer 105, respectively; another portion of the first passivation layer 1061 in the receiving groove abuts against the drain electrode contact 103 and the dielectric layer 105, respectively; another portion of the first passivation layer 1061 in the receiving groove abuts against the dielectric layer 105, the source electrode contact 104 and the drain electrode contact 103, respectively; wherein the surface of the first passivation layer 1061 away from the dielectric layer 105 is flush with the surface of at least one of the source electrode contact 104 and the drain electrode contact 103 away from the semiconductor stack 101.

[0046] See also Figure 4 The receiving groove includes a first receiving groove O1, a second receiving groove O2 and a third receiving groove O3. The first passivation layer 1061 in the first receiving groove O1 contacts the source electrode contact 103 and the dielectric layer 105, but does not contact the drain electrode contact 104 and the gate electrode 102; the first passivation layer 1061 in the second receiving groove O2 contacts the drain electrode contact 104 and the dielectric layer 105, but does not contact the source electrode contact 103 and the gate electrode 102; the first passivation layer 1061 in the third receiving groove O3 abuts against the dielectric layer 105, the source electrode contact 103 and the drain electrode contact 104.

[0047] In some embodiments, see Figure 1 and Figure 4 , the surface of the first passivation layer 1061 placed in the first receiving groove O1 away from the dielectric layer 105 is flush with the surface X1 of the source electrode contact 103 at the contact position; the surface of the first passivation layer 1061 placed in the second receiving groove O2 away from the dielectric layer 105 is flush with the surface Y1 of the drain electrode contact 104 at the contact position; the surface of the first passivation layer 1061 placed in the third receiving groove O3 away from the dielectric layer 105 is flush with the surface X2 of the source electrode contact 103 and the surface Y2 of the drain electrode contact 104 at the contact position respectively.

[0048] In the embodiments of the present application, Figure 1 and Figure 4 As shown, the cross section of a portion of the first passivation layer 1061 is step-shaped, which can facilitate the growth of the second passivation layer 1062 and reduce the tensile stress of the passivation layer 106 .

[0049] See also Figure 5, Figure 5 Schematic diagram of a gallium nitride semiconductor device 10 in some embodiments of the present application. The second passivation layer 1062 includes a first sub-passivation layer 401, a second sub-passivation layer 402 and a third sub-passivation layer 403 which are sequentially stacked. The first sub-passivation layer 401 is covered on the source electrode contact 103, the drain electrode contact 104 and the first passivation layer 1061; the second sub-passivation layer 402 is stacked on the first sub-passivation layer 401; the third sub-passivation layer 403 is disposed on the second sub-passivation layer 402, and the surface H1 of the third sub-passivation layer 403 away from the second sub-passivation layer 402 is parallel to the surface H2 of the semiconductor stack 101 away from the gate electrode 102, the source electrode contact 103 and the drain electrode contact 104, that is, the surface H1 of the third sub-passivation layer 403 is parallel to the surface H2 of the substrate 201 in the semiconductor stack 101.

[0050] In one application scenario, the first passivation layer 1061 and the first sub-passivation layer 401 are prepared by plasma enhanced chemical vapor deposition (PECVD); the second sub-passivation layer 402 is prepared by atomic layer deposition; and the third sub-passivation layer 403 is obtained by coating with a coater.

[0051] In some embodiments, the first passivation layer 1061 , the first sub-passivation layer 401 , the second sub-passivation layer 402 , and the third sub-passivation layer 403 are made of different materials.

[0052] In one application scenario, the first passivation layer 1061 is a silicon oxide passivation layer, the first sub-passivation layer 401 is a silicon nitride passivation layer, the second sub-passivation layer 402 is an aluminum oxide passivation layer, and the third sub-passivation layer 403 is a double-layer photosensitive polyimide passivation layer.

[0053] In some embodiments, the thickness of the third sub-passivation layer 403 is greater than the thickness of the first sub-passivation layer 401 and the second sub-passivation layer 402, the thickness of the second sub-passivation layer 402 is less than the thickness of the first sub-passivation layer 401, and the thickness of the first sub-passivation layer 401 is greater than or equal to the thickness of the first passivation layer 1061.

[0054] In an embodiment of the present application, a portion of the first passivation layer 1061 has a step-shaped cross-section, which can avoid stratification of the first sub-passivation layer 401 and the second sub-passivation layer 402 at the step and reduce the warping of the first sub-passivation layer 401 and the second sub-passivation layer 402, thereby achieving better growth of the passivation layer 106 while reducing tensile stress.

[0055] The thickness of the first passivation layer 1061 can be determined according to the steps of the interconnected metal (i.e., the source electrode contact 104 and / or the drain electrode contact 103). For example, the source electrode contact 103 is interconnected, and the thickness of the first passivation layer 1061 can be determined according to the thickness of the source electrode contact 103. The thickness of the first sub-passivation layer 401 is set to ensure a certain passivation effect. The function of the second sub-passivation layer 402 is to be used for device opening process packaging in the process. The thickness of the second sub-passivation layer 402 should not be too thick or too thin to ensure the passivation effect of the opening position and the non-opening position on the second sub-passivation layer 402. The third sub-passivation layer 403 is the thickest layer in the passivation layer 106. The third sub-passivation layer 403 has a self-flattening effect and can prevent water vapor intrusion.

[0056] In one application scenario, the thickness of the first passivation layer 1061 is determined according to the step depth of the surface metal layer, wherein the surface metal layer is formed by the source electrode contact 103 and / or the drain electrode contact 104. For example, the thickness of the first passivation layer 1061 is in the range of 100 to 350 nm, the thickness of the first sub-passivation layer 401 is in the range of 300 to 1000 nm, the thickness of the second sub-passivation layer 402 is in the range of 20 to 50 nm, and the thickness of the third sub-passivation layer 403 is in the range of 4 to 10 μm.

[0057] Specifically, when the first passivation layer 1061 is a SiO layer with a thickness range of 100 to 350 nm, the preparation process of the SiO layer includes: after the SiO layer is prepared, the first passivation layer 1061 of the gallium nitride semiconductor device 10 is obtained by photoresist coating, photolithography development, and ICP processes. Specifically, when preparing the SiO layer, the device needs to be placed in a nitrogen environment for preheating for 50 seconds and then heated with N 2 O plasma for pretreatment, and then the reaction gas SiH 4 、N 2 O and H 2 The reaction is carried out to prepare a SiO layer with a thickness of 100 to 350 nm at a reaction temperature of 300±20°C, a chamber pressure of 10 to 20 Pa, and a radio frequency power of 100 to 500 W. The SiO layer prepared in the above manner can optimize the structure of the gallium nitride semiconductor device 10, making the subsequent second passivation layer 1062 flatter and reducing the risk of cracking.

[0058] When the first sub-passivation layer 401 is a SiN layer with a thickness range of 300 to 1000 nm, the preparation process of the SiN layer includes: preheating in a nitrogen environment for 50 seconds, and then introducing SiH 4 and NH 3 The reaction gas and a large amount of N 2, a SiN layer with a thickness of 300 to 1000 nm is prepared under the conditions of a reaction temperature of 300±20°C, a chamber pressure of 10-20 Pa and a radio frequency power of 100 to 500 W. The SiN layer prepared in the above manner has good resistance to water vapor erosion.

[0059] When the second sub-passivation layer 402 is an AlO layer with a thickness ranging from 20 to 50 nm, the preparation process of the AlO layer includes: at a reaction temperature of 300±20° C., trimethylaluminum vapor and H 2 O or H 2 O 2 After the vapor reaction, it is adsorbed on the above structure to prepare a thin AlO layer with a thickness of 20 to 50 nm. The AlO layer prepared in the above manner can make the third sub-passivation layer 403 easier to adsorb and prepare, and the second sub-passivation layer 402 is between the first sub-passivation layer 401 and the third sub-passivation layer 403, which can disperse the pressure of the passivation layer 106.

[0060] When the third sub-passivation layer 403 is a double-layer photosensitive polyimide passivation layer with a thickness range of 4 to 10 μm, the preparation process of the double-layer photosensitive polyimide passivation layer includes: preparing a photosensitive polyimide layer with a thickness of 5 to 10 μm by a coating machine, baking at a temperature of 300 to 400° C., and then depositing a second photosensitive polyimide layer with a thickness of 5 to 10 μm, and baking at a temperature of 300 to 400° C. again, finally obtaining a double-layer photosensitive polyimide passivation layer with a uniform thickness of 4 to 10 μm. The double-layer photosensitive polyimide passivation layer prepared in the above manner can better prevent ion contamination, optimize packaging testing and stress during operation, so as to protect the gallium nitride semiconductor device 10.

[0061] In some embodiments, the gallium nitride semiconductor device 10 further includes conductor through-holes, which are respectively arranged on the first sub-passivation layer 401, the second sub-passivation layer 402 and the third sub-passivation layer 403, wherein the third sub-passivation layer 403 includes two conductor through-holes, which are respectively arranged when baking at a temperature of 300-400°C.

[0062] In some embodiments of the present application, the tensile stress of the passivation layer 106 is positively correlated with the corresponding thickness. That is, the thicker the passivation layer 106 is, the greater the tensile stress is.

[0063] See also Figure 6 , Figure 6Schematic diagram of the receiving groove in some embodiments of the present application. The receiving groove includes a first receiving groove O1 and a second receiving groove O2. The first passivation layer 1061 in the first receiving groove O1 contacts the source electrode contact 103 and the dielectric layer 105, and does not contact the drain electrode contact 104 and the gate electrode 102, and the first passivation layer 1061 in the second receiving groove O2 contacts the dielectric layer 105, the source electrode contact 103 and the drain electrode contact 104, respectively.

[0064] In some embodiments, see Figure 7 , the surface of the first passivation layer 1061 placed in the first receiving groove O1 away from the dielectric layer 105 is flush with the surface X3 of the source electrode contact 103 and covers the portion of the dielectric layer 105; the surface of the first passivation layer 1061 placed in the second receiving groove O2 away from the dielectric layer 105 is flush with the surface X3 of the source electrode contact 103 and covers the portion of the drain electrode contact 104 and the dielectric layer 105.

[0065] In some embodiments, see Figure 7 The second passivation layer 1062 includes a first sub-passivation layer 401, a second sub-passivation layer 402, and a third sub-passivation layer 403 which are sequentially stacked. The first sub-passivation layer 401 is covered on the source electrode contact 103 and the first passivation layer 1061; the second sub-passivation layer 402 is covered on the first sub-passivation layer 401; and the third sub-passivation layer 403 is covered on the second sub-passivation layer 402.

[0066] In summary, compared with the gallium nitride semiconductor devices in the related art, the gallium nitride semiconductor device 10 provided in some embodiments of the present application can alleviate the stress diffusion generated by the enhanced gallium nitride chip product during the packaging test and application process of high temperature and high pressure, thereby reducing the stress extension degree of the passivation layer 106 in the gallium nitride semiconductor device 10, making the protection effect of the passivation layer 106 better, enhancing the water vapor erosion resistance of the gallium nitride semiconductor device 10, and improving the reliability and service life of the gallium nitride semiconductor device 10.

[0067] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gallium nitride semiconductor device, characterized in that: The gallium nitride semiconductor device comprises: A semiconductor stack, wherein a two-dimensional electron gas is generated in the semiconductor stack; A gate electrode, a source electrode contact, and a drain electrode contact disposed on the semiconductor stack; A dielectric layer is filled and arranged on the semiconductor stack, and is in contact with the gate electrode, the source electrode, and the drain electrode, respectively; wherein a side of the dielectric layer away from the semiconductor stack is lower than a side of the source electrode and / or the drain electrode away from the semiconductor stack; The passivation layer includes a first passivation layer and a second passivation layer stacked in a direction from the semiconductor stack to the dielectric layer, wherein the first passivation layer is filled in a receiving groove formed by the dielectric layer, the source electrode contact and / or the drain electrode contact, and the second passivation layer is covered on the first passivation layer, the source electrode contact and the drain electrode contact on a side away from the semiconductor stack.

2. The gallium nitride semiconductor device according to claim 1, characterized in that: The source electrode contact and the drain electrode contact are respectively arranged on two opposite sides of the semiconductor stack, and the gate electrode is arranged on the semiconductor stack and between the source electrode contact and the drain electrode contact.

3. The gallium nitride semiconductor device according to claim 2, characterized in that: The source electrode contact, the drain electrode contact and the gate electrode are respectively formed by interconnecting multiple metal layers.

4. The gallium nitride semiconductor device according to claim 1, characterized in that: A portion of the first passivation layer in the containing groove is in contact with the source electrode and abuts against the dielectric layer; Another portion of the first passivation layer in the containing groove is in contact with the drain electrode and abuts against the dielectric layer; Another portion of the first passivation layer in the containing groove is in contact with the dielectric layer, the source electrode and the drain electrode respectively; The surface of the first passivation layer away from the dielectric layer is flush with the surface of at least one of the source electrode contact and the drain electrode contact away from the semiconductor stack.

5. The gallium nitride semiconductor device according to claim 1, characterized in that: The second passivation layer includes a first sub-passivation layer, a second sub-passivation layer and a third sub-passivation layer which are stacked in sequence; The first sub-passivation layer is covered on the source electrode contact, the drain electrode contact and the first passivation layer; the second sub-passivation layer is arranged on the first sub-passivation layer; the third sub-passivation layer is arranged on the second sub-passivation layer, and the surface of the third sub-passivation layer away from the second sub-passivation layer is parallel to the surface of the semiconductor stack away from the gate electrode, the source electrode contact and the drain electrode contact.

6. The gallium nitride semiconductor device according to claim 5, characterized in that: The first passivation layer, the first sub-passivation layer, the second sub-passivation layer and the third sub-passivation layer are made of different materials; The first passivation layer is a silicon oxide passivation layer, the first sub-passivation layer is a silicon nitride passivation layer, the second sub-passivation layer is an aluminum oxide passivation layer, and the third sub-passivation layer is a double-layer photosensitive polyimide passivation layer.

7. The gallium nitride semiconductor device according to claim 6, characterized in that: The thickness of the third sub-passivation layer is greater than that of the first and second sub-passivation layers, the thickness of the second sub-passivation layer is less than that of the first sub-passivation layer, and the thickness of the first sub-passivation layer is greater than or equal to that of the first passivation layer.

8. The gallium nitride semiconductor device according to claim 1, characterized in that: The magnitude of the tensile stress of the passivation layer is positively correlated with the corresponding thickness.

9. The gallium nitride semiconductor device according to any one of claims 1 to 8, characterized in that: The thickness of the first passivation layer is determined according to the step depth of the surface metal layer; wherein the surface metal layer is formed by the source electrode contact and / or the drain electrode contact.

10. The gallium nitride semiconductor device according to claim 1, characterized in that: The semiconductor stack includes a substrate and an epitaxial layer disposed on the substrate, wherein the epitaxial layer includes a semiconductor composite structure that generates a two-dimensional electron gas.

11. The gallium nitride semiconductor device according to claim 10, characterized in that: The semiconductor stack further includes an isolation region, which is disposed in the epitaxial layer, extends along a surface of the epitaxial layer toward the substrate, and extends to below the two-dimensional electron gas.

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