Plasma processing device

Abstract

A semiconductor manufacturing apparatus for performing a process is disclosed. A plasma processing apparatus includes a chamber configured to receive a wafer for an etch process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etching direction of the etching process; and the insulating cover ring is arranged in the cavity. The insulating cover ring is configured to vary the electric field. The insulating cover ring has an inner ring insulating portion and an outer ring insulating portion, and wherein a gap is defined between the inner ring insulating portion and the outer ring insulating portion.

Description

Technical Field

[0001] The present disclosure relates to a plasma processing device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and units thereon.

[0003] The semiconductor industry continues to reduce the minimum feature size, which can continuously improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to integrate more components into a given area. However, as the minimum feature size decreases, each process used will have additional problems that need to be solved. Utility Model Content

[0004] According to some embodiments of the present disclosure, a plasma processing apparatus includes a chamber, a conductive focus ring, and an insulating cover ring. The chamber is configured to receive a wafer for an etching process. The conductive focus ring is disposed in the chamber and is used to focus an electric field to control an etching direction of the etching process. The insulating cover ring is disposed in the chamber. The insulating cover ring is configured to change the electric field. The insulating cover ring has an inner ring insulating portion and an outer ring insulating portion, and a gap is defined between the inner ring insulating portion and the outer ring insulating portion.

[0005] According to some embodiments of the present disclosure, a plasma processing apparatus includes a chamber, an electrostatic chuck, a focus ring, an inner shield, and an outer shield. The electrostatic chuck is disposed in the chamber, and the electrostatic chuck is used to support a wafer during a plasma processing process performed on the wafer. The focus ring is disposed in the chamber and surrounds a portion of the electrostatic chuck. The focus ring has an inner portion adjacent to an inner edge of the focus ring and an outer portion adjacent to an outer edge of the focus ring. The inner shield is located above the inner portion of the focus ring. The outer shield is located above the outer portion of the focus ring.

[0006] According to some embodiments of the present disclosure, a plasma processing apparatus includes an electrostatic chuck, a focus ring, and a cover ring. The electrostatic chuck is disposed in a chamber, and the electrostatic chuck is configured to support a wafer. The focus ring is disposed in the chamber, and the focus ring surrounds a portion of the electrostatic chuck. The cover ring is disposed in the chamber and above the focus ring, and the cover ring is configured to change an electric field. The cover ring has an inner ring insulating portion and an outer ring insulating portion, and a gap is defined between the inner ring insulating portion and the outer ring insulating portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a diagram of a semiconductor processing apparatus according to an embodiment of the present disclosure;

[0009] Figure 2 is a flow chart of a semiconductor processing method according to an embodiment of the present disclosure;

[0010] Figure 3 is a schematic partial cross-sectional view more clearly illustrating a cover ring and a focus ring in a semiconductor processing device according to an embodiment of the present disclosure;

[0011] Figure 4 is a schematic partial cross-sectional view of a cover ring and a focus ring in a semiconductor processing device according to an embodiment of the present disclosure;

[0012] Figure 5 is a perspective view of a two-piece cover ring according to an embodiment of the present disclosure;

[0013] Figure 6 yes Figure 5 A top view of a two-piece cover ring;

[0014] Figure 7 yes Figure 5 Two-piece cover ring Figure 5 Sectional view of midline 7-7;

[0015] Figure 8 is a perspective view of an integrated cover ring according to an embodiment of the present disclosure;

[0016] Fig. 9 yes Figure 8 A top view of the one-piece cover ring;

[0017] Fig.10 The annular portion of the cover ring according to the embodiment of the present disclosure is along Figure 5 Sectional view along the midline 7-7.

[0018]

Explanation of symbols

[0019] 100: Installation

[0020] 1000: Ring part

[0021] 1001: Edge

[0022] 1002: Edge

[0023] 1003: Bottom surface

[0024] 1004: Upper surface

[0025] 1009: Surface

[0026] 1010: upper part

[0027] 1013: Surface

[0028] 1020: Lower part

[0029] 1021: Surface

[0030] 105: Wafer

[0031] 106: Upper surface

[0032] 109: Plane

[0033] 110: Chamber

[0034] 112: Upper part

[0035] 113: Upper electrode

[0036] 114:lower part

[0037] 116: Insulation ceramic frame

[0038] 120:RF power source

[0039] 125: Plasma

[0040] 126: Plasma Sheath

[0041] 127: Ion

[0042] 129: Exposed Area

[0043] 130: Electrostatic chuck

[0044] 131: Base

[0045] 132: Center

[0046] 133: Upper surface

[0047] 134: Outer wall

[0048] 135: Suction cup electrode

[0049] 136: External

[0050] 137: Upper surface

[0051] 138: Outer wall

[0052] 139: Plane

[0053] 140: DC power source

[0054] 160: Pump

[0055] 170: Focus ring

[0056] 171: Upper surface

[0057] 172: Inner ring groove

[0058] 173: Outer ring groove

[0059] 174: Inner edge

[0060] 175: Outer edge

[0061] 176: Bottom surface

[0062] 177: Inner annular surface

[0063] 178: Outer annular surface

[0064] 179: Middle annular surface

[0065] 180: Cover ring

[0066] 181: Inner ring

[0067] 182: Outer ring

[0068] 190:Support ring

[0069] 192: Outer edge

[0070] 195:O-ring

[0071] 310: Gas source

[0072] 320: Traffic Verification Unit

[0073] 60: Controller

[0074] 7-7: Line

[0075] 80: Gap

[0076] 811: Inner edge

[0077] 812: Outer edge

[0078] 813: Upper surface

[0079] 814: Bottom surface

[0080] 815: Groove

[0081] 821:Inner edge

[0082] 822: Outer edge

[0083] 823: Upper surface

[0084] 824: Bottom surface

[0085] 825: Groove

[0086] 90: Adhesive layer

[0087] 900: Bridge section

[0088] H1: Height

[0089] H2: Height

[0090] H3: Height

[0091] H4: Height

[0092] H5: Height

[0093] H6: Height

[0094] H7: Height

[0095] H8: Height

[0096] H9: Height

[0097] S210: Operation

[0098] S220: Operation

[0099] S230: Operation

[0100] S240: Operation

[0101] S250: Operation

[0102] S260: Operation

[0103] S261: Operation

[0104] S262: Operation

[0105] W1: Width

[0106] W2: Width

[0107] W3: Width

[0108] W4: Width

[0109] W5: Width

[0110] W6: Width

[0111] W7: Width

[0112] X: Axis

[0113] Z: Axis DETAILED DESCRIPTION

[0114] The disclosure that follows provides many different implementations or embodiments to implement different features of the subject matter provided. Specific embodiments of components and configurations are described below to simplify the disclosure. These are of course only embodiments and are not intended to be limiting. For example, in the subsequent description, forming a first feature higher than or above a second feature may include implementations in which the first and second features are formed in direct contact, and may also include implementations in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat numbers and / or letters in various embodiments. Such repetition is for the sake of simplicity and clarity and does not refer to the relationship between the various embodiments and / or configurations discussed.

[0115] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0116] For ease of explanation, terms such as "about", "approximately", "substantially", etc. may be used herein. A person of ordinary skill in the art will be able to understand and deduce the meaning of such terms. For example, "about" may indicate a change in a dimension of 20%, 10%, 5%, and similar values, but other values ​​may be used as appropriate. Large features such as the longest dimension of a semiconductor fin may have a change of less than 5%, while very small features such as the thickness of an interface layer may have a change of up to 50%, and both types of changes may be represented by the term "about". "Substantially" is generally stricter than "about", so that a change of 10%, 5%, or less may be appropriate, but is not limited to this. A "substantially flat" feature may have a deviation of 10% or less relative to a straight line. A material with a "substantially constant concentration" may have a concentration change of 5% or less along one or more dimensions. Again, a person of ordinary skill in the art will be able to understand and deduce the appropriate meaning of such terms based on industry knowledge, current manufacturing techniques, etc.

[0117] In certain embodiments herein, a "material layer" is a layer comprising at least 50 wt.% of an identified material, such as at least 50 wt.% of an identified material, at least 75 wt.% of an identified material, at least 90 wt.% of an identified material, or substantially 100 wt.% of an identified material; and a layer of "material" comprising at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, or at least 90 wt.% of an identified material, or substantially 100 wt.% of an identified material. For example, in certain embodiments, each titanium nitride layer and a layer of titanium nitride is at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, or at least 90 wt.% or substantially 100 wt.% titanium nitride.

[0118] Semiconductor manufacturing generally involves forming electronic circuits by performing multiple deposition, etching, annealing processes and / or implantation of material layers, thereby forming a stacked structure including many semiconductor devices and interconnections therebetween. Scaling (reduction) is a technique for fitting more semiconductor devices in the same area. However, scaling becomes increasingly difficult in advanced technology nodes.

[0119] According to various embodiments, an apparatus for processing semiconductor wafers to manufacture semiconductor devices is described. Specifically, the apparatus may be an etching apparatus, such as a plasma etching apparatus. Plasma etching of semiconductor wafers or workpieces typically uses a reactive gas, including etching chemicals such as chlorine or fluorine for etching silicon, dielectrics, and metals. During etching, the reactive gas is excited by a high-frequency electromagnetic field to generate an etching plasma containing ions that bombard the surface of the semiconductor workpiece.

[0120] In some embodiments, the plasma etching apparatus includes a conductive focusing ring to guide the plasma to the wafer and ensure that the plasma is evenly distributed on the wafer. Specifically, the conductive focusing ring generates or focuses an electric field to control the etching direction of the plasma ions.

[0121] Plasma etchers can experience tilt angle issues near the edge of the wafer, especially when the plasma etching process is run at high radio frequency (RF) power for extended periods of time. This issue can cause non-uniform etching of the wafer, which can affect the quality and yield of the manufactured devices. Tilt angle issues occur due to the uneven distribution of the electric field near the edge of the wafer. The electric field is strongest at the center of the electrode and weakens toward the edge of the electrode. This can cause a difference in etch rate between the center and edge of the wafer, resulting in a tilted profile. The problem becomes more severe at high RF times because the electric field is amplified, causing the wafer to heat up and deform. The deformation of the wafer further exacerbates the non-uniformity of the electric field distribution, resulting in a larger tilt angle issue.

[0122] In some embodiments, the focus ring surrounding the wafer may be equipped with a direct current (DC) power supply. Although applying DC power through the focus ring can reduce the tilt angle problem, via-to-metal overlap shifting still exists at a wafer radius of 130 to 145 mm (150 mm radius wafer).

[0123] Embodiments of the present disclosure reduce or eliminate the tilt angle problem and via-to-metal overlap at a wafer radius of 130 to 145 mm. Specifically, in one embodiment of the present disclosure, an insulating cover ring is located above a conductive focus ring. The insulating cover ring includes an inner ring portion or shield located directly above the inner edge of the focus ring. In addition, the insulating cover ring includes an outer ring portion or shield located above the outer edge of the focus ring. An annular gap or opening is formed in the cover ring between the inner ring portion and the outer ring portion. The center annular gap is directly above the center ring portion of the focus ring. As a result, the insulating cover ring is configured to change the electric field focused by the focus ring. Due to the modification of the cover ring, the exposed area of ​​the focus ring affects the plasma sheath thickness and affects the ion incidence angle toward the wafer. Therefore, the wafer edge profile tilt can be resolved and the via-to-metal overlap can be reduced or eliminated.

[0124] In addition, in some embodiments, the sizes of the inner ring portion and the outer ring portion of the cover ring can be easily modified to adjust the plasma sheath near the edge of the wafer as needed. For example, the radial width of the inner ring portion, the annular gap, and the outer ring portion can be modified. Moreover, the cross-sectional profiles of the inner ring portion and the outer ring portion can be modified, including the height of the inner and / or outer side walls of both the inner ring portion and the outer ring portion, and the angle between the side wall surface and the top surface. In some embodiments, the cross-sectional profiles of the inner ring portion and the outer ring portion can be regular polygons, irregular polygons, concave polygons, and / or stepped polygons, and in some embodiments can have a shape such as a polygon, but can be formed with one or more curved sides.

[0125] Figure 1 FIG. 1 is a schematic diagram of a semiconductor processing device 100 according to various embodiments of the present disclosure. In some embodiments, the semiconductor processing device 100 is configured to perform etching, deposition or other suitable processes.

[0126] like Figure 1As shown, the semiconductor processing apparatus 100 includes a processing chamber 110 and a radio frequency (RF) power source 120 configured to provide RF power in the processing chamber 110. The semiconductor processing apparatus 100 also includes an electrostatic chuck 130 within the processing chamber 110, and the electrostatic chuck 130 is configured to receive and fix the wafer 105. The semiconductor processing apparatus 100 also includes a chuck electrode 135 and a direct current (DC) power source 140 connected to the chuck electrode 135. The DC power source 140 is configured to provide power to the chuck electrode 135. The semiconductor processing apparatus 100 also includes a gas source 310, which is configured to introduce a process gas and / or a carrier gas into the processing chamber 110. The semiconductor processing apparatus 100 may also include a flow verification unit 320, which is configured to measure and / or verify the flow of the process gas and / or the carrier gas entering the processing chamber 110.

[0127] In some embodiments, the semiconductor processing device 100 is an etching device 100, such as a plasma etching device 100. In some embodiments, the semiconductor processing device 100 is any plasma etching or dry etching tool that generates plasma from a processing gas (usually oxygen, chlorine-containing gas, or fluorine-containing gas) and uses a radio frequency (RF) electric field. In some embodiments, the semiconductor processing device 100 is an ion beam etcher, a reactive ion etcher, etc. In other embodiments, the semiconductor processing device 100 is not an etching device, but a plasma deposition device, such as a plasma-enhanced atomic layer deposition (PEALD) device, etc. Plasma etching devices and plasma deposition devices can be collectively referred to as plasma processing devices.

[0128] In some embodiments, wafer 105 includes a single crystal semiconductor layer at least on its surface. In some embodiments, wafer 105 includes a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In some embodiments, wafer 105 is made of Si. In some embodiments, wafer 105 is a silicon wafer. In some embodiments, wafer 105 is a semiconductor substrate on an insulator manufactured using oxygen implantation separation (SIMOX), wafer bonding and / or other suitable methods, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, wafer 105 is a Si wafer having a mirror-polished surface on one or both sides. In some embodiments, wafer 105 includes one or more integrated circuit (IC) wafers at an intermediate (unfinished) stage of fabrication such that plasma etching or deposition is performed on at least the topmost layer of each IC wafer by semiconductor processing apparatus 100 .

[0129] In some embodiments, the processing chamber 110 includes an upper portion 112 and a lower portion 114, and the upper portion 112 and the lower portion 114 may include at least one conductive material, such as aluminum, and other non-conductive or semiconductor materials. In some embodiments, the upper portion 112 includes an upper electrode 113. In some embodiments, the lower portion 114 includes an insulating ceramic frame 116 and includes an electrostatic chuck 130 within the insulating ceramic frame 116. For example, the electrostatic chuck 130 is disposed within the insulating ceramic frame 116 within the lower portion 114 of the processing chamber 110, such as Figure 1 In some embodiments, the electrostatic chuck 130 includes a conductive sheet that serves as a chuck electrode 135. In some embodiments, the conductive sheet includes at least two sheet portions that are electrically isolated from each other. Figure 1 As shown, the chuck electrode 135 is connected to a DC power source 140. When a DC voltage from the DC power source 140 is applied to the chuck electrode 135 of the electrostatic chuck 130 on which the wafer 105 is disposed, a Coulomb force is generated between the wafer 105 and the chuck electrode 135. The Coulomb force attracts the wafer 105 and holds it on the electrostatic chuck 130 until the application of the DC voltage from the DC power source 140 is stopped. In some embodiments, at least one DC voltage is applied to at least two sheet portions of the chuck electrode 135 by the DC power source 140.

[0130] In some embodiments, to improve heat transfer between wafer 105 and electrostatic chuck 130, one or more gases, such as He or Ar, are introduced between wafer 105 and electrostatic chuck 130 through gas source 310. In some embodiments, the gas dissipates heat generated between wafer 105 and electrostatic chuck 130 during application of the DC voltage.

[0131] like Figure 1 As shown, the semiconductor processing apparatus 100 further includes a pump 160 connected to the processing chamber 110. The pump 160 is configured to provide a vacuum or maintain a certain gas pressure in the processing chamber 110. In some embodiments, the pressure in the processing chamber 110 is maintained by a combination of one or more gases introduced by the gas source 310 and a level of pumping performed by the pump 160. In some embodiments, the pressure in the processing chamber 110 is maintained only by the pumping of the pump 160.

[0132] In some embodiments, the RF power source 120 is turned on to apply the plasma 125 for a plasma etching operation. The RF power source 120 can be configured to generate an RF signal operating at a set frequency (e.g., 13.56 MHz) that transfers energy from the RF power source 120 to the gas within the processing chamber 110. When sufficient energy is delivered to the gas, the plasma is ignited. In some embodiments, the power applied during the etching operation is in the range of about 200 watts to about 700 watts. In some embodiments, the application of the RF pulses lasts for a duration of about 10 seconds to about 60 seconds.

[0133] In some embodiments, the semiconductor processing apparatus 100 further includes a focus ring 170. The focus ring 170 surrounds at least a portion of the electrostatic chuck 130 and / or the wafer 105 and may have a generally annular shape. Along a vertical radial plane, such as the plane of the drawing, the focus ring 170 may have a rectangular cross-section, such as Figure 1 As shown, or may have an irregular cross section or a cross section of a different shape, for example, a regular polygon, an irregular polygon, a concave polygon and / or a staircase polygon, and in some embodiments may have such a polygonal shape but formed with a curved side or sides. The focus ring 170 may have a vertical thickness, i.e., a thickness in the Z-axis direction, of 2.5 mm to 50 mm. However, any suitable size or suitable shape may be used.

[0134] The focus ring 170 may be made of conductive material, metallic material, semiconductor material or other material. In some embodiments, the focus ring 70 may be made of doped or undoped silicon.

[0135] In some embodiments, the focus ring 170 may be coupled to the DC power source 140. For example, at least one DC voltage is applied to the focus ring 170 by the DC power source 140, so that the focus ring 170 may be electrically biased with a DC voltage by the DC power source 140 during the etching process.

[0136] like Figure 1 As further shown, the semiconductor processing apparatus 100 also includes a cover ring 180. In some embodiments, the cover ring 180 includes an inner ring portion or shield 181 and an outer ring portion or shield 182. Each portion 181 and 182 of the cover ring 180 can be made of an insulating material that can withstand high temperatures and harsh environments, for example, a ceramic material such as quartz, alumina, silicon nitride, or other suitable materials. The ring portions 181 and 182 can be made of the same material, or can be made of different materials.

[0137] In an exemplary embodiment, each of the annular portions 181 and 182 may independently have a Figure 1 The rectangular cross-section shown, or each annular portion 181 and 182 can independently have an irregular cross-section or a cross-section of a different shape, for example, the polygon can be a regular polygon, an irregular polygon, a concave polygon and / or a stepped polygon, and in some embodiments, each polygon can independently have the shape of such a polygon, but is formed with a curved edge or multiple edges.

[0138] As described below, the annular portions 181 and 182 may be separate pieces that are disconnected, or may be connected pieces. For example, one or more bridging portions ( Figure 1 Annular portions 181 and 182 may be interconnected (not shown).

[0139] In some embodiments, the cover ring 180 may be used to achieve a more uniform plasma distribution across the entire surface of the wafer 105 and to limit the distribution of the plasma cloud to only the wafer surface area.

[0140] The operation of the various components of the processing device 100 can be controlled by a controller 60 connected to the components, for example, through one or more wired connections and / or wireless connections. The wired connection can be an electrical connection, an optical connection, or other suitable connection type. The wireless connection can be through an electrical antenna, an optical receiver, or other suitable wireless connection type. In some embodiments, the controller 60 is connected to one or more of the RF power source 120, the DC power source 140, the pump 160, the gas source 310, and the flow verification unit 320 for controlling the operation thereof.

[0141] Although the semiconductor processing apparatus 100 may be described above as a capacitively coupled plasma generator, the embodiments are not intended to be limited to capacitively coupled plasma generators. Rather, any suitable method of generating plasma may be utilized, such as an inductively coupled plasma system, magnetically enhanced reactive ion etching, electron cyclotron resonance, a remote plasma generator, etc. All such methods are fully intended to be included within the scope of the embodiments.

[0142] Although a number of specific components of the semiconductor processing apparatus 100 have been described above, other suitable components may also be included. For example, endpoint mounts, liners, and any other components that may help operate or control the etching process may also be included. All of these parts are fully intended to be included within the scope of the embodiments.

[0143] Figure 2 A method 200 for etching a wafer 10 is depicted.

[0144] As shown, the method 200 includes, at operation S210, determining a via-to-metal overlap offset caused by via tilting of an etching process (e.g., a plasma etching process using a focus ring 170). In addition, the method 200 includes, at operation S220, determining a design of a cover ring 180 to modify an electric field of the focus ring 170 to reduce or eliminate the via-to-metal overlap offset caused by via tilting. Furthermore, the method 200 includes installing a cover ring 180 having an appropriate design on and / or around the focus ring 170 at operation S230.

[0145] As shown, the method 200 includes positioning the wafer 105 on the electrostatic chuck 130 at operation S240. The wafer 105 can be fixed in place by the electrostatic chuck 130. For example, the semiconductor wafer can be clamped in a single stage by the electrostatic force on the electrostatic chuck, where the entire semiconductor wafer is clamped at the same time. Alternatively, the electrostatic force can be gradually applied to the semiconductor wafer and the electrostatic chuck in a staggered manner.

[0146] In addition, the method 200 includes applying the plasma 125 at operation S250. For example, the apparatus 100 is operated to introduce the desired etchant into the chamber 110 and ignite them into the plasma 125 by applying RF power. The RF power source 120 can be configured to generate an RF signal operating at a set frequency (e.g., 13.56 MHz) that transfers energy from the RF power source 120 to the etching gas within the processing chamber 110. When sufficient energy is delivered to the gas, the plasma is ignited. In some embodiments, the power applied during the etching operation is in the range of about 200 watts to about 700 watts. In some embodiments, the application of the RF pulse lasts for a duration of about 10 seconds to about 60 seconds.

[0147] In operation S260 , the method 200 includes focusing the plasma 125 using the focus ring 170 and the cover ring 180 to achieve a more uniform plasma distribution over the entire surface of the wafer 105 and to limit the distribution of the plasma cloud to only the surface area of ​​the wafer.

[0148] Specifically, operation S260 includes providing an electrical bias from the DC power source 140 to the focus ring 170 in operation S261 to maintain the plasma during the etching process by maintaining the bias and help accelerate ions from the plasma to the semiconductor. For example, the biased focus ring 170 focuses the electric field to control the etching direction of the etching process.

[0149] Simultaneously with operation S261, operation S260 includes changing the electric field with the cover ring 180 at operation S262. Specifically, the insulating cover ring 180 blocks or weakens the electric field focused by the focus ring 170 to affect the sheath of the plasma 125.

[0150] Because the cover ring 180 can be designed and installed over and / or around an existing focus ring 170 in an existing semiconductor processing apparatus 100, the semiconductor processing apparatus 100 can be optimized for performance in a particular processing operation without replacing or modifying the focus ring 170. In addition, the cover ring 180 can be replaced or redesigned and replaced to process additional wafers in a different operation.

[0151] Now refer to Figure 3 , the schematic partial cross-sectional view more clearly depicts the shape and size of the cover ring 180 and the focus ring 170 in the semiconductor processing device 100 according to the embodiment of the present disclosure. Specifically, Figure 3 The focus is on one edge of the wafer 105 on the chuck 130 and adjacent portions of the focus ring 170 and the cover ring 180 .

[0152] like Figure 3As shown, the suction cup 130 is positioned above or includes a base 131. In addition, the suction cup 130 has a central portion 132 having an upper surface 133, and an outer sidewall 134. The central portion 132 has an upper surface 133, and the wafer 105 is located on the upper surface 133. As shown, the suction cup 130 has an outer portion 136, and the outer portion 136 has an upper surface 137 and an outer sidewall 138.

[0153] exist Figure 3 , the adhesive layer 90 is located on the upper surface 137 of the outer portion 136 of the suction cup 130. In addition, the focus ring 170 is fixed to the adhesive layer 90.

[0154] As shown, the semiconductor processing device 100 further includes a support ring 190 located radially outward of the outer sidewall 138 of the chuck 130 and radially outward of the focus ring 170. In addition, the semiconductor processing device 100 includes a conductive O-ring 195 located between the support ring 190 and the base 131 of the chuck 130 and the focus ring 170.

[0155] exist Figure 3 , the inner ring portion 181 of the cover ring 180 is located above the interface between the sidewall 134 of the central portion 132 of the suction cup 130 and the focus ring 170. In addition, the outer ring portion 182 of the cover ring 180 is located above the exterior of the focus ring 170 and extends above the O-ring 195 and the support ring 190.

[0156] As configured, the cover ring 180 and focus ring 170 control the focus ring exposed area 129 and the electric field, which affects the plasma sheath 126 and the flow direction of the ions 127 .

[0157] exist Figure 3 , upper surface 133 of electrostatic chuck 130 is defined as plane 139. In addition, plane 139 extends through inner ring portion 181 and outer ring portion 182 of cover ring 180 such that plane 139 is located between the lower surface and the upper surface of each ring portion 181 and 182.

[0158] exist Figure 3 , wafer 105 has an upper surface 106. In some embodiments, upper surface 106 is substantially planar and defined as plane 109. As shown, inner ring portion 181 and outer ring portion 182 have uppermost surfaces located between plane 109 and electrostatic chuck 130 or coplanar with plane 109.

[0159] Figure 4A focus view of the focus ring 170 and the cover ring 180 of the semiconductor processing apparatus 100 is provided. As shown, the upper surface 171 of the focus ring 170 is formed with an inner ring groove 172 and an outer ring groove 173. In some embodiments, the upper surface 171 of the focus ring 170 is substantially planar and can be horizontal, i.e., perpendicular to the Z axis. The focus ring 170 extends radially outward from an inner edge 174 to an outer edge 175. As shown, the focus ring 170 has a bottom surface 176 that can be adhered or otherwise fixed to the suction cup 130.

[0160] Furthermore, the upper surface 171 of the focus ring 170 includes an inner annular surface 177 adjacent to the inner edge 174 , an outer annular surface 178 adjacent to the outer edge 175 , and an intermediate annular surface 179 between the inner annular surface 177 and the outer annular surface 179 .

[0161] exist Figure 4 , the inner ring portion 181 of the cover ring 180 extends radially outward from the inner edge 811 to the outer edge 812. In addition, the inner ring portion 181 is located above the inner ring surface 177 of the focus ring 170. As shown, the inner ring portion 181 has an upper surface 813. In some embodiments, the upper surface 813 is substantially planar and can be horizontal, i.e., perpendicular to the Z-axis. As further shown, the inner ring portion has a bottom surface 814 adjacent to the focus ring 170. In some embodiments, the inner ring portion 181 is formed with a groove 815. As shown, the groove 815 can be formed at the intersection of the inner annular edge 811 and the bottom surface 814. In some embodiments, the bottom surface 814 is substantially planar and can be horizontal, i.e., perpendicular to the Z-axis.

[0162] exist Figure 4 , the inner ring portion 181 has a vertical height H1 from the bottom surface 814 at the groove 815 to the upper surface 813, and has a vertical height H2 from the bottom surface 814 to the upper surface 813 adjacent to the outer edge 812. In some embodiments, the vertical height H1 is the minimum vertical height of the inner ring portion 181. In some embodiments, the vertical height H2 is the maximum vertical height of the inner ring portion 181. In some embodiments, the height H1 is 1 to 15 millimeters (mm) and the height H2 is 1 to 30 millimeters (mm).

[0163] According to the structure of the inner ring portion 181 and the focus ring 170, it can be seen that the inner ring portion 181 can be located in the inner ring groove 172 of the focus ring 170. In addition, the inner ring portion 181 can extend above the inner edge 174 of the focus ring. In some embodiments, the inner edge 811 of the inner ring portion 181 can be aligned with the inner edge 174 of the focus ring.

[0164] exist Figure 482, the outer ring portion 182 of the cover ring 180 extends radially outward from the inner edge 821 to the outer edge 822. As shown, the outer ring portion 182 is located above the outer annular surface 178 of the focus ring 170. As shown, the outer ring portion 182 has an upper surface 823. In some embodiments, the upper surface 823 is substantially planar and can be horizontal, i.e., perpendicular to the Z axis. As further shown, the inner ring portion has a bottom surface 824 adjacent to the focus ring 170. In some embodiments, the outer annular portion 182 is formed with a groove 825. As shown, the groove 825 can be formed at the intersection of the inner annular edge 821 and the bottom surface 824. In some embodiments, the bottom surface 824 is substantially planar and can be horizontal, i.e., perpendicular to the Z axis.

[0165] exist Figure 4 In the embodiment of the present invention, the outer ring portion 182 has a maximum vertical height H3 from the bottom surface 824 to the upper surface 823 adjacent to the inner edge 821, has a minimum vertical height H5 from the bottom surface 824 at the groove 825 to the upper surface 823, and has a vertical height H4 from the bottom surface 824 to the upper surface 823 adjacent to the outer edge 822. In some embodiments, the vertical height H5 is the minimum vertical height of the outer ring portion 182. In some embodiments, the vertical height H3 is the maximum vertical height of the outer ring portion 182. In some embodiments, the height H3 is 1 to 30 millimeters (mm), the height H4 is 1 to 15 millimeters (mm), and the height H5 is 1 to 15 millimeters (mm).

[0166] Through the structure of the outer ring portion 182 and the focus ring 170, it can be seen that the outer ring portion 182 can be located in the outer ring groove 173 of the focus ring 170. In addition, the outer ring portion 182 can extend above the outer edge 175 of the focus ring 170. In some embodiments, the outer ring portion 182 extends on the support ring 190. In some embodiments, the outer edge 822 is aligned with the outer edge 192 of the support ring 190.

[0167] exist Figure 4 In the embodiment, the inner ring portion 181 has a horizontal radial width W1 from the inner edge 811 to the outer edge 812, and the outer ring portion 182 has a horizontal radial width W2 from the inner edge 821 to the outer edge 822. In some embodiments, the radial width W1 is 1 to 92 millimeters (mm) and the radial width W2 is 1 to 92 millimeters (mm).

[0168] exist Figure 4In some embodiments, the ratio of width W1 to width W2 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of width W1 to width W2 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0169] In addition, a gap 80 is formed in the cover ring 180 between the inner ring portion 181 and the outer ring portion 182. As shown, the gap 80 is located above the intermediate annular surface 179 of the focus ring 170. As shown, the gap 80 has a radial distance or width W3. In some embodiments, the radial width W3 is 1 to 180 millimeters (mm).

[0170] Figures 5 to 7 An embodiment of a cover ring 180 having two broken and separate annular portions 181 and 182 is depicted. Figure 5 It is a perspective view. Figure 6 It is a top view. Figure 7 is along Figure 5 A cross-sectional view taken along line 7-7 in FIG.

[0171] like Figures 5 to 7 As shown, the annular portions 181 and 182 may be substantially circular. In addition, each annular portion 181 and 182 may have a substantially rectangular cross-section.

[0172] As shown, the inner ring portion 181 has a substantially linear inner edge 811, a substantially linear outer edge 812, a substantially flat upper surface 813, and a substantially flat bottom surface 814. The inner ring portion 181 has a vertical height H1 extending from the bottom surface 814 to the upper surface 813 adjacent to the inner edge 811, and has a vertical height H2 extending from the bottom surface 814 to the upper surface 813 adjacent to the outer edge 812. Figures 5 to 7 , the inner edge 811 and the outer edge 812 are substantially vertical, and the upper surface 813 and the bottom surface 814 are substantially horizontal, so that the heights H1 and H2 are substantially equal.

[0173] As shown, the outer annular portion 182 has a substantially linear inner edge 821, a substantially linear outer edge 822, a substantially flat upper surface 823, and a substantially flat bottom surface 824. The outer annular portion 182 has a vertical height H3 extending from the bottom surface 824 to the upper surface 823 adjacent to the inner edge 821, and has a vertical height H4 extending from the bottom surface 824 to the upper surface 823 adjacent to the outer edge 822. Figures 5 to 7 , the inner edge 821 and the outer edge 822 are substantially vertical, and the upper surface 813 and the bottom surface 814 are substantially horizontal, so that the heights H3 and H4 are substantially equal.

[0174] In some embodiments, bottom surfaces 814 and 824 are coplanar, and heights H1 and H2 are greater than heights H3 and H4, such that upper surface 813 is located at a higher height above the focus ring than upper surface 823.

[0175] exist Figures 5 to 7 , the inner edge 811 and the outer edge 812 are spaced apart from each other by a radial width W1, and the inner edge 821 and the outer edge 822 are spaced apart from each other by a radial width W2. Further, the outer edge 812 and the inner edge 821 are spaced apart from each other by a radial width W3.

[0176] In some embodiments, width W1, width W2, and width W3 are independently at least 1 mm, at least 2 mm, at least 5 mm, at least 10 mm, at least 15 mm, at least 20 mm, at least 25 mm, at least 30 mm, at least 35 mm, at least 40 mm, at least 45 mm, at least 50 mm, at least 55 mm, at least 60 mm, at least 65 mm, at least 70 mm, at least 75 mm, at least 80 mm, at least 85 mm, at least 90 mm. In some embodiments, width W1 and width W2 are independently at most 2 mm, at most 5 mm, at most 10 mm, at most 15 mm, at most 20 mm, at most 25 mm, at most 30 mm, at most 35 mm, at most 40 mm, at most 45 mm, at most 50 mm, at most 55 mm, at most 60 mm, at most 65 mm, at most 70 mm, at most 75 mm, at most 80 mm, at most 85 mm, at most 90 mm, or at most 92 mm.

[0177] In some embodiments, the ratio of width W1 to width W2 is at least 1:20; at least 1:10; at least 1:9; at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; at least 8:1; at least 9:1; at least 10:1; or at least 20:1.

[0178] In some embodiments, the ratio of width W1 to width W2 is at most 1:20; at most 1:10; at most 1:9; at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; at most 8:1; at most 9:1; at most 10:1; or at most 20:1.

[0179] In some embodiments, the ratio of width W1 to width W3 is at least 1:20; at least 1:10; at least 1:9; at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; at least 8:1; at least 9:1; at least 10:1; or at least 20:1.

[0180] In some embodiments, the ratio of width W1 to width W3 is at most 1:20; at most 1:10; at most 1:9; at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; at most 8:1; at most 9:1; at most 10:1; or at most 20:1.

[0181] In some embodiments, the vertical height H1 and the vertical height H4 are independently at least 1 mm, at least 2 mm, at least 3 mm, at least 4 mm, at least 5 mm, at least 6 mm, at least 7 mm, at least 8 mm, at least 9 mm, at least 10 mm, at least 11 mm, at least 12 mm, at least 13 mm, or at least 14 mm. In some embodiments, the vertical height H1 and the vertical height H4 are independently at most 2 mm, at most 3 mm, at most 4 mm, at most 5 mm, at most 6 mm, at most 7 mm, at most 8 mm, at most 9 mm, at most 10 mm, at most 11 mm, at most 12 mm, at most 13 mm, at most 14 mm, or at most 15 mm.

[0182] In some embodiments, the vertical height H2 and the vertical height H3 are independently at least 1 mm, at least 2 mm, at least 3 mm, at least 4 mm, at least 5 mm, at least 6 mm, at least 7 mm, at least 8 mm, at least 9 mm, at least 10 mm, at least 11 mm, at least 12 mm, at least 13 mm, at least 14 mm, at least 15 mm, at least 16 mm, at least 17 mm, at least 18 mm, at least 19 mm, at least 20 mm, at least 21 mm, at least 22 mm, at least 23 mm, at least 24 mm, at least 25 mm, at least 26 mm, at least 27 mm, at least 28 mm or at least 29 mm. In some embodiments, the vertical height H2 and the vertical height H3 are independently at most 2 mm, at most 3 mm, at most 4 mm, at most 5 mm, at most 6 mm, at most 7 mm, at most 8 mm, at most 9 mm, at most 10 mm, at most 11 mm, at most 12 mm, at most 13 mm, at most 14 mm, at most 15 mm, at most 16 mm, at most 17 mm, at most 18 mm, at most 19 mm, at most 20 mm, at most 21 mm, at most 22 mm, at most 23 mm, at most 24 mm, at most 25 mm, at most 26 mm, at most 27 mm, at most 28 mm, at most 29 mm or at most 30 mm.

[0183] Figures 8 to 9 An embodiment of a cover ring 180 having annular portions 181 and 182 interconnected by a bridge portion 900 is depicted. Figure 8 It is a stereogram. Fig. 9 It is a top view.

[0184] exist Figures 8 to 9 In the embodiment, at least one bridge portion 900 extends between and interconnects the outer edge 812 of the inner ring portion 181 and the inner edge 821 of the outer ring portion 182. In an exemplary embodiment, each bridge portion 900 extends radially from the outer edge 812 to the inner edge 821.

[0185] Although two bridge portions 900 are depicted, the cover ring 180 may include any suitable number of bridge portions 900. In some embodiments, the cover ring 180 has between one and thirty-two bridge portions 900. In some embodiments, the bridge portions 900 are equally spaced around the circumference of the cover ring 180.

[0186] In some embodiments, the bridge portion 900 is insulating. For example, the bridge portion can be a ceramic material, such as quartz, aluminum oxide, silicon nitride or other suitable materials. In some embodiments, the bridge portion 900, the inner ring portion 181 and the outer ring portion 182 are formed as a single piece, i.e., monolithic. In some embodiments, the bridge portion 900 is conductive. For example, the bridge portion can be a metal material, a semiconductor material such as doped or undoped silicon, or another material.

[0187] Fig.10 Provides along Figure 5 A cross-sectional view of the inner ring portion 181 or the outer ring portion 182 (individually referred to as the annular portion 1000) taken along line 7-7 in FIG. Fig.10 , the annular portion 1000 extends along an overall radial width W5 from a first annular edge 1001 to a second annular edge 1002. In some embodiments, the first edge 1001 is an inner annular edge and the second edge 1002 is an outer annular edge.

[0188] As shown, annular portion 1000 extends along an overall vertical height H6 from bottom surface 1003 to upper surface 1004. In some embodiments, height H6 can be 1 mm to 30 mm, such as within the range disclosed above for height H2 or H3.

[0189] As shown, the annular portion 1000 has a concave polygonal shape and includes an upper portion 1010 and a lower portion 1020. The upper portion 1010 extends downward from the upper surface 1004 along a vertical height H7 to a surface 1013. Therefore, the first edge 1001 can have a length equal to the vertical height H7. Moreover, the upper portion 1010 extends inwardly from the edge 1001 to the surface 1021.

[0190] Lower portion 1020 extends inwardly from edge 1002 along radial width W7 to surface 1021. Thus, bottom surface 1003 may have a length equal to radial width W7. In addition, lower portion 1020 extends upwardly from surface 1003 to surface 1013 along vertical height H8. Thus, surface 1021 may have a length equal to height H8.

[0191] As further shown, annular portion 1000 includes angled surface 1009 interconnecting edge 1002 and upper surface 1004. Edge 1002 extends from surface 1003 to angled surface 1009 along vertical height H9. Surface 1004 extends from edge 1001 to angled surface 1009 along radial width W6.

[0192] As shown, the total height H6 is equal to the sum of the height H7 and the height H8. In some embodiments, the ratio of height H7 to height H8 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of height H7 to height H8 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0193] exist Fig.10 In some embodiments, the ratio of width W7 to height H7 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of width W7 to height H7 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0194] exist Fig.10In some embodiments, the ratio of height H8 to height H9 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of height H8 to height H9 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0195] exist Fig.10 In some embodiments, the ratio of width W6 to width W7 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of width W6 to width W7 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0196] exist Fig.10In some embodiments, the ratio of width W5 to height H6 is at least 1:8; at least 1:7; at least 1:6; at least 1:5; at least 1:4; at least 1:3; at least 1:2; at least 2:3; at least 3:4; at least 5:6; at least 1:1; at least 6:5; at least 4:3; at least 3:2; at least 2:1; at least 3:1; at least 4:1; at least 5:1; at least 6:1; at least 7:1; or at least 8:1. In some embodiments, the ratio of width W5 to height H6 is at most 1:8; at most 1:7; at most 1:6; at most 1:5; at most 1:4; at most 1:3; at most 1:2; at most 2:3; at most 3:4; at most 5:6; at most 1:1; at most 6:5; at most 4:3; at most 3:2; at most 2:1; at most 3:1; at most 4:1; at most 5:1; at most 6:1; at most 7:1; or at most 8:1.

[0197] In some embodiments, the lower portion 1020 of the annular portion 1000 is located within a groove formed in the focus ring 170 , or is located outside the focus ring 170 , such as against an outer edge of the focus ring 170 .

[0198] In some embodiments, Figures 1 to 10 The apparatus and components are configured to hold and process wafers 105 having a diameter of 100 mm, 150 mm, 200 mm, or 300 mm, or other desired diameter.

[0199] As described herein, the cover ring 180 is provided with an annular gap 80 having a desired width W3. The gap 80 extends from an outer edge 812 of an inner ring portion 181 having a desired height H2 to an inner edge 821 of an outer ring portion 182 having a desired height H3. The inner ring portion 181 has an inner edge 811 having a desired height H1, and the outer ring portion 182 has an outer edge 822 having a desired height H4. Each dimension of the cover ring 180 can be optimized to provide a desired focus ring exposure area 129 and electric field to affect the plasma sheath 126 and change the flow direction of the ions 127. As a result, the cover ring 180 can reduce or eliminate tilt angle issues and via-to-metal overlap, particularly at a wafer radius of 130 to 145 mm for a wafer with a radius of 150 mm.

[0200] Therefore, one embodiment of the present disclosure describes an etching device, which includes a chamber configured to receive a wafer for an etching process; a conductive focusing ring disposed in the chamber, which is configured to focus an electric field to control the etching direction of the etching process; and an insulating cover ring disposed in the chamber, wherein the insulating cover ring is configured to change the electric field, wherein the insulating cover ring has an inner ring insulating portion and an outer ring insulating portion, and wherein a gap is defined between the inner ring insulating portion and the outer ring insulating portion.

[0201] In some embodiments of this device, the conductive focusing ring has an inner ring surface adjacent to the inner edge, an outer ring surface adjacent to the outer edge, and a center ring surface located between the inner ring surface and the outer ring surface; an inner ring insulating portion located above the inner ring surface; and an outer ring insulating portion located above the outer ring surface.

[0202] In some embodiments of the device, the outer ring insulating portion extends radially beyond the outer edge.

[0203] In some embodiments of the device, the inner ring insulating portion has a radial width of 1 to 92 mm; and the outer ring insulating portion has a radial width of 1 to 92 mm.

[0204] In some embodiments of this device, the vertical height of the inner edge of the inner ring insulating portion is 1 to 15 mm; the vertical height of the outer edge of the inner ring insulating portion is 1 to 30 mm; the vertical height of the inner edge of the outer ring insulating portion is 1 to 30 mm; and the vertical height of the outer edge of the outer ring insulating portion is 1 to 15 mm.

[0205] In some embodiments of the device, the insulating cover ring further includes a plurality of bridge portions interconnecting the inner ring insulating portion and the outer ring insulating portion, wherein the bridge portions are insulated.

[0206] In some embodiments of the device, the insulating cover ring further includes a plurality of bridge portions interconnecting the inner ring insulating portion and the outer ring insulating portion, wherein the bridge portions are conductive.

[0207] In some embodiments of the device, the inner ring insulating portion and the outer ring insulating portion are unconnected and independent of each other.

[0208] In another embodiment of the present disclosure, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber; an electrostatic chuck disposed in the chamber, the electrostatic chuck configured to support a wafer during a plasma processing process performed on the wafer; a focus ring disposed in the chamber and surrounding a portion of the electrostatic chuck, wherein the focus ring has an inner portion adjacent to an inner edge of the focus ring and an outer portion adjacent to an outer edge of the focus ring; an inner shield located above the inner portion of the focus ring; and an outer shield located above the outer portion of the focus ring.

[0209] In some embodiments of the plasma etching apparatus, the focus ring is configured to control the direction of ions in a plasma treatment process; and the inner shield and the outer shield are configured to modify the control of the direction of the ions in the plasma treatment process.

[0210] In some embodiments of the plasma etching apparatus, each shield has a lower surface and an upper surface, wherein the electrostatic chuck has an upper surface defined as a plane, and wherein the plane is located between the lower surface and the upper surface of each shield.

[0211] In some embodiments of the plasma etching apparatus, the electrostatic chuck is configured to support the wafer during a plasma treatment process performed on the wafer so that an upper surface of the wafer is located in a first plane, and wherein the inner shield and the outer shield have a plurality of uppermost surfaces located between the first plane and the electrostatic chuck or coplanar with the first plane.

[0212] In some embodiments of the plasma etching apparatus, the outer ring insulating portion extends radially beyond the outer edge.

[0213] In some embodiments of the plasma etching apparatus, the inner ring insulating portion has a radial width of 1 to 92 millimeters (mm); and the outer ring insulating portion has a radial width of 1 to 92 mm.

[0214] In some embodiments of the plasma etching apparatus, the vertical height of the inner edge of the inner shield is 1 to 15 millimeters (mm); the vertical height of the outer edge of the inner shield is 1 to 30 mm; the vertical height of the inner edge of the outer shield is 1 to 30 mm; and the vertical height of the outer edge of the outer shield is 1 to 15 mm.

[0215] In some embodiments, the plasma etching apparatus further comprises a plurality of bridges interconnecting the inner shield and the outer shield, wherein the bridges are insulated.

[0216] In some embodiments, the plasma etching apparatus further comprises a plurality of bridges interconnecting the inner shield and the outer shield, wherein the bridges are conductive.

[0217] In some embodiments of the plasma etching apparatus, the inner shield and the outer shield are not connected and are independent of each other.

[0218] In another embodiment of the present disclosure, a method for plasma processing is provided. A wafer is placed on an electrostatic chuck in a plasma chamber, the plasma chamber comprising a focus ring and a cover ring, wherein the focus ring surrounds a portion of the electrostatic chuck, and wherein the cover ring is located above the focus ring. Plasma in the plasma chamber is excited. An ion flow is directed toward the wafer by biasing the focus ring with a DC power source to form an electric field. The electric field is altered with the cover ring, wherein an inner portion of the focus ring is shielded by the cover ring, a middle portion of the focus ring is not shielded by the cover ring, and an outer portion of the focus ring is shielded by the cover ring.

[0219] In some implementations of the method, an inner portion of the focus ring is obscured by an inner ring portion of the cover ring, and an outer portion of the focus ring is obscured by an outer ring portion of the cover ring.

[0220] In some implementations of the method, a middle portion of the focus ring is not blocked by the cover ring.

[0221] In some embodiments, the method further includes determining a design of the cover ring to modify the electric field of the focus ring to reduce or eliminate via tilt.

[0222] In another embodiment of the present disclosure, a plasma processing apparatus is provided, which includes an electrostatic chuck, a focus ring, and a cover ring. The electrostatic chuck is disposed in a chamber, and the electrostatic chuck is configured to support a wafer. The focus ring is disposed in the chamber, and the focus ring surrounds a portion of the electrostatic chuck. The cover ring is disposed in the chamber and is located above the focus ring, and the cover ring is configured to change an electric field. The cover ring has an inner ring insulating portion and an outer ring insulating portion, and a gap is defined between the inner ring insulating portion and the outer ring insulating portion.

[0223] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the various embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the various embodiments of the present disclosure, and that they can make various changes, substitutions, and replacements herein without departing from the spirit and scope of the various embodiments of the present disclosure.

Claims

1. A plasma processing device, characterized in that: Include: a chamber for receiving a wafer for an etching process; a conductive focusing ring disposed in the chamber and used to focus an electric field to control an etching direction of the etching process; as well as An insulating cover ring is disposed in the chamber, wherein the insulating cover ring is used to change the electric field, wherein the insulating cover ring has an inner ring insulating portion and an outer ring insulating portion, and wherein a gap is defined between the inner ring insulating portion and the outer ring insulating portion.

2. The plasma processing device according to claim 1, characterized in that: in: The conductive focusing ring has an inner ring surface adjacent to an inner edge, an outer ring surface adjacent to an outer edge, and a central ring surface located between the inner ring surface and the outer ring surface; The inner ring insulating portion is located above the inner ring surface; and The outer ring insulating portion is located above the outer ring surface.

3. The plasma processing device according to claim 2, characterized in that: The outer ring insulating portion radially extends beyond the outer edge.

4. The plasma processing device according to any one of claims 1 to 3, characterized in that: in: The inner annular insulating portion has a radial width of 1 to 92 mm; and The outer annular insulating portion has a radial width of 1 to 92 mm.

5. The plasma processing device according to any one of claims 1 to 3, characterized in that: in: A vertical height of an inner edge of the inner ring insulating portion is 1 to 15 mm; A vertical height of an outer edge of the inner ring insulating portion is 1 to 30 mm; A vertical height of an inner edge of the outer ring insulating portion is 1 to 30 mm; and A vertical height of an outer edge of the outer ring insulating portion is 1 to 15 mm.

6. A plasma processing device, characterized in that: Include: One chamber; An electrostatic chuck is disposed in the chamber, and the electrostatic chuck is used to support a wafer during a plasma treatment process performed on the wafer; a focus ring disposed within the chamber and surrounding a portion of the electrostatic chuck, wherein the focus ring has an inner portion adjacent to an inner edge of the focus ring and an outer portion adjacent to an outer edge of the focus ring; an inner shield positioned over the inner portion of the focus ring; as well as An outer shield is positioned over the outer portion of the focus ring.

7. The plasma processing device according to claim 6, characterized in that: Each shield has a lower surface and an upper surface, the electrostatic chuck has an upper surface defined as a plane, and the plane is located between the lower surface and the upper surface of each shield.

8. The plasma processing device according to claim 6 or 7, characterized in that: The outer shield extends radially beyond the outer edge.

9. The plasma processing device according to claim 6 or 7, characterized in that: in: A vertical height of an inner edge of the inner shield is 1 to 15 mm; A vertical height of an outer edge of the inner shield is 1 to 30 mm; A vertical height of an inner edge of the outer shield is 1 to 30 mm; and A vertical height of an outer edge of the outer shield is 1 to 15 mm.

10. A plasma processing device, characterized in that: Include: An electrostatic chuck is disposed in a chamber, and the electrostatic chuck is configured to support a wafer; a focusing ring disposed in the chamber and surrounding a portion of the electrostatic chuck; as well as A cover ring is arranged in the chamber and above the focusing ring, and the cover ring is used to change an electric field, wherein the cover ring has an inner ring insulating part and an outer ring insulating part, and wherein a gap is defined between the inner ring insulating part and the outer ring insulating part.

Images