Packaging module and packaging structure

Abstract

The utility model provides a packaging module and a packaging structure. The packaging module comprises an intermediate layer; a plurality of semiconductor dies on the interposer and including a semiconductor die upper surface; an upper molding material layer on the plurality of semiconductor dies and including a recessed upper surface recessed from the upper surfaces of the semiconductor dies; and a back metal layer on the recessed upper surface of the upper molding material layer.

Description

Technical Field

[0001] The embodiments of the utility model relate to a packaging module and a packaging structure. Background Art

[0002] A typical packaging module may include a plurality of semiconductor dies and an upper molding material layer surrounding the semiconductor dies. The upper surface of the upper molding material layer may be ground down (e.g., chemical mechanical polishing (CMP)) to make the upper surface of the upper molding material layer coplanar with the upper surface of the semiconductor dies. Then, a packaging structure including these packaging modules may be formed without a lid (e.g., a lidless packaging structure) to facilitate heat dissipation from the packaging module. Utility Model Content

[0003] An embodiment of the present invention provides a packaging module, comprising: an interposer; a plurality of semiconductor grains located on the interposer and including an upper surface of the semiconductor grains; an upper molding material layer located on the plurality of semiconductor grains and including a recessed upper surface recessed from the upper surface of the semiconductor grains; and a back metal layer located on the recessed upper surface of the upper molding material layer.

[0004] An embodiment of the present invention provides a packaging structure, comprising: a packaging substrate; a packaging module, located on the packaging substrate, comprising: an intermediate layer; a plurality of semiconductor grains, located on the intermediate layer and comprising an upper surface of the semiconductor grains; an upper molding material layer, located on the plurality of semiconductor grains and comprising a recessed upper surface recessed from the upper surface of the semiconductor grains; and a back metal layer, located on the recessed upper surface of the upper molding material layer; and one of a packaging cover or a reinforcement ring, located on the packaging module. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A is a vertical cross-sectional view of a package module according to one or more embodiments.

[0007] Figure 1B is a plan view (eg, top view) of a package module according to one or more embodiments.

[0008] Figure 1C is a vertical cross-sectional view of a detailed portion of a package module according to one or more embodiments.

[0009] Figure 2Ais a vertical cross-sectional view of an intermediate structure including a portion of an interposer redistribution layer (RDL) portion (eg, an organic interposer) formed on a first carrier substrate (eg, a carrier wafer) in accordance with an embodiment of the present invention.

[0010] Figure 2B is a vertical cross-sectional view of an intermediate structure including a local silicon interconnect (LSI) die in accordance with one or more embodiments.

[0011] Figure 2C is a vertical cross-sectional view of an intermediate structure including a layer of molding material according to one or more embodiments.

[0012] Figure 2D is a vertical cross-sectional view of an intermediate structure including a first semiconductor die, a second semiconductor die, a fourth semiconductor die, and a fifth semiconductor die on a molded portion of an interposer according to one or more embodiments.

[0013] Figure 2E is a vertical cross-sectional view of an intermediate structure including an underfill layer of a package module according to one or more embodiments.

[0014] Figure 2F A vertical cross-sectional view of an intermediate structure including an upper molding material layer is shown in accordance with one or more embodiments.

[0015] Figure 2G A vertical cross-sectional view of an intermediate structure including a plurality of controlled collapse chip connect (C4) bumps and an integrated passive device (IPD) is shown in accordance with one or more embodiments.

[0016] Figure 2H is a vertical cross-sectional view of an intermediate structure including a recessed upper surface according to one or more embodiments.

[0017] Figure 3 is a flow chart illustrating a method of forming a package module according to one or more embodiments.

[0018] Figure 4 is a vertical cross-sectional view of a package module having a first alternative design according to one or more embodiments.

[0019] Figure 5A is a plan view of a first alternative design (eg, pattern) of a back metal layer according to one or more embodiments.

[0020] Figure 5B is a plan view of a second alternative design of a back metal layer in accordance with one or more embodiments.

[0021] Figure 6 is a vertical cross-sectional view of a package structure according to one or more embodiments.

[0022] Figure 7 is a vertical cross-sectional view of a package structure having a first alternative design according to one or more embodiments.

[0023] Figure 8 is a vertical cross-sectional view of a package structure having a second alternative design according to one or more embodiments.

[0024] Fig. 9 is a vertical cross-sectional view of a package structure having a third alternative design according to one or more embodiments.

[0025] Fig. 10A is a plan view of an adhesive layer having a first design pattern according to one or more embodiments.

[0026] Fig. 10B is a plan view of an adhesive layer having a second design pattern according to one or more embodiments.

[0027] Fig.11A is a vertical cross-sectional view of a package structure having a fourth alternative design according to one or more embodiments.

[0028] Fig. 11B is a plan view (ie, top view) of a package structure having a fourth alternative design according to one or more embodiments.

[0029] Fig.12 is a vertical cross-sectional view of a package structure having a fifth alternative design according to one or more embodiments.

[0030] Fig.13 is a vertical cross-sectional view of a package structure having a sixth alternative design according to one or more embodiments.

[0031] Fig.14 is a vertical cross-sectional view of a package structure having a seventh alternative design according to one or more embodiments.

[0032] Fig.15 is a plan view of a third alternative design of a back side metal layer in accordance with one or more embodiments.

[0033] Fig.16 is a plan view of an adhesive layer having a third design pattern according to one or more embodiments. DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments or examples to implement different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0035] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to have the same material composition and have a thickness within the same thickness range.

[0036] Package structures including typical package modules (e.g., lidless package structures) may experience warpage control issues. The high temperatures to which the package structures may be exposed, along with various materials having different coefficients of thermal expansion (CTE), may cause warpage and stress on components of the package structures. In particular, the package structures may experience board level process yield loss and reliability issues due to high warpage. Structures such as stiffener rings and lids may mitigate warpage.

[0037] Package structures may also experience thermal dissipation issues and, therefore, require thermal interface materials (TIMs) with high thermal conductivity (high dielectric constant (k)). These issues may be particularly problematic for packages targeting high performance computing (HPC) products. As described above, structures such as stiffeners and lids can mitigate warpage. However, the use of structures such as lids may hinder heat dissipation. Therefore, solutions are needed to mitigate warpage and / or improve heat dissipation so that using a lid that improves warpage characteristics does not affect heat dissipation.

[0038] One or more embodiments of the present disclosure may include a packaging module that can solve a typical packaging structure (e.g., chip on wafer on substrate, In at least one embodiment, the package module may include a molding-based interposer including a local silicon interconnect (LSI) chip for connecting semiconductor dies in the package structure.

[0039] In one or more embodiments, the packaging module may include an interposer, the interposer including an interposer redistribution layer (RDL) portion and an interposer molding portion located on the interposer RDL portion. The packaging module may also include a plurality of semiconductor dies located on the interposer. The packaging module may also include an upper molding material layer surrounding the semiconductor dies. Compared to a typical packaging structure in which an upper surface of the upper molding material layer (e.g., located between the semiconductor dies) is coplanar with an upper surface of the semiconductor dies, in the present disclosure, the upper surface of the upper molding material layer may not be coplanar with an upper surface of the semiconductor dies.

[0040] In one or more embodiments, the package module may also include one or more dummy dies mounted on the interposer. The upper molding material layer may be formed around the dummy dies. The dummy dies may contribute to the mechanical stability of the package module.

[0041] In one or more embodiments, the upper molding material layer may include a recessed upper surface recessed from the upper surfaces of the plurality of semiconductor grains. Specifically, the height of the upper surface of the upper molding material layer may be less than the height of the upper surface of the semiconductor grains. In at least one embodiment, the recessed upper surface is formed between the semiconductor grains. The package module may also include a backside metal (BSM) layer located on the recessed upper surface of the upper molding material layer.

[0042] Compared to other packaging modules, the various embodiments of the packaging modules disclosed herein may include a recessed upper surface of an upper molding material layer (e.g., epoxy molding compound (EMC)). The various embodiments of the packaging modules may also include a BSM layer located on the semiconductor die and on the recessed upper surface of the upper molding material layer located between the semiconductor die. In at least one embodiment, the BSM layer may be formed on the recessed upper surface of the upper molding material layer located outside the semiconductor die. The recessed upper surface may increase the surface area of ​​a heat dissipation material such as a BSM layer so that the heat dissipation characteristics are improved, thereby allowing the use of a cover to help control warping. In this way, the features of the embodiments disclosed herein may enable the packaging module to avoid warping control problems and heat dissipation problems.

[0043] Therefore, the features of various embodiments disclosed herein (e.g., the combination of the recessed upper surface of the upper molding material layer and the BSM layer located on the semiconductor die and the recessed upper surface) can improve the heat dissipation characteristics of the package module. Although the use of a lid may result in reduced heat dissipation, this improved heat dissipation can make the package module more capable of incorporating a lid structure to improve warpage characteristics.

[0044] One or more embodiments may include a packaging structure including a packaging module. In such an embodiment, a TIM layer may be positioned on a BSM layer located on a recessed upper surface of an upper molding material layer. A packaging cap may be positioned on the upper molding material layer above the TIM layer. The packaging cap may be attached to the packaging module by adhesive walls around the area of ​​the semiconductor die and adhesive feet around the edge of the packaging structure. Specifically, the packaging cap may be attached to the upper surface (e.g., the recessed upper surface) of the BSM layer and / or the upper molding material layer. The BSM layer may have different patterns in a plan view (e.g., a top view). The adhesive walls and adhesive feet may also have different patterns in a plan view.

[0045] The package structure may include several features that are different from typical package structures. In such an embodiment, the package structure may include a package cover, a TIM layer, an adhesive, and a BSM layer. The package structure may have different configurations with different BSM layer patterns and / or adhesive patterns. The package structure may also include a recessed upper surface of an upper molding material layer (e.g., epoxy molding compound (EMC)). The features of the package structure may help reduce package warpage and may provide a current tool for on substrate (oS) loops.

[0046] The package structure may have a variety of different configurations. In at least one embodiment, the package structure may have different configurations that vary with the selected manufacturing method. In at least one embodiment, the package structure may have a first configuration in which the package substrate is bonded to the interposer wafer and then singulated into a complete unit. In at least one embodiment, the package structure may have a second configuration different from the first configuration, in which the package module is singulated and then bonded to the package substrate.

[0047] The packaging structures of various embodiments may provide several advantages over other packaging structures. Specifically, the packaging structures of various embodiments may provide better warpage control. For example, the packaging structures of various embodiments may have improved heat dissipation characteristics, which will enable the use of a packaging cap in the packaging structure. As described above, although the packaging cap can improve warpage control, the use of the packaging cap may not be conducive to heat dissipation. Therefore, the packaging structures of various embodiments may also provide good heat dissipation. For example, by recessing the upper surface of the upper molding material layer, the total upper surface area of ​​the upper molding material layer may be increased due to the grooves and sidewall surfaces that may be formed in the subsequently deposited BSM layer located above the semiconductor grains and the recessed surface. In addition, the use of a thermally conductive BSM layer may also improve the heat dissipation characteristics of the embodiment packaging structure.

[0048] Figure 1A is a vertical cross-sectional view of a packaging module 120 according to one or more embodiments. Figure 1B is a plan view (eg, top view) of a packaging module 120 according to one or more embodiments. Figure 1A The vertical cross-section view is along Figure 1B The package module 120 may include a first group of semiconductor die on the interposer 5, including a first semiconductor die 141, a second semiconductor die 142 and a third semiconductor die 143 (see Figure 1B The packaging module 120 may also include a second set of semiconductor die on the interposer 5, including a fourth semiconductor die 144, a fifth semiconductor die 145, and a sixth semiconductor die 146 (see Figure 1BThe first semiconductor grain 141, the second semiconductor grain 142, the third semiconductor grain 143, the fourth semiconductor grain 144, the fifth semiconductor grain 145, and the sixth semiconductor grain 146 may be collectively referred to as semiconductor grains 140 (see Figure 1B ).

[0049] Although the packaging module 120 is shown as including a specific number of semiconductor dies with a specific arrangement, the number of semiconductor dies and the arrangement of semiconductor dies are not limited to any specific number and arrangement. Specifically, the packaging module 120 may include any number and any arrangement of semiconductor dies and any number and any arrangement of semiconductor dies.

[0050] The interposer 5 is not necessarily limited to any particular material or configuration. The interposer 5 may include, for example, an organic material (eg, a dielectric polymer), an inorganic material (eg, silicon), a glass substrate, etc. In at least one embodiment, Figure 1A As shown, the interposer 5 may include an interposer RDL portion 10 and an interposer molding portion 20 located on the interposer RDL portion 10 .

[0051] In at least one embodiment, the interposer RDL portion 10 may include a plurality of polymer layers 12 and a plurality of redistribution layers 12a stacked alternately. The number of polymer layers 12 and / or the number of redistribution layers 12a in the interposer RDL portion 10 is not limited by the present disclosure.

[0052] In at least one embodiment, the polymer layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layer 12a may include a conductive material. The conductive material may include metals such as copper, aluminum, nickel, titanium, or combinations thereof. Other suitable conductive materials may also be within the scope of the present disclosure.

[0053] The redistribution layer 12a may include a metallic connection structure, i.e., a metallic structure that provides electrical connection between nodes in the structure. The redistribution layer 12a may include a metallic seed layer and a metallic filling material on the metallic seed layer. The metallic seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness in the range of 50 nanometers to 500 nanometers, and the copper seed layer may have a thickness in the range of 50 nanometers to 500 nanometers, but a smaller or larger thickness may also be used. The metallic filling material of the redistribution layer 12a may include copper, nickel, or copper and nickel. Other suitable metallic filling materials are also within the scope of the present disclosure. The thickness of the metallic filling material deposited for each redistribution layer 12a may be in the range of 2 microns to 40 microns (e.g., 4 microns to 10 microns), but a smaller or larger thickness may also be used.

[0054] In at least one embodiment, the redistribution layer 12a may include a plurality of traces (lines) and a plurality of vias connecting the plurality of traces to each other. Each trace may be located on the polymer layer 12, and may extend in the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the polymer layer 12.

[0055] An upper passivation layer 13 may be formed on the chip-side surface of the interposer RDL portion 10. The upper passivation layer 13 may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0056] One or more interposer upper bonding pads 13a may be formed in the upper passivation layer 13 located on the chip side surface of the interposer RDL portion 10. The upper passivation layer 13 may at least partially cover the interposer upper bonding pads 13a. That is, the interposer upper bonding pads 13a may be at least partially exposed on the chip side surface of the interposer RDL portion 10. The interposer upper bonding pads 13a may be connected to the redistribution layer 12a. The interposer upper bonding pads 13a may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0057] A lower passivation layer 14 may be formed on the board side surface of the interposer RDL portion 10. The lower passivation layer 14 may also include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0058] One or more interposer lower bonding pads 14a may be positioned on the board side surface of the interposer RDL portion 10. The interposer lower bonding pads 14a may be bonded to and electrically connected to the redistribution layer 12a. The interposer lower bonding pads 14a may be located in the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the interposer lower bonding pads 14a. That is, the interposer lower bonding pads 14a may be at least partially exposed on the board side surface of the interposer RDL portion 10. The interposer lower bonding pads 14a may also include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0059] One or more integrated passive devices (IPDs) 30 may also be positioned on the board side surface of the interposer RDL portion 10. The IPD 30 may be bonded to and electrically connected to the redistribution layer 12a. The IPD 30 may be located in the lower passivation layer 14. The IPD 30 may include an exposed portion protruding from the lower passivation layer 14. The IPD 30 may include one or more electronic components such as a resistor, a capacitor, an inductor, a coil, a choke, a microstripline, an impedance matching component, a balun, etc. The IPD 30 may be electrically coupled to the semiconductor die 140 via the interposer 5.

[0060] like Figure 1A As further shown in , a plurality of controlled collapse chip connection (C4) bumps 121 may be respectively connected to the interposer lower bonding pads 14a located on the board side surface of the interposer RDL portion 10. In at least one embodiment, the C4 bumps 121 may include an underbump metallurgy (UBM) layer located on the interposer lower bonding pads 14a. The C4 bumps 121 may also include contact pads (e.g., copper / nickel contact pads) located on the UBM layer and solder bumps (e.g., SnAg solder bumps) located on the contact pads. The C4 bumps 121 may enable the package module 120 to be connected to a substrate such as a package substrate.

[0061] The interposer molding portion 20 may have a length in the x-direction substantially the same as a length in the x-direction of the interposer RDL portion 10. The interposer molding portion 20 may have a width in the y-direction substantially the same as a width in the y-direction of the interposer RDL portion 10. The interposer molding portion 20 may have a thickness in the z-direction that is smaller than a thickness of the interposer RDL portion 10.

[0062] The interposer molding portion 20 may include a molding material layer 227 (e.g., an encapsulation layer) formed on the upper passivation layer 13 of the interposer RDL portion 10. In at least one embodiment, the molding material layer 227 may be formed of a curable material that can be cured to form a hard solid structure. The molding material layer 227 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the molding material layer 227 may include a polymeric material and, in particular, an epoxy-based polymeric material. Other suitable molding materials may also be used.

[0063] In at least one embodiment, the molding material layer 227 may have a coefficient of thermal expansion (CTE) substantially similar to that of the interposer RDL portion 10. In at least one embodiment, the molding material layer 227 may include an added material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the molding material layer 227. The added material may include, for example, metal powder, metal oxide powder, etc. Other materials in the molding material layer 227 are also within the scope of the present disclosure.

[0064] The interposer molding portion 20 of the interposer 5 may also include one or more local silicon interconnect (LSI) dies 200a, 200b, 200c. A molding material layer 227 may be formed around the LSI dies 200a, 200b, 200c in the x-direction and the y-direction. In at least one embodiment, the LSI dies 200a, 200b, 200c may be substantially embedded in the molding material layer 227.

[0065] The LSI die 200a, 200b, 200c may be mounted on the interposer RDL portion 10. The LSI die 200a, 200b, 200c may be bonded to the interposer RDL portion 10, for example, by a "hybrid" bonding including oxide-oxide bonding and metal-metal bonding. Specifically, the LSI die 200a, 200b, 200c may include a lower contact (not shown) bonded to the interposer upper bonding pad 13a in the interposer RDL portion 10. The LSI die 200a, 200b, 200c may be electrically connected to the interposer upper bonding pad 13a of the interposer RDL portion 10 through this.

[0066] The LSI die 200a, 200b, 200c may include one or more interconnect structures 204 (e.g., metal traces and metal vias) for interconnecting the semiconductor die in the package module 120. Specifically, the LSI die 200a may include a first semiconductor die 141 connected to the second semiconductor die 142 and the third semiconductor die 143 (see Figure 1B ) of one or more interconnect structures 204. The LSI die 200b may include one or more interconnect structures 204 for connecting the first semiconductor die 141 to the fourth semiconductor die 144. The LSI die 200c may include one or more interconnect structures 204 for connecting the fourth semiconductor die 144 to the fifth semiconductor die 145 and the sixth semiconductor die 146 (see Figure 1B )'s one or more inline structures 204.

[0067] In at least one embodiment, the plurality of interconnect structures 204 in each of the LSI dies 200a, 200b, 200c may provide high wiring density die-to-die interconnection by multi-level sub-micron metal (e.g., copper) lines. The interconnect structures 204 may enable the LSI dies 200a, 200b, 200c to adapt to a variety of different connection architectures (e.g., system on chip (SoC) to SoC, SoC to chiplet, SoC to high-bandwidth memory (HBM), etc.). The interconnect structures 204 may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0068] The interposer molding portion 20 may also integrate additional components such as a stand-alone IPD (not shown). In at least one embodiment, the IPD may be located in the molding material layer 227 below one or more of the first semiconductor die 141, the second semiconductor die 142, the third semiconductor die 143, the fourth semiconductor die 144, the fifth semiconductor die 145, and the sixth semiconductor die 146 to support signal communication.

[0069] The interposer molding portion 20 may also include one or more upper RDL layers 202a (e.g., metal traces) located on a chip-side surface (e.g., upper surface) of the interposer molding portion 20 (e.g., on an upper surface of the molding material layer 227). The interposer molding portion 20 may also include one or more lower RDL layers 202b located on a board-side surface (e.g., lower surface) of the interposer molding portion 20 (e.g., on an upper surface of the molding material layer 227). The interposer molding portion 20 may also include one or more through interposer vias (TIVs) 206 located in the molding material layer 227. The TIVs 206 may be connected to the interposer upper bonding pads 13a of the interposer RDL portion 10 and to the semiconductor die 140.

[0070] The upper RDL layer 202a and the lower RDL layer 202b may include a wide pitch and may be connected to each other by TIV 206 for efficient signal and power transmission. The upper RDL layer 202a, the lower RDL layer 202b and the TIV 206 may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure. With this configuration, the interposer molding portion 20 can provide low-loss high-frequency signals in high-speed transmission.

[0071] The semiconductor die 140 may be mounted on the interposer molding portion 20. In general, the thickness of each of the semiconductor die 140 in the z-direction may be substantially the same. Therefore, the upper surface of each of the first semiconductor die 141, the second semiconductor die 142, the third semiconductor die 143, the fourth semiconductor die 144, the fifth semiconductor die 145, and the sixth semiconductor die 146 may be substantially coplanar (e.g., formed in the same xy plane) and collectively referred to as semiconductor die upper surface 140 a (upper surface). In the case where the semiconductor die 140 includes non-coplanar upper surfaces, the semiconductor die upper surface 140 a may refer to the lowest upper surface among the upper surfaces of the semiconductor die 140.

[0072] The semiconductor die 140 may be mounted on the interposer molded portion 20, for example, by microbumps 128. The microbumps 128 may each include a copper post and a solder bump on the copper post. The microbumps 128 may be bonded (e.g., by solder bumps) to metal contacts on the chip side surface of the interposer molded portion 20. In at least one embodiment, the microbumps 128 may be bonded to the interconnect structures 204 in the LSI die 200a, 200b, 200c. In at least one embodiment, the microbumps 128 may be bonded to the TIV 206 in the interposer molded portion 20. In at least one embodiment, the microbumps 128 may be bonded to the upper RDL layer 202a on the chip side surface of the interposer molded portion 20. Therefore, the semiconductor die 140 may be connected to the redistribution layer 12a in the interposer RDL portion 10 via the microbumps 128.

[0073] A package module underfill layer 129 may be formed under and around each of the semiconductor dies 140 (e.g., individually or connectedly). The package module underfill layer 129 may also be formed around the micro bumps 128. The package module underfill layer 129 may thereby secure each of the semiconductor dies 140 to the interposer molding portion 20. The package module underfill layer 129 may be formed of an epoxy-based polymer material.

[0074] Each of the semiconductor dies 140 may include, for example, a monolithic semiconductor die, a system-on-chip (SOC) die, or a system on integrated chips (SoIC) die, and may be implemented by a chip-on-wafer-on-substrate (CoWoS) technology or an integrated fan-out on substrate (INFO-oS) technology. Specifically, each of the semiconductor dies 140 may include, for example, a semiconductor chip or chiplet for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and fifth-generation (5G) cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a high-bandwidth memory (HBM) die, a hybrid memory cube (HMC), a dynamic random access memory (DRAM) die, a wide input / output (I / O) die, a magnetic random access memory (M-RAM) die, a resistive random access memory (R-RAM) die, an AND (NAND) die, a static random access memory (SRAM), etc.), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a graphics processing unit (GPU). unit, GPU) chips, field-programmable gate array (FPGA) chips, network chips, application-specific integrated circuit (ASIC) chips, artificial intelligence / deep neural network (AI / DNN) accelerator chips, co-processors, accelerators, on-chip memory buffers, high data rate transceiver chips, I / O interface chips, integrated passive device (IPD) chips, power management chips (e.g., power management integrated circuit (PMIC) chips), radio frequency (RF) chips, etc.RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), monolithic 3D heterogeneous chiplet stacking die, etc. Other die are also within the scope of the present disclosure.

[0075] In at least one embodiment, the first semiconductor die 141 may include a primary die (e.g., a SOC die), and the second semiconductor die 142 and the third semiconductor die 143 may each include an ancillary die (e.g., a memory / SOC die, an HBM die, etc.). In at least one embodiment, the fourth semiconductor die 144 may include a primary die (e.g., a SOC die), and the fifth semiconductor die 145 and the sixth semiconductor die 146 may each include an ancillary die (e.g., a memory / SOC die, an HBM die, etc.).

[0076] The package module 120 may also include an upper molding material layer 127 formed around the semiconductor die 140. The upper molding material layer 127 may also be formed on and around the package module underfill layer 129. The upper molding material layer 127 may have an outer sidewall substantially aligned with an outer sidewall of the interposer 5.

[0077] In at least one embodiment, the upper molding material layer 127 may be formed on the sidewalls (inner and outer sidewalls) of each of the semiconductor dies 140. The upper molding material layer 127 may be formed between and bonded to the sidewalls of each of the semiconductor dies 140. The upper molding material layer 127 may also be bonded to the chip side surface of the interposer molding portion 20 and the package module underfill layer 129.

[0078] like Figure 1A As shown, the upper molding material layer 127 may include a substantially uniform (e.g., flat) upper surface. The upper surface of the upper molding material layer 127 may include a recessed upper surface 300 recessed from the semiconductor die upper surface 140a in the z-direction. In at least one embodiment, the recessed upper surface 300 may constitute the entire upper surface of the upper molding material layer 127. In at least one embodiment, the recessed upper surface 300 may constitute an upper surface smaller than the entire upper surface of the upper molding material layer 127.

[0079] The recessed upper surface 300 of the upper molding material layer 127 may include inner recessed surface portions 300a located between the semiconductor dies 140. The recessed upper surface 300 of the upper molding material layer 127 may also include outer recessed surface portions 300b located outside the semiconductor dies 140 in the horizontal direction, lateral direction, or xy direction.

[0080] In at least one embodiment, the upper molding material layer 127 may be formed of a curable material that can be cured to form a hard solid structure. The upper molding material layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the upper molding material layer 127 may include a material substantially similar to the package module bottom fill layer 129 and / or to the molding material layer 227 in the interposer molding portion 20. In at least one embodiment, the upper molding material layer 127 may include a polymeric material and, in particular, an epoxy-based polymeric material. Other suitable molding materials may also be within the scope of the present disclosure.

[0081] In at least one embodiment, the upper molding material layer 127 may have a CTE substantially similar to the CTE of the interposer molding portion 20 and / or the CTE of the interposer RDL portion 10. In at least one embodiment, the upper molding material layer 127 may include an additive material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the upper molding material layer 127. The additive material may include, for example, metal powder, metal oxide powder, etc. Other materials in the upper molding material layer 127 are also within the scope of the present disclosure.

[0082] The package module 120 may also include a back metal layer 400 located on the upper surface of the upper molding material layer 127. The back metal layer 400 may include an inner back metal layer portion 400a located on the inner recessed surface portion 300a of the recessed upper surface 300 of the upper molding material layer 127. The back metal layer 400 may also include an outer back metal layer portion 400b located on the outer recessed surface portion 300b of the recessed upper surface 300 of the upper molding material layer 127. The back metal layer 400 may also include a semiconductor die covering portion 400c located on the semiconductor die upper surface 140a of the semiconductor die 140. The back metal layer 400 may or may not include a semiconductor die sidewall covering portion 400d located on the sidewalls (e.g., the exposed sidewalls above the recessed upper surface 300) of each of the semiconductor die 140.

[0083] The back metal layer 400 may have a substantially uniform thickness throughout. In at least one embodiment, the back metal layer 400 may have a thickness in the range of 0.1 microns to 1.5 microns. In at least one embodiment, the thickness of the semiconductor grain sidewall covering portion 400d may be less than the thickness of the rest of the back metal layer 400. The back metal layer 400 may include, for example, one or more layers of metal materials, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. In at least one embodiment, the back metal layer 400 may include one or more layers of aluminum, titanium, nickel vanadium (NiV), and gold.

[0084] exist Figure 1B In FIG. 4 , hatching and dashed lines are used to indicate the location of semiconductor grains 140 that may be located below the back metal layer 400. Figure 1B As shown, the back metal layer 400 may be formed on substantially the entire upper surface of the package module 120 including the upper molding material layer 127 and the semiconductor die 140. Specifically, the back metal layer 400 may have a pattern in which the outer edge of the back metal layer 400 is substantially aligned with the outer edge of the upper molding material layer 127 located around the entire outer periphery of the package module 120.

[0085] Figure 1C is a vertical cross-sectional view of a portion of a packaging module 120 according to one or more embodiments. Specifically, Figure 1C An inner recessed surface portion 300a and an outer recessed surface portion 300b of the recessed upper surface 300 of the upper molding material layer 127 are shown. Figure 1C Also shown are an inner back metal layer portion 400a located on the inner recessed surface portion 300a and an outer back metal layer portion 400b located on the outer recessed surface portion 300b. Figure 1C Also shown are the semiconductor die covering portion 400 c located on the semiconductor die upper surface 140 a and the semiconductor die sidewall covering portion 400 d located on the sidewalls of the first semiconductor die 141 and the second semiconductor die 142 .

[0086] like Figure 1C As shown, the recessed upper surface 300 of the upper molding material layer 127 may have a substantially uniform height H1 (e.g., from the upper surface of the interposer molding portion 20). Specifically, the height H1 of the recessed upper surface 300 may be substantially the same for the inner recessed surface portion 300a and the outer recessed surface portion 300b. The semiconductor die upper surface 140a may have a substantially uniform height H2 (e.g., from the upper surface of the interposer molding portion 20) on all semiconductor die 140. Figure 1CAs shown, the height H2 of the semiconductor die upper surface 140a may be greater than the height H1 of the recessed upper surface 300. In at least one embodiment, the depth D1 (eg, H2-H1) of the recessed upper surface 300 from the semiconductor die upper surface 140a may be less than 10 micrometers.

[0087] The space between each of the semiconductor grains 140 may have a length L1 in the range of 1 micrometer to 5000 micrometers. The length L1 may also constitute the length of the inner recessed surface portion 300a of the recessed upper surface 300. The length L1 may also constitute the length of the inner back metal layer portion 400a.

[0088] In at least one embodiment, the semiconductor grain sidewall covering portion 400d may connect the semiconductor grain covering portion 400c to the inner back metal layer portion 400a. The length of the semiconductor grain sidewall covering portion 400d in the z direction may be substantially equal to the depth D1 (e.g., H2-H1) of the recessed upper surface 300 (e.g., less than about 10 microns). A plurality of gaps G may be formed between opposite faces of the semiconductor grain sidewall covering portion 400d of each of the semiconductor grains 140.

[0089] FIG. 2A to FIG. 2H Various intermediate structures are shown in a method of forming package module 120 according to one or more embodiments. Figure 2A 1 is a vertical cross-sectional view of an intermediate structure including a portion of an interposer RDL portion 10 (e.g., an organic interposer) formed on a first carrier substrate 1 (e.g., a carrier wafer) according to an embodiment of the present invention. The lower passivation layer 14 and the interposer lower bonding pad 14a of the interposer RDL portion 10 may be formed later in the method of forming the package module 120.

[0090] The first carrier substrate 1 may include a circular wafer or a rectangular wafer. The lateral dimension of the first carrier substrate 1 (e.g., the diameter of a circular wafer or one side of a rectangular wafer) may be in the range of 100 mm to 500 mm (e.g., 200 mm to 400 mm), although smaller or larger lateral dimensions may also be used. The first carrier substrate 1 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 1 may be transparent or opaque. The thickness of the first carrier substrate 1 may be sufficient to provide mechanical support for the array of interposers to be formed on the first carrier substrate 1. For example, the thickness of the first carrier substrate 1 may be in the range of 60 microns to 1 mm, although smaller or larger thicknesses may also be used.

[0091] An adhesive layer (not shown) may be applied to the top surface of the first carrier substrate 1. In one embodiment, the first carrier substrate 1 may include an optically transparent material such as glass or sapphire. In this embodiment, the adhesive layer may include a light-to-heat conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin coating method. The LTHC layer may form a layer that converts ultraviolet light into heat to cause the LTHC layer to lose adhesion. For example, the LTHC layer may include a commercially available light-to-heat conversion release coating (LTHC) ink. TM Alternatively, the adhesive layer may include a thermally decomposable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The peeling temperature of the thermally decomposable adhesive material may be in the range of 150° C. to 400° C. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of the present disclosure.

[0092] A plurality of dielectric layers 12 and a plurality of redistribution layers 12a may be alternately formed on the first carrier substrate 1 (eg, on an adhesive layer on the first carrier substrate 1). Figure 2A Three dielectric layers 12 and three redistribution layers 12 a are shown, but the present disclosure also encompasses more or less dielectric layers 12 and redistribution layers 12 a .

[0093] Each dielectric layer 12 may be formed, for example, by depositing (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques) a layer of dielectric polymer material (e.g., polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO)). Other suitable materials are also within the scope of the present disclosure. The thickness of the layer of dielectric polymer material may be in the range of 4 microns to 60 microns, but lesser or greater thicknesses may also be used. The dielectric layer 12 may then be patterned by a lithography process to form via holes in the dielectric layer 12. The lithography process may include: forming a patterned photoresist mask (not shown) on the layer of dielectric material, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the dielectric material exposed through the opening in the photoresist mask. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during an etching process.

[0094] Then, a redistribution layer 12a (e.g., metal traces and metal vias) may be formed on the dielectric layer 12. The redistribution layer 12a may be formed, for example, by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of metal material (e.g., copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 12 and in the via windows formed by patterning the dielectric layer 12. Then, the redistribution layer 12a may be patterned by a lithography process. The lithography process may include: forming a patterned photoresist mask (not shown) on the layer of metal material, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the metal material exposed through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0095] like Figure 2A As further shown in , then, an interposer upper bonding pad 13a may be formed on the uppermost dielectric layer 12. The interposer upper bonding pad 13a may include any metallic material that can be bonded to the solder material. The interposer upper bonding pad 13a may be formed by depositing one or more metal layers including metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.) (e.g., by CVD, PVD or other suitable deposition techniques). Then, the metal layer may be patterned by a lithography process to form the interposer upper bonding pad 13a. The lithography process may include: forming a patterned photoresist mask (not shown) on the metallic material, and etching the upper surface of the metallic material exposed through the opening in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0096] In at least one embodiment, the interposer upper bonding pad 13a may include an under bump metal (UBM) layer stack deposited on an adhesive layer. The order of the material layers within the UBM layer stack may be selected so that the solder material portion may be subsequently bonded to some portion of the bottom surface of the UBM layer stack. Layer stacks that may be used for the UBM layer stack include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the scope of the present disclosure. The thickness of the UBM layer stack may be in the range of 5 microns to 60 microns (e.g., 10 microns to 30 microns), but lesser or greater thicknesses may also be used. A photoresist layer may be applied over the UBM layer stack, and the photoresist layer may be lithographically patterned to form an array of discrete patterned photoresist material portions. An etching process may be performed to remove unshielded portions of the UBM layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The remaining portion of the UBM layer stack may form the interposer upper bonding pads 13a. In at least one embodiment, the interposer upper bonding pads 13a may be arranged in a two-dimensional array, which may be a two-dimensional periodic array such as a rectangular periodic array. In at least one embodiment, the interposer upper bonding pads 13a may be formed as a controlled collapse chip connection (C4) bump structure.

[0097] Then, an upper passivation layer 13 may be formed on the chip side surface of the interposer RDL portion 10 and on the interposer upper bonding pad 13a. The upper passivation layer 13 may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of passivation materials (including silicon oxide, silicon nitride, low dielectric constant dielectric materials such as carbon-doped oxides, very low dielectric constant dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials). Then, the passivation material may be planarized (e.g., by wet etching, dry etching, chemical mechanical polishing (CMP), etc.) to form the upper passivation layer 13.

[0098] Figure 2B200a, 200b, 200c according to one or more embodiments. The lower RDL layer 202b can be formed on the upper passivation layer 13 by a lithography process. Specifically, a metal layer can be deposited (e.g., by CVD, PVD or other suitable deposition processes) on the upper passivation layer 13. Then, the metal layer can be patterned by a lithography process to form the lower RDL layer 202b. The lithography process may include: forming a patterned photoresist mask (not shown) on the metal layer, and etching the upper surface of the metal layer exposed through the opening in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0099] Then, the TIV 206 may be formed in one or more electroplating processes. In one or more embodiments, a seed layer (not shown) may be formed on the upper passivation layer 13. Then, a metal material may be electroplated on the seed layer to form the TIV 206. The metal material used for electroplating may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0100] Then, the LSI dies 200a, 200b, 200c may be placed on the interposer RDL portion 10, for example, using an electromechanical pick-and-place (PNP) machine. Each of the LSI dies 200a, 200b, 200c may be bonded to, for example, the interposer RDL portion 10 including a corresponding subset of the interposer upper bonding pads 13a by a hybrid bonding process (e.g., metal-metal bonding, oxide-oxide bonding). It should be noted that the LSI dies 200a, 200b, 200c may be mounted on the interposer RDL portion 10 before or after forming the TIV 206.

[0101] Figure 2C2 is a vertical cross-sectional view of an intermediate structure including a molding material layer 227 according to one or more embodiments. The molding material layer 227 (e.g., an encapsulant layer) may be formed by a series of over-molding processes and planarization processes. Specifically, the molding material layer 227 may include an epoxy polymer material (e.g., an epoxy molding compound (EMC)). The molding material layer 227 may be formed on the interposer RDL portion 10 and fill the gaps between the LSI die 200a, 200b, 200c and the TIV 206. The molding material layer 227 may encapsulate the LSI die 200a, 200b, 200c and the TIV 206 (e.g., in the x-direction and the y-direction). The molding material layer 227 may be formed, for example, by a deposition process such as CVD, plasma enhanced CVD (PECVD), PVD, spin coating, lamination, or other suitable deposition techniques.

[0102] The molding material layer 227 may be deposited to completely cover the LSI die 200a, 200b, 200c and the TIV 206. After the molding material layer 227 has been cured, a planarization process may then be used to make the upper surface of the molding material layer 227 coplanar with the upper surfaces of the LSI die 200a, 200b, 200c and the upper surface of the TIV 206. Specifically, the planarization process may be performed on the upper surface of the molding material layer 227 until the upper surfaces of the LSI die 200a, 200b, 200c and the upper surface of the TIV 206 are exposed. The planarization process may include, for example, a mechanical grinding process and / or a CMP process. Then, the upper RDL layer 202a may be formed on the upper surface of the molding material layer 227 in a manner similar to the formation of the lower RDL layer 202b to complete the formation of the interposer molding portion 20.

[0103] Figure 2D is a vertical cross-sectional view of an intermediate structure including a first semiconductor die 141, a second semiconductor die 142, a fourth semiconductor die 144, and a fifth semiconductor die 145 located on an interposer molding portion 20 according to one or more embodiments. Figure 2D Although not shown, all of the semiconductor dies 140 (ie, the third semiconductor die 143 and the sixth semiconductor die 146 ) may be simultaneously mounted on the interposer molding portion 20 in the same process.

[0104] Each of the semiconductor dies 140 may be bonded to the interposer molding portion 20 by one or more microbumps 128. In at least one embodiment, the microbumps 128 may include a two-dimensional array of microbumps 128, and each of the semiconductor dies 140 may be attached to the interposer upper bonding pad 13a by C2 bonding (e.g., solder bonding). After the microbumps 128 on the semiconductor die 140 are disposed on the corresponding bonding pads in the upper surface of the interposer molding portion 20, a C2 bonding process of reflowing the solder portion of the microbumps 128 may be performed. Specifically, the microbumps 128 may be bonded to the interconnect structures 204 in the LSI dies 200a, 200b, 200c, the TIVs 206 in the interposer molding portion 20, and / or the upper RDL layer 202a on the chip side surface of the interposer molding portion 20.

[0105] Figure 2E is a vertical cross-sectional view of an intermediate structure including a package module bottom fill layer 129 according to one or more embodiments. The package module bottom fill layer 129 can be applied by depositing and / or injecting an epoxy-based polymer material onto the interposer mold portion 20. The epoxy-based polymer material can be applied to the interposer mold portion 20 to form below the semiconductor die 140 and around the microbumps 128. In at least one embodiment, the epoxy-based polymer material can fill substantially all gaps between the semiconductor die 140 and the interposer mold portion 20. The package module bottom fill layer 129 can then be cured, for example, in a box oven at about 150° C. for about 90 minutes to provide the package module bottom fill layer 129 with sufficient stiffness and mechanical strength.

[0106] Figure 2F FIG. 1 shows a vertical cross-sectional view of an intermediate structure including an upper molding material layer 127 according to one or more embodiments. The liquid molding material (eg, EMC, epoxy molding material) may be dispensed to the mold by a suitable dispensing tool. Figure 2E An upper molding material layer 127 is formed on the intermediate structure as shown. The upper molding material layer 127 can be dispensed on the intermediate structure to have a height greater than a height H2 of the upper surface 140a of the semiconductor die.

[0107] In at least one embodiment, the dispensing of the molding material may be automated. Specifically, various aspects of the dispensing process may be computer controlled by a control system (e.g., an electronic control system; a central processing unit (CPU)). In at least one embodiment, the start of the dispensing of the molding material, the flow rate of the dispensing of the molding material, and the stopping of the dispensing of the molding material may be controlled by the control system. For example, the control system may be programmed to dispense a predetermined amount of molding material based on various input parameters. The input parameters may include, for example, the volume of the space around the interposer molding portion 20, the size of the interposer molding portion 20, the size of the semiconductor die 140, etc.

[0108] In at least one embodiment, the molding material of the upper molding material layer 127 may include a capillary material (e.g., a capillary underfill type material). The molding material may have a low viscosity. Specifically, the viscosity may be less than about 5,000 centipoise (cP) at 10 revolutions per minute (rpm). In at least one embodiment, the molding material may include a low-viscosity suspension of a thermally conductive material (e.g., a metal, a metal oxide) in a prepolymer. The low viscosity may help facilitate the transport of the molding material around the semiconductor die 140. The low viscosity may also help avoid the formation of voids in the upper molding material layer 127. In at least one embodiment, the upper molding material layer 127 may be substantially free of voids.

[0109] After the upper molding material layer 127 has been sufficiently cured, the upper molding material layer 127 may be planarized so that the upper surface of the upper molding material layer 127 is substantially coplanar with the semiconductor die upper surface 140a. The upper molding material layer 127 may be planarized, for example, by grinding, chemical mechanical polishing (CMP), or other suitable planarization techniques.

[0110] Figure 2G FIG. 1 shows a vertical cross-sectional view of an intermediate structure including the plurality of C4 bumps 121 and the IPD 30 according to one or more embodiments. After the upper molding material layer 127 has been cured and planarized (eg, by grinding, CMP, etc.), the second carrier substrate 2 may be attached to the Figure 2F Specifically, the second carrier substrate 2 can be attached to the upper surface of the molding material layer 127 and the semiconductor die upper surface 140 a of the semiconductor die 140 .

[0111] Then, Figure 2FThe intermediate structure shown can be inverted and the first carrier substrate 1 can be detached from the lower polymer layer 12 of the interposer RDL portion 10. The first carrier substrate 1 can be detached from the interposer RDL portion 10, for example, by deactivating an adhesive layer (not shown) that bonds the first carrier substrate 1 to the interposer RDL portion 10. The adhesive layer can be deactivated, for example, by thermal annealing at an elevated temperature (e.g., for an adhesive material that is thermally deactivated) or by exposing the adhesive layer to ultraviolet light (e.g., for an adhesive material that is ultraviolet deactivated).

[0112] Then, an interposer lower bonding pad 14a may be formed on the lower polymer layer 12 of the interposer RDL portion 10. The interposer lower bonding pad 14a may be formed using substantially the same material and substantially the same lithography process as described above for the interposer upper bonding pad 13a. Then, a lower passivation layer 14 may be formed on the lower polymer layer 12 of the interposer RDL portion 10 and over the interposer lower bonding pad 14a. The lower passivation layer 14 may be formed using the same material and process as described above for the upper passivation layer 13.

[0113] Then, the lower passivation layer 14 may be etched by a suitable etching process (e.g., by wet etching, dry etching, etc.) to form an opening above the interposer lower bonding pad 14a and expose the surface of the interposer lower bonding pad 14a. The etching process may also form an IPD opening in the lower passivation layer 14 for the IPD 30.

[0114] Then, the IPD 30 may be mounted on the lower polymer layer 12 through the IPD opening in the lower passivation layer 14. The IPD 30 may be mounted on the lower polymer layer 12 to contact the metal interconnects 12a in the lower polymer layer 12. The IPD 30 may be mounted, for example, using an electromechanical pick-and-place (PNP) machine. Then, the plurality of C4 bumps 121 may be formed on the intermediate structure. The C4 bumps 121 may include, for example, solder bumps formed in openings in the lower passivation layer 14 over the interposer lower bonding pads 14a by, for example, an electroplating process. The plurality of C4 bumps 121 may make contact with the interposer lower bonding pads 14a through the openings in the lower passivation layer 14. In at least one embodiment, the C4 bumps 121 may be formed by forming one or more under bump metallurgy (UBM) layers (not shown) on the interposer lower bonding pads 14a, forming contact pads on the UBM layers, and forming solder bumps on the contact pads.

[0115] Figure 2His a vertical cross-sectional view of an intermediate structure including a recessed upper surface 300 according to one or more embodiments. After mounting IPD 30 and forming C4 bumps 121, second carrier substrate 2 may be detached from the intermediate structure using a process similar to that described above for detaching first carrier substrate 1.

[0116] The upper surface of the upper molding material layer 127 may then be etched to form a recessed upper surface 300. The upper surface of the molding material layer 127 may be recessed from the semiconductor die upper surface 140a of the semiconductor die 140 using a suitable etching process (e.g., wet etching, dry etching). After the upper surface has been sufficiently recessed (e.g., to a depth of less than about 10 microns), the etching process may be stopped and the intermediate structure may be cleaned (e.g., using a solvent, etc.) and polished.

[0117] Then, the back metal layer 400 (see Figure 1A ) may be formed on the recessed upper surface 300 and the semiconductor grain upper surface 140a. The back metal layer 400 may be formed by conformally depositing (e.g., by CVD, PVD or other suitable deposition techniques) a metal material on the recessed upper surface 300 and the semiconductor grain upper surface 140a. In at least one embodiment, the metal material may be deposited by a sputtering process. Then, the metal material may be patterned (e.g., etched) by a lithography process as needed to form the back metal layer 400. The lithography process may include: forming a patterned photoresist mask (not shown) on the metal material, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the metal material exposed through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0118] After forming the back metal layer 400 , a singulation process (eg, dicing, sawing, etc.) may be performed. The singulation process may separate the package module 120 from surrounding wafer materials and complete the formation of the package module 120 .

[0119] Figure 3 3 is a flow chart illustrating a method of forming a package module 120 according to one or more embodiments. Step 310 includes forming an interposer. Step 320 includes mounting a plurality of semiconductor dies on the interposer, wherein the plurality of semiconductor dies include a semiconductor die upper surface. Step 330 includes forming an upper molding material layer on the plurality of semiconductor dies, such that the upper molding material layer includes a recessed upper surface recessed from the semiconductor die upper surface. Step 340 includes forming a back metal layer on the recessed upper surface of the upper molding material layer.

[0120] Figure 4FIG. 1 is a vertical cross-sectional view of a package module 125 having a first alternative design according to one or more embodiments. The first alternative design is substantially the same as Figure 1A , and can be formed in a manner similar to the manner in which the original design is formed. However, in a first alternative design, the package module 125 may include one or more dummy die 510 located in the upper molding material layer 127. The dummy die 510 may be mounted on the interposer molding portion 20 and have an upper surface that is substantially coplanar with the recessed upper surface 300 of the upper molding material layer 127. The back metal layer 400 may be formed on the upper surface of the dummy die 510.

[0121] The dummy die 510 may be non-functional and may be formed of a variety of materials such as silicon dioxide, glass, etc. In at least one embodiment, the dummy die 510 may have substantially the same CTE as the upper molding material layer 127. The dummy die 510 may have substantially the same size (e.g., length in the x-direction, width in the y-direction, thickness in the z-direction) as one of the semiconductor die 140. For example, the dummy die 510 may be added to provide structural stability.

[0122] The dummy die 510 may be mounted on the interposer molding portion 20 before forming the upper molding material layer 127. The dummy die 510 may be fixed to the interposer molding portion 20, for example, by an adhesive (eg, a silicone adhesive or an epoxy adhesive).

[0123] FIG. 5A to FIG. 5B is a plan view of an alternative design of the back metal layer 400 according to one or more embodiments. FIG. 5A to FIG. 5B , hatching and dashed lines are used to indicate the locations of semiconductor die 140 that may be located below back metal layer 400.

[0124] Figure 5A 1 is a plan view of a first alternative design (e.g., pattern) of a back metal layer 400 according to one or more embodiments. In the first alternative design, the back metal layer 400 may be formed on an upper molding material layer 127 that is smaller than the entire upper molding material layer 127. Specifically, the back metal layer 400 may include a central portion 410 located on the semiconductor die 140. The central portion 410 of the back metal layer 400 may include an inner back metal layer portion 400a located on an inner recessed surface portion 300a of the recessed upper surface 300 of the upper molding material layer 127 (see FIG. 1 ). Figure 1C ). The central portion 410 of the back metal layer 400 may also include an outer back metal layer portion 400b located on the outer recessed surface portion 300b of the recessed upper surface 300 of the upper molding material layer 127 (see Figure 1CThe central portion 410 of the back metal layer 400 may also include a semiconductor grain covering portion 400c and a semiconductor grain sidewall covering portion 400d (see Figure 1C ).

[0125] However, compared to Figure 1B In the first alternative design, the outer back metal layer portion 400b may be formed on an outer recessed surface portion 300b that is smaller than the entire outer recessed surface portion 300b of the recessed upper surface 300 of the upper molding material layer 127. That is, the central portion 410 may include only the outer back metal layer portion 400b (see Figure 1C ) part.

[0126] Figure 5B is a plan view of a second alternative design of the back metal layer 400 according to one or more embodiments. Figure 5A Similar to the first alternative design in FIG. 1 , in the second alternative design, the back metal layer 400 may include a central portion 410 located on the semiconductor die 140. However, in the second alternative design, the back metal layer 400 may additionally include a peripheral portion 420 located around the outer periphery of the central portion 410 of the back metal layer 400. In at least one embodiment, the peripheral portion 420 may have a partial frame shape formed around a portion of the outer periphery of the semiconductor die 140.

[0127] Figure 6 FIG. 6 is a vertical cross-sectional view of a package structure 600 according to one or more embodiments. Figure 6 As shown, the package structure 600 may include a package substrate 110 , a package module 120 located on the package substrate 110 , and a package cover 130 located on the package module 120 .

[0128] The package substrate 110 may include a core substrate or a coreless substrate. In at least one embodiment, for example, the package substrate 110 may include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or chip side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the package substrate 110). Specifically, the package substrate 110 may include a build-up film substrate (e.g., an Ajinomoto build-up film (ABF) substrate). That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0129] The core 112 may help provide rigidity to the package substrate 110. The core 112 may include, for example, an epoxy resin (e.g., bismaleimide triazine (BT) epoxy) and / or a woven glass laminate. Alternatively or additionally, the core 112 may include an organic material such as a polymer material. Specifically, the core 112 may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0130] The core 112 may include one or more through-holes 112a. The through-holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through-holes 112a may enable electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. The through-holes 112a may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0131] The upper package substrate dielectric layer 114 may be formed on the upper surface of the core 112. The upper package substrate dielectric layer 114 may include a plurality of layers, and in particular, may include a constituent film (e.g., ABF). The upper package substrate dielectric layer 114 may also include an organic material such as a polymer material. In particular, the upper package substrate dielectric layer 114 may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0132] The package substrate upper dielectric layer 114 may include one or more package substrate upper bonding pads 114a on the chip side surface of the package substrate upper dielectric layer 114. Specifically, the package substrate upper bonding pads 114a may be exposed on the chip side surface of the package substrate upper dielectric layer 114. The package substrate upper dielectric layer 114 may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may be connected to the package substrate upper bonding pads 114a and the through-holes 112a in the core 112. The metal interconnect structure 114b may include a metal layer (e.g., a copper trace) and a metal via connecting the metal layer. The package substrate upper bonding pads 114a and the metal interconnect structure 114b may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0133] A package substrate upper passivation layer 110a may be formed on the chip side surface of the package substrate upper dielectric layer 114. The package substrate upper passivation layer 110a may partially cover the package substrate upper bonding pad 114a. The package substrate upper passivation layer 110a may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0134] The package substrate lower dielectric layer 116 may be formed on the lower surface of the core 112. The package substrate lower dielectric layer 116 may also include multiple layers, and in particular, may include a constituent film (e.g., ABF). The package substrate lower dielectric layer 116 may also include an organic material such as a polymer material. In particular, the package substrate lower dielectric layer 116 may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0135] The package substrate lower dielectric layer 116 may include one or more package substrate lower bonding pads 116a on the board side surface of the package substrate lower dielectric layer 116. Specifically, the package substrate lower bonding pads 116a may be exposed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may be connected to the package substrate lower bonding pad 116a and the through hole 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., a copper trace) and a metal via connecting the metal layer. The package substrate lower bonding pad 116a and the metal interconnect structure 116b may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0136] A package substrate lower passivation layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower passivation layer 110b may partially cover the package substrate lower bonding pad 116a. The package substrate lower passivation layer 110b may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0137] A ball-grid array (BGA) including a plurality of solder balls 110c may be formed on the board side surface of the lower dielectric layer 116 of the package substrate. The solder balls 110c may enable the package structure 600 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower bonding pads 116a of the package substrate, respectively. Therefore, the solder balls 110c may be electrically connected to the upper bonding pads 114a of the package substrate through the metal interconnect structure 116b, the through-hole 112a, and the metal interconnect structure 114b.

[0138] The package module 120 may be connected to the package substrate 110 by C4 bumps 121 located on the board side surface of the interposer RDL portion 10. Specifically, the C4 bumps 121 may be bonded (e.g., using solder reflow, compression bonding, thermal compression bonding, etc.) to the package substrate upper bonding pads 114a of the package substrate 110. Figure 6 As shown, the package substrate 110 may have a length in the x-direction that is smaller than the length of the package module 120 in the x-direction. The package substrate 110 may also have a width in the y-direction that is smaller than the width of the package module 120 in the y-direction.

[0139] The package structure 600 may further include a thermal interface material (TIM) layer 170 located on the package module 120. The TIM layer 170 may be located on the back metal layer 400 of the package module 120. The TIM layer 170 may be located above the semiconductor die 140 and surround the portion of the semiconductor die 140 that extends above the upper molding material layer 127. The TIM layer 170 may also include a TIM layer protruding portion 170a that protrudes from the bottom of the TIM layer 170 into the gap G between the semiconductor die 140. In at least one embodiment, the TIM layer protruding portion 170a may contact the inner back metal layer portion 400a, the semiconductor die covering portion 400c, and the semiconductor die sidewall covering portion 400d (see Figure 1C ) In at least one embodiment, the TIM layer protruding portion 170a can substantially fill the gap G.

[0140] The TIM layer 170 may include, for example, a TIM paste, a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. In at least one embodiment, the TIM layer 170 may include a film-type TIM layer. In at least one embodiment, the TIM layer 170 may include an indium base, a silver base, and / or a solder base. Other types of TIMs are also within the scope of the present disclosure. In at least one embodiment, the TIM layer 170 may have a thickness in the range of 100 microns to 300 microns (e.g., the maximum thickness in the z direction).

[0141] The TIM layer 170 may be formed on the package module 120 to dissipate heat generated during the operation of the package structure 600 (e.g., the operation of the semiconductor die 140). The TIM layer 170 may be bonded to the package module 120, for example, by a thermally conductive adhesive. The TIM layer 170 may have a low bulk thermal impedance and a high thermal conductivity. The bond-line-thickness (BLT) (e.g., the distance between the package lid 130 and the package module 120) may be less than about 100 microns, but larger or smaller distances may also be used.

[0142] The package cover 130 may be located on the TIM layer 170 and connected to the package module 120. The package cover 130 may be fixed to the package module 120 by the adhesive layer 160. The package cover 130 may contact at least a portion of the TIM layer 170. In one or more embodiments, the package cover 130 may directly contact the entire upper surface of the TIM layer 170. The TIM layer 170 may be compressed between the package cover 130 and the package module 120. Specifically, the TIM layer 170 may be compressed between the package cover 130 and the back metal layer 400 of the package module 120.

[0143] The package cover 130 may be formed of, for example, metal, ceramic, or polymer material. The package cover 130 may have a plate shape (eg, a flat shape) and be substantially parallel to the upper surface of the package substrate 110. The package cover 130 may be, for example, Figure 6 The package cover 130 may include an outer sidewall substantially aligned with the outer sidewall of the upper molding material layer 127. The package cover 130 may include a central portion substantially aligned with the central portion of the package module 120 in the z direction. The package cover 130 may include a substantially flat upper surface and a lower surface. Alternatively, the package cover 130 may also include a bottom step area (not shown) that may protrude from the bottom surface and contact the TIM layer 170.

[0144] The adhesive layer 160 may be bonded to the upper surface of the back metal layer 400 and / or the upper molding material layer 127. The adhesive layer 160 may include an adhesive foot portion 160a located near the sidewall of the package module 120. The adhesive foot portion 160a may bond the package cover 130 to the package module 120. The adhesive layer 160 may also include an adhesive wall portion 160b located between the adhesive foot portion 160a and the semiconductor die 140. The adhesive wall portion 160b may also bond the package cover 130 to the package module 120. The adhesive wall portion 160b may also be used to contain the expansion of the TIM layer 170 when the TIM layer 170 is compressed between the package cover 130 and the package module 120. The thickness of the adhesive layer 160 may be in the range of 50 microns to 200 microns. The adhesive layer 160 may include, for example, a silicone adhesive (e.g., containing aluminum oxide, zinc oxide, resin, etc.) or an epoxy adhesive. Other suitable adhesives may also be used. The adhesive layer 160 may contact the recessed upper surface of the back metal layer or the upper molding material layer.

[0145] The package structure 600 may further include a lower molding material layer 327 located on the package substrate 110. The lower molding material layer 327 may be formed between the package module 120 and the package substrate 110 and used to bond the package module 120 to the package substrate 110. The lower molding material layer 327 may be formed around the C4 bump 121 and substantially fill the space between the package module 120 and the package substrate 110. The lower molding material layer 327 may also be formed on the sidewall of the package substrate 110. The lower molding material layer 327 may have an outer sidewall substantially aligned with the sidewall of the interposer RDL portion 10. The bottom of the lower molding material layer 327 may be substantially aligned with the package substrate lower passivation layer 110b. The lower molding material layer 327 may include, for example, a polymer material and specifically include an epoxy-based polymer material (e.g., EMC).

[0146] The package structure 600 may be formed, for example, by attaching the package substrate 110 to the package module 120 before a singulation process for singulating the package module 120. Specifically, the back metal layer 400 is formed at Figure 2H After the intermediate structure in the package module 120 is formed, the TIM layer 170 can be formed on the package module 120. The adhesive layer 160 can then be formed on the package module 120 and the package cover 130 can be clamped to the package module 120 and the adhesive layer 160. The package cover 130 and the package module 120 can be clamped together for a period of time to allow the adhesive layer 160 to cure and form a secure bond between the package cover 130 and the package module 120. The clamping can be performed, for example, using a heat clamp module. The heat clamp module can apply a uniform force on the entire upper surface of the package cover 130.

[0147] After the adhesive layer 160 has been cured, the intermediate structure can be inverted and the package substrate 110 can be positioned over the intermediate structure so that the package substrate upper bonding pads 114a are located over the C4 bumps 121. The package substrate 110 can then be lowered onto the C4 bumps 121, and a reflow process can then be performed to reflow the solder in the C4 bumps 121.

[0148] After the reflow process is completed, the lower molding material layer 327 may be dispensed as a liquid molding material onto the interposer RDL portion 10. The liquid molding material may flow around the C4 bumps 121 and between the interposer RDL portion 10 and the package substrate 110. The liquid molding material may then be cured and hardened to form the lower molding material layer 327. A singulation process may then be performed to singulate the package module 120 using the attached package cap 130 and package substrate 110.

[0149] Figure 7 is a vertical cross-sectional view of a package structure 700 having a first alternative design according to one or more embodiments. The first alternative design is substantially the same as Figure 6 , and can be formed in a manner similar to the manner in which the original design is formed. However, in a first alternative design, the package structure 700 may include Figure 4 That is, the package module 120 in the first alternative design of the package structure 700 may include one or more dummy dies 510 located in the upper molding material layer 127 .

[0150] Figure 8 FIG. 8 is a vertical cross-sectional view of a package structure 800 having a second alternative design according to one or more embodiments. The second alternative design may be substantially similar to Figure 6 However, the second alternative design may be different from the original design in at least the size of the packaging substrate 110 and the manner in which the packaging module 120 is bonded to the packaging substrate 110. Figure 6 Different from the original design.

[0151] like Figure 8 As shown, the package substrate 110 may have a length in the x-direction greater than the length in the x-direction of the interposer RDL portion 10. In at least one embodiment, the length of the package substrate 110 may be at least 10% greater than the length of the interposer RDL portion 10. The package substrate 110 may have a width in the y-direction greater than (e.g., at least 10% greater than) the width of the interposer RDL portion 10 in the y-direction.

[0152] The package module 120 may be bonded to the package substrate 110 by a package underfill layer 729. The package underfill layer 729 may be substantially similar to the package module underfill layer 129 in the package module 120. The package underfill layer 729 may be formed under the interposer RDL portion 10 and around the C4 bumps 121. The package underfill layer 729 may also be formed on the sidewalls of the interposer RDL portion 10.

[0153] A molding material layer (not shown) may be formed on the package underfill layer 729 (similar to the upper molding material layer 127) as needed to provide additional stability to the package structure 800. In this case, the package underfill layer 729 may have a relatively large area on the package substrate 110 (e.g., in a plan view). Figure 8 Specifically, the package underfill layer 729 may include an outermost wall substantially aligned with the outer sidewalls of the interposer RDL portion 10 , and the molding material layer may be formed on the outermost wall of the package underfill layer 729 .

[0154] Figure 8 The way to form the second alternative design in the Figure 6 In the second alternative design, after performing a singulation process for singulating the package module 120, the package module 120 may be mounted on the package substrate 110. Specifically, the package module 120 may be positioned on the package substrate 110 so that the C4 bump 121 is located on the package substrate upper bonding pad 114a. Then, the C4 bump 121 may be lowered onto the package substrate upper bonding pad 114a, and then a reflow process may be performed to reflow the solder in the C4 bump 121.

[0155] Then, a package underfill layer 729 may be applied by depositing and / or injecting an epoxy-based polymer material onto the package substrate. The epoxy-based polymer material may be applied onto the package substrate 110 and diffused (e.g., by capillary action) under the interposer RDL portion 10 and around the C4 bumps 121. In at least one embodiment, the epoxy-based polymer material may fill substantially all gaps between the interposer RDL portion 10 and the package substrate 110. Then, the epoxy-based polymer material may be cured, for example, at about 150° C. in a box oven for about 90 minutes to provide a package underfill layer 729 having sufficient stiffness and mechanical strength.

[0156] After the encapsulation underfill layer 729 has been cured, a TIM layer 170 may be formed on the encapsulation module 120. An adhesive layer 160 may then be formed on the encapsulation module 120, and the encapsulation lid 130 may be clamped to the encapsulation module 120 and the adhesive layer 160. The encapsulation lid 130 may be clamped together with the encapsulation module 120 and the encapsulation substrate 110 for a period of time to allow the adhesive layer 160 to cure and form a secure bond between the encapsulation lid 130 and the encapsulation module 120. The clamping may be performed, for example, using a thermal clamping module. The thermal clamping module may apply a uniform force across the entire upper surface of the encapsulation lid 130.

[0157] After the adhesive layer 160 has been sufficiently cured, the intermediate structure may be inverted and solder balls 110c of the BGA may be formed on the board side surface of the package substrate 110. The formation of the solder balls 110c may complete the formation of the second alternative design of the package structure 600.

[0158] Fig. 9 is a vertical cross-sectional view of a package structure 900 having a third alternative design according to one or more embodiments. The third alternative design may be substantially the same as Figure 8 The second alternative design in the embodiment of the present invention can be formed in a manner similar to the manner in which the second alternative design is formed. However, in the third alternative design, the package structure 900 can include Figure 4 That is, the package module 120 in the third alternative design of the package structure 900 may include one or more dummy dies 510 located in the upper molding material layer 127 .

[0159] FIG. 10A to FIG. 10B 1 is a possible design pattern of the adhesive layer 160 in the package structures 600 , 700 , 800 , 900 according to one or more embodiments. FIG. 10A to FIG. 10B The design patterns in Figure 6 The original design of the package structure 600, Figure 7 The first alternative structure 700 design, Figure 8 The second alternative structure 800 design and Fig. 9 In the third alternative structure 900 design. In general, the adhesive foot portion 160a and / or the adhesive wall portion 160b can have a frame shape or a partial frame shape.

[0160] Fig. 10A is a plan view of an adhesive layer 160 having a first design pattern according to one or more embodiments. Figures 6 to 9 The vertical cross-section view is along Fig. 10A The line B-B' in is intercepted. Fig. 10AAs shown, adhesive foot portion 160a may have a partial frame shape. Specifically, adhesive foot portion 160a may not be continuously formed around the entire periphery of semiconductor die 140. Instead, adhesive foot portion 160a may be discontinuous at one or more locations around the periphery of semiconductor die 140. Adhesive foot portion 160a may be formed as two or more separate beads of adhesive material located around the periphery of adhesive wall portion 160b. In at least one embodiment ( Fig. 10A ), the adhesive foot portion 160a may be formed into two U-shaped sections separated near the center portion of the package structure 600, 700, 800, 900. The two U-shaped sections may have substantially similar sizes and shapes.

[0161] The width of adhesive foot portion 160a may be substantially uniform across adhesive wall portion 160b. The width of adhesive foot portion 160a may be greater than the width of adhesive wall portion 160b. In at least one embodiment, the width of adhesive foot portion 160a may be at least 50% greater than the width of adhesive wall portion 160b.

[0162] In contrast, the adhesive wall portion 160b in the first design pattern may have a frame shape. Specifically, the adhesive wall portion 160b may be formed as a continuous weld of adhesive material around the outer periphery of the semiconductor die 140. The width of the adhesive wall portion 160b may be substantially uniform over the entire adhesive wall portion 160b. The adhesive layer 160 in the first design pattern may be formed and patterned, for example, by any suitable dispensing technique.

[0163] Fig. 10B FIG. 1 is a plan view of an adhesive layer 160 having a second design pattern according to one or more embodiments. Fig. 10B As shown, it can be omitted from the second design pattern Fig. 10A 140. The adhesive layer 160 may be formed by an adhesive foot portion 160a. The adhesive foot portion 160a may be formed as a continuous weld of adhesive material around the outer periphery of the semiconductor die 140. The width of the adhesive foot portion 160a may be substantially uniform over the entire periphery of the semiconductor die 140. The adhesive layer 160 may also be formed and patterned in a second design pattern, for example, by any suitable dispensing technique.

[0164] FIG. 11A to FIG. 14 is a vertical cross-sectional view of a package structure 600 having an alternative design according to one or more embodiments. Specifically, Fig.11A is a vertical cross-sectional view of a package structure 600 having a fourth alternative design according to one or more embodiments. Fig. 11B is a plan view (ie, top view) of a package structure 1100 having a fourth alternative design according to one or more embodiments. Fig.11A The vertical cross-section view is along Fig. 11B The line C-C' is intercepted.

[0165] like Fig.11A As shown, the package structure 1100 having the fourth alternative design may be substantially similar to Figure 6 Specifically, the fourth alternative design may include a packaging substrate 110 and a packaging module 120 located on the packaging substrate 110.

[0166] However, in Fig.11A In the fourth alternative design of FIG. 1 , the package structure 1100 may not include the TIM layer 170 and may not include the package cover 130. In contrast, in the fourth alternative design, the package structure 1100 may include a reinforcement ring 630 located on the package module 120. The reinforcement ring 630 may be formed of a material similar to that of the package cover 130. The reinforcement ring 630 may be attached to the package module 120 by the adhesive layer 160. Specifically, the reinforcement ring 630 may be attached to the back metal layer 400 located on the outer recessed surface portion 300b of the upper molding material layer 127 via the adhesive layer 160. The reinforcement ring 630 may be similar to the reinforcement ring 630 described above. Figure 6 The packaging cover 130 is attached in a similar manner as described above.

[0167] Despite Fig.11A Although not shown in the figure, in at least one embodiment, the back metal layer 400 may not be formed at at least a portion of the outer recessed surface portion 300b of the upper molding material layer 127. In this embodiment, at least a portion of the reinforcement ring 630 may be directly attached to the outer recessed surface portion 300b of the upper molding material layer 127. In addition, although in Fig.11A , but in at least one embodiment, the reinforcement ring 630 can be attached to the molding material layer 227 (eg, encapsulation layer) of the interposer molding portion 20 via the adhesive layer 160. In this embodiment, the reinforcement ring 630 can be embedded in the upper molding material layer 127.

[0168] like Fig. 11BAs shown, the reinforcement ring 630 may be continuously formed around the entire periphery of the semiconductor die 140. The back metal layer 400 may cover the entire upper molding material layer 127 and the semiconductor die 140. The reinforcement ring 630 may have a shape substantially similar to the outer shape of the upper molding material layer 127 (e.g., the outer shape of the packaging module 120) and the outer shape of the back metal layer 400. Specifically, the reinforcement ring 630 may have a substantially rectangular outer shape and a substantially rectangular inner shape. Other suitable shapes of the reinforcement ring 630 may also be used. In at least one embodiment, the distance between the inner wall of the reinforcement ring 630 and the semiconductor die 140 may be greater than the distance between the outer wall of the reinforcement ring 630 and the outermost edge of the packaging module 120 (e.g., the outermost edge of the back metal layer 400).

[0169] The width of the reinforcement ring 630 may be substantially uniform around the entire perimeter of the semiconductor die 140. In at least one embodiment, the width of the reinforcement ring 630 may be greater than the distance between the inner wall of the reinforcement ring and the semiconductor die 140. In at least one embodiment, the width of the reinforcement ring 630 may be in the range of 20% to 90% of the distance between the semiconductor die 140 and the outermost edge of the packaging module 120 (e.g., the outermost edge of the back metal layer 400).

[0170] Fig.12 1 is a vertical cross-sectional view of a package structure 1200 having a fifth alternative design according to one or more embodiments. A plan view (ie, a top view) of the package structure 1200 having the fifth alternative design may be substantially the same as Fig. 11B FIG. 1 is a plan view of a package structure 1100 having a fourth alternative design.

[0171] like Fig.12 As shown, the package structure 1200 having the fifth alternative design may be substantially similar to Figure 7 Specifically, in the fifth alternative design, the package structure 1200 may include one or more dummy die 510 located in the upper molding material layer 127. However, in Fig.12 In the fifth alternative design of FIG. 1 , the package structure 1200 may not include the TIM layer 170 and may not include the package cover 130. In contrast, in the fifth alternative design, the package structure 1200 may include a reinforcement ring 630 located on the package module 120. The material, design, and location of the reinforcement ring 630 in the fifth alternative design may be substantially the same as those in FIG. FIG. 11A to FIG. 11B The material, design and location of the reinforcement ring 630 in the fourth alternative design of FIG. In addition, the reinforcement ring 630 can be located on at least a portion of the dummy die 510 .

[0172] Fig.131 is a vertical cross-sectional view of a package structure 1300 having a sixth alternative design according to one or more embodiments. A plan view (ie, a top view) of the package structure 1300 having the sixth alternative design may be substantially the same as Fig. 11B FIG. 1 is a plan view of a package structure 1100 having a fourth alternative design.

[0173] like Fig.13 As shown, the package structure 1300 having the sixth alternative design may be substantially similar to Figure 8 800 with a second alternative design. Thus, for example, the package substrate 110 may have a length in the x-direction greater than the length of the interposer RDL portion 10 and a width in the y-direction greater than the width of the interposer RDL portion 10, respectively. The package module 120 may be bonded to the package substrate 110 by a package underfill layer 729. A molding material layer (not shown) (similar to the upper molding material layer 127) may be formed over the package underfill layer 729 as needed to provide additional stability to the package structure 1300.

[0174] However, compared to Figure 8 For the second alternative design, Fig.13 In the sixth alternative design of FIG. 1 , the package structure 1300 may not include the TIM layer 170 and may not include the package cover 130. Instead, in the sixth alternative design, the package structure 1300 may include a reinforcement ring 630 located on the package module 120. The material, design, and location of the reinforcement ring 630 in the sixth alternative design may be substantially the same as those in FIG. FIG. 11A to FIG. 11B The materials, design and location of the reinforcement ring 630 in the fourth alternative design.

[0175] Fig.14 1 is a vertical cross-sectional view of a package structure 1400 having a seventh alternative design according to one or more embodiments. The plan view (ie, top view) of the package structure 1400 having the seventh alternative design may be substantially the same as Fig. 11B FIG. 1 is a plan view of a package structure 1100 having a fourth alternative design.

[0176] like Fig.14 As shown, the package structure 1400 having the seventh alternative design may be substantially similar to Fig. 9 Specifically, in the seventh alternative design, the package structure 1400 may include one or more dummy die 510 located in the upper molding material layer 127. However, in Fig.14In the seventh alternative design of FIG. 1 , the package structure 1400 may not include the TIM layer 170 and may not include the package cover 130. Instead, in the seventh alternative design, the package structure 1400 may include a reinforcement ring 630 located on the package module 120. The material, design, and location of the reinforcement ring 630 in the seventh alternative design may be substantially the same as those in FIG. FIG. 11A to FIG. 11B The material, design and location of the reinforcement ring 630 in the fourth alternative design of FIG. In addition, the reinforcement ring 630 can be located on at least a portion of the dummy die 510 .

[0177] Fig.15 is a plan view of a third alternative design of the back metal layer 400 according to one or more embodiments. Fig.15 , hatching and dashed lines are used to indicate the locations of semiconductor die 140 that may be located below back metal layer 400.

[0178] In addition to including Figures 6 to 9 In addition to the package structures 600, 700, 800, and 900 of the package cover 130, a third alternative design of the back metal layer 400 may include FIG. 11A to FIG. 14 The third alternative design of the back metal layer 400 may be substantially similar to Figure 5B In the second alternative design. That is, the back metal layer 400 may include a central portion 410 and a peripheral portion 420. However, compared to Figure 5B As for the second alternative design in FIG. 4 , in a third alternative design, the peripheral portion 420 may have a complete frame shape continuously formed around the central portion 410 .

[0179] Fig.16 is a plan view of an adhesive layer 160 having a third design pattern according to one or more embodiments. Fig.11A and Figure 12 to Figure 14 The vertical cross-section view is along Fig.16 In addition to the line D-D' Figures 6 to 9 In addition to the package structure 600 of the package cover 130, a third alternative design of the back metal layer 400 may include FIG. 11A to FIG. 14 In the packaging structure 600 of the reinforcement ring 630.

[0180] like Fig.16 As shown, the third design pattern of the adhesive layer 160 may be substantially similar to Fig. 10B That is, the adhesive layer 160 may be composed of the adhesive foot portion 160a. However, compared to Fig. 10B For the second design pattern in FIG. 1 , in the third design pattern, the adhesive foot portion 160a may have a frame shape. The position and width of the adhesive foot portion 160a may substantially correspond to FIG. 11A to FIG. 14 The adhesive foot portion 160a may be formed continuously around the entire periphery of the semiconductor die 140. Specifically, the adhesive foot portion 160a may be formed as a continuous weld of adhesive material located around the outer periphery of the semiconductor die 140. The width of the adhesive foot portion 160a may be substantially uniform over the entire adhesive foot portion 160a. The adhesive foot portion 160a in the third design pattern may be formed and patterned, for example, by any suitable dispensing technique.

[0181] Reference Figures 1A to 16 The packaging module 120 may include: an interposer 5; a plurality of semiconductor grains 140, which are located on the interposer 5 and include an upper surface 140a of the semiconductor grains; an upper molding material layer 127, which is located on the plurality of semiconductor grains 140 and includes a recessed upper surface 300 that may be recessed from the upper surface 140a of the semiconductor grains; and a back metal layer 400, which is located on the recessed upper surface 300 of the upper molding material layer 127.

[0182] In one embodiment, the recessed upper surface 300 of the upper molding material layer 127 may include an inner recessed surface portion 300a located between the plurality of semiconductor grains 140, and the back metal layer 400 may include an inner back metal layer portion 400a located on the inner recessed surface portion 300a. In one embodiment, the recessed upper surface 300 of the upper molding material layer 127 may also include an outer recessed surface portion 300b located outside the plurality of semiconductor grains 140, and the back metal layer 400 may include an outer back metal layer portion 400b located on the outer recessed surface portion 300b. In one embodiment, the recessed upper surface 300 of the upper molding material layer 127 may include the entire upper surface of the upper molding material layer 127, and the back metal layer 400 may be located on the entire upper surface of the upper molding material layer 127. In one embodiment, the back metal layer 400 may be located on the semiconductor grain upper surfaces 140a of the plurality of semiconductor grains 140. In one embodiment, the back metal layer 400 may be continuously formed between the semiconductor die upper surface 140a, the sidewalls of the plurality of semiconductor die 140, and the recessed upper surface 300 of the upper molding material layer 127. In one embodiment, the interposer 5 may include an interposer redistribution layer (RDL) portion 10 and an interposer molding portion 20 located on the interposer RDL portion 10, wherein the interposer molding portion 20 may include local silicon interconnect (LSI) die 200a, 200b, 200c for interconnecting the plurality of semiconductor die 140. In one embodiment, the package module 120 may further include a dummy die 510 located on the interposer molding portion 20 and in the upper molding material layer 127. In one embodiment, the depth of the recessed upper surface 300 from the semiconductor die upper surface 140a may be less than 10 microns.

[0183] Reference again Figures 1A to 16 The package structure 600 may include a package substrate 110 and a package module 120 located on the package substrate 110. The package module 120 may include: an interposer 5; a plurality of semiconductor dies 140 located on the interposer 5 and including a semiconductor dies upper surface 140a; an upper molding material layer 127 located on the plurality of semiconductor dies 140 and including a recessed upper surface 300 that may be recessed from the semiconductor dies upper surface 140a; and a back metal layer 400 located on the recessed upper surface 300 of the upper molding material layer 127.

[0184] In one embodiment, the package structure 600 may further include one of a package cover 130 or a stiffener ring 630 located on the package module 120. In one embodiment, the package structure 600 may include the package cover 130 and further include a thermal interface material (TIM) layer 170 located on the package module 120, wherein the package cover 130 may be located on the TIM layer 170. In one embodiment, the recessed upper surface 300 of the upper molding material layer 127 may include an inner recessed surface portion 300a located between the plurality of semiconductor grains 140, the back metal layer 400 may include an inner back metal layer portion 400a located on the inner recessed surface portion 300a, and the TIM layer 170 may include a TIM layer 170 protruding portion protruding onto the inner back metal layer portion 400a. In one embodiment, the package structure 600 may further include an adhesive layer 160 connecting the package cover 130 to the package module 120, wherein the adhesive layer 160 contacts at least one of the back metal layer 400 or the recessed upper surface 300 of the upper molding material layer 127. In one embodiment, the adhesive layer 160 may include an adhesive foot portion 160a at the sidewall of the package module 120 and an adhesive wall portion 160b between the adhesive foot portion 160a and the plurality of semiconductor dies 140. The thickness of the adhesive layer 160 may be in the range of 50 micrometers to 200 micrometers.

[0185] Reference again Figures 1A to 16 , the method for forming the packaging module 120 may include: forming an interposer 5; installing a plurality of semiconductor grains 140 on the interposer 5, wherein the plurality of semiconductor grains 140 include a semiconductor grain upper surface 140a; forming an upper molding material layer 127 on the plurality of semiconductor grains 140, so that the upper molding material layer 127 includes a recessed upper surface 300 that can be recessed from the semiconductor grain upper surface 140a; and forming a back metal layer 400 on the recessed upper surface 300 of the upper molding material layer 127.

[0186] In one embodiment, forming the upper molding material layer 127 may include forming the recessed upper surface 300 of the upper molding material layer 127 to include an inner recessed surface portion 300a located between the plurality of semiconductor grains 140, and forming the back metal layer 400 may include forming the back metal layer 400 to include an inner back metal layer portion 400a located on the inner recessed surface portion 300a. In one embodiment, forming the upper molding material layer 127 may include forming the recessed upper surface 300 of the upper molding material layer 127 to include an outer recessed surface portion 300b located outside the plurality of semiconductor grains 140, and the back metal layer 400 may include an outer back metal layer portion 400b located on the outer recessed surface portion 300b. In one embodiment, forming the back metal layer 400 may include forming the back metal layer 400 on the semiconductor grain upper surfaces 140a of the plurality of semiconductor grains 140. In one embodiment, forming the interposer 5 may further include: forming an interposer redistribution layer (RDL) portion 10 on the carrier substrate 1; and forming an interposer molding portion 20 on the interposer RDL portion 10, wherein the interposer molding portion 20 may include local silicon interconnect (LSI) grains 200a, 200b, 200c for interconnecting the plurality of semiconductor grains 140.

[0187] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging module, characterized in that: include: Intermediary layer; a plurality of semiconductor grains, located on the interposer and including upper surfaces of the semiconductor grains; an upper molding material layer located on the plurality of semiconductor dies and comprising a recessed upper surface recessed from an upper surface of the semiconductor dies; as well as A back metal layer is located on the recessed upper surface of the upper molding material layer.

2. The packaging module according to claim 1, characterized in that: The recessed upper surface of the upper molding material layer includes an inner recessed surface portion located between the plurality of semiconductor grains, and the back metal layer includes an inner back metal layer portion located on the inner recessed surface portion.

3. The packaging module according to claim 1, characterized in that: The recessed upper surface of the upper molding material layer includes an entire upper surface of the upper molding material layer, and the back metal layer is located on the entire upper surface of the upper molding material layer.

4. The packaging module according to claim 1, characterized in that: The back metal layer is located on the upper surfaces of the semiconductor grains of the plurality of semiconductor grains.

5. The packaging module according to claim 1, characterized in that: The back metal layer is continuously formed between the upper surface of the semiconductor die, the side surfaces of the plurality of semiconductor die, and the recessed upper surface of the upper molding material layer.

6. The packaging module according to claim 1, characterized in that: The intermediate layer includes: The interposer redistribution layer portion; and The interposer molding portion is located on the interposer redistribution layer portion, wherein the interposer molding portion includes a local silicon interconnection die for interconnecting the plurality of semiconductor dies.

7. The packaging module according to claim 1, characterized in that: The depth of the recessed upper surface from the upper surface of the semiconductor grain is less than 10 micrometers.

8. A packaging structure, characterized in that: include: Package substrate; The packaging module is located on the packaging substrate and includes: Intermediary layer; a plurality of semiconductor grains, located on the interposer and including upper surfaces of the semiconductor grains; an upper molding material layer located on the plurality of semiconductor dies and comprising a recessed upper surface recessed from an upper surface of the semiconductor dies; and a back metal layer located on the recessed upper surface of the upper molding material layer; and One of a packaging cover and a reinforcement ring is located on the packaging module.

9. The packaging structure according to claim 8, characterized in that: The packaging structure includes the packaging cover, and the packaging structure also includes: A thermal interface material layer is located on the packaging module, wherein the packaging cover is located on the thermal interface material layer.

10. The packaging structure according to claim 9, characterized in that: The recessed upper surface of the upper molding material layer includes an inner recessed surface portion located between the plurality of semiconductor grains, the back metal layer includes an inner back metal layer portion located on the inner recessed surface portion, and the thermal interface material layer includes a thermal interface material layer protruding portion protruding onto the inner back metal layer portion.

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