Novel double-satellite digital-analog compound low-noise frequency demultiplier

Abstract

The utility model relates to a novel double-satellite digital-analog compound low-noise frequency demultiplier, which comprises a shell and a circuit module arranged in the shell, the circuit module comprises a satellite A input module, a satellite B input module, a CMOS satellite tuner, a full-spectrum satellite digital chip, a signal selection switch circuit, a digital channel stacking chip and four output terminals, the number of the output terminals is four, two of the output terminals are dCSS output ports, and the other two are traditional satellite signal output terminals. The two traditional satellite signal output ends can support the use of two users; the two dCSS output ends can respectively provide two groups of same 24 channels or 48 different channels through one cable, each channel can be used by one user, and the channels do not interfere with each other; therefore, the product realizes that double satellites can support a relatively large satellite television receiving system of as many as 50 users at the same time.

Description

Technical Field

[0001] The utility model relates to the technical field of microwave communications, in particular to a novel dual-satellite digital-analog composite low-noise frequency reducer. Background Art

[0002] With the development of global economy, the universalization of television and the existence of multiple televisions in one family, the traditional dual-satellite low-noise downconverter on the market only supports 4 users at most. The existing downconverter only supports 1 to 24 users, which is relatively small for users in high-rise buildings and hotels. In addition, there is no traditional satellite TV signal terminal, and the user's existing set-top box cannot be used. At the same time, the user's existing satellite search and installation equipment cannot be used during product installation, which will cause a waste of resources and increase costs. Utility Model Content

[0003] The utility model aims to provide a novel dual-satellite digital-analog composite low-noise frequency reducer.

[0004] To achieve the above-mentioned purpose, the technical solution of the utility model is as follows.

[0005] A novel dual-satellite digital-analog composite low-noise frequency converter, the frequency converter comprising a housing and a circuit module in the housing, the circuit module comprising a satellite A input module, a satellite B input module, a first CMOS satellite tuner, a second CMOS satellite tuner, a first full-spectrum satellite digital chip, a second full-spectrum satellite digital chip, a first signal selection switch circuit, a second signal selection switch circuit, a first digital channel stacking chip, a second digital channel stacking chip, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal, the satellite A input module is respectively connected to the first CMOS satellite tuner and the first full-spectrum satellite digital chip, the satellite B input module is respectively connected to the second CMOS satellite tuner and a second full-spectrum satellite digital chip, the first CMOS satellite tuner is respectively connected to the first signal selection switch circuit and the second signal selection switch circuit, the second CMOS satellite tuner is respectively connected to the first signal selection switch circuit and the second signal selection switch circuit, the first full-spectrum satellite digital module is respectively connected to the first digital channel stacking chip and the second digital channel stacking chip, the second full-spectrum satellite digital modules are respectively connected to the first digital channel stacking chip and the second digital channel stacking chip, the first signal selection switch circuit, the second signal selection switch circuit, the first digital channel stacking chip and the second digital channel stacking chip are respectively connected to the first output terminal, the second output terminal, the third output terminal and the fourth output terminal.

[0006] Preferably, the satellite A input module includes a first-level horizontal signal amplifier, a first-level vertical signal amplifier, a satellite signal filter and a satellite signal distributor, and the output ends of the first-level horizontal signal amplifier and the first-level vertical signal amplifier are respectively connected to the satellite signal filter and the satellite signal distributor in sequence, wherein the two output ends of the satellite signal distributor connected to the first-level horizontal signal amplifier are respectively connected to the horizontal signal input end of the first full-spectrum satellite digital chip and the horizontal signal input end of the first CMOS satellite tuner.

[0007] The two output ends of the satellite signal distributor connected to the first-level vertical signal amplifier are respectively connected to the vertical signal input end of the first full-spectrum satellite digital chip and the vertical signal input end of the first CMOS satellite tuner.

[0008] Preferably, the satellite B input module includes a first-level horizontal signal amplifier, a first-level vertical signal amplifier, a satellite signal filter and a satellite signal distributor, and the output ends of the first-level horizontal signal amplifier and the first-level vertical signal amplifier are respectively connected to the satellite signal filter and the satellite signal distributor in sequence, wherein the two output ends of the satellite signal distributor connected to the first-level horizontal signal amplifier are respectively connected to the horizontal signal input end of the second full-spectrum satellite digital chip and the horizontal signal input end of the second CMOS satellite tuner, wherein the two output ends of the satellite signal distributor connected to the first-level vertical signal amplifier are respectively connected to the vertical signal input end of the second full-spectrum satellite digital chip and the vertical signal input end of the second CMOS satellite tuner.

[0009] Preferably, two output ends of the first CMOS satellite tuner are respectively connected to a first signal selection switch circuit and a second signal selection switch circuit, and two output ends of the second CMOS satellite tuner are respectively connected to the first signal selection switch circuit and the second signal selection switch circuit.

[0010] Preferably, the first signal selection switch circuit and the second signal selection switch circuit are both provided with a DiseqC switching switch circuit, and the DiseqC switching switch circuit is connected to the first signal selection switch circuit and the second signal selection switch circuit through a DC conversion circuit.

[0011] Preferably, the horizontal signal output end and the vertical signal output end of the first full-spectrum satellite digital chip are both connected to a UHF filter and a UHF distributor, wherein the two ports of the UHF distributor connected to the horizontal signal output end of the first full-spectrum satellite digital chip are respectively connected to the horizontal signal input ports of the first digital channel stacking chip and the second digital channel stacking chip through UHF balanced and unbalanced circuits, and the two ports of the UHF distributor connected to the vertical signal output end of the first full-spectrum satellite digital chip are respectively connected to the vertical signal input ports of the first digital channel stacking chip and the second digital channel stacking chip through UHF balanced and unbalanced circuits.

[0012] Preferably, the horizontal signal output end and the vertical signal output end of the second full-spectrum satellite digital chip are both connected to a UHF filter and a UHF distributor, wherein the two ports of the UHF distributor connected to the horizontal signal output end of the second full-spectrum satellite digital chip are respectively connected to the horizontal signal input ports of the first digital channel stacking chip and the second digital channel stacking chip through UHF balanced and unbalanced circuits, and the two ports of the UHF distributor connected to the vertical signal output end of the second full-spectrum satellite digital chip are respectively connected to the vertical signal input ports of the first digital channel stacking chip and the second digital channel stacking chip through UHF balanced and unbalanced circuits.

[0013] Preferably, the first digital channel stacking chip is provided with an MCU, and the first digital channel stacking chip is connected to the third output terminal through a balanced and unbalanced circuit and a bandpass filter; the second digital channel stacking chip is provided with an MCU, and the first digital channel stacking chip is connected to the fourth output terminal through a balanced and unbalanced circuit and a bandpass filter.

[0014] Preferably, the circuit module also includes a power supply module.

[0015] The utility model has four output terminals, two of which are digital signal output terminals, namely, DCS output ports, and the other two are analog signal output terminals, namely, Legacy output terminals, namely, traditional satellite signal output terminals. The two traditional satellite signal output terminals can support two users; the two DCS output terminals can each provide two identical 24 channels through a cable, or different 48 channels, each channel can be used by one user, and the channels do not interfere with each other; thus, the product realizes a relatively large satellite TV receiving system that can support up to 50 users with dual satellites at the same time. The selection of the program source of the analog signal output is to switch the frequency band / polarization / satellite through tone or switching voltage and Diseqc signal; the program source and selection of the digital signal output are to select the frequency band / polarization / satellite / channel through tone and switching voltage and Diseqc signal that complies with EN50494&EN50607 protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is a schematic diagram of a circuit module of this embodiment. DETAILED DESCRIPTION

[0017] The utility model is described in detail below with reference to the accompanying drawings.

[0018] like Figure 1 As shown, a novel dual-satellite digital-analog composite low-noise downconverter, the downconverter includes a housing and a circuit module in the housing, the circuit module includes a satellite A input module, a satellite B input module, a first CMOS satellite tuner 13, a second CMOS satellite tuner 14, a first full-spectrum satellite digital chip 15, a second full-spectrum satellite digital chip 16, a first signal selection switch circuit 51, a second signal selection switch circuit 52, a first digital channel stacking chip 37, a second digital channel stacking chip 38, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal;

[0019] The satellite A input module is respectively connected to the first CMOS satellite tuner 13 and the first full spectrum satellite digital chip 15;

[0020] The satellite B input module is respectively connected to the second CMOS satellite tuner 14 and the second full spectrum satellite digital chip 16;

[0021] The first CMOS satellite tuner 13 is connected to the first signal selection switch circuit 51 and the second signal selection switch circuit 52 respectively;

[0022] The second CMOS satellite tuner 14 is connected to the first signal selection switch circuit 51 and the second signal selection switch circuit 52 respectively;

[0023] A full spectrum satellite digital module is connected to the first digital channel stacking chip 37 and the second digital channel stacking chip 38 respectively;

[0024] The two full-spectrum satellite digital modules are respectively connected to the first digital channel stacking chip 37 and the second digital channel stacking chip 38;

[0025] The first signal selection switch circuit 51 , the second signal selection switch circuit 52 , the first digital channel stacking chip 37 , and the second digital channel stacking chip 38 are connected to the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal, respectively.

[0026] Preferably, the satellite A input module comprises a first-level horizontal signal amplifier 1, a first-level vertical signal amplifier 2, a satellite signal filter 5 and a satellite signal distributor 9;

[0027] The output ends of the first-stage horizontal signal amplifier 1 and the first-stage vertical signal amplifier 2 are respectively connected to a satellite signal filter 5 and a satellite signal distributor 9 in sequence;

[0028] The two output ends of the satellite signal distributor 9 connected to the first-level horizontal signal amplifier 1 are respectively connected to the horizontal signal input end of the first full-spectrum satellite digital chip 15 and the horizontal signal input end of the first CMOS satellite tuner 13;

[0029] The two output ends of the satellite signal distributor 9 connected to the first-stage vertical signal amplifier 2 are respectively connected to the vertical signal input end of the first full-spectrum satellite digital chip 15 and the vertical signal input end of the first CMOS satellite tuner 13 .

[0030] Preferably, the satellite B input module comprises a first-level horizontal signal amplifier 1, a first-level vertical signal amplifier 2, a satellite signal filter 5 and a satellite signal distributor 9;

[0031] The output ends of the first-stage horizontal signal amplifier 1 and the first-stage vertical signal amplifier 2 are respectively connected to a satellite signal filter 5 and a satellite signal distributor 9 in sequence;

[0032] The two output ends of the satellite signal distributor 9 connected to the first-level horizontal signal amplifier 1 are respectively connected to the horizontal signal input end of the second full-spectrum satellite digital chip 16 and the horizontal signal input end of the second CMOS satellite tuner 14;

[0033] The two output ends of the satellite signal distributor 9 connected to the first-stage vertical signal amplifier 2 are connected to the vertical signal input end of the second full-spectrum satellite digital chip 16 and the vertical signal input end of the second CMOS satellite tuner 14 respectively.

[0034] Preferably, two output terminals of the first CMOS satellite tuner 13 are connected to the first signal selection switch circuit 51 and the second signal selection switch circuit 52 respectively;

[0035] Two output terminals of the second CMOS satellite tuner 14 are respectively connected to the first signal selection switch circuit 51 and the second signal selection switch circuit 52;

[0036] Preferably, the first signal selection switch circuit 51 and the second signal selection switch circuit 52 are also provided with a DiseqC switching switch circuit 47, and the DiseqC switching switch circuit 47 is connected to the first signal selection switch circuit 51 and the second signal selection switch circuit 52 through a DC conversion circuit 49. The corresponding DiseqC switching switch circuit 47 provides corresponding voltage and tone to the corresponding circuit according to the instructions issued by the user's set-top box.

[0037] Preferably, the horizontal signal output terminal and the vertical signal output terminal of the first full-spectrum satellite digital chip 15 are both connected to a UHF filter 21 and a UHF distributor 25;

[0038] The two ports of the UHF distributor 25 connected to the horizontal signal output end of the first full-spectrum satellite digital chip 15 are respectively connected to the horizontal signal input ports of the first digital channel stacking chip 37 and the second digital channel stacking chip 38 through the UHF balanced and unbalanced circuit 29;

[0039] The two ports of the UHF distributor 25 connected to the vertical signal output end of the first full-spectrum satellite digital chip 15 are respectively connected to the vertical signal input ports of the first digital channel stacking chip 37 and the second digital channel stacking chip 38 through the UHF balanced and unbalanced circuit 29.

[0040] Preferably, the horizontal signal output terminal and the vertical signal output terminal of the second full-spectrum satellite digital chip 16 are both connected to a UHF filter 21 and a UHF distributor 25;

[0041] The two ports of the UHF distributor 25 connected to the horizontal signal output end of the second full-spectrum satellite digital chip 16 are respectively connected to the horizontal signal input ports of the first digital channel stacking chip 37 and the second digital channel stacking chip 38 through the UHF balanced and unbalanced circuit 29;

[0042] The two ports of the UHF distributor 25 connected to the vertical signal output end of the second full-spectrum satellite digital chip 16 are respectively connected to the vertical signal input ports of the first digital channel stacking chip 37 and the second digital channel stacking chip 38 through the UHF balanced and unbalanced circuit 29.

[0043] Preferably, the first digital channel stack chip 37 is provided with an MCU 43, and the first digital channel stack chip 37 is connected to the third output terminal via a balanced and unbalanced circuit 41 and a bandpass filter 45;

[0044] The second digital channel stack chip 38 is provided with an MCU 43 , and the first digital channel stack chip 37 is connected to the fourth output terminal via a balanced and unbalanced circuit 41 and a bandpass filter 45 .

[0045] Preferably, the circuit module also includes a power module, and supplies power to the overall structure.

[0046] It is worth noting that the first-level horizontal signal amplifier 1 and the first-level vertical signal amplifier 2 constitute the amplification of the two polarizations of satellite A, namely horizontal polarization and vertical polarization: the first-level horizontal signal amplifier 1 is the horizontal polarization amplifier of satellite A; the first-level vertical signal amplifier 2 is the vertical polarization amplifier of satellite A.

[0047] Another set of first-level horizontal signal amplifier 1 and first-level vertical signal amplifier 2 constitutes the two polarizations of satellite B, namely horizontal polarization and vertical polarization amplification. First-level horizontal signal amplifier 1 is the horizontal polarization amplifier of satellite B; first-level vertical signal amplifier 2 is the vertical polarization amplifier of satellite B.

[0048] In this embodiment, the function of the signal selection switch circuit is to select two satellite signals so that only one of them can pass through at the same time.

[0049] The first output terminal, the second output terminal, the third output terminal and the fourth output terminal are respectively a conventional satellite signal output terminal 1, a conventional satellite signal output terminal 2, a dCSS output port 1 and a dCSS output port 2.

[0050] The function of the first full-spectrum satellite digital chip 17 and the second full-spectrum satellite digital chip 18 is to reduce the frequency of the two polarization input signals to 0.3-2.35 GHz respectively and output them from the corresponding output terminals. The two output terminals are respectively connected to the corresponding UHF filters, and are input to the first digital channel stacking chip 37 and the second digital channel stacking chip 38 through the UHF balanced and unbalanced circuit after the UHF distributor. The first digital channel stacking chip 37 and the second digital channel stacking chip 38 and the MCU 43 connected to them respectively will detect the signals input from the output terminals dCSS output port 1 and dCSS output port 2 to move the corresponding satellite signals to the corresponding channels and output them to the corresponding users through the 950-2150 MHz balanced and unbalanced circuit and bandpass filter connected thereto.

[0051] In this embodiment, the CMOS satellite tuner is RDA3567 series of Tsinghua Unigroup, the full spectrum satellite digital chip is MXL802, and the digital channel stacking chip is MXL865.

[0052] In this embodiment, the first CMOS satellite tuner 13, the second CMOS satellite tuner 14, the first full-spectrum satellite digital chip 15, the second full-spectrum satellite digital chip 16, the first digital channel stack chip 37 and the second digital channel stack chip 38 are all provided with a frequency crystal oscillator, and a surface mount crystal oscillator with a frequency of 25 MHz is used.

[0053] In this embodiment, the balanced-unbalanced circuit, UHF filter, power supply filtering and isolation circuit, and 0.95-2150 bandpass filter are all composed of capacitors, resistors, and inductors. This is the application of the prior art, so no further description is given in this embodiment.

[0054] The power supply module is an application of the prior art and is used to supply power to the circuit module of this embodiment.

[0055] The above is a detailed description of the utility model in combination with specific embodiments, and it cannot be determined that the specific implementation methods of the utility model are limited to these descriptions. For ordinary technicians in the technical field to which the utility model belongs, making several equivalent substitutions or obvious modifications without departing from the concept of the utility model, and having the same performance or use, should be regarded as belonging to the patent protection scope of the utility model determined by the submitted claims.

Claims

1. A novel dual-satellite digital-analog composite low-noise frequency converter, the frequency converter comprising a housing and a circuit module in the housing, characterized in that: The circuit module comprises a satellite A input module, a satellite B input module, a first CMOS satellite tuner (13), a second CMOS satellite tuner (14), a first full-spectrum satellite digital chip (15), a second full-spectrum satellite digital chip (16), a first signal selection switch circuit (51), a second signal selection switch circuit (52), a first digital channel stacking chip (37), a second digital channel stacking chip (38), a first output terminal, a second output terminal, a third output terminal and a fourth output terminal; The satellite A input module is respectively connected to a first CMOS satellite tuner (13) and a first full-spectrum satellite digital chip (15); The satellite B input module is respectively connected to a second CMOS satellite tuner (14) and a second full-spectrum satellite digital chip (16); The first CMOS satellite tuner (13) is connected to a first signal selection switch circuit (51) and a second signal selection switch circuit (52) respectively; The second CMOS satellite tuner (14) is connected to the first signal selection switch circuit (51) and the second signal selection switch circuit (52) respectively; The full-spectrum satellite digital module is connected to the first digital channel stacking chip (37) and the second digital channel stacking chip (38) respectively; The two full-spectrum satellite digital modules are respectively connected to the first digital channel stacking chip (37) and the second digital channel stacking chip (38); The first signal selection switch circuit (51), the second signal selection switch circuit (52), the first digital channel stacking chip (37) and the second digital channel stacking chip (38) are respectively connected to the first output terminal, the second output terminal, the third output terminal and the fourth output terminal.

2. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The satellite A input module comprises a first-level horizontal signal amplifier (1), a first-level vertical signal amplifier (2), a satellite signal filter (5) and a satellite signal distributor (9); The output ends of the first-stage horizontal signal amplifier (1) and the first-stage vertical signal amplifier (2) are respectively connected in sequence to a satellite signal filter (5) and a satellite signal distributor (9); The two output ends of the satellite signal distributor (9) connected to the first-level horizontal signal amplifier (1) are respectively connected to the horizontal signal input end of the first full-spectrum satellite digital chip (15) and the horizontal signal input end of the first CMOS satellite tuner (13); The two output ends of the satellite signal distributor (9) connected to the first-level vertical signal amplifier (2) are respectively connected to the vertical signal input end of the first full-spectrum satellite digital chip (15) and the vertical signal input end of the first CMOS satellite tuner (13).

3. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The satellite B input module comprises a first-level horizontal signal amplifier (1), a first-level vertical signal amplifier (2), a satellite signal filter (5) and a satellite signal distributor (9); The output ends of the first-stage horizontal signal amplifier (1) and the first-stage vertical signal amplifier (2) are respectively connected in sequence to a satellite signal filter (5) and a satellite signal distributor (9); wherein two output ends of a satellite signal distributor (9) connected to the first-level horizontal signal amplifier (1) are respectively connected to a horizontal signal input end of a second full-spectrum satellite digital chip (16) and a horizontal signal input end of a second CMOS satellite tuner (14); The two output ends of the satellite signal distributor (9) connected to the first-level vertical signal amplifier (2) are respectively connected to the vertical signal input end of the second full-spectrum satellite digital chip (16) and the vertical signal input end of the second CMOS satellite tuner (14).

4. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The two output ends of the first CMOS satellite tuner (13) are respectively connected to a first signal selection switch circuit (51) and a second signal selection switch circuit (52); The two output ends of the second CMOS satellite tuner (14) are respectively connected to a first signal selection switch circuit (51) and a second signal selection switch circuit (52).

5. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The first signal selection switch circuit (51) and the second signal selection switch circuit (52) are both provided with a DiseqC switching switch circuit (47), and the DiseqC switching switch circuit (47) is connected to the first signal selection switch circuit (51) and the second signal selection switch circuit (52) via a DC conversion circuit (49).

6. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The horizontal signal output end and the vertical signal output end of the first full-spectrum satellite digital chip (15) are both connected to a UHF filter (21) and a UHF distributor (25); The two ports of the UHF distributor (25) connected to the horizontal signal output end of the first full-spectrum satellite digital chip (15) are respectively connected to the horizontal signal input ports of the first digital channel stacking chip (37) and the second digital channel stacking chip (38) through the UHF balanced and unbalanced circuit (29); The two ports of the UHF distributor (25) connected to the vertical signal output end of the first full-spectrum satellite digital chip (15) are respectively connected to the vertical signal input ports of the first digital channel stacking chip (37) and the second digital channel stacking chip (38) through the UHF balanced and unbalanced circuit (29).

7. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The horizontal signal output terminal and the vertical signal output terminal of the second full-spectrum satellite digital chip (16) are both connected to a UHF filter (21) and a UHF distributor (25); The two ports of the UHF distributor (25) connected to the horizontal signal output end of the second full-spectrum satellite digital chip (16) are respectively connected to the horizontal signal input ports of the first digital channel stacking chip (37) and the second digital channel stacking chip (38) through the UHF balanced and unbalanced circuit (29); The two ports of the UHF distributor (25) connected to the vertical signal output end of the second full-spectrum satellite digital chip (16) are respectively connected to the vertical signal input ports of the first digital channel stacking chip (37) and the second digital channel stacking chip (38) through the UHF balanced and unbalanced circuit (29).

8. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The first digital channel stacking chip (37) is provided with an MCU (43), and the first digital channel stacking chip (37) is connected to the third output terminal via a balanced and unbalanced circuit (41) and a bandpass filter (45); The second digital channel stacking chip (38) is provided with an MCU (43), and the first digital channel stacking chip (37) is connected to the fourth output terminal via a balanced and unbalanced circuit (41) and a bandpass filter (45).

9. The novel dual-satellite digital-analog composite low-noise downconverter according to claim 1 is characterized in that: The circuit module also includes a power supply module.

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