Semiconductor device and semiconductor package

Abstract

The utility model provides a semiconductor device, a semiconductor package and a method for forming the semiconductor device. A multilayer structure of a semiconductor device includes a metal ring structure and a dielectric sidewall structure along an interior sidewall of the metal ring structure. An interconnect line structure (e.g., a through-silicon via interconnect line structure) is along a central inner axis of the metal ring structure. The protective layer is between the interconnect structure and the dielectric sidewall structure. The protective layer may protect the dielectric sidewall structure from damage during a deposition operation of filling the cavity with the conductive material to form the interconnect line structure to improve quality and / or reliability of the semiconductor device.

Description

Technical Field

[0001] The utility model relates to a semiconductor device and a semiconductor package. Background Art

[0002] A multi-die package may include one or more integrated circuit (IC) dies bonded to an interposer. Examples of IC dies include system-on-chip (SoC) IC dies, dynamic random access memory (DRAM) IC dies, logic IC dies, and / or high bandwidth memory (HBM) IC dies, etc. An interposer may be used to redistribute ball contact areas from IC dies to a larger area of ​​the interposer. An interposer may enable three-dimensional (3D) packaging and / or other advanced semiconductor packaging technologies. Utility Model Content

[0003] The embodiment of the utility model provides a device. The device includes a multilayer structure, the multilayer structure includes a metal ring structure and a dielectric sidewall structure along the inner surface of the metal ring structure. The device includes an interconnection line structure arranged along the approximate central axis of the metal ring structure. The device includes a protective layer located between the interconnection line structure and the dielectric sidewall structure.

[0004] An embodiment of the utility model provides a semiconductor package. The semiconductor package includes an integrated circuit device. The semiconductor package includes an interconnection line structure array. The semiconductor package includes an interposer structure located between the integrated circuit device and the interconnection line structure array. The interposer structure includes a multilayer structure, which includes a metal ring structure and a metal layer connected to the metal ring structure above the metal ring structure. The interposer structure includes a semiconductor layer structure located below the multilayer structure and an interconnection line structure that passes through the semiconductor layer structure, along the approximate central axis of the metal ring structure and reaches the metal layer. The interposer structure also includes a protective layer located between the interconnection line structure and the metal ring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present invention will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 is a diagram of an example semiconductor structure described herein.

[0007] FIG. 2A to FIG. 2D is a diagram of an example implementation described herein.

[0008] Figure 3 is a diagram of an example semiconductor structure described herein.

[0009] FIG. 4A to FIG. 4C is a diagram of an example implementation described herein.

[0010] Figure 5 and Figure 6 is a diagram of an example implementation of a semiconductor package described herein.

[0011] FIG. 7A to FIG. 7D is a diagram of an example implementation described herein.

[0012] Figure 8 is a flow chart of an example process related to a semiconductor device and a method for manufacturing the same. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to be of the same material composition and having a thickness within the same thickness range.

[0015] In some cases, a semiconductor device (e.g., a semiconductor die or a semiconductor package) may include an interconnect structure, such as a through silicon via structure that passes through a multi-layer interconnect structure (including a multi-layer interconnect structure within an integrated circuit device, a substrate, or an interposer, etc.). In addition, the multi-layer structure may include a metal ring structure (e.g., a protective shell) that is inserted into the surrounding materials (e.g., multiple layers of surrounding dielectric and / or conductive materials) of the through silicon via structure and the multi-layer interconnect structure. The metal ring structure can reduce the possibility of damage to the surrounding materials during the formation of the through silicon via structure. In addition, the metal ring structure can inhibit the diffusion and / or migration of materials from the through silicon via structure into the surrounding materials to reduce the possibility of contamination within the surrounding materials and / or the possibility of electrical short circuits between layers of the surrounding materials.

[0016] The formation of the through silicon via structure may include etching through one or more dielectric layers within the inner perimeter of the metal ring structure and / or etching into a cavity in one or more dielectric layers within the inner perimeter of the metal ring structure. After etching the cavity, the dielectric sidewall structure may remain on the inner surface of the metal ring structure. During the deposition operation of filling the cavity with a conductive material to form the through silicon via structure, the dielectric sidewall structure may be susceptible to delamination defects due to damage that occurs during cavity etching. Such damage and / or delamination defects may reduce the quality (e.g., manufacturing yield) and / or reliability (e.g., during field use) of the semiconductor package.

[0017] Some embodiments of the present invention provide semiconductor devices and methods for forming semiconductor devices. The multilayer structure of the semiconductor device includes a metal ring structure and a dielectric sidewall structure along the inner sidewall of the metal ring structure. The interconnection line structure (e.g., silicon through hole structure) is along the central inner axis of the metal ring structure. The protective layer is located between the interconnection line structure and the dielectric sidewall structure.

[0018] During the deposition operation of filling the cavity with conductive material along the central inner axis to form the interconnect structure, the protective layer can protect the dielectric sidewall structure from damage (e.g., delamination effect and / or pitting). In addition, the protective layer can inhibit the conductive material from diffusing into the dielectric sidewall structure and / or the metal ring structure.

[0019] As a result, the quality and / or reliability of a semiconductor device including an interconnect structure and formed using a protective layer is improved relative to another semiconductor device including an interconnect structure but not formed using a protective layer. By improving the quality and / or reliability of the semiconductor device, the amount of resources (e.g., raw materials, labor, semiconductor manufacturing tools, and / or computing resources) used to manufacture and support the volume of the semiconductor device including the interconnect structure is reduced.

[0020] Figure 11 is a diagram of an example semiconductor structure 100 described herein. The example semiconductor structure 100 includes a multilayer structure 102a and a semiconductor layer structure 104a. Figure 1 As shown, relative to the multilayer structure 102a, the semiconductor layer structure 104a is located above the multilayer structure 102a.

[0021] The multilayer structure 102a includes one or more dielectric layers 106a. The one or more dielectric layers 106a may include a dielectric material, such as a silicon oxide material, a silicon nitride material, a low-k dielectric material, or another suitable dielectric material. In addition, one or more metal layers may be dispersed within the one or more dielectric layers 106a to form a metal ring structure 108a. Among other examples, the one or more metal layers may include a titanium nitride material, a titanium material, a copper material, a gold material, a nickel material, an aluminum material, or another suitable metal material. Additionally or alternatively, the one or more metal layers forming the metal ring structure 108a may include one or more conductive materials other than metal materials. Furthermore, in some embodiments and as Figure 1 As shown, the metal layer 110a is connected to the bottom periphery of the metal ring structure 108a and is included as a part of the metal ring structure 108a. As a part of a semiconductor device (for example, a semiconductor die or a semiconductor package), the metal ring structure 108a and / or the metal layer 110a can provide circuits and / or electrical connections between circuits and interconnect structures (for example, internal interconnect structures and / or external interconnect structures).

[0022] The semiconductor layer structure 104a may further include a semiconductor layer 112a including a material such as silicon. In some embodiments, the semiconductor layer structure 104a includes semiconductor devices and / or components formed in the semiconductor layer 112a. For example, Figure 1 As shown, the semiconductor layer structure 104a includes a shallow trench isolation region 114a (eg, a non-conductive region that electrically isolates adjacent devices within the semiconductor layer 112a).

[0023] like Figure 1As shown, the interconnection line structure 116a is arranged along the approximate central axis 118a of the metal ring structure 108. The interconnection line structure 116a corresponding to the backside through silicon via (BTSV) structure may include a conductive material, such as titanium nitride material, titanium material, copper material, gold material, nickel material, aluminum material or other suitable conductive materials. In a semiconductor package (ball grid array semiconductor package, wafer-on-wafer semiconductor package, image sensor semiconductor package, stacked die semiconductor package or three-dimensional integrated circuit die package, etc.), the interconnection line structure 116a may provide electrical connectivity between the metal layer 110a and another conductive structure (such as an integrated circuit die pad, wire bonding, pillar or solder ball, etc.).

[0024] Figure 1 The multilayer structure 102a further includes a dielectric sidewall structure 120a along the inner surface of the metal ring structure 108a. In some embodiments, and in combination with FIG. 2A to FIG. 2D As described elsewhere herein, the dielectric sidewall structure 120a includes portions of the one or more dielectric layers 106a remaining after an etching operation to form a cavity used by the interconnect line structure 116a.

[0025] like Figure 1 As further shown, a protection layer 122a (eg, a protection sidewall layer) is located between the interconnect structure 116a and the dielectric sidewall structure 120a. The protection layer 122a may include silicon dioxide material, aluminum oxide material, or another suitable oxide material.

[0026] exist Figure 1 In the embodiment, the metal layer 110a and the protective layer 122a are separated. Figure 1 As shown, metal layer 110a is connected to interconnect line structure 116a.

[0027] As combined FIG. 2A to FIG. 2D As described in more detail elsewhere herein, the protective layer 122a can protect the dielectric sidewall structure 120a from damage (e.g., delamination effects and / or pitting) during the deposition operation of forming the interconnect structure 116a. In addition, the protective layer 122a can inhibit the diffusion of the material used to form the interconnect structure 116a into the dielectric sidewall structure 120a, the metal ring structure 108a, and / or one or more dielectric layers 106a.

[0028] Thus, the quality and / or reliability of a semiconductor device including the interconnect structure 116a and formed using the protective layer 122a is improved relative to another similar semiconductor device formed without the protective layer. By improving the quality and / or reliability of semiconductor devices, the amount of resources (e.g., raw materials, labor, semiconductor manufacturing tools, and / or computing resources) required to manufacture and support a certain volume of semiconductor devices is reduced.

[0029] Figure 1 The number and arrangement of devices shown in the figure are provided as one or more examples. In practice, there may be Figure 1 Additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG.

[0030] FIG. 2A to FIG. 2D is a diagram of an example embodiment 200 described herein. Embodiment 200 includes forming Figure 1 A series of semiconductor manufacturing operations of the semiconductor structure 100. The series of semiconductor manufacturing operations can be performed by one or more semiconductor processing tool groups, such as a deposition tool group (e.g., a vapor deposition tool group and / or an electroplating tool), a lithography tool group (a photoresist coating tool, an exposure tool, a development tool and / or a photoresist removal tool), an etching tool group (e.g., a dry etching tool group or a wet etching tool group), a planarization tool group (e.g., a chemical mechanical planarization (CMP) tool) and / or a bonding tool group (e.g., a eutectic bonding tool group), as well as other examples.

[0031] Figure 2A A semiconductor layer structure 104a is shown on and / or over the multilayer structure 102a. In some embodiments, the layers of the multilayer structure 102a (e.g., one or more dielectric layers 106a, metal layers of metal ring structures 108a, and / or metal layer 110a) are sequentially deposited by a deposition tool disposed therein, such as a chemical vapor deposition (CVD) operation, a physical vapor deposition (PVD) operation, an atomic layer deposition (ALD) operation, an electroplating operation, and / or other suitable deposition operations.

[0032] In some embodiments, the planarization tool set planarizes a layer of the multilayer structure 102a after the deposition tool set deposits the layer. In some embodiments, the lithography tool set and / or the etching tool set can perform a series of patterning and / or etching operations to form features from the layer after deposition and / or planarization.

[0033] In some embodiments, and as part of forming the semiconductor layer structure 104a, the deposition tool set may form a semiconductor layer 112a on the multilayer structure 102a using an epitaxial growth operation or another suitable deposition operation. Alternatively, the bonding tool set may bond the semiconductor layer structure 104a (e.g., the semiconductor layer structure 104a including the shallow trench isolation region 114a) and the multilayer structure 102a using a eutectic bonding operation or another suitable bonding operation.

[0034] like Figure 2B As shown, and as part of embodiment 200, a cavity 202a is formed through the semiconductor layer structure 104a and into one or more dielectric layers 106a. The cavity 202a is formed within the metal ring structure 108a and along the approximate central axis 118a. In some embodiments, the pattern in the photoresist layer is used to etch a portion of the semiconductor layer structure 104a and one or more dielectric layers 106a to form the cavity 202a. In these embodiments, a photoresist coating tool forms a photoresist layer on the semiconductor layer structure 104a. An exposure tool exposes the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool develops and removes a portion of the photoresist layer to expose a pattern. An etching tool etches the semiconductor layer structure 104a (e.g., a portion of the semiconductor layer 112a and / or the shallow trench isolation region 114a) and the multilayer structure 102a (e.g., a portion of the one or more dielectric layers 106a) to form the cavity 202a on the pattern. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching through the semiconductor layer structure 104a and into the one or more dielectric layers 106a.

[0035] After forming cavity 202a, the deposition tool may deposit protective layer 122a in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, or another type of deposition operation. The deposition tool may deposit protective layer 122a within cavity 202a, including forming cavity 202a on and / or over dielectric sidewall structure 120a (e.g., portions of one or more dielectric layers 106a exposed and / or left behind by an etching operation).

[0036] like Figure 2CAs shown, and as part of embodiment 200, a cavity 202b is formed through the protective layer 122a and through a portion of one or more dielectric layers 106a to expose the metal layer 110a. The cavity 202b is along the approximate central axis 118a. In some embodiments, the pattern in the photoresist layer is used to etch through the protective layer 122a and etch through a portion of one or more dielectric layers 106a to form the cavity 202b. In these embodiments, a photoresist coating tool forms a photoresist layer on the semiconductor layer structure 104a and in the cavity 202a. The exposure tool exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool develops and removes a portion of the photoresist layer to expose the pattern. The etching tool etches through the protective layer 122a and through a portion of one or more dielectric layers 106a based on the pattern to form the cavity 202b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching through the protective layer 122a and through a portion of one or more dielectric layers 106a.

[0037] like Figure 2D As shown, and as part of embodiment 200, interconnect structure 116a is formed along approximate central axis 118a (e.g., within cavities 202a and 202b). The deposition tool and / or the electroplating tool can deposit the interconnect structure 116a in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, and / or another suitable deposition operation. In some embodiments, after the deposition tool and / or the electroplating tool deposits the interconnect structure 116a, a planarization tool planarizes the interconnect structure 116a.

[0038] exist Figure 2D During the deposition operation of the dielectric sidewall structure 120a, the protective layer 122a can protect the dielectric sidewall structure 120a from damage (e.g., delamination effects and / or pitting). In addition, the protective layer 122a can inhibit the diffusion of materials used to form the interconnect structure 116a into the dielectric sidewall structure 120a, the metal ring structure 108a, and / or one or more dielectric layers 106a. In this way, the quality and / or reliability of a semiconductor device including the multilayer structure 102a and formed using the protective layer 122a is improved relative to another semiconductor device including a similar multilayer structure but not formed using the protective layer 122a.

[0039] Although FIG. 2A to FIG. 2D An exemplary series of manufacturing operations is shown, which in some embodiments may include FIG. 2A to FIG. 2DIn addition or alternatively, one or more manufacturing operations may be performed in addition to the manufacturing operations depicted in the drawings. FIG. 2A to FIG. 2D The present invention may be performed with a semiconductor processing tool other than the semiconductor processing tool described herein.

[0040] Figure 3 1 is a diagram of an example semiconductor structure 300 described herein. The example semiconductor structure 300 includes a multilayer structure 102b and a semiconductor layer structure 104b. Figure 3 As shown, relative to the multilayer structure 102b, the semiconductor layer structure 104b is located below the multilayer structure 102b.

[0041] The multilayer structure 102b includes one or more dielectric layers 106b. The one or more dielectric layers 106b may include a dielectric material, such as a silicon oxide material, a silicon nitride material, a low-k dielectric material, or another suitable dielectric material. In addition, one or more metal layers may be dispersed within the one or more dielectric layers 106b to form a metal ring structure 108b. Among other examples, the one or more metal layers may include a titanium nitride material, a titanium material, a copper material, a gold material, a nickel material, an aluminum material, or another suitable metal material. Additionally or alternatively, the one or more metal layers forming the metal ring structure 108b may include one or more conductive materials other than a metal material.

[0042] Providing circuits and / or electrical connections between circuits, internal interconnect structures and / or external interconnect structures, etc. Additionally or alternatively, within the semiconductor device, the semiconductor layer structure 104b may include a semiconductor layer 112b including a material such as silicon.

[0043] like Figure 3 As shown, the interconnect structure 116b is arranged along the approximate central axis 118b of the metal ring structure 108b. Figure 3 As shown, at least a portion of the interconnect structure 116b penetrates into the semiconductor layer structure 104b below the multilayer structure 102b. The interconnect structure 116b corresponding to the frontside through silicon via (FTSV) structure may include a conductive material, such as titanium nitride material, titanium material, copper material, gold material, nickel material, aluminum material, or other suitable conductive materials. In a semiconductor package (such as a ball grid array semiconductor package, a wafer-on-wafer semiconductor package, an image sensor semiconductor package, a stacked die semiconductor package, or a three-dimensional integrated circuit die package), the interconnect structure 116b may be connected to another conductive structure, such as an integrated circuit die pad, a wire bond, a column or a solder ball.

[0044] Figure 3The multilayer structure 102b further includes a dielectric sidewall structure 120b along the inner surface of the metal ring structure 108b. In some embodiments, and in combination with FIG. 4A to FIG. 4C As described elsewhere herein, the dielectric sidewall structure 120b includes portions of one or more dielectric layers 106b remaining after a cavity is formed during an etching operation used to form the interconnect line structure 116b.

[0045] like Figure 3 As further shown, a protection layer 122b (eg, a protection sidewall layer) is located between the interconnect structure 116b and the dielectric sidewall structure 120b. The protection layer 122b may include silicon dioxide material, aluminum oxide material, or another suitable oxide material.

[0046] As combined FIG. 4A to FIG. 4C As described in more detail elsewhere herein, the protective layer 122b can protect the dielectric sidewall structure 120b from damage (e.g., delamination effects and / or pitting) during the deposition operation of forming the interconnect structure 116b. In addition, the protective layer 122b can inhibit the diffusion of materials used to form the interconnect structure 116b into the dielectric sidewall structure 120b, the metal ring structure 108b, and / or one or more dielectric layers 106b.

[0047] As a result, the quality and / or reliability of the semiconductor device including the interconnect structure 116b and formed using the protective layer 122b is improved relative to another similar semiconductor device formed without the protective layer. By improving the quality and / or reliability of the semiconductor device, the amount of resources (e.g., raw materials, labor, semiconductor manufacturing tools, and / or computing resources) required to manufacture and support a certain volume of semiconductor devices is reduced.

[0048] Figure 3 The number and arrangement of devices shown in the figure are provided as one or more examples. Figure 3 There may be additional devices, fewer devices, different devices, or differently arranged devices than those shown.

[0049] FIG. 4A to FIG. 4C is a diagram of an example embodiment 400 described herein. Embodiment 400 includes forming Figure 3A series of semiconductor manufacturing operations of the semiconductor structure 300. The series of semiconductor manufacturing operations can be performed by one or more semiconductor processing tool groups, such as a deposition tool group (e.g., a vapor deposition tool group and / or an electroplating tool), a lithography tool group (a photoresist coating tool, an exposure tool, a development tool and / or a photoresist removal tool), an etching tool group (e.g., a dry etching tool group or a wet etching tool), a planarization tool group (e.g., a chemical mechanical planarization (CMP) tool) and / or a bonding tool group (e.g., a eutectic bonding tool group).

[0050] Figure 4A The semiconductor layer structure 104b above and / or below the multilayer structure 102b is shown. In some embodiments, the layers of the multilayer structure 102b (e.g., one or more dielectric layers 106b and metal layers 108b of the metal ring structure 108b) are sequentially deposited by a deposition tool group in a chemical vapor deposition (CVD) operation, a physical vapor deposition (PVD) operation, an atomic layer deposition (ALD) operation, an electroplating operation, and / or other suitable deposition operations. In some embodiments, a planarization tool group planarizes the layers of the multilayer structure 102b after the deposition tool group deposits the multilayer structure 102b.

[0051] In some embodiments, and as part of forming the semiconductor layer structure 104b, the deposition tool set can form the semiconductor layer 112b on the multilayer structure 102b using an epitaxial growth operation or another suitable deposition operation. Alternatively, the bonding tool set can bond the semiconductor layer structure 104b and the multilayer structure 102b using a eutectic bonding operation or another suitable bonding operation.

[0052] like Figure 4BAs shown, and as part of embodiment 400, a cavity 202c is formed by passing through one or more dielectric layers 106b and entering semiconductor layer 112b. Cavity 202c is formed in metal ring structure 108b and along approximate central axis 118b. In some embodiments, the pattern in the photoresist layer is used to etch a portion of multilayer structure 102b (e.g., one or more dielectric layers 106b) and semiconductor layer structure 104b (e.g., a portion of semiconductor layer 112b) to form cavity 202c. In these embodiments, a photoresist coating tool forms a photoresist layer on multilayer structure 102b. An exposure tool exposes the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool develops and removes a portion of the photoresist layer to expose a pattern. An etching tool etches a portion of one or more dielectric layers 106b and a portion of semiconductor layer 112b based on the pattern to form cavity 202c. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching through the semiconductor layer structure 104b and into the one or more dielectric layers 106b.

[0053] After forming cavity 202c, the deposition tool may deposit protective layer 122b in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, or another type of deposition operation. The deposition tool may deposit protective layer 122b within cavity 202c, including forming cavity 202c on and / or over dielectric sidewall structure 120b (e.g., portions of one or more dielectric layers 106b exposed and / or left behind by an etching operation).

[0054] like Figure 4C As shown, and as part of embodiment 400, interconnect structure 116b is formed along approximate central axis 118b (e.g., within cavity 202c). The deposition tool and / or electroplating tool can deposit interconnect structure 116b in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, and / or another suitable deposition operation. In some embodiments, after the deposition tool and / or electroplating tool deposits interconnect structure 116b, a planarization tool planarizes interconnect structure 116b.

[0055] exist Figure 4CDuring the deposition operation of the dielectric sidewall structure 120b, the protective layer 122b can protect the dielectric sidewall structure 120b from damage (e.g., delamination effects and / or pitting). In addition, the protective layer 122b can inhibit the diffusion of materials used to form the interconnect structure 116b into the dielectric sidewall structure 120b, the metal ring structure 108b, and / or one or more dielectric layers 106b. In this way, the quality and / or reliability of a semiconductor device including the multilayer structure 102b and formed using the protective layer 122b is improved relative to another semiconductor device including a similar multilayer structure but not formed using the protective layer 122b.

[0056] Although FIG. 4A to FIG. 4C An exemplary series of manufacturing operations is shown, which in some embodiments may include FIG. 4A to FIG. 4C In addition or alternatively, one or more manufacturing operations may be performed in addition to the combined manufacturing operations. FIG. 4A to FIG. 4C The invention may be performed using semiconductor processing tools other than those described.

[0057] As combined Figures 1 to 4C As described, a device (e.g., a semiconductor die and / or a semiconductor package) includes a multilayer structure (e.g., multilayer structure 102a and / or 102b) including a metal ring structure (e.g., metal ring structure 108a and / or 108b) and a dielectric sidewall structure (e.g., dielectric sidewall structure 120a and / or 120b) along an inner surface of the metal ring structure. The device includes an interconnect structure (e.g., interconnect structure 116a and / or 116b) disposed along an approximate central axis (e.g., central axis 118a and / or 118b) of the metal ring structure. The device includes a protective layer (e.g., protective layer 122a and / or 122b) located between the interconnect structure and the dielectric sidewall structure.

[0058] Figure 5 is a diagram of an example embodiment 500 of an example semiconductor package 502c. The semiconductor package 502c may include, in whole or in part, features associated with a ball grid array semiconductor package, a wafer-on-wafer semiconductor package, an image sensor semiconductor package, a stacked die semiconductor package, or a three-dimensional integrated circuit die package, among others.

[0059] like Figure 5As shown, semiconductor package 502c includes one or more integrated circuit dies 504c. Among other examples, one or more integrated circuit dies 504c may correspond to one or more of a memory integrated circuit die, a logic integrated circuit die, or a computer image sensor integrated circuit die. In some embodiments, one or more integrated circuit dies 504c are "stacked" integrated circuit dies (e.g., a three-dimensional structure including integrated circuit dies stacked and / or bonded by a "wafer-on-wafer" manufacturing process).

[0060] In addition, if Figure 5 As shown, the semiconductor package includes an interposer structure 506c located between one or more integrated circuit dies 504c and an array of interconnect structures 508c (e.g., an array of external interconnect structures). The interposer structure 506c may correspond to a multi-layer printed circuit board or a silicon interposer with one or more redistribution layers, etc. The array of interconnect structures 508c may include an array of integrated circuit die pads, wire bonds, pillars, solder balls, etc.

[0061] Interposer structure 506c may include semiconductor structure 510. Semiconductor structure 510 may include multilayer structure 102c on and / or over semiconductor layer structure 104c. Figure 1 The multilayer structure 102a, the multilayer structure 102c may include an array of one or more dielectric layers 106c, metal ring structures 108c and metal layers 110c. Figure 1 Similar to the semiconductor layer structure 104 a , the semiconductor layer structure 104 c may include a semiconductor layer 112 c and a shallow trench isolation region 114 c within the semiconductor layer 112 c .

[0062] Similar to Figure 1 1. The semiconductor structure 510 of FIG. 100 includes an interconnect line structure 116c disposed along an approximate central axis 118c of the metal ring structure 108c.

[0063] In the interposer structure 506c, and for Figure 5 As shown in the backside through silicon via type interconnect structure, the interconnect structure 116c may include a tapered shape. In addition, and in some embodiments, the width D1 of the interconnect structure 116c may be included in the range of about 10 microns to about 500 microns. However, other values ​​and ranges of width D1 are also within the scope of the present invention.

[0064] The semiconductor structure 510 further includes a protection layer 122c located between the interconnect structure 116c and the metal ring structure 108c. Figure 1Compared to the semiconductor structure 100 of FIG. 5 , the semiconductor structure 510 does not have a dielectric sidewall structure (eg, similar to the dielectric sidewall structure 120 a of the semiconductor structure 100 ). Therefore, the interconnect structure 116 c is “self-aligned” with the metal ring structure 108 c.

[0065] Figure 5 The number and arrangement of devices shown in the figure are provided as one or more examples. In practice, there may be Figure 5 The devices shown may include additional devices, fewer devices, different devices, or differently arranged devices.

[0066] Figure 6 6 is a diagram of an example embodiment 600 of an example semiconductor package 502d described herein. The semiconductor package 502d may include, in whole or in part, features associated with a ball grid array semiconductor package, a wafer-on-wafer semiconductor package, an image sensor semiconductor package, a stacked die semiconductor package, or a three-dimensional integrated circuit die package, among others.

[0067] like Figure 6 As shown, semiconductor package 502d includes one or more integrated circuit dies 504d. Among other examples, one or more integrated circuit dies 504d can correspond to one or more of a memory integrated circuit die, a logic integrated circuit die, or a computer image sensor integrated circuit die. In some embodiments, one or more integrated circuit dies 504d are "stacked" integrated circuit dies (e.g., a three-dimensional structure including integrated circuit dies stacked and / or bonded by a "wafer-on-wafer" manufacturing process).

[0068] In addition, if Figure 6 As shown, the semiconductor package includes an interposer structure 506d located between one or more integrated circuit dies 504d and an array of interconnect structures 508d (e.g., an array of external interconnect structures). The interposer structure 506d may correspond to a multi-layer printed circuit board or a silicon interposer having one or more redistribution layers, etc. The array of interconnect structures 508d may include an array of integrated circuit die pads, wire bonds, pillars, solder balls, etc.

[0069] Interposer structure 506d may include semiconductor structure 602. Semiconductor structure 602 may include multilayer structure 102d on and / or over semiconductor layer structure 104d. Figure 1 The multilayer structure 102a, the multilayer structure 102d may include an array of one or more dielectric layers 106d, metal ring structures 108d and metal layers 110d. Figure 1 Similar to the semiconductor layer structure 104 a , the semiconductor layer structure 104 d may include a semiconductor layer 112 d and a shallow trench isolation region 114 d within the semiconductor layer 112 d .

[0070] Similar to Figure 1 1. The semiconductor structure 602 of the embodiment of the present invention includes an interconnect line structure 116d disposed along an approximately central axis 118d of the metal ring structure 108d.

[0071] In the interposer structure 506d, and for Figure 6 As shown in the backside through silicon via type interconnect structure, the interconnect structure 116d may include a tapered shape. In addition, and in some embodiments, the width D1 of the interconnect structure 116d may be included in the range of about 10 microns to about 500 microns. However, other values ​​and ranges of width D1 are also within the scope of the present invention.

[0072] The semiconductor structure 602 further includes a protection layer 122d between the interconnect structure 116d and the dielectric sidewall structure 120d. As a result, the interconnect structure 116d and the metal ring structure 108d are “non-self-aligned”.

[0073] Figure 6 The number and arrangement of devices shown in the figure are provided as one or more examples. In practice, there may be Figure 6 Additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG.

[0074] FIG. 7A to FIG. 7D is a diagram of an example embodiment 700 described herein. Figure 5 The semiconductor package 502c and / or Figure 6 The series of semiconductor manufacturing operations of the semiconductor package 502d can be performed by one or more semiconductor processing tool groups, such as a deposition tool group (e.g., a vapor deposition tool and / or an electroplating tool), a lithography tool group (a photoresist coating tool, an exposure tool, a development tool, and / or a photoresist removal tool), an etching tool group (e.g., a dry etching tool group or a wet etching tool), a planarization tool group (e.g., a chemical mechanical planarization (CMP) tool), and / or a bonding tool group (e.g., a eutectic bonding tool group).

[0075] like Fig. 7A As shown, one or more integrated circuit dies 504e are on and / or over interposer structure 506e. Interposer structure 506e may include metal ring structure 108e and / or metal layer 110e. In some embodiments, a method similar to bonding is used. Figure 2A and / or Figure 4A Techniques are described to form interposer structures.

[0076] In some embodiments, Fig. 7AAs shown, one or more integrated circuit dies 504e and interposer structure 506e are bonded. As an example, a bonding tool may bond one or more integrated circuit dies 504e to interposer structure 506e using a eutectic bonding process or another suitable bonding process.

[0077] like Figure 7B As shown, and as part of embodiment 700, a temporary carrier 702 (e.g., a silicon substrate or a glass substrate) is bonded to one or more integrated circuit dies 504e. As an example, a bonding tool can use a eutectic bonding process or another suitable bonding process to bond the temporary carrier 702 and the one or more integrated circuit dies 504e.

[0078] like Figure 7C As shown, and as part of embodiment 700, temporary carrier 702, one or more integrated circuit dies 504e, and interposer structure 506e are inverted. Figure 2B and / or Figure 4B Similar to the techniques described above, the photolithography tool set and the etching tool set can form cavity 202e through a portion of interposer structure 506e to expose metal layer 110e. In addition, the deposition tool set can form a protective layer 122e in cavity 202e, wherein the protective layer 122e is formed on and / or over the sidewall structure within the cavity (which may include the remaining portion of the dielectric layer in interposer structure 506e exposed during the etching process).

[0079] like Fig.7D As shown, and as part of embodiment 700, interconnect structure 116e is formed on and / or over protection layer 122e (eg, within cavity 202e). Figure 2D and / or Figure 4C A deposition tool set and / or a planarization tool set may form interconnect structure 116e on and / or over protection layer 122e using techniques similar to those described above.

[0080] After forming interconnect line structure 116e on and / or over the protective layer, interposer structure 506e may be connected to the interconnect line structure array (eg, Figure 5 The interconnection line structure array 508c, Figure 6 In some embodiments, bonding the interposer structure 506e to the interconnect structure array includes filling the interposer structure 506e into the interconnect structure array using a solder ball formation process or a bump process. In some embodiments, bonding the interposer structure 506e to the interconnect structure array includes bonding the interposer to another structure including the interconnect structure array (e.g., using a wire bonding process or a surface mount process).

[0081] Although FIG. 7A to FIG. 7D An exemplary series of manufacturing operations is shown, which in some embodiments may include FIG. 7A to FIG. 7D In addition or alternatively, one or more manufacturing operations may be performed in addition to the combined manufacturing operations. FIG. 7A to FIG. 7D The invention may be performed using semiconductor processing tools other than those described.

[0082] As combined Figures 5 to 7D As described, a semiconductor package (e.g., semiconductor package 502c and / or 502d) includes an integrated circuit device (e.g., one or more integrated circuit dies 504c and / or 504d). The semiconductor package includes an array of interconnect line structures (e.g., interconnect line structure arrays 508c and / or 508d). The semiconductor package includes an interposer structure (e.g., interposer structure 506c and / or 506d) located between the integrated circuit device and the array of interconnect line structures. The interposer structure includes a multi-layer structure (e.g., multi-layer structure 102c and / or 102d) including a metal ring structure (e.g., metal ring structure 108c and / or 108d) and a metal layer (e.g., metal layer 110c and / or 110d) connected to the metal ring structure on the metal ring structure. The interposer structure includes a semiconductor layer structure (e.g., semiconductor layer structure 104c and / or 104d) located below the multilayer structure and an interconnection line structure (e.g., interconnection line structure 116c and / or 116c) passing through the multilayer structure along the approximate central axis of the metal ring structure (e.g., approximate central axis 118c and / or 118d) and onto the metal layer. The interposer structure also includes a protective layer (e.g., protective layer 122c and / or 122d) located between the interconnection line structure and the metal ring structure.

[0083] Figure 8 is a flow chart of an example process 800 associated with a semiconductor device and a method for manufacturing the same. In some embodiments, Figure 8 One or more process blocks are combined as follows FIG. 2A to FIG. 2D , FIG. 4A to FIG. 4C , FIG. 7A to FIG. 7D and one or more semiconductor processing tools described elsewhere herein.

[0084] like Figure 8 As shown, process 800 may include forming a multilayer structure including a metal ring structure (block 810). For example, one or more semiconductor processing tools may form a multilayer structure (eg, multilayer structure 102) including a metal ring structure (eg, metal ring structure 108) as described herein.

[0085] like Figure 8As further shown, process 800 may include forming a cavity within one or more dielectric layers within the metal ring structure and along an approximate central axis of the metal ring structure (block 820). For example, one or more semiconductor processing tools may form a cavity within one or more dielectric layers (e.g., one or more dielectric layers 106) within the metal ring structure and along an approximate central axis (e.g., as described herein, approximate central axis 118 of the metal ring structure).

[0086] like Figure 8 As further shown, process 800 may include forming a protective layer within the cavity (block 830). For example, one or more semiconductor processing tools may form a protective layer (eg, protective layer 122) within the cavity, as described herein.

[0087] like Figure 8 As further shown, process 800 may include forming an interconnect structure over the protective layer (block 840). For example, one or more semiconductor processing tools may form an interconnect structure (eg, interconnect structure 116) over the protective layer as described herein.

[0088] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0089] In a first embodiment, forming the cavity includes exposing portions of one or more dielectric layers within the metal ring structure to form a dielectric sidewall structure (eg, dielectric sidewall structure 120 ) along an inner surface of the metal ring structure.

[0090] In a second embodiment, alone or in combination with the first embodiment, forming a protection layer within the cavity includes forming a protection layer on a surface of the dielectric sidewall structure.

[0091] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the multi-layer structure includes forming a metal layer (eg, metal layer 110 ) directly connected to the metal ring structure below the metal ring structure.

[0092] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the cavity includes forming a first cavity (e.g., cavity 202a) through a semiconductor layer structure (e.g., semiconductor layer structure 104a). Above the multilayer structure, a second cavity (e.g., cavity 202b) is formed through the protective layer to expose the metal layer.

[0093] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming an interconnect structure over the protection layer includes forming a portion of the interconnect structure in the second cavity to connect the interconnect structure and the metal layer.

[0094] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming a cavity includes forming a portion of a cavity (e.g., a portion of cavity 202c) in a semiconductor layer structure (e.g., semiconductor layer structure 104b) located below a multilayer structure (e.g., located below multilayer structure 102b).

[0095] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, forming a protective layer in the cavity includes forming a portion of the protective layer on the surface of the semiconductor layer structure (the surface of the semiconductor layer structure 104b) so that a portion of the cavity (for example, a portion of the cavity 202c) is exposed.

[0096] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, forming an interconnect structure above the protective layer includes forming the interconnect structure to include a penetrating portion (e.g., a portion of the interconnect structure 116b) into the semiconductor layer structure (e.g., the semiconductor layer structure 104b).

[0097] In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, process 800 includes forming an interposer structure (e.g., interposer structure 506) including a multi-layer structure and an interconnect line structure array (e.g., interconnect line structure array 508) as part of forming a semiconductor package (e.g., semiconductor package 502).

[0098] although Figure 8 Example blocks of process 800 are shown, but in some embodiments, process 800 includes Figure 8 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 800. Additionally or alternatively, two or more blocks of process 800 may be performed in parallel.

[0099] As FIG. 2A to FIG. 2D , FIG. 4A to FIG. 4C , FIG. 7A to FIG. 7D and Figure 8 As described, a series of semiconductor manufacturing operations may include forming a multilayer structure including a metal ring structure. The series of semiconductor manufacturing operations include forming a cavity within one or more dielectric layers within the metal ring structure and along an approximate central axis of the metal ring structure. In addition, the series of semiconductor manufacturing operations include forming a protective layer within the cavity. The series of semiconductor manufacturing operations include forming an interconnect structure above the protective layer.

[0100] This series of semiconductor manufacturing operations can be applied to the formation of semiconductor devices (e.g., semiconductor dies or semiconductor packages). One or more semiconductor manufacturing operations can be performed in a semiconductor wafer manufacturing facility for manufacturing semiconductor dies. Additionally or alternatively, one or more semiconductor manufacturing operations can be performed in an outsourced assembly and test (OSAT) manufacturing facility for assembling and testing semiconductor packages.

[0101] Some embodiments of the present invention provide semiconductor devices and methods for forming semiconductor devices. The multilayer structure of the semiconductor device includes a metal ring structure and a dielectric sidewall structure along the inner sidewall of the metal ring structure. The interconnection line structure (e.g., a through silicon via interconnection line structure) is along the central inner axis of the metal ring structure. The protective layer is located between the interconnection line structure and the dielectric sidewall structure.

[0102] During the deposition operation of filling the cavity with a conductive material to form an interconnect structure, the protective layer can protect the dielectric sidewall structure from damage (eg, delamination and / or pitting). In addition, the protective layer can inhibit the conductive material from diffusing into the dielectric sidewall structure and / or the metal ring structure.

[0103] As a result, the quality and / or reliability of a semiconductor device including an interconnect structure and formed using a protective layer is improved relative to another semiconductor device including an interconnect structure but not formed using a protective layer. By improving the quality and / or reliability of the semiconductor device, the amount of resources (e.g., raw materials, labor, semiconductor manufacturing tools, and / or computing resources) used to manufacture and support the volume of the semiconductor device including the interconnect structure is reduced.

[0104] As described in more detail above, some embodiments described herein provide a device. The device includes a multilayer structure, the multilayer structure including a metal ring structure and a dielectric sidewall structure along the inner surface of the metal ring structure. The device includes an interconnect structure arranged along the approximate central axis of the metal ring structure. The device includes a protective layer located between the interconnect structure and the dielectric sidewall structure.

[0105] In some embodiments, the interconnection line structure passes through a semiconductor layer structure above the multi-layer structure.

[0106] In some embodiments, the device further includes: a metal layer located at the bottom of the metal ring structure and connected to the metal ring structure, wherein the metal layer and the protection layer are separated, and wherein the metal layer is connected to the interconnection line structure.

[0107] In some embodiments, the interconnect structure penetrates into a semiconductor layer below the multi-layer structure.

[0108] In some embodiments, the protection layer comprises: an oxide material.

[0109] As described in more detail above, some embodiments described herein provide a semiconductor package. The semiconductor package includes an integrated circuit device. The semiconductor package includes an array of interconnection line structures. The semiconductor package includes an interposer structure located between the integrated circuit device and the array of interconnection line structures. The interposer structure includes a multilayer structure, the multilayer structure including a metal ring structure and a metal layer connected to the metal ring structure above the metal ring structure. The interposer structure includes a semiconductor layer structure located below the multilayer structure and an interconnection line structure passing through the semiconductor layer structure, along the approximate central axis of the metal ring structure and reaching the metal layer. The interposer structure also includes a protective layer located between the interconnection line structure and the metal ring structure.

[0110] In some embodiments, the protective layer is directly connected to the inner surface of the metal ring structure.

[0111] In some embodiments, the semiconductor package further includes: a dielectric sidewall structure located between the inner surface of the metal ring structure and the protection layer.

[0112] In some embodiments, the interconnect line structure comprises a tapered shape.

[0113] As described in more detail above, some embodiments described herein provide a method. The method includes forming a multilayer structure including a metal ring structure. The method includes forming a cavity within one or more dielectric layers within the metal ring structure and along an approximate central axis of the metal ring structure. The method includes forming a protective layer within the cavity. The method includes forming an interconnect structure above the protective layer.

[0114] In some embodiments, forming the cavity includes exposing portions of the one or more dielectric layers within the metal ring structure to form a dielectric sidewall structure along an inner surface of the metal ring structure.

[0115] In some embodiments, forming the protection layer in the cavity includes: forming the protection layer on a surface of the dielectric sidewall structure.

[0116] In some embodiments, forming the multi-layer structure includes: forming a metal layer directly connected to the metal ring structure below the metal ring structure.

[0117] In some embodiments, forming the cavity includes forming a first cavity through a semiconductor layer structure above the multi-layer structure, and further includes: forming a second cavity through the protection layer to expose the metal layer.

[0118] In some embodiments, forming the interconnect structure above the protection layer includes forming a portion of the interconnect structure connecting the interconnect structure and the metal layer in the second cavity.

[0119] In some embodiments, forming the cavity includes: forming a portion of the cavity in a semiconductor layer structure below the multilayer structure.

[0120] In some embodiments, forming the protection layer within the cavity includes forming a portion of the protection layer on a surface of the semiconductor layer structure exposed by the portion of the cavity.

[0121] In some embodiments, forming the interconnect line structure over the protection layer includes forming the interconnect line structure to include a portion penetrating into the semiconductor layer structure.

[0122] In some embodiments, the method further includes bonding an interposer structure including the multi-layer structure to an array of interconnect line structures as part of forming a semiconductor package.

[0123] As used herein, the term "and / or", when used in conjunction with multiple items, is intended to cover each of the multiple items individually as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and non-B", and "B and non-A".

[0124] As used herein, “satisfying a threshold” may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0125] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to them herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Multi-layer structure, including: A metal ring structure; and a dielectric sidewall structure along an inner surface of the metal ring structure; an interconnect line structure disposed along an approximate central axis of the metal ring structure; and A protection layer is located between the interconnection line structure and the dielectric sidewall structure.

2. The semiconductor device according to claim 1, wherein: The interconnection line structure passes through the semiconductor layer structure above the multi-layer structure.

3. The semiconductor device according to claim 1, wherein: Also includes: a metal layer, located at the bottom of the metal ring structure and connected to the metal ring structure, wherein the metal layer and the protective layer are separated, and The metal layer is connected to the interconnection line structure.

4. The semiconductor device according to claim 1, wherein: The interconnect structure penetrates into the semiconductor layer below the multi-layer structure.

5. The semiconductor device according to claim 1, wherein: The interconnect line structure includes a tapered shape.

6. A semiconductor package, characterized in that: include: Integrated circuit devices; An array of interconnect wire structures; as well as An interposer structure is located between the integrated circuit device and the interconnection line structure array, and the interposer structure includes: Multi-layer structure, including: A metal ring structure; and A metal layer, located above the metal ring structure and connected to the metal ring structure; a semiconductor layer structure, located below the multilayer structure; an interconnection line structure, passing through the semiconductor layer structure and reaching the metal layer along an approximate central axis of the metal ring structure; and A protection layer is located between the interconnection line structure and the metal ring structure.

7. The semiconductor package according to claim 6, wherein: The protective layer is directly connected to the inner surface of the metal ring structure.

8. The semiconductor package according to claim 6, wherein: Also includes: The dielectric sidewall structure is located between the inner surface of the metal ring structure and the protection layer.

9. The semiconductor package according to claim 6, wherein: The interconnect line structure includes a tapered shape.

10. The semiconductor package according to claim 6, wherein: The interconnection line structure corresponds to a through silicon via structure.

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