Semiconductor device

Abstract

The utility model relates to a semiconductor device. The semiconductor device includes a first conductive feature and a second conductive feature over a substrate; a dielectric layer between the first conductive feature and the second conductive feature; an air gap in the dielectric layer between the first conductive feature and the second conductive feature; a protective layer over the first conductive feature, the second conductive feature, and the dielectric layer; and a first opening through the protective layer, a second opening through the protective layer, and a third opening through the protective layer, the first opening, the second opening, and the third opening over the air gap, where the first opening, the second opening, and the third opening form a triangle in a plan view.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor processing and, in particular embodiments, to the fabrication of semiconductor devices. Background Art

[0002] Semiconductor devices have circuit components formed on and / or in a substrate layer. The substrate layer may be, for example, a bulk semiconductor substrate or a silicon-on-insulator substrate (SOI). The fabrication of the circuit is referred to in the art as a front-end-of-line (FEOL) process. After the FEOL process is completed, the fabrication of the device is completed by forming a network of signal and power paths connected to the circuit components. This is referred to in the art as a back-end-of-line (BEOL) process.

[0003] Path routing in BEOL processes requires the formation of multiple levels (or layers) of metallization above the substrate layer including the circuits formed during the FEOL process. The metallization includes metal vias extending perpendicular to the top surface of the substrate layer and metal lines extending parallel to the top surface of the substrate layer. It is common to use copper (Cu) as the metal material for the vias and lines, although other metal materials are also known in the art. The metallization includes an insulating dielectric material at each level, wherein the vias and lines are surrounded by the insulating dielectric material. As semiconductor devices become smaller and more complex, the complexity of BEOL metallization increases accordingly, including the requirement for metallization structures with increasingly smaller sizes. Utility Model Content

[0004] An object of the present disclosure is to provide a semiconductor device to at least partially solve the above-mentioned problems existing in the prior art.

[0005] According to an embodiment, a semiconductor device includes: a first conductive feature and a second conductive feature over a substrate; a dielectric layer between the first conductive feature and the second conductive feature; an air gap in the dielectric layer between the first conductive feature and the second conductive feature; a protective layer over the first conductive feature, the second conductive feature, and the dielectric layer; and a first opening through the protective layer, a second opening through the protective layer, and a third opening through the protective layer, the first opening, the second opening, and the third opening being over the air gap, wherein the first opening, the second opening, and the third opening form a triangle in a plan view.

[0006] In some embodiments, the protective layer includes nitride.

[0007] In some embodiments, the protection layer also covers sidewalls of the first conductive feature and the second conductive feature.

[0008] In some embodiments, the highest point of the air gap is below the top surface of the protective layer.

[0009] In some embodiments, the air gap is above the transistor gate structure.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed.

[0011] With embodiments of the present disclosure, the protective layer may include, for example, a nitride, and protect the sidewalls and / or top surfaces of the conductive features from damage during subsequent processes, such as dry and wet etching processes that form air gaps. The air gaps may reduce the dielectric constant of the insulating dielectric material of the BEOL structure and the underlying FEOL structure, which may reduce electrical shorts between adjacent conductive features. The air gaps may be formed in a staggered pattern so that adjacent air gaps merge together and advantageously increase the total air gap volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 illustrates an example semiconductor structure according to some embodiments;

[0014] Figures 2 to 10 illustrates a cross-sectional view of an intermediate step in a semiconductor manufacturing process according to some embodiments;

[0015] Figures 11 to 18 illustrates a cross-sectional view of an intermediate step in another semiconductor manufacturing process according to some embodiments;

[0016] Figures 19 to 26 illustrates a cross-sectional view of an intermediate step in another semiconductor manufacturing process according to some embodiments;

[0017] Figures 27 to 35 illustrates a cross-sectional view of an intermediate step in another semiconductor manufacturing process according to some embodiments;

[0018] Figures 36A to 36C illustrates a top view and a cross-sectional view of a semiconductor device according to some embodiments;

[0019] Fig.37 A process flow diagram illustrating a method for manufacturing a semiconductor device according to some embodiments; and

[0020] Fig.38 A process flow diagram of another method for fabricating a semiconductor device according to some embodiments is illustrated.

[0021] Unless otherwise indicated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the scope of the features. DETAILED DESCRIPTION

[0022] The making and use of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to various specific contexts. The specific embodiments discussed only illustrate specific ways to make and use the various embodiments and should not be interpreted in a limited scope.

[0023] References to "an embodiment" or "an embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this description do not necessarily refer to the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments. References used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0024] According to one or more embodiments of the present disclosure, the present application relates to forming a protective layer on a conductive feature of a BEOL structure (e.g., a metal line) and forming an air gap in a dielectric layer of the BEOL structure and the underlying FEOL structure. The protective layer may include, for example, a nitride, and is advantageous by protecting the sidewalls and / or top surfaces of the conductive feature from damage in subsequent processes (e.g., dry and wet etching processes to form the air gap). In a cross-sectional view, the protective layer may be formed with an umbrella-shaped profile, which may reduce the height of the seam at the top of the subsequently formed air gap.

[0025] It may be advantageous to form air gaps and thereby reduce the dielectric constant of the insulating dielectric material of the BEOL structure and the underlying FEOL structure. This may reduce electrical shorts between adjacent conductive features. The air gaps may be formed in a staggered pattern so that adjacent air gaps merge together and advantageously increase the total air gap volume.

[0026] Embodiments of the present disclosure are described in the context of the accompanying drawings. Figure 1 Embodiments of example semiconductor structures are described. Figures 2 to 10 Embodiments of semiconductor manufacturing processes including forming a protective layer over conductive features are described. Figures 11 to 18 Another embodiment of a semiconductor manufacturing process including forming a protective layer over a conductive feature is described. Figures 19 to 26 An embodiment of another semiconductor manufacturing process is described that includes forming a protective layer over a conductive feature. Figures 27 to 35 Embodiments of a semiconductor manufacturing process are described that include forming a protective layer over a conductive feature having a mushroom-shaped profile. Figures 36A to 36C Embodiments of semiconductor devices including air gaps having staggered openings are described. Fig.37An embodiment of a method for manufacturing a semiconductor device is described. Fig.38 An embodiment of another method for manufacturing a semiconductor device is described.

[0027] Figure 1 A cross-sectional view of an example semiconductor structure 100 according to some embodiments is illustrated. The semiconductor structure 100 includes a substrate 102 over which active devices are formed. In some embodiments, the substrate 102 is made of silicon, or is a silicon-on-insulator (SOI) substrate including a buried oxide layer. A transistor gate structure 105 (e.g., a planar FET, a FinFET, etc.) is formed on the substrate 102. Although Figure 1 Two transistor gate structures 105 are illustrated in FIG. 1 , but any suitable number of transistor gate structures 105 may be formed.

[0028] like Figure 1 As shown, each transistor gate structure 105 includes a gate electrode 106 and a gate dielectric 108 between the gate electrode 106 and the substrate 102. In some embodiments, the gate electrode 106 includes a conductive material such as tungsten, titanium, copper, gold, tin, silver, etc. or a combination thereof. In other embodiments, the gate electrode 106 is a dummy gate including, for example, polysilicon. The gate dielectric 108 extends between the gate electrode 106 and the substrate 102. The gate dielectric 108 can cover the sidewalls of the gate electrode 106. In some embodiments, the gate dielectric 108 includes silicon oxide, silicon dioxide, etc. or a combination thereof. The gate dielectric 108 can be a thermal oxide. In some embodiments, a cap layer 112 covers the top surface of the gate electrode 106 and the gate dielectric 108. The cap layer 112 includes a suitable conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, etc. or a combination thereof. However, any suitable material can be used for the cap layer 112.

[0029] Each transistor gate structure 105 may be between corresponding gate spacers 110 (also referred to as sidewall spacers). In some embodiments, in a gate-last process, gate spacers 110 are formed on opposite sides of a dummy gate, which is subsequently removed and replaced with a corresponding transistor gate structure 105 (also referred to as a replacement gate). In other embodiments, gate spacers 110 are formed on either side of the transistor gate structure 105 in a gate-first process. The gate spacers 110 include one or more dielectric layers. In some embodiments, the gate spacers 110 include silicon oxide, silicon dioxide, silicon nitride (e.g., Si3N4), etc. or a combination thereof. For example, the gate spacers 110 may include a first layer of silicon nitride, a second layer of silicon dioxide above the first layer, and a third layer of silicon nitride above the second layer. As Figure 1 As illustrated, the gate spacer 110 may include a first layer and a second layer having an L-shaped profile in a cross-sectional view.

[0030] Source / drain regions 104 (also referred to as source and drain regions) are formed in the substrate 102 adjacent to and / or between transistor gate structures 105. The source / drain regions 104 may be formed, for example, by etching recesses adjacent to and / or between the transistor gate structures 105 and epitaxially growing silicon and / or silicon germanium in the recesses. In some embodiments, facets of the source / drain regions 104 extend above the top surface of the substrate 102. The source / drain regions 104 located between adjacent transistor gate structures 105 include a source region for one transistor gate structure 105 and a drain region for another transistor gate structure 105.

[0031] An etch stop layer 114 is formed over the transistor gate structure 105, the source / drain region 104, and the gate spacer 110. The etch stop layer 114 can be used to control a subsequent etching process for forming a contact with, for example, the source / drain region 104 or the transistor gate structure 105. Therefore, the etch stop layer 114 is also referred to as a contact etch stop layer. In some embodiments, the etch stop layer 114 includes a nitride, such as silicon nitride. However, any suitable material (e.g., hafnium oxide (HfO2)) may be used.

[0032] A pre-metal dielectric (PMD) layer 116 is formed over the etch stop layer 114. In some embodiments, the PMD layer 116 includes silicon oxide, silicon dioxide, etc., or a combination thereof, and is formed using a suitable process (e.g., phosphosilicate glass high density plasma (PSG HDP) deposition or conventional oxides formed by tetraethyl orthosilicate (TEOS) deposition, such as plasma enhanced (PE) CVD). In other embodiments, the PMD layer 116 includes borophosphosilicate glass (BPSG), undoped silicate glass (USG), etc., or a combination thereof. However, the PMD layer 116 may include any suitable material.

[0033] Contacts 120 are formed through the PMD layer 116 and the etch stop layer 114 to physically and electrically contact the source / drain regions 104. Openings for the contacts 120 may be formed using suitable patterning and etching processes.

[0034] Next, a barrier layer 124 is conformally deposited in the opening. The barrier layer 124 includes a suitable conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, etc. or a combination thereof. The barrier layer 124 is formed using a suitable method such as CVD, PVD, ALD, electroplating, etc. A conductive fill material 122 is formed over the barrier layer 124 to fill the opening. In some embodiments, the conductive fill material 122 includes tungsten, cobalt, copper, tin, gold, silver, etc. or a combination thereof. The conductive fill material is formed using a suitable method such as CVD, PVD, ALD, electroplating, etc. The top portion of the barrier layer 124 and the conductive fill material 122 can be removed using a suitable planarization process such as chemical mechanical polishing (CMP). The contact 120 includes the conductive fill material 122 and the remaining portion of the barrier layer 124.

[0035] Figures 2 to 26 Various embodiments of processes for forming a protective layer over a conductive feature and forming an air gap in an adjacent dielectric layer are illustrated. Conductive features such as metal lines (also referred to as metallization lines) may be sensitive elements that may be damaged during subsequent manufacturing steps. For example, the conductive feature may not be protected during different etching processes used to form the air gap in the adjacent dielectric material. The sidewalls and / or top surfaces of the conductive feature may be protected by a protective layer (also referred to as a protective cap layer or protective cap) comprising, for example, a nitride material. The protective layer may be formed over a conductive feature formed by a subtractive process or a damascene process.

[0036] Figures 2 to 10 A cross-sectional view of an intermediate step in a subtractive process for forming conductive features (eg, metal lines) protected by a protective cap layer and forming air gaps between and / or adjacent to the conductive features is illustrated in accordance with some embodiments. Figures 2 to 10 The structure is to use Figure 1 The example semiconductor structure 100 is formed, but Figures 2 to 10 The structures may be formed using any suitable semiconductor structures or substrates, and any such structures are within the scope of the disclosed embodiments.

[0037] exist Figure 2 In the embodiment of the present invention, a conductive layer 132 is formed over the PMD layer 116 and the contact 120, and a protective layer 134 is formed over the conductive layer 132. The protective layer 134 and the conductive layer 132 will then be patterned to form conductive features protected by the protective cap layer over their respective top surfaces and sidewalls (see below). Figures 3 to 4 ).

[0038] Conductive layer 132 includes a conductive material, such as a metal. In some embodiments, conductive layer 132 includes aluminum or the like. Conductive layer 132 is formed using a suitable process such as CVD, PVD, electroplating, etc. However, any suitable process can be used to form conductive layer 132.

[0039] Next, a protective layer 134 is formed over the conductive layer 132. The protective layer 134 may include any suitable material, such as a material that provides protection for the underlying layer during etching (e.g., etching using HF). In some embodiments, the protective layer 134 includes a nitride, such as silicon nitride (e.g., Si3N4). The material of the protective layer 134 may be doped with, for example, boron, indium, phosphorus, arsenic, antimony, aluminum, gallium, bismuth, lithium, or the like, or a combination thereof. In some embodiments, the material of the protective layer 134 is tensile or may be aluminum oxide (Al2O3). However, the protective layer 134 is formed using a suitable method, such as CVD, low pressure CVD (LPCVD), or the like, or a combination thereof. However, any suitable method may be used to form the protective layer 134.

[0040] Still refer to Figure 2 , a photomask 136 is formed over the protective layer 134 and patterned, such as using a suitable photolithography technique. The photomask 136 covers the protective layer 134 and portions of the conductive layer 132 that will be subsequently etched to form conductive features (e.g., metal lines) protected by the protective layer. As an example of forming the photomask 136, a photosensitive material is formed over the protective layer 134. Portions of the photosensitive material are then exposed to light (e.g., UV light). The photosensitive material is developed and etched to form the photomask 136.

[0041] Next, in Figure 3 In the embodiment of the present invention, the photomask 136 is used as an etching mask to pattern the protective layer 134 and the conductive layer 132 using an etching process. The patterning can be performed using a suitable anisotropic etching process (such as an RIE process). The remaining portion of the conductive layer 132 forms a conductive feature 142 (e.g., a metal line). The remaining portion of the protective layer 134 forms a patterned protective layer 144 covering the top surface of the conductive feature 142. In some embodiments, the etched photomask 146 remains above the patterned protective layer 144. In other embodiments, the photomask 136 is removed by the etching process.

[0042] exist Figure 4 In the embodiment of the present invention, the etched photomask 146 (if present) is removed, and additional protective material is conformally deposited to form a protective layer 148 over the conductive features 142 and the PMD layer 116. The etched photomask 146 can be removed by a suitable process (such as an ashing process). Figure 2The additional protective material is deposited using materials and methods similar to those described for the protective layer 134, and the details are not repeated herein. The protective layer 148 is formed by combining the additional protective material with the patterned protective layer 144. The protective layer 148 covers the top surface and sidewalls of the conductive feature 142 and the exposed surface of the PMD layer 116. In some embodiments, the respective thicknesses of the portions of the protective layer 148 on the top surface of the conductive feature 142 are greater than the respective thicknesses of the portions of the protective layer 148 on the sidewalls of the conductive feature 142 and the thicknesses of the portions of the protective layer 48 on the PMD layer 116.

[0043] exist Figure 5 In the embodiment of the present invention, the portion of the protective layer 148 above the PMD layer 116 is removed to form the protective cap layer 150. The portion of the protective layer 148 above the PMD layer 116 can be removed by a suitable process, such as an anisotropic etching process (e.g., RIE process). Removing the portion of the protective layer 148 above the PMD layer 116 can allow a larger air gap to be subsequently formed (see below). Figures 9 to 10 ). The remaining portion of the protective layer 148 forms a protective cap layer 150 that covers the top surface and sidewalls of the conductive feature 142. The protective cap layer 150 can protect the underlying conductive feature 142 during subsequent manufacturing processes, such as etching of the air gap (see below). Figures 8 to 10 ).

[0044] exist Figure 6 In the embodiment of the present invention, an intermetallic dielectric (IMD) layer 152 is formed over the exposed surface of the protective cap layer 150 and the PMD layer 116 to fill the gap between the conductive features 142. In some embodiments, the IMD layer 152 includes silicon oxide, silicon dioxide, etc., or a combination thereof. However, any suitable dielectric material can be used to form the IMD layer 152. In some embodiments, the IMD layer 152 is formed by depositing tetraethyl orthosilicate (TEOS) with a suitable deposition process (e.g., CVD, PECVD, etc., or a combination thereof) and then oxidizing the deposited TEOS with a suitable oxidation process (e.g., oxygen, ozone, or steam treatment). However, any suitable method can be used to form the IMD layer 152. The excess portion of the IMD layer 152 can be removed by planarization such as CMP, which can stop on the protective cap layer 150. Planarization can also remove the top portion of the protective cap layer 150.

[0045] exist Figure 7 In the embodiment, a protective layer 154 is formed over the IMD layer 152 and the protective cap layer 150, and a photomask 156 is formed over the protective layer 154. The protective layer 154 may be formed using the same method as above. Figure 2The protective layer 134 is deposited using similar materials and methods as described above, and the details are not repeated herein. A photomask 156 is then used to form air gaps in the IMD layer 152 and the PMD layer 116 (see below). Figures 8 to 10 ). You can use the same Figure 2 Similar materials and methods are used to form and pattern photomask 156 as described for photomask 136 , and the details are not repeated herein. Gaps in photomask 156 may be formed at desired locations for air gaps, such as over transistor gate structures 105 .

[0046] exist Figure 8 In the embodiment of the present invention, using photomask 156 as an etching mask, holes 158 are etched through IMD layer 152 and into PMD layer 116. Holes 158 can be formed using a suitable anisotropic etching process, such as dry etching (e.g., a plasma process or RIE process performed using CF4 gas). Holes 158 will then be widened to form air gaps (see below). Figures 8 to 9 ). The protective cap layer 150 can protect the conductive features 142 during the anisotropic etching process.

[0047] exist Fig. 9 , the photomask 156 is removed, and the hole 158 is widened into the space 160. The photomask 156 can be removed by a suitable process such as an ashing process. The hole 158 is then widened into the space 160 using an isotropic etching process. The isotropic etching process may be selective to the materials of the IMD layer 152 and the PMD layer 116 above the material of the protective layer 154. In some embodiments, the isotropic etching process is a wet etch performed with HF, HF vapor, HCl, KOH, TMAH, NaOH, BHF, HNO3, BOE (buffered oxide etch), etc. The wet etching chemical(s) may be selected depending on the surrounding materials, and a mixture of more than one chemical may be used. The protective cap layer 150 may protect the conductive feature 142 during the isotropic etching process. The portion of the protective layer 148 above the PMD layer 116 is removed (see above, Figure 5 ) may allow space 160 (and the subsequent air gap; see below, Fig.10 ) is wider, which can advantageously increase the dielectric constant of the PMD layer 16 and the IMD layer 152.

[0048] exist Fig.10 In the embodiment, the IMD layer 164 is formed over the exposed surface of the protective layer 154 and the space 160 to form the air gap 162. The IMD layer 164 may be formed using the same method as above. Figure 6The IMD layer 152 described above is formed of similar materials and methods, and the details are not repeated herein. The IMD layer 164 seals the air gap 162, and the material of the IMD layer 164 can cover the inner surface of the air gap 162. The air gap 162 includes ambient (such as residual) gas present in the process chamber (for example, from the PECVD process used to form the IMD layer 164). In some embodiments, the air gap 162 is above the transistor gate structure 105 and has a width greater than the combined width of the transistor gate structure 105 and the adjacent gate spacer 110. The seam at the top of the air gap 162 can extend into the IMD layer 164 through the gap in the protective layer 154.

[0049] Figures 11 to 18 A cross-sectional view of an intermediate step in another subtractive process for forming conductive features (eg, metal lines) protected by a protective cap layer and forming air gaps between and / or adjacent to the conductive features is illustrated in accordance with some embodiments. Figures 11 to 18 The structure is to use Figure 1 The example semiconductor structure 100 is formed, but Figures 11 to 18 The structures may be formed using any suitable semiconductor structures or substrates, and any such structures are within the scope of the disclosed embodiments.

[0050] exist Fig.11 relay Figure 1 Thereafter, a conductive layer 132 is formed over the PMD layer 116 and the contact 120, and a photomask 136 is formed and patterned over the conductive layer 132. The conductive layer 132 and the photomask 136 may be patterned using the same pattern as above. Figure 2 Similar materials and methods are described, and the details are not repeated herein. In some embodiments, conductive layer 132 includes aluminum.

[0051] exist Fig.12 In the embodiment, the photomask 136 is used as an etching mask to pattern the protective layer 132 using an etching process. The etching process for forming the conductive features 142 can be used in the same manner as above with respect to Figure 3 The method similar to that described in the present invention is described in detail, and the details are not repeated herein. The etched photomask 146 can remain above the conductive features 142. In some embodiments, the openings 170 between the conductive features 142 extend into the PMD layer 116 below the bottom surface of the conductive features 142. For example, depending on the technology node and the thickness of the PMD layer 116, the bottom surface of the openings 170 can be a first distance D1 in the range of 0nm to 500nm above the transistor gate structure 105. For example, the openings 170 can extend through up to 95% of the thickness of the PMD layer 116.

[0052] Next, in Fig.13In the embodiment of the present invention, the etched photomask 146 (if present) is removed and a protective cap layer 174 is formed over the conductive features 142 and the PMD layer 116. The protective cap layer 174 covers the top surface and sidewalls of the conductive features 142 and the exposed surface of the PMD layer 116. The protective cap layer 174 can be formed using the same method as above. Figure 2 The protective cap layer 174 may be formed of similar materials and methods as described above, and the details are not repeated herein. The protective cap layer 174 may protect the underlying conductive features 142 during subsequent manufacturing processes, such as etching of air gaps (see below, Figures 16 to 18 ). In some embodiments, the protective cap layer 174 has a square wave profile in a cross-sectional view.

[0053] exist Fig.14 In the embodiment, the IMD layer 152 is formed over the exposed surface of the protective cap layer 174 and the PMD layer 116 to fill the openings 170 between the conductive features 142. The IMD layer 152 may be formed using the same method as above. Figure 6 Similar materials and methods are described, and the details are not repeated herein. Excess portions of the IMD layer 152 can be removed using planarization such as CMP, which can stop on the protective cap layer 174, such as through the mechanical resistance of the protective cap layer 174 to CMP. Planarization can also remove the top portion of the protective cap layer 174.

[0054] Next, in Fig.15 In the embodiment, a protective layer 154 is formed over the IMD layer 152 and the protective cap layer 174, and a photomask 176 is formed over the protective layer 154. The protective layer 154 may be formed using the same method as above. Figure 2 The protective layer 134 is deposited using similar materials and methods as described above, and the details are not repeated herein. A photomask 176 is then used to form air gaps in the IMD layer 152 and the PMD layer 116 (see below, Figures 16 to 18 ). You can use the same Figure 2 Similar materials and methods are used to form and pattern photomask 176 as described for photomask 136 , and the details are not repeated herein. Gaps in photomask 176 may be formed at desired locations for air gaps, such as over transistor gate structures 105 .

[0055] exist Fig.16, using photomask 176 as an etching mask, hole 178 is etched through protective layer 154, IMD layer 152, protective cap layer 174 and into PMD layer 116. Hole 178 can be formed using an anisotropic etching process, such as dry etching (e.g., a plasma process or RIE process performed with CF4 gas). In some embodiments, the anisotropic etching process includes more than one etching step. For example, a first dry etch selective to the protective material can be used to etch through protective layer 154, a second dry etch selective to the oxide material can be used to etch through IMD layer 152, and a third dry etch selective to the protective material can be used to etch through protective cap layer 174. However, any suitable combination of etching processes may be used. Due to the presence of protective cap layer 174, hole 178 may have a smaller width than hole 158. Hole 178 will subsequently widen to form an air gap (see below, Figures 17 to 18 ). The protective cap layer 174 can protect the conductive features 142 during the anisotropic etching process.

[0056] Next, in Fig.17 In the embodiment of the present invention, the photomask 176 is removed and the hole 178 is widened into the space 180. The photomask 176 can be removed by a suitable process such as an ashing process. The hole 178 is then widened into the space 180 using an isotropic etching process. The isotropic etching process can be used in the same manner as above with respect to Fig. 9 The isotropic etching process described above is performed with similar methods and reagents, and the details are not repeated herein. Protective cap layer 174 can protect conductive features 142 during the isotropic etching process.

[0057] exist Fig.18 In the embodiment, the IMD layer 164 is formed over the exposed surface of the protective layer 154 and the space 180 to form an air gap 182. The IMD layer 164 may be formed using the same method as above. Figure 6 The IMD layer 152 described above is formed of similar materials and methods, and the details are not repeated herein. The IMD layer 164 seals the air gap 182, and the material of the IMD layer 164 can cover the inner surface of the air gap 182. In some embodiments, the air gap 182 is above the transistor gate structure 105 and has a width that is smaller than the combined width of the transistor gate structure 105 and the adjacent gate spacer 110. The seam at the top of the air gap 182 can extend into the IMD layer 164 through the gap in the protective layer 154.

[0058] Figures 19 to 26 A cross-sectional view of an intermediate step in a damascene process for forming conductive features (eg, metal lines) protected by a protective cap layer and forming air gaps between and / or adjacent to the conductive features is illustrated in accordance with some embodiments. Figures 19 to 26 The structure is to use Figure 1 The example semiconductor structure 100 is formed, but Figures 19 to 26 The structures may be formed using any suitable semiconductor structures or substrates, and any such structures are within the scope of the disclosed embodiments.

[0059] exist Fig.19 relay Figure 1 Afterwards, a protective layer 184 is formed over the PMD layer 116 and the contact 120. The protective layer 184 may be formed with respect to the above Figure 2 The protective layer 134 is formed by similar materials and methods as described.

[0060] Next, in Fig. 20 In the embodiment, an IMD layer 186 is formed on the protective layer 184, and a photomask 188 is formed and patterned on the protective layer 134. The IMD layer 186 may be used in the same manner as above. Figure 6 The IMD layer 152 is formed using similar materials and methods as described above. A photomask 188 is used to subsequently pattern the IMD layer 186 to form conductive features (eg, metal lines).

[0061] exist Fig.21 184, an opening 190 is etched through the IMD layer 186 and the protective layer 184 to expose the top surface of the contact 120. The opening 190 can be formed using one or more anisotropic etching processes (e.g., dry etching). For example, a first dry etch that is selective to the oxide material can be used to etch through the IMD layer 186, and a second dry etch that is selective to the protective material can be used to etch through the protective layer 184. However, any suitable method can be used to form the opening 190. After the opening 190 is formed, the photomask 188 can be removed using a suitable process (e.g., an ashing process).

[0062] Next, in Fig. 22 In the embodiment, a protective layer 192 is formed over the exposed surface of the IMD layer 186 and the contact 120. The protective layer 192 may be formed using the same method as above. Figure 2 Similar materials and methods are described for forming the protective layer 134 , and the details are not repeated herein.

[0063] exist Fig.2318, a portion of the protective layer 192 above the IMD layer 186 and a top surface of the contact 120 are removed to form a protective layer 194. The portion of the protective layer 192 above the IMD layer 186 and the top surface of the contact 120 may be removed by a suitable process, such as an anisotropic etching process (e.g., a plasma process performed with CF4 gas or an RIE process). The remaining portion of the protective layer 192 forms a protective layer 194 covering the sidewalls of the opening 190. The protective layer 194 may be useful for protecting subsequently formed conductive features during subsequent manufacturing processes (see below, Figures 24 to 25 ), such as air gap etching (see below, Fig.26 ).

[0064] exist Fig.24 , a barrier layer 196 is formed over the opening 190 and the exposed surface of the IMD layer 186, and a conductive filling material 198 is formed over the barrier layer 196 to fill the opening 190. The barrier layer 196 includes a suitable conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, etc. or a combination thereof. In some embodiments, the barrier layer 196 includes tantalum or tantalum nitride. The barrier layer 196 is formed using a suitable method such as CVD, PVD, ALD, electroplating, etc. A conductive filling material 198 is then formed over the barrier layer 196 to fill the opening. The conductive filling material 198 includes a suitable conductive material, such as copper, tungsten, cobalt, copper, tin, gold, silver, aluminum, etc. or a combination thereof. In some embodiments, the conductive filling material 198 includes copper. The conductive filling material is formed using a suitable method such as electroplating, CVD, PVD, ALD, etc.

[0065] Next, in Fig.25 In the embodiment of the present invention, the top portion of the barrier layer 196 and the conductive fill material 198 is removed by a suitable planarization process (such as chemical mechanical polishing (CMP)). The remaining portion of the conductive fill material 198 and the barrier layer 196 forms a conductive feature 202 (e.g., a metal line). In some embodiments, the sidewalls of the conductive feature 202 are covered by the protective layer 194.

[0066] exist Fig.26 In the embodiment, protective layer 154 is formed over conductive features 202 and IMD layer 186. Protective layer 154 may be formed over conductive features 202 and IMD layer 186. Figure 2 The protective layer 134 described above is formed of similar materials and methods, and the details are not repeated herein. Next, air gaps 182 are formed in the PMD layer 116 and the IMD layer 186, and an IMD layer 164 is formed over the protective layer 154. The air gaps 182 and the IMD layer 164 may be formed using the same materials and methods as described above with respect to FIG. Figures 15 to 18 Similar materials and methods are formed as described, and the details are not repeated here.

[0067] Figures 27 to 35A cross-sectional view of an intermediate step in a process for forming an air gap between and / or adjacent to conductive features beneath a protective layer having a mushroom-shaped profile in accordance with some embodiments is illustrated. The mushroom-shaped profile of the protective layer can reduce the height of the seam at the top of the air gap, thereby reducing the likelihood that the seam may reopen during subsequent processing. This facilitates improvements to the device structure (e.g., forming additional conductive features or intermetallic dielectric layers) in subsequent manufacturing steps. Although Figures 27 to 35 The structure is to use Figure 5 The example semiconductor structure 100 is formed, but Figures 27 to 35 The structures may be formed using any suitable semiconductor structures or substrates, and any such structures are within the scope of the disclosed embodiments.

[0068] Fig. 27 From Figure 5 , and illustrates an IMD layer 212 formed over the conductive features 142 (eg, metal lines), the protective cap layer 150, and the PMD layer 116. Fig. 27 In the example of FIG. 1 , the conductive feature 142 is illustrated as having a top surface and sidewalls covered by the protective cap layer 150, but in some embodiments, only the sidewalls of the conductive feature 142 are covered by the protective cap layer 150, and the top surface of the conductive feature 142 is exposed. In other embodiments, the protective cap layer 150 is not present.

[0069] IMD layer 212 can be used with respect to the above Figure 6 The IMD layer 152 is formed by similar methods and materials as described above, and the details are not repeated herein. Indentations 214 exist in the top surface of the IMD layer 212 between adjacent conductive features 142. The indentations 214 may be caused by conformal deposition of the IMD layer 212 over the conductive features 142.

[0070] Next, in Fig.28 In the embodiment of the present invention, the IMD layer 212 is recessed to form the IMD layer 216 by a suitable anisotropic etching process (also referred to as direct etching), such as dry etching (e.g., a plasma process or an RIE process performed with CF4 gas). In some embodiments, the anisotropic etching process exposes the top surface of the protective cap layer 150. The protective cap layer 150 can be thinned by the anisotropic etching process. In other embodiments where the protective cap layer 150 is not present on the top surface of the conductive feature 142, the top surface of the conductive feature 142 is exposed by the anisotropic etching process. After the anisotropic etching process, the indentation 214 extends below the top surface of the conductive feature 142.

[0071] exist Fig.29 In the embodiment of the present invention, a protective layer 220 is formed over the IMD layer 216, the protective cap layer 150 (if present), and the conductive features 142. The protective layer 220 may be formed using the same method as above. Figure 2 The protective layer 134 is formed by similar methods and materials as described above, and the details are not repeated herein. In some embodiments, the protective layer 220 has a curved corner profile in a cross-sectional view where it covers the indentation 214 .

[0072] Next, in Fig.30 In the embodiment of the present invention, a photomask 222 is formed over the protective layer 220. Gaps in the patterned photomask 222 expose portions of the protective layer 220 over the indentations 214. The photomask 222 is then used as an etching mask to etch holes through the indentations 214 (see below, Figures 31 to 32 ). You can use the same Figure 2 Photomask 222 is formed using similar methods and materials as described for photomask 136 , and the details are not repeated herein.

[0073] exist Fig.31 In the embodiment of the present invention, the portion of the protective layer 220 above the indentation 214, which is exposed by the photomask 222, is removed. The portion of the protective layer 220 can be removed by a suitable anisotropic etching process that is selective to the material of the protective layer 220 (e.g., a nitride, such as Si3N4). In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma process or an RIE process performed with CF4 gas). However, any suitable etching process can be used. The remaining portion of the protective layer 220 has a corresponding umbrella-shaped profile in the cross-sectional view.

[0074] exist Fig.32 2, a photomask 222 is used to etch a hole 224 through the IMD layer 216 and into the PMD layer 116 in the location of the indentation 214. The IMD layer 216 and the PMD layer 116 can be etched by a suitable anisotropic etching process, which is selective to the material (e.g., silicon dioxide) of the IMD layer 216 and the PMD layer 116. In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma process or an RIE process performed with a fluorocarbon reactant such as CHF3, CF4). However, any suitable etching process can be used.

[0075] Next, in Fig.33 In the embodiment of the present invention, the photomask 222 is removed to expose the protective layer 220. The photomask 222 may be removed by a suitable process such as an ashing process.

[0076] exist Fig.34 In the embodiment, the hole 224 is widened to the space 226 by an isotropic etching process. The isotropic etching process can be used in the same manner as above. Fig. 9The isotropic etching process described above is performed with similar methods and reactants, and the details are not repeated herein. In some embodiments, the curved tip of the protection layer 220 extends over the space 226 .

[0077] exist Fig.35 In the embodiment, the IMD layer 164 is formed over the exposed surface of the protective layer 220 and the space 226 to form the air gap 230. The IMD layer 164 may be formed using the same method as above. Figure 6 152 described above, and the details are not repeated herein. IMD layer 164 seals air gap 230, and the material of IMD layer 164 can cover the inner surface of air gap 230. In some embodiments, air gap 230 is above transistor gate structure 105. The seam at the top of air gap 162 can be truncated below the upper surface of protective layer 220, so that the highest point in air gap 162 is below the top surface of the protective layer. This may be due to the umbrella profile of protective layer 220 allowing more material of IMD layer 164 to enter and fill the top of space 226 (see above, Fig.34 ).

[0078] Figures 36A to 36C An embodiment of an extended air gap formed by an isotropic etch performed through a plurality of staggered holes in a protective layer is illustrated. Fig.36A The semiconductor structure 100 (eg, similar to FIG. 1 ) is illustrated at the level of the conductive features 142 (eg, metal lines) and the IMD layer 152 between the conductive features 142. Fig.10 , 17 26). In some embodiments, the width W1 of the IMD layer 142 measured between the conductive features 142 is in the range of 0.200 μm to 5 μm. The IMD layer 142 has a keep-out zone 304 adjacent to each conductive feature 142, and in order to avoid damage to the conductive features 142, these keep-out zones 304 are expected not to be etched to form air gaps. The width W2 of the keep-out zone 304 is in the range of 0.01 μm to 1 μm. In order to achieve a wider air gap, the keep-out zone 304 may desirably have a width W2 that is closer to the minimum value of the range (0.01 μm) rather than the maximum value of the range.

[0079] Through the protection layer 154 above the IMD layer 152 (see below, Figures 36B to 36C ) are arranged in a staggered pattern. Figure 8The opening 240 is formed in a similar manner to the hole 158 described above, and the details are not repeated herein. Although the opening 240 is illustrated as having a square shape, the opening 240 can have any suitable shape, such as a rectangle, a circle, an oval, a triangle, a hexagon, an octagon, etc. For example, the opening 240 can have alternating squares and rectangles or alternating circles and ovals. In some embodiments, the width W3 of the opening 240 is in the range of 50nm to 300nm.

[0080] The openings 240 are arranged in a staggered pattern, which facilitates the subsequent formation of merged air gaps. Fig.36A As shown, the openings 240 are arranged in two columns between the conductive features 142. However, the openings 240 can be arranged in any suitable number of columns, such as one to five columns. The openings 240 of each column are offset from the corresponding openings of the other column so that each opening 240 forms a triangle with the two nearest other openings 240 in a plan view. In some embodiments, the openings 240 are arranged to have a pitch P1 in the range of 50nm to 200nm or 300nm, with the maximum value depending on the HF etching rate. However, the openings 240 can be arranged in any suitable pattern. For example, the openings 240 can be separated by different pitches.

[0081] After forming the opening 240, an air gap 250 is formed by an isotropic etching process and then sealed by forming an IMD layer 164 (see below, Figures 36B to 36C ). The air gap 250 is illustrated by overlapping circles around each opening 240. The isotropic etching process can be used with respect to the above Fig. 9 The isotropic etching process expands each opening 240 to a width W4 in the range of 0 μm to 0.5 μm, so that the widened openings merge together, as illustrated by overlapping circles. The merged widened openings can be sealed by forming an IMD layer 164 thereover to form an air gap 250, which can be formed using the same method as above. Fig.10 The size of the air gap 250 can advantageously be increased with the staggered pattern of the openings 240 followed by an isotropic etching process, which can allow for a reduction in the dielectric constant of the IMD layer 152 .

[0082] In some embodiments, the width W5 of the air gap 250 is in the range of 0.1 μm to 4.98 μm, which is equal to the sum of twice the width W3 and the width W4 and the pitch P1. The anisotropic etching process to form the opening 240 and the isotropic etching process to widen the opening 240 (thereby forming the merged air gap 250) can be performed so that the width W5 of the air gap 250 is less than or equal to the combined width W2 of the IMD layer 152 minus the width W1 of the keep-out region 304.

[0083] Fig.36B The diagram is similar to Fig.18 1 and 1 , wherein the staggered openings 240 are formed through the protective layer 154. Thus, the air gaps 250 are wider than the air gaps 182 (see above, Fig.18 Additionally, the seam at the top of air gap 250 may be lower than the seam at the top of air gap 182, such that the highest point of air gap 250 is located below the top surface of protective layer 154. Due to the staggered pattern of openings 240 and the resulting merged air gaps 250, openings 240 and air gaps 250 may be asymmetrically closer to first conductive features 142 than to second conductive features 142 (e.g., as shown in FIG. Fig.36B As illustrated, closer to the left conductive feature 142 or the right conductive feature 142 than to the center conductive feature 142).

[0084] Fig.36C The diagram is similar to Fig.26 1 and 1 , wherein the staggered openings 240 are formed through the protective layer 154. Thus, the air gaps 250 are wider than the air gaps 182 (see above, Fig.26 Additionally, the seam at the top of air gap 250 can be lower than the seam at the top of air gap 182, so that the highest point of air gap 250 is below the top surface of protective layer 154. Due to the staggered pattern of openings 240 and the resulting merged air gaps 250, openings 240 and air gaps 250 may be asymmetrically closer to first conductive feature 202 than to second conductive feature 202 (e.g., as shown in FIG. Fig.36C As illustrated, closer to the left conductive feature 202 or the right conductive feature 202 than to the center conductive feature 202).

[0085] Fig.37 A process flow diagram of a method 1000 for manufacturing a semiconductor device according to some embodiments is illustrated. In step 1002, a first conductive feature and a second conductive feature (eg, conductive feature 142) are formed over a substrate 102, as described above with respect to Figures 2 to 3 Described.

[0086] In step 1004, a first protective layer (eg, protective layer 148) is deposited over the first conductive feature and the second conductive feature, as described above with respect to Figure 4 The first protection layer covers the corresponding sidewalls and top surfaces of the first conductive feature and the second conductive feature.

[0087] In step 1006, a portion of the first protective layer between the first conductive feature and the second conductive feature is removed, as described above with respect to Figure 5In step 1008, after removing a portion of the first protective layer, an intermetallic dielectric layer 152 is formed between the first conductive feature and the second conductive feature, as described above with respect to Figure 6 Described.

[0088] Fig.38 1 is a process flow diagram of a method 2000 for manufacturing a semiconductor device according to some embodiments. In step 2002, a first metal line (eg, conductive feature 142) and a second metal line (eg, conductive feature 142) are formed over substrate 102, as described above with respect to Figures 2 to 3 Described.

[0089] In step 2004, a first dielectric layer (eg, IMD layer 212) is conformally deposited over the first metal line and the second metal line, as described above with respect to FIG. Fig. 27 The first dielectric layer includes a notch 214 between the first metal line and the second metal line.

[0090] In step 2006, the first dielectric layer is recessed using an anisotropic etching process, as described above with respect to Fig.28 After the anisotropic etching process, the indentations 214 extend below the top surfaces of the first metal line and the second metal line.

[0091] In step 2008, a first protective layer (eg, protective layer 220) is formed over the first dielectric layer, as described above with respect to Fig.29 In step 2010, a portion of the first protective layer above the indentation 214 is removed, as described above with respect to Figures 30 to 31 The remaining part of the first protective layer has a corresponding mushroom-shaped profile in the cross-sectional view.

[0092] In step 2012, a hole 224 is etched through the first dielectric layer at the location of the indentation 214, as described above with respect to Fig.32 In step 2014, hole 224 is widened into space 226 using an isotropic etching process, as described above with respect to Fig.34 Described.

[0093] Example embodiments of the present disclosure are summarized here. Other embodiments are also possible through the entire content of this specification and the claims submitted herein.

[0094] Example 1. A method for manufacturing a semiconductor device, the method comprising: forming a first conductive feature and a second conductive feature over a substrate; depositing a first protective layer over the first conductive feature and the second conductive feature, the first protective layer covering corresponding side walls and top surfaces of the first conductive feature and the second conductive feature; removing a portion of the first protective layer between the first conductive feature and the second conductive feature; and after removing the portion of the first protective layer, forming an intermetallic dielectric layer between the first conductive feature and the second conductive feature.

[0095] Example 2. The method of example further includes: forming a second protection layer over the first protection layer and the intermetallic dielectric layer.

[0096] Example 3. The method of Example 2, wherein the first protective layer and the second protective layer include nitride.

[0097] Example 4. The method of one of Examples 2 or 3, further comprising: etching an opening through the second protective layer.

[0098] Example 5. The method of Example 4, wherein etching the opening comprises performing a dry etch using CF4.

[0099] Example 6. The method of one of Examples 4 or 5, further comprising: widening the opening by etching the intermetal dielectric layer.

[0100] Example 7. The method of Example 6, wherein etching the intermetal dielectric layer includes performing a wet etching process using HF.

[0101] Example 8. A method for manufacturing a semiconductor device, the method comprising: forming a first metal line and a second metal line above a substrate; conformally depositing a first dielectric layer above the first metal line and the second metal line, wherein the first dielectric layer includes a dent between the first metal line and the second metal line; recessing the first dielectric layer using an anisotropic etching process, wherein after the anisotropic etching process, the dent extends below the top surface of the first metal line and the second metal line; forming a first protective layer above the first dielectric layer; removing a portion of the first protective layer above the dent, wherein the remaining portion of the first protective layer has a corresponding umbrella-shaped profile in a cross-sectional view; etching a hole through the first dielectric layer at the location of the dent; and widening the hole into the space using an isotropic etching process.

[0102] Example 9. The method of Example 8, wherein the first protective layer comprises a nitride.

[0103] Example 10. The method of one of Examples 8 or 9, wherein the nitride is Si3N4.

[0104] Example 11. The method of one of Examples 8 to 10, further comprising: forming an air gap by depositing a second dielectric layer over the first protective layer and the hole.

[0105] Example 12. The method of Example 11, wherein a highest point of the air gap is below a top surface of the first protective layer.

[0106] Example 13. The method of one of Examples 11 or 12, wherein the curved tip of the first protective layer extends over the air gap.

[0107] Example 14. The method of one of Examples 8 to 13, further comprising: forming a second protection layer over sidewalls of the first metal line and the second metal line.

[0108] Example 15. The method of Example 14, wherein the first protective layer and the second protective layer are the same material.

[0109] Example 16. A semiconductor device comprising: a first conductive feature and a second conductive feature over a substrate; a dielectric layer between the first conductive feature and the second conductive feature; an air gap between the first conductive feature and the second conductive feature in the dielectric layer; a protective layer over the first conductive feature, the second conductive feature, and the dielectric layer; and a first opening through the protective layer, a second opening through the protective layer, and a third opening through the protective layer, the first opening, the second opening, and the third opening being located over the air gap, wherein the first opening, the second opening, and the third opening form a triangle in a plan view.

[0110] Example 17. The semiconductor device of Example 16, wherein the protective layer comprises a nitride.

[0111] Example 18. The semiconductor device of one of Examples 16 or 17, wherein the protective layer also covers sidewalls of the first conductive feature and the second conductive feature.

[0112] Example 19. The semiconductor device of one of Examples 16 to 18, wherein a highest point of the air gap is below a top surface of the protective layer.

[0113] Example 20. The semiconductor device of one of Examples 16 to 19, wherein the air gap is above the transistor gate structure.

[0114] Although this description has been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure defined by the appended claims. In each of the accompanying drawings, the same elements are designated by the same reference numerals. Moreover, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because those of ordinary skill in the art will easily understand from this disclosure that the processes, machines, manufactures, material compositions, parts, methods or steps that exist now or will be developed later can perform the same functions as the corresponding embodiments described herein or achieve the same results. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, parts, methods or steps within their scope.

Claims

1. A semiconductor device, characterized in that: include: a first conductive feature and a second conductive feature over the substrate; a dielectric layer between the first conductive feature and the second conductive feature; an air gap in the dielectric layer between the first conductive feature and the second conductive feature; a protective layer over the first conductive feature, the second conductive feature, and the dielectric layer; as well as A first opening through the protective layer, a second opening through the protective layer, and a third opening through the protective layer, the first opening, the second opening, and the third opening are above the air gap, wherein the first opening, the second opening, and the third opening form a triangle in a plan view.

2. The semiconductor device according to claim 1, wherein: The protection layer includes nitride.

3. The semiconductor device according to claim 1, wherein: The protection layer also covers sidewalls of the first conductive feature and the second conductive feature.

4. The semiconductor device according to claim 1, wherein: The highest point of the air gap is below the top surface of the protection layer.

5. The semiconductor device according to claim 1, wherein: The air gap is above the transistor gate structure.

Images