Signal acquisition circuit and keyboard control chip

Abstract

The utility model discloses a signal acquisition circuit and a keyboard control chip, and relates to the technical field of keyboards. The signal acquisition circuit comprises a data acquisition module, a data compression module and a data transmission module, the data acquisition module is used for being connected with at least one key, and the data acquisition module samples the at least one key to obtain sampling data; the data compression module is connected with the data acquisition module, and the data compression module is used for compressing invalid data in the sampled data; and the data transmission module is connected with the data compression module and is used for transmitting the sampling data. According to the utility model, invalid data in the sampled data sampled by the data acquisition module is compressed through the data compression module, so that the transmission of the invalid data is avoided, the energy consumption of the keyboard is remarkably reduced, the data transmission efficiency is improved, and the transmission delay is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of keyboards, in particular to a signal acquisition circuit and a keyboard control chip. Background Art

[0002] The traditional detection technology of keyboards is to obtain data by continuously scanning keys and transmit key status information. Key chips are mostly connected in daisy chain form. On the same signal chain, after passing through multiple key chips, the signal chain length continues to accumulate and is finally transmitted to the main control chip.

[0003] Mis-touch and signal crosstalk between keys are common problems in current keyboard designs. They transmit unnecessary information, lengthen the signal chain, and cause problems such as reduced transmission rate, reduced accuracy, and excessive energy consumption. Utility Model Content

[0004] In view of the deficiencies in the prior art, the purpose of the utility model is to provide a signal acquisition circuit and a keyboard control chip for avoiding the transmission of invalid data, thereby significantly reducing keyboard energy consumption, improving data transmission efficiency, and reducing transmission delay.

[0005] According to a first aspect of the utility model, a signal acquisition circuit is provided, comprising:

[0006] A data acquisition module, the data acquisition module is used to connect to at least one button, and the data acquisition module samples at least one button to obtain sampled data;

[0007] A data compression module, the data compression module is connected to the data acquisition module, and the data compression module is used to compress invalid data in the sampled data;

[0008] A data transmission module, wherein the data transmission module is connected to the data compression module, and the data transmission module is used to transmit the sampled data.

[0009] The signal acquisition circuit of the utility model compresses invalid data in the sampled data obtained by the data acquisition module through the data compression module, thereby avoiding the transmission of invalid data, thereby significantly reducing keyboard energy consumption, improving data transmission efficiency, and reducing transmission delay.

[0010] In some implementations, the data acquisition module includes an ADC module, and the ADC module is used to perform ADC sampling on at least one of the keys to obtain an ADC sampling value.

[0011] In some implementations, the data compression module is configured to determine that the ADC sampling value is invalid data when the ADC sampling value is lower than a first preset threshold, and set a flag bit in the ADC sampling value to a first specific value and a data bit to zero.

[0012] In some implementations, the data compression module is further configured to determine that the ADC sampling value is valid data when the ADC sampling value is not lower than a first preset threshold value, and set a flag bit in the ADC sampling value to a second specific value.

[0013] In some embodiments, the data compression module includes:

[0014] A differential encoder, the differential encoder is connected to the ADC module, and the differential encoder is used to perform differential operation processing on the ADC sampling values;

[0015] An average value module is connected to the differential encoder and is used to perform average processing on the differential ADC sampling values ​​processed by the differential operation.

[0016] In some implementations, an anti-interference module is further included. The anti-interference module is connected between the data compression module and the data transmission module. The anti-interference module is used to perform anti-interference processing on the ADC sampling value.

[0017] In some embodiments, the anti-interference module includes:

[0018] A timestamp recording module, the timestamp recording module is connected to the data compression module, and the timestamp recording module is used to record the start time and end time of at least one of the key actions to obtain timestamp information;

[0019] an interference detection module, the interference detection module being connected to the timestamp recording module, and the interference detection module being configured to determine that the ADC sampling value is interference data based on the timestamp information or when the ADC sampling value at a preset number of times is lower than a second preset threshold;

[0020] An interference signal elimination circuit, wherein the interference signal elimination circuit is connected to the interference detection module, and the interference signal elimination circuit is used to eliminate the interference data.

[0021] According to a second aspect of the utility model, a keyboard control chip is provided, and the keyboard control chip includes the above-mentioned signal acquisition circuit.

[0022] In some implementations, a variable delay circuit is further included, wherein the variable delay circuit is used to be connected to a host via a daisy chain, and the variable delay circuit performs delay processing on a digital signal sent by the host.

[0023] In some embodiments, the variable delay circuit includes:

[0024] A plurality of delay circuits, each of which has a different delay time;

[0025] A control circuit is connected to the host and the plurality of delay circuits respectively, and the control circuit is configured to selectively conduct the host and one of the delay circuits.

[0026] In some embodiments, it further comprises:

[0027] An interface module, the interface module is used to be connected to a host through a daisy chain, and the interface module receives at least one pulse signal sent by the host;

[0028] A control module is connected to the interface module, and the control module controls the keyboard control chip to perform corresponding operations according to at least one of the pulse signals.

[0029] In some embodiments, the control module includes:

[0030] A counter, the counter being connected to the interface module, and the counter being used to count at least one of the pulse signals;

[0031] An instruction detection and processing module is connected to the counter, and is used to control the keyboard control chip to perform a corresponding operation according to at least one pulse signal counted.

[0032] In some embodiments, the instruction detection and processing module is configured to control the keyboard control chip to perform a first operation when at least one of the pulse signals meets a first preset time, and / or to control the keyboard control chip to perform a second operation when at least one of the pulse signals meets a second preset time, and / or to control the keyboard control chip to perform a third operation when at least one of the pulse signals meets a third preset time.

[0033] Compared with the prior art, the signal acquisition circuit and keyboard control chip of the utility model compress invalid data in the sampled data obtained by the data acquisition module through the data compression module, so as to avoid the transmission of invalid data, thereby significantly reducing keyboard energy consumption, improving data transmission efficiency, and reducing transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the connection between the signal acquisition circuit and the key in one embodiment of the utility model;

[0035] Figure 2This is a schematic diagram of the key signal transmission module composition of an embodiment of the utility model;

[0036] Figure 3 A schematic diagram of data bit composition of invalid data according to an embodiment of the present utility model;

[0037] Figure 4 This is a schematic diagram of the data bit composition of effective data in one embodiment of the utility model;

[0038] Figure 5 A schematic diagram of the first composition of a data compression module of a signal acquisition circuit according to an embodiment of the utility model

[0039] Figure 6 This is a second schematic diagram of the composition of the data compression module of the signal acquisition circuit according to one embodiment of the utility model;

[0040] Figure 7 This is a schematic diagram of the connection between the signal acquisition circuit and the key in another embodiment of the utility model;

[0041] Figure 8 It is a schematic diagram of the composition of the anti-interference module of the signal acquisition circuit in another embodiment of the utility model;

[0042] Fig. 9 This is a circuit schematic diagram of a variable delay circuit of a keyboard control chip according to an embodiment of the utility model;

[0043] Fig.10 This is a schematic diagram of the module composition of a keyboard control chip according to another embodiment of the present utility model;

[0044] Fig.11 This is a schematic diagram of the composition of a control module of a keyboard control chip according to another embodiment of the present invention.

[0045] Explanation of the accompanying drawings: button 10, keyboard control chip 20, variable delay circuit 21, delay circuit 22, regulation circuit 23, interface module 24, control module 25, counter 26, instruction detection and processing module 27, keyboard master control 30, data acquisition module 100, ADC module 110, data compression module 200, differential encoder 210, average module 220, data transmission module 300, anti-interference module 400, timestamp recording module 410, interference detection module 420, interference signal elimination circuit 430. DETAILED DESCRIPTION

[0046] The utility model is further described in detail below in conjunction with the accompanying drawings.

[0047] According to the first aspect of the utility model, Figure 1The signal acquisition circuit according to one embodiment of the present invention is schematically shown, and the signal acquisition circuit is used to sample the key signal of the key 10 on the keyboard. Figure 1 As shown, the signal acquisition circuit includes a data acquisition module 100 , a data compression module 200 and a data transmission module 300 , wherein the signal acquisition circuit can be integrated into a keyboard control chip 20 .

[0048] For sampling and transmission of the key signal of the key 10 on the keyboard, such as Figure 2 As shown, it is usually implemented by multiple keyboard control chips 20 as slaves and a keyboard main control 30 (MCU) as a host, wherein each keyboard control chip 20 samples at least one key 10 on the keyboard through a key channel to obtain sampled data (i.e., key signal), and the multiple keyboard control chips 20 as slaves and the keyboard main control 30 as a host are connected via a daisy chain (Serial PeripheralInterface, SPI communication) connection, each keyboard control chip 20 transmits the sampled data obtained by sampling the key 10 to the keyboard master 30 through a daisy chain. During the entire transmission process, the sampled data is packaged according to the data transmission format. For ease of understanding, the present embodiment takes the 16-bit data transmission format as an example for explanation. Of course, the above-mentioned 16-bit data transmission format is only for ease of explanation, and it is not a limitation of the present embodiment. The present embodiment can also replace it with a data transmission format of other bits; for the 16-bit data transmission format, it is generally 2-bit flag bit + 12-bit ADC data bit + 2-bit parity check bit, the 2-bit flag bit is used to distinguish the validity of the data, the 12-bit ADC data bit is used to carry the ADC acquisition value corresponding to the actual key 10, the ADC acquisition value reflects the pressing state or strength of the key 10, and the 2-bit parity check bit is used to ensure the accuracy of data transmission. It generates a 2-bit check bit by performing parity check calculation on the 12-bit ADC data bit and embeds it into the data packet. The receiving end (such as the keyboard master 30) recalculates the parity check and compares it when unpacking. If it is consistent, the data is confirmed to be correct, otherwise it is marked as a transmission error.

[0049] like Figure 1As shown, the data acquisition module 100 is used to connect with at least one button 10, and the data acquisition module 100 samples at least one button to obtain sampling data; when sampling the button 10, since the button 10 generates an analog signal, it is necessary to convert the analog signal generated by the button 10 into a digital signal for subsequent modules / circuits to process. Specifically, the data acquisition module includes an ADC module 110, and the ADC module 110 has a button channel, each button channel is connected to each button 10, and the ADC module 110 is used to perform real-time ADC sampling on at least one button 10 through the button channel to obtain a changing ADC sampling value (i.e., sampling data), that is, the ADC module 110 converts the analog signal generated by the button 10 into an ADC sampling value as a digital signal.

[0050] The data compression module 200 is connected to the data acquisition module 100, and the data compression module 200 is used to compress invalid data in the sampled data; specifically, the data compression module 200 is configured to determine that the ADC sampled value is invalid data when the ADC sampled value is lower than a first preset threshold value, and set the flag bit in the ADC sampled value to a first specific value and the data position to zero, such as Figure 3 As shown, when the ADC sampling value is lower than the first preset threshold, the ADC sampling value is judged as invalid data. In order to reduce the transmission of unnecessary data, the invalid data can be compressed. The specific compression method is to set the flag bit in the ADC sampling value to a first specific value, wherein the first specific value indicates that the flag bit is an invalid bit, that is, the ADC sampling value is invalid data, and at the same time, the data position in the ADC sampling value is set to zero, that is, all 12 ADC data bits are set to zero. A data sequence of all 0s can usually obtain a good compression rate, and the amount of compressed data is smaller, which can be transmitted faster, thereby improving data transmission efficiency and reducing transmission delay, thereby achieving a faster reading speed after decompression at the receiving end. In addition, by comparing the ADC sampling value obtained by sampling the key 10 with the first preset threshold to determine whether the ADC sampling value is invalid data, the transmission of false touch signals can be avoided; the transmission of low-value invalid data is avoided, thereby significantly reducing the energy consumption of the keyboard.

[0051] Furthermore, the data compression module 200 is further configured to determine that the ADC sampling value is valid data when the ADC sampling value is not lower than the first preset threshold value, and set the flag bit in the ADC sampling value to a second specific value, such as Figure 4 As shown, when the ADC sampling value is not lower than the first preset threshold value, the ADC sampling value is judged as valid data. In order to distinguish it from invalid data, the flag bit in the ADC sampling value is set to a second specific value, wherein the second specific value indicates that the flag bit is a valid bit, that is, it indicates that the ADC sampling value is valid data, and the 12-bit ADC data bit is not changed, and the original data is maintained.

[0052] In an optional embodiment, if Figure 5 As shown, the data compression module 200 includes a comparator 201, a register 202 and a combinational logic circuit 203. The comparator 201 is connected to the data acquisition module 100 and is used to compare the ADC sampling value with the first preset threshold value. The combinational logic circuit 203 is connected to the comparator 201. The combinational logic circuit 203 is used to set the flag bit in the ADC sampling value to a first specific value and the data position to zero when the ADC sampling value is lower than the first preset threshold value. In addition, the combinational logic circuit 203 also sets the flag bit in the ADC sampling value to a second specific value when the ADC sampling value is not lower than the first preset threshold value. The combinational logic circuit 203 can be a NAND gate, a NOR gate or a combination of the two. The register 202 is connected to the combinational logic circuit 203 and is used to store the operation result and the zero result.

[0053] The signal acquisition circuit of this embodiment compresses invalid data in the sampled data obtained by the data acquisition module 100 through the data compression module 200, so as to avoid the transmission of invalid data, thereby significantly reducing keyboard energy consumption, improving data transmission efficiency, and reducing transmission delay.

[0054] In an optional embodiment, if Figure 6 As shown, the data compression module 200 includes a differential encoder 210 and an average module 220. The differential encoder 210 is connected to the ADC module 110. The differential encoder is used to perform differential operation processing on multiple ADC sampling values ​​obtained by continuous sampling of the ADC module 110, that is, encoding is performed using the differential encoding principle of the differential encoder 210. Since the ADC module 110 samples the analog signal generated by the button 10, and the analog signal has a continuous characteristic, the difference in the ADC sampling values ​​of the ADC module 110 is small. Therefore, the output of the ADC module 110 is differentially encoded, and the first ADC sampling value and the difference are recorded for transmission. The amount of data obtained is relatively low, which can reduce the amount of signal transmission.

[0055] The average module 220 is connected to the differential encoder 210. The average module 220 is used to average the differential ADC sampling values ​​processed by the differential operation. Specifically, the average module 220 can be an average circuit, that is, the average function of the average circuit is used to average the differential ADC sampling values ​​processed by the differential operation, so that the final data volume is lower, which can further reduce the signal transmission volume. Among them, the average circuit can be an integration circuit, which integrates the ADC sampling values ​​to obtain the average value of the ADC sampling values. The average circuit can also be an operational amplifier average circuit, which can perform weighted averaging on the ADC sampling values ​​and output the calculated average value.

[0056] It should be noted that the average value module 220 may be omitted for the data compression module 200 , that is, only the data compression capability of the differential encoder 210 is utilized.

[0057] The data transmission module 300 is connected to the data compression module 200. The data transmission module 300 is used to transmit sampled data. Specifically, the data compression module 200 compresses the ADC sampling values ​​processed by the ADC module 110 in the data acquisition module 100 and transmits them to the data transmission module 300. The data transmission module 300 transmits the compressed ADC sampling values ​​to the keyboard master control 30 via a daisy chain.

[0058] In an optional embodiment, if Figure 7 As shown, the signal acquisition circuit further includes an anti-interference module 400, which is connected between the data compression module 200 and the data transmission module 300, and is used to perform anti-interference processing on the ADC sampling value.

[0059] Specifically, Figure 8 As shown, the anti-interference module 400 includes a timestamp recording module 410, an interference detection module 420 and an interference signal elimination circuit 430; the timestamp recording module 410 is connected to the data compression module 200, and the timestamp recording module 410 is used to record the start time and end time of at least one key 10 action to obtain timestamp information. The key action of the key 10 includes a press judgment (corresponding to the start time of the key action) and a release judgment (corresponding to the end time of the key action). Specifically, the timestamp recording module 410 compares the ADC sampling value with a preset press threshold value. When the ADC sampling value is higher than the preset press threshold value, it is determined that the key is pressed. At this time, the time corresponding to the ADC sampling value is recorded as the start time of the key action. The timestamp recording module 410 compares the ADC sampling value with the preset release threshold value. When the ADC sampling value is lower than the preset release threshold value, it is determined that the key is released. At this time, the time corresponding to the ADC sampling value is recorded as the end time of the key action; the start time and end time in the timestamp information can be used to determine the sequence of key events.

[0060] The interference detection module 420 is connected to the timestamp recording module 410. The interference detection module 420 is configured to determine that the ADC sampling value is interference data based on the timestamp information and when the ADC sampling value of a preset number of times is lower than the second preset threshold value; specifically, when a key 10 is pressed, due to factors such as mechanical coupling, the adjacent unpressed keys generate interference waveforms, and because the crosstalk occurs before the key event begins, when the crosstalk occurs, it will be reflected in the ADC sampling value. Therefore, the interference detection module 420 can know which data in the ADC sampling value is the key data through the start time and end time of the key action in the timestamp information, and the data other than that is considered to be interference data. In addition, the interference detection module 420 can also determine whether the ADC sampling value is interference data by comparing the ADC sampling value of a preset number of times with the second preset threshold value. When the ADC sampling values ​​of a preset number of times (such as two or three consecutive times, etc.) are lower than the second preset threshold value, these ADC sampling values ​​are judged to be interference data.

[0061] The interference signal elimination circuit 430 is connected to the interference detection module 420. The interference signal elimination circuit 430 is used to eliminate interference data, effectively suppress and eliminate false key signals generated by crosstalk, and further reduce the amount of transmitted data. Exemplarily, the ADC sampling value judged as an interference signal can be filtered and deducted, such as deducting 10 to avoid key 10 being mistakenly regarded as triggering "pressing". In addition, the time for crosstalk filtering can be one key cycle, such as 125us, and digital filtering, such as a filtering circuit, can be selected for crosstalk filtering.

[0062] According to a second aspect of the present invention, a keyboard control chip 20 is provided. The keyboard control chip 20 includes the above-mentioned signal acquisition circuit.

[0063] In an optional embodiment, if Fig. 9 As shown, the keyboard control chip 20 also includes a variable delay circuit 21, which is used to connect to a host (such as a keyboard master control 30) via a daisy chain. The variable delay circuit 21 delays the digital signal sent by the host, wherein in the daisy chain line, the host performs spectrum spreading on the sent data signal.

[0064] Specifically, the variable delay circuit 21 includes multiple delay circuits 22 and a control circuit 23; the number of delay elements connected in series in each delay circuit 22 is different, so that the delay time of each delay circuit 22 is different, and the input end (such as In1-In4) of each delay circuit 22 receives the data signal to be transmitted, and the output end (such as Out1-Out4) outputs the delayed data signal.

[0065] The control circuit 23 is respectively connected to the host and multiple delay circuits 22. The control circuit 23 is configured to select and connect the host and one of the delay circuits 22. Specifically, the control circuit 23 can be a selection switch K1. The selection switch K1 has a common end and multiple branch ends. The common end of the selection switch K1 is connected to the host through a daisy chain, and each branch end is respectively connected to the input end of a different delay circuit 22. The selection switch K1 can randomly or regularly connect the host and one of the delay circuits 22, thereby regulating the delay circuit 22 through which the data signal passes, and then controlling the delay time of the data signal.

[0066] By adjusting the variable delay circuit 21, the frequency of the data signal is changed randomly or regularly within a certain range, so as to disperse the energy spectrum density and reduce the electromagnetic radiation intensity at a single frequency.

[0067] In an optional embodiment, if Fig.10 As shown, the keyboard control chip 20 also includes an interface module 24 and a control module 25. Since multiple keyboard control chips 20 as slaves are used when sampling the key signals of the keys 10 on the keyboard, the interface module 24 of each keyboard control chip 20 is connected to the host (such as the keyboard master control 30 (MCU)) through a daisy chain, so that the interface module 24 can receive at least one pulse signal sent by the host; specifically, the interface module 24 includes a clock terminal CLK, a signal input terminal In, a signal output terminal Out and a chip select input terminal CMD&CS. The clock terminal CLK of each keyboard control chip 20 is connected to the clock terminal of the host at the same time. The signal input terminal of the first keyboard control chip 20 is connected to the clock terminal of the host. The input terminal In is connected to the signal output terminal of the host, the signal output terminal Out of the first keyboard control chip 20 is connected to the signal input terminal In of the second keyboard control chip 20, the signal output terminal Out of the second keyboard control chip 20 is connected to the signal input terminal In of the third keyboard control chip 20, and the above connection method is followed until the signal output terminal Out of the last keyboard control chip 20 is connected to the signal input terminal of the host. The chip select input terminal CMD&CS of each keyboard control chip 20 is connected to the chip select input terminal of the host at the same time. The chip select input terminal CMD&CS of the keyboard control chip 20 is configured to receive at least one pulse signal sent by the host and send the pulse signal to the control module 25.

[0068] The control module 25 is connected to the interface module 24. The control module 25 controls the keyboard control chip 20 to perform corresponding operations according to at least one pulse signal. That is, the control module 25 analyzes different pulse signals and controls the keyboard control chip 20 as a slave to execute different operation commands, thereby expanding the function of the interface module 24. Specifically, Fig.11As shown, the control module 25 includes a counter 26 and an instruction detection processing module 27; the counter is connected to the chip select input terminal CMD&CS of the interface module 24, and the counter 26 is used to count at least one pulse signal, that is, when the chip select input terminal CMD&CS of the interface module 24 receives a pulse signal, it is counted in turn by the counter 26 and transmitted to the instruction detection processing module 27 for command conversion.

[0069] The instruction detection processing module 27 is connected to the counter 26. The instruction detection processing module 27 is used to control the keyboard control chip 20 to perform a corresponding operation according to at least one pulse signal after counting. Specifically, the instruction detection processing module 27 is configured to control the keyboard control chip 20 to perform a first operation when at least one pulse signal meets a first preset time. Exemplarily, when the pulse time corresponding to the pulse signal received by the instruction detection processing module 27 is 15ms (the pulse time is obtained by counting the counter 26), it indicates that the keyboard control chip 20 should execute the key brightness configuration, and the instruction detection processing module 27 controls the keyboard control chip 20 to perform the key brightness configuration operation.

[0070] Furthermore, the instruction detection and processing module 27 is also configured to control the keyboard control chip 20 to perform a second operation when at least one pulse signal meets a second preset time. For example, when the pulse time corresponding to the pulse signal received by the instruction detection and processing module 27 is 25ms (the pulse time is obtained by counting the counter 26), it indicates that the keyboard control chip 20 should execute the key color configuration, and the instruction detection and processing module 27 controls the keyboard control chip 20 to perform the key color configuration operation.

[0071] Furthermore, the instruction detection processing module 27 is also configured to control the keyboard control chip 20 to perform a third operation when at least one pulse signal meets a third preset time. For example, when the pulse time corresponding to the pulse signal received by the instruction detection processing module 27 is 30ms (the pulse time is obtained by counting the counter 26), it indicates that the keyboard control chip 20 should activate the data transmission channel (ie, the interface module 24), and the instruction detection processing module 27 corresponds to controlling the keyboard control chip 20 to activate the data transmission channel (ie, the interface module 24).

[0072] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A signal acquisition circuit, characterized in that: include: A data acquisition module, the data acquisition module is used to connect to at least one button, and the data acquisition module samples at least one button to obtain sampled data; A data compression module, the data compression module is connected to the data acquisition module, and the data compression module is used to compress invalid data in the sampled data; A data transmission module, wherein the data transmission module is connected to the data compression module, and the data transmission module is used to transmit the sampled data.

2. The signal acquisition circuit according to claim 1, characterized in that: The data acquisition module includes an ADC module, and the ADC module is used to perform ADC sampling on at least one of the keys to obtain an ADC sampling value.

3. The signal acquisition circuit according to claim 2, characterized in that: The data compression module is configured to determine that the ADC sampling value is invalid data when the ADC sampling value is lower than a first preset threshold, and set the flag bit in the ADC sampling value to a first specific value and the data bit to zero.

4. The signal acquisition circuit according to claim 3, characterized in that: The data compression module is further configured to determine that the ADC sampling value is valid data when the ADC sampling value is not lower than a first preset threshold value, and set a flag bit in the ADC sampling value to a second specific value.

5. The signal acquisition circuit according to any one of claims 2 to 4, characterized in that: The data compression module comprises: A differential encoder, the differential encoder is connected to the ADC module, and the differential encoder is used to perform differential operation processing on the ADC sampling values; An average value module is connected to the differential encoder and is used to perform average processing on the differential ADC sampling values ​​processed by the differential operation.

6. The signal acquisition circuit according to any one of claims 2 to 4, characterized in that: It also includes an anti-interference module, which is connected between the data compression module and the data transmission module, and is used to perform anti-interference processing on the ADC sampling value.

7. The signal acquisition circuit according to claim 6, characterized in that: The anti-interference module comprises: A timestamp recording module, the timestamp recording module is connected to the data compression module, and the timestamp recording module is used to record the start time and end time of at least one of the key actions to obtain timestamp information; an interference detection module, the interference detection module being connected to the timestamp recording module, and the interference detection module being configured to determine that the ADC sampling value is interference data based on the timestamp information or when the ADC sampling value at a preset number of times is lower than a second preset threshold; An interference signal elimination circuit, wherein the interference signal elimination circuit is connected to the interference detection module, and the interference signal elimination circuit is used to eliminate the interference data.

8. A keyboard control chip, characterized in that: The invention comprises the signal acquisition circuit as described in any one of claims 1 to 7.

9. The keyboard control chip according to claim 8, characterized in that: It also includes a variable delay circuit, which is used to connect to the host through a daisy chain, and the variable delay circuit delays the digital signal sent by the host.

10. The keyboard control chip according to claim 9, characterized in that: The variable delay circuit comprises: A plurality of delay circuits, each of which has a different delay time; A control circuit is connected to the host and the plurality of delay circuits respectively, and the control circuit is configured to selectively conduct the host and one of the delay circuits.

11. The keyboard control chip according to any one of claims 8 to 10, characterized in that: Also includes: An interface module, the interface module is used to be connected to a host through a daisy chain, and the interface module receives at least one pulse signal sent by the host; A control module is connected to the interface module, and the control module controls the keyboard control chip to perform corresponding operations according to at least one of the pulse signals.

12. The keyboard control chip according to claim 11, characterized in that: The control module comprises: A counter, the counter being connected to the interface module, and the counter being used to count at least one of the pulse signals; An instruction detection and processing module is connected to the counter, and is used to control the keyboard control chip to perform a corresponding operation according to at least one pulse signal counted.

13. The keyboard control chip according to claim 12, characterized in that: The instruction detection and processing module is configured to control the keyboard control chip to perform a first operation when at least one of the pulse signals meets a first preset time, and / or to control the keyboard control chip to perform a second operation when at least one of the pulse signals meets a second preset time, and / or to control the keyboard control chip to perform a third operation when at least one of the pulse signals meets a third preset time.

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