Electrical detection structure and system for grid spacing drift in FinFET process
By designing an electrical detection structure in the FinFET process and using capacitance to test the reverse gate pitch, the problem of difficult to test gate pitch drift in the prior art is solved, and fast and accurate detection and adjustment are achieved, and device performance and chip yield are improved.
Patent Information
- Application Number
- CN202420562884.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2034-03-22
AI Technical Summary
The prior art is difficult to quickly and large-sample test the difference in gate center spacing in FinFET processes, and it is impossible to effectively characterize the gate spacing drift, affecting device performance and chip yield.
An electrical detection structure for gate pitch drift in FinFET process is designed. Through capacitance testing of multiple gates and the metallic layer, the gate pitch is reversed, and the gate pitch drift is characterized by the difference in capacitance values.
The difference in gate center spacing is achieved in a fast, large sample test, which can clearly characterize the gate spacing drift, help adjust the width and distance of the mandrel, and improve device performance and chip yield.
Smart Images
Figure CN222562628U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical detection, in particular to an electrical detection structure and system for gate spacing drift in a FinFET process. Background Art
[0002] With the continuous development of large-scale integrated circuit technology, the integration of circuits continues to increase. When the process technology node is less than 28nm, there is a trend that traditional planar MOS devices are gradually replaced by three-dimensional fin field effect transistors (FinFETs) due to the sharp degradation of performance. Compared with planar transistors, FinFETs generally include a semiconductor substrate, an oxide layer and a gate structure. A protruding structure is formed on the semiconductor substrate. The oxide layer covers the surface of the semiconductor substrate and a part of the sidewall of the protruding structure. The part of the protruding structure that exceeds the oxide layer becomes the fin of the FinFET. The gate structure spans over the fin and covers the top and sidewalls of the fin. The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. For FinFET, the top of the fin and the part of the sidewalls on both sides that contact the gate structure become channel regions, that is, there are multiple gates, which is conducive to increasing the drive current and improving device performance.
[0003] As traditional lithography technology in logic processes is difficult to achieve small-scale exposure, self-aligned processes have begun to shine. The preparation of the fins of fin field-effect transistors uses self-aligned double patterning (SADP, sel to small scale, faligned double patterning) or self-aligned quadruple patterning (SAQP, self aligned quadruple patterning) to achieve fin uniformity. Similarly, the preparation of the gate of the field-effect transistor is also full of challenges. Self-aligned technology is also used for the preparation of gates at advanced nodes.
[0004] The simple process of preparing the gate by self-aligned double patterning technology is as follows: 1. Prepare the mandrel (Mandrel) by traditional photolithography process; 2. Deposit the sidewalls (Spacer) on both sides of the mandrel and etch the mandrel; 3. Etch out the gate. Figure 1 As shown in the figure, the gate center spacing is pitch1 and pitch2, which are determined by the core axis width (w), core axis distance (s) and sidewall width (w0). Pitch1 = w + w0, pitch2 = s - w0. The mismatch between pitch1 and pitch2 is called pitch walking, which will affect the device performance and thus affect the chip yield.
[0005] Currently, there are two main methods for detecting Pitch Walking problems: one is optical measurement, which directly measures the distance between different Fins through optical means to find abnormal points. This detection method is slow, inefficient, and requires a small number of samples. It also relies on the selection of the measurement area and is easily affected by random fluctuations. The other is transistor performance testing. If the transistor performance fluctuates greatly, it is suspected that the gate uniformity is poor. This method has poor targeting and many factors affect transistor performance. This method takes a long time to detect. At the same time, since there are many factors that affect transistor performance, it cannot be determined whether the abnormality is caused by Pitch Walking. Utility Model Content
[0006] The main technical problem solved by the utility model is to provide an electrical detection structure and system for gate spacing drift in FinFET process, which can quickly and large-sample test the difference in gate center spacing and characterize the specific difference.
[0007] In order to solve the above technical problems, a technical solution adopted by the utility model is: to provide an electrical detection structure for gate spacing drift in FinFET process, including a plurality of gates vertically arranged in a horizontal direction,
[0008] At least one set of detection units is included, wherein the detection unit includes at least one first connection part and at least two second connection parts, and
[0009] The unit to be tested includes a plurality of gates formed with a first spacing, and a connecting metal layer arranged between adjacent gates; the first connecting portion is electrically connected to the gate, and the two second connecting portions are electrically connected to different connecting metal layers respectively. The gate spacing drift is characterized by the degree of difference between multiple groups of different gate spacings and capacitance values, the capacitance is inversely proportional to the gate center spacing, and when different capacitance values differ by a certain threshold, it can be considered that there is a spacing offset problem, and the gate spacing drift is characterized by the degree of difference between at least two groups of measured capacitance values by respectively measuring different capacitance values on at least one first connecting portion and at least two second connecting portions.
[0010] The gate is formed by etching the sidewalls deposited on both sides of the mandrel. There are at least three gates, denoted as Gate11, Gate12, Gate21, ..., GateNM (N≥2, 1≤M≤2, N and M are both positive integers), and the gate GateN1 and the gate GateN2 are formed by etching the sidewalls deposited on the left and right sides of the same mandrel, the connecting metal M0 between GateN1 and GateN2 is M0_1, the connecting metal layer M0 adjacent to M0_1 is M0_2, and M0_1 and M0_2 are electrically connected to different second connecting parts respectively.
[0011] The gates and the connecting metal layers are sequentially arranged between the adjacent gates, starting from the connecting metal layer located at the head, and are sequentially and alternately electrically connected to at least two of the second connecting parts.
[0012] The gate and the connecting metal layer both belong to the same metal layer.
[0013] The connection metal layer is arranged in parallel with the gate.
[0014] The first connection part and the second connection part span the gate and the connecting metal layer. At least two of the second connection parts are electrically connected to the upper and lower parts of different connecting metal layers, respectively. A first lead-out interface is configured on the first connection part, and a second lead-out interface is configured on the second connection part. The first connection part and the second connection part belong to the same layer of metal. The first connection part is electrically connected to the gate, and the second connection part is electrically connected to the connecting metal layer. By measuring the capacitance value between the lead-out interface I of at least one first connection part and the different lead-out interfaces II on at least two second connection parts, the gate spacing drift is characterized by the degree of difference in the capacitance values measured by at least two groups.
[0015] The utility model discloses an electrical detection structure and system for gate spacing drift in FinFET process, which reversely infers gate spacing through electrical capacitance test. The detection structure of this scheme can test a large number of samples in a large area, and the test speed is fast. By numerically representing the difference in gate center spacing, it can be clearly known how to adjust the width and distance of the core axis. Moreover, the detection structure with the same construction parameters can construct a fitting curve through data modeling. The corresponding gate spacing value can be obtained by testing the capacitance value of the detection structure without actual measurement. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The gate is formed by etching the sidewalls deposited on both sides of the mandrel;
[0017] Figure 2 It is a cross-sectional view of Embodiment 1 of an electrical detection system for gate spacing drift in a FinFET process of the utility model;
[0018] Figure 3 This is a schematic structural diagram of Embodiment 1 of an electrical detection system for gate spacing drift in a FinFET process of the utility model;
[0019] Figure 4 It is a cross-sectional view of Embodiment 2 of an electrical detection system for gate spacing drift in a FinFET process of the utility model;
[0020] Figure 5 It is the relationship curve 1 between capacitance C and gate spacing d;
[0021] Figure 6 This is the relationship curve 2 between capacitance C and gate spacing d. DETAILED DESCRIPTION
[0022] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.
[0023] The utility model embodiment includes:
[0024] Embodiment 1:
[0025] An electrical detection structure for gate spacing drift in FinFET process, see Figure 2 and Figure 3 , including a unit to be tested, the unit to be tested including a plurality of gates arranged in vertical and horizontal directions, and a connecting metal layer (i.e. Figure 2 and Figure 3 The simple process of preparing the gate using self-aligned double patterning technology is as follows: 1. Prepare the mandrel (Mandrel) using traditional photolithography; 2. Deposit sidewalls (Spacer) on both sides of the mandrel and etch the mandrel; 3. Etch out the gate. Figure 1 , the gate center spacing is pitch1 and pitch2, which are determined by the core axis width (w), core axis distance (s) and sidewall width (w0) respectively. pitch1=w+w0, pitch2=s-w0. The mismatch between pitch1 and pitch2 is called pitch walking, which will affect the device performance and thus the chip yield. The gate is on both sides of the 0th layer of metal. The 0th layer of metal located at the original core axis position is M0_1, and the 0th layer of metal located at the original core axis spacing position is M0_2. The capacitance between the 0th layer of metal and the gate is inversely proportional to the gate spacing. The capacitance between M0_1 and the gate is defined as C1, and the capacitance between M0_2 and the gate is defined as C2. A first connection portion is provided above the gate, and the first connection portion is connected to multiple gates through the 0th layer through-holes. The first connection portion is configured with an extraction interface I. A second connection portion is provided above M0_1 and M0_2, and the two second connection portions are respectively configured with extraction interfaces II and III, one of the second connection portions is connected to the 0th layer metal layer MO_1, and the other second connection portion is connected to the 0th layer metal layer M0_2. The first connection portion and the second connection portion belong to the 1st layer metal and are connected to the 0th layer metal through the 0th layer through-holes.
[0026] The measured capacitance of lead-out interface I and lead-out interface II is C1, and the measured capacitance of lead-out interface I and lead-out interface III is C2. Because the capacitance is inversely proportional to the gate center spacing, a threshold value is set between C1 and C2. The threshold value can be a set value such as 5%. If the threshold value of the difference between the measured capacitance values C1 and C2 meets the set value, it can be considered that there is a gate spacing offset problem in the FINFET process.
[0027] If C1 is greater than C2, pitch1 (mandrel width + side wall width) is less than pitch2 (mandrel spacing - side wall width), and the mandrel width needs to be increased. If C1 is less than C2, pitch1 (mandrel width + side wall width) is less than pitch2 (mandrel spacing - side wall width), and the mandrel width needs to be reduced.
[0028] Embodiment 2:
[0029] Example 2 provides an electrical detection system for gate spacing drift in a FinFET process, which applies the electrical detection structure of Example 1 and combines it with a data modeling module to construct a fitting curve of gate spacing and capacitance value based on the correspondence between multiple groups of different gate spacings and capacitance values, and then obtains the corresponding gate spacing value on the fitting curve based on the actual test values of the two capacitors of the electrical detection structure, and adjusts the width and distance of the core axis according to the size of the two gate distance values.
[0030] The gate is flanked by the 0th layer of metal, and the capacitance between the gate and the 0th layer of metal is inversely proportional to the distance between the gates. The relationship between the 0th layer of metal and the gate capacitance is: C = a / (dw) (Formula 1), where a is the capacitance between the 0th layer of metal and the gate, a is a constant, d is the gate distance, and w is the 0th layer of metal width.
[0031] Arrays with different gate spacings are designed, with gate spacings of d_1, d_2, d_3, d_4, and d_5, respectively. The measured gate capacitances are C_1, C_2, C_3, C_4, and C_5, respectively. Substituting into formula 1, the relationship between capacitance C and gate spacing d is obtained: C = a_0 / (d-w_0) (formula 2). For the relationship curve between capacitance C and gate spacing d, see Figure 5 and Figure 6 The red points in the figure are experimental points, and the blue curve is the fitting curve.
[0032] Using the above electrical detection structure, the 0th metal layer located inside the original core axis is connected to the lead interface II, the 0th metal layer located outside the original core axis is connected to the lead interface III, and the gate is connected to the lead interface I. The capacitance of the lead interface I and the lead interface II is measured as C1, and the capacitance of the lead interface I and the lead interface III is measured as C2.
[0033] Substituting C1 and C2 into formula 2, we can get the gate distance inside the core axis as D1 and the gate distance outside the core axis as D2.
[0034] Adjust the mandrel width and distance according to the relative sizes of D1 and D2.
[0035] The present application discloses an electrical detection structure and system for gate spacing drift in FinFET process, which reversely infers gate spacing through electrical capacitance test. The detection structure of this scheme can test a large number of samples over a large area, and the test speed is fast. By numerically characterizing the difference in gate center spacing, it can be clearly known how to adjust the width and distance of the core axis. Moreover, the detection structure with the same construction parameters can construct a fitting curve through data modeling. The corresponding gate spacing value can be obtained by testing the capacitance value of the detection structure without actual measurement.
[0036] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. An electrical detection structure for gate spacing drift in FinFET process, characterized in that: At least one set of detection units is included, wherein the detection unit includes at least one first connection part and at least two second connection parts, and The unit to be tested includes a plurality of gates formed at a first pitch and a connecting metal layer arranged between adjacent gates; the first connecting portion is electrically connected to the gates, and two second connecting portions are electrically connected to different connecting metal layers respectively.
2. The electrical detection structure for gate spacing drift in FinFET process according to claim 1, characterized in that: The gate is formed by etching the two sides of the core axis and depositing the sidewalls.
3. The electrical detection structure for gate spacing drift in FinFET process according to claim 2, characterized in that: The connecting metal layers are sequentially arranged between the adjacent gates, and starting from the connecting metal layer located at the head, they are sequentially and alternately electrically connected to at least two of the second connecting parts.
4. The electrical detection structure for gate spacing drift in FinFET process according to claim 1, characterized in that: The gate and the connecting metal layer both belong to the same metal layer.
5. The electrical detection structure for gate spacing drift in FinFET process according to claim 4, characterized in that: The connection metal layer is arranged in parallel with the gate.
6. The electrical detection structure for gate spacing drift in FinFET process according to claim 1, characterized in that: The first connecting portion and the second connecting portion cross the gate and the connecting metal layer.
7. The electrical detection structure for gate spacing drift in FinFET process according to claim 3, characterized in that: At least two of the second connection parts are electrically connected to the upper part and the lower part of different connection metal layers respectively.
8. The electrical detection structure for gate spacing drift in FinFET process according to claim 1, characterized in that: The first connection portion is provided with a first lead-out interface, and the second connection portion is provided with a second lead-out interface.
9. The electrical detection structure for gate spacing drift in FinFET process according to claim 6, characterized in that: The first connection portion and the second connection portion belong to the same metal layer.
10. The electrical detection structure for gate spacing drift in FinFET process according to claim 6, characterized in that: The first connection portion and the gate, and the second connection portion and the connection metal layer are electrically connected through a through hole.