Integrated circuit

Abstract

The utility model relates to an integrated circuit. A hold flip-flop includes a first latch, a second latch, and a hold latch. The first latch and the second latch are powered by an interruptible primary supply voltage, while the hold latch is powered by an uninterruptible secondary supply voltage. The hold flip-flop receives a single hold control signal that controls whether the flip-flop is in a standard mode or a hold mode. In the hold mode, the flip-flop clock signal is paused.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits, and more particularly to integrated circuits having retention flip-flops. Background Art

[0002] An integrated circuit may include a large number of flip-flops. Each flip-flop typically receives a data value at a data input terminal and transmits the data value to an output terminal according to a clock signal. Each flip-flop may include a first latch and a second latch. Each latch may be composed of a plurality of transistors. In addition to the latch, each flip-flop may include additional circuits. Utility Model Content

[0003] In some cases, it is desirable for a flip-flop to hold a particular data value for a selected duration. To hold the data value in a standard flip-flop, all circuits of the flip-flop are continuously powered. This can result in an undesirable amount of power dissipation in the form of leakage current. If an integrated circuit has a very large number of flip-flops used to maintain a selected period of time under static conditions, the power dissipation can be very large.

[0004] The present disclosure provides an integrated circuit, including a retention trigger, wherein the retention trigger includes: a first latch, configured to receive a main supply voltage; a second latch, configured to receive the main supply voltage; a retention latch, configured to receive an auxiliary supply voltage and including a first terminal, the first terminal being configured to receive a retention control signal to activate the retention latch; and a clock generation circuit, configured to generate a clock signal, and including a second terminal, the second terminal being configured to receive the retention control signal.

[0005] In some embodiments of the present disclosure, the clock generation circuit is configured to interrupt generation of the clock signal in response to receiving a hold control signal.

[0006] In some embodiments of the present disclosure, the retention control signal causes the retention trigger to transition from a standard mode to a retention mode.

[0007] In some embodiments of the present disclosure, supply of a main supply voltage to the first latch and the second latch is interrupted in response to a retention control signal.

[0008] In some embodiments of the present disclosure, the retention flip-flop includes a tri-state inverter coupled between an output of the retention latch and an input of the first latch.

[0009] In some embodiments of the present disclosure, the tri-state inverter includes a third terminal configured to receive a hold control signal.

[0010] In some embodiments of the present disclosure, the retention flip-flop includes a transmission gate coupled between the first latch and the second latch, wherein the transmission gate is configured to transfer a signal from the first latch to the second latch when a retention control signal is present at the second terminal.

[0011] In some embodiments of the present disclosure, the first latch includes a tri-state inverter configured to receive a clock signal as a control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of an integrated circuit including a retention flip-flop according to one embodiment.

[0013] Figure 2A is a schematic diagram of a retention trigger according to one embodiment.

[0014] Figure 2B is in standard mode according to one embodiment Figure 2A Schematic diagram of a hold trigger.

[0015] Figure 2C is the first stage of the hold mode according to one embodiment Figure 2A Schematic diagram of a hold trigger.

[0016] Figure 2D is the second phase of the hold mode according to one embodiment Figure 2A Schematic diagram of a hold trigger.

[0017] Figure 3A is a timing diagram including multiple signals associated with a retention flip-flop according to one embodiment.

[0018] Figure 3B is a timing diagram including multiple signals associated with a retention flip-flop according to one embodiment.

[0019] Figure 4 is a flow chart of a method for operating a retention trigger according to one embodiment.

[0020] Figure 5 is a flow chart of a method for operating a retention trigger according to one embodiment. DETAILED DESCRIPTION

[0021] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, one skilled in the relevant art will appreciate that the embodiments may be implemented without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuits associated with integrated circuits are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0022] Unless the context requires otherwise, throughout the specification and the claims that follow, the word "include" and variations thereof (such as "comprises") should be interpreted in an open, inclusive sense, that is, as "including but not limited to." Additionally, the terms "first," "second," and similar sequential indicators should be interpreted as interchangeable unless the context clearly dictates otherwise.

[0023] References throughout this specification to "one embodiment" or "an embodiment" mean that the particular features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its broadest sense, that is, to mean "and / or," unless the content clearly dictates otherwise.

[0025] Figure 1 1 is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a retention flip-flop 102. The retention flip-flop 102 includes a first latch 104, a second latch 106, and a retention latch 108. The retention flip-flop also includes an input multiplexer 110 and a clock generation circuit 112. As explained in more detail below, the retention flip-flop 102 is a single pin retention flip-flop configured to operate in a clockless retention mode.

[0026] The retention trigger 102 includes a first power supply terminal for receiving a main supply voltage VDDP. The retention trigger 102 includes a second power supply terminal for receiving an auxiliary supply voltage VDDS. Figure 1 Not shown, the retention flip-flop 102 may also include a ground terminal configured to receive a ground voltage.

[0027] The main supply voltage VDDP is supplied to the first latch 104 and the second latch 106. Figure 1 1 , but the main supply voltage VDDP may also be supplied to the input multiplexer 110 and the clock generation circuit 112. The auxiliary supply voltage VDDS is supplied to the holding latch 108. As explained in more detail below, the main supply voltage VDDP is interruptible, while the auxiliary supply voltage VDDS is non-interruptible.

[0028] In one embodiment, the main supply voltage VDDP is provided to various components of the retention flip-flop 102 via the interrupt circuit 114. In particular, the interrupt circuit 114 receives the main supply voltage VDDP and then provides the main supply voltage VDDP to the components of the retention flip-flop 102. During the standard mode of the retention flip-flop 102, the interrupt circuit 114 provides the main supply voltage VDDP to the components of the retention flip-flop 102. As explained in more detail below, the interrupt circuit 114 is capable of interrupting the supply of the main supply voltage VDDP during the retention mode of the retention flip-flop 102. Further details on the standard mode and the retention mode are provided below.

[0029] In one embodiment, the interrupt circuit 114 is not part of the retention flip-flop 102. Alternatively, the interrupt circuit 114 may be located outside the retention flip-flop 102. The external interrupt circuit 114 may selectively supply or temporarily supply the main supply voltage VDDP to delay the plurality of retention flip-flops 102. Various other schemes, circuits, and methods can be used to interrupt or suspend the supply of the main supply voltage VDDP to the components of the retention flip-flop 102 without departing from the scope of the present disclosure.

[0030] The retention flip-flop 102 includes a data input terminal D coupled to the input multiplexer 110. The data input terminal D corresponds to a terminal through which an input data value is provided to the retention flip-flop 102. The retention flip-flop 102 includes a data output terminal Q. The data output terminal Q corresponds to a terminal through which an output data value is provided from the retention flip-flop 102.

[0031] The retention flip-flop 102 includes a clock input terminal CLK. The clock input terminal CLK receives a global clock signal CP. The clock generation circuit 112 receives the global clock signal CP and generates a local clock signal CPI. The local clock signal CPI may have the same frequency as the global clock signal CP. Figure 11 , the clock generation circuit 112 may also generate a complementary local clock signal CPN corresponding to the logical complement of the global clock signal CP. The clock generation circuit 112 may supply the local clock signal CPI to the input multiplexer 110, the first latch 104, and the second latch 106. As described in more detail below, the clock generation circuit 112 may interrupt the supply of the local clock signal CPI in the hold mode.

[0032] In standard mode, input multiplexer 110 , first latch 104 and second latch 106 receive main supply voltage VDDP. In standard mode, clock generation circuit 112 generates local clock signal CPI and provides local clock signal CPI to input multiplexer 110 , first latch 104 and second latch 106 .

[0033] Input multiplexer 110 receives input data values ​​from input data terminal D. Figure 1 100. Although not shown in the figure, the input multiplexer 110 may also receive other inputs. The input multiplexer 110 may receive a selection signal (not shown) that determines which input will be provided to the output of the input multiplexer 110. In order to simply describe the function of the holding flip-flop 102, only a single input is shown for the input multiplexer 110. In addition, in the standard mode, it will be assumed that the single input is selected by the selection signal.

[0034] In one embodiment, when the local clock signal CPI transitions, the multiplexer 110 passes the input signal (D) to the output of the input multiplexer 110. Therefore, in one embodiment, when the local clock signal CPI is valid, the input multiplexer 110 only outputs the newly received input data value. In one embodiment, the input multiplexer 110 outputs the logical complement of the input data value.

[0035] The input of the first latch 104 is coupled to the output of the input multiplexer 110. In standard mode, the first latch 104 receives a data value from the input multiplexer 110 and outputs a logical complement of the data value. The input of the second latch 106 is coupled to the output of the first latch 104. In standard mode, the second latch 106 receives an inverted data value from the first latch 104 and outputs the data value to the data output terminal Q. Therefore, in standard mode, no matter what value the first latch 104 and the second latch 106 receive, the first latch 104 and the second latch 106 are inverted.

[0036] In the standard mode, the data value is received at the input multiplexer 110. At the next transition of the local clock signal CPI, the data value is transmitted to the data output terminal Q through the first latch and the second latch. Therefore, with each clock signal, the data value can be transmitted from the data input terminal D to the data output terminal Q.

[0037] As previously mentioned, in some cases, the following situation is beneficial: the retention flip-flop 102 is placed in a type of low power mode without losing the current data value. In a standard flip-flop, if power is completely removed from the flip-flop, the data value will be lost. If it is not expected to receive a new data value during a relatively long duration, it will be more power-consuming to maintain the data value in a standard flip-flop because all the circuits of the flip-flop will be effective. The retention flip-flop 102 includes a retention latch 108 so that power consumption can be reduced in the retention mode. In particular, in the retention mode, for at least a portion of the retention mode, the main supply voltage VDDP is interrupted. In the retention mode, the auxiliary supply voltage VDDS is not interrupted but remains effective. This allows the retention latch 108 to store the current output data value when entering the retention mode. Because most of the circuits of the retention flip-flop 102 are effective during the retention mode due to the interruption of the main supply voltage VDDP, the retention mode results in reduced power consumption while the current output data value is maintained in the retention latch 108.

[0038] In one embodiment, the retention flip-flop 102 is a single-pin clockless retention flip-flop. The retention flip-flop 102 includes a single retention input terminal that receives the retention control signal RET. The single retention input terminal corresponds to the "single pin" of the retention flip-flop 102. As explained in more detail below, in one embodiment, only the retention control signal RET can enable and control the transition between the standard mode and the retention mode.

[0039] In one embodiment, the clock generation circuit 112, the retention latch 108 and the interrupt circuit 114 all receive the retention control signal RET. In fact, the retention control signal RET can have a first value or a second value. The retention control signal RET with a first value may correspond to the operation of the retention flip-flop 102 in the standard mode. The retention control signal RET with a second value may correspond to the operation of the retention flip-flop 102 in the retention mode. In response to the retention control signal RET changing from the first value to the second value, the retention mode may be entered. As used herein, "receipt of a retention control signal" may correspond to the transition of the retention control signal RET from the first value to the second value. In addition, in response to the phrase "receipt of a retention control signal" and equivalents, the retention control signal RET may correspond to the transition from the first value to the second value.

[0040] In one embodiment, the clock generation circuit 112 is controlled by the retention control signal RET. When the retention control signal RET indicates the standard mode, the clock generation circuit 112 actively generates the local clock signal CPI. When the retention control signal RET indicates the retention mode, the clock generation circuit 112 does not generate the local clock signal CPI. Therefore, in response to the reception of the retention control signal RET, the clock generation circuit 112 can stop generating the local clock signal CPI.

[0041] In one embodiment, when the retention control signal RET indicates the retention mode, the retention latch 108 captures and stores the current data value (or the inverted data value of the current data value) at the data output terminal Q. Because the retention latch 108 receives the auxiliary supply voltage VDDS that is not interrupted in the retention mode, the retention latch 108 continues to store the output data value during the retention mode.

[0042] In one embodiment, the interrupt circuit 114 receives the retention control signal RET. When the retention control signal RET indicates entering the retention mode, the interrupt circuit 114 interrupts the supply of the main supply voltage VDDP to the input multiplexer 110, the first latch 104, and the second latch 106. This results in reduced power consumption of the retention flip-flop 102 in the retention mode.

[0043] In one embodiment, when retention control signal RET indicates a return to the standard mode, retention latch 108 provides the retained data value to data output terminal Q. Various methods and circuits can be used to provide the retained data value from retention latch 108 to data output terminal Q when resuming the standard mode.

[0044] In one embodiment, the hold mode has a first phase and a second phase. In the first phase of the hold mode, the clock generation circuit 112 does not generate the local clock signal CPI. In the first phase of the hold mode, the interrupt circuit 114 does not supply the main supply voltage VDDP. As a result, the input multiplexer 110, the first latch 104 and the second latch 106 are all invalid in the first phase of the hold mode.

[0045] In one embodiment, in the second stage of the hold mode, the interrupt circuit 114 restores the supply of the main supply voltage VDDP. In the second stage of the hold mode, the clock generation circuit 112 does not supply the local clock signal CPI. Therefore, in the second stage of the hold mode, the first latch 104 and the second latch 106 become valid again. Because the output of the hold latch is coupled to the input of the first latch 104, during the second stage of the hold mode, the data value stored in the hold latch 108 is provided to the first latch 104. The data value is then provided from the first latch 104 to the second latch 106, and from the second latch 106 to the data output terminal Q. Therefore, the second stage of the hold mode corresponds to the preparation to restore the standard mode. During the second stage of the hold mode, the data value maintained is provided to the data output terminal Q.

[0046] Because the local clock signal CPI is not generated during the second phase of the retention mode, the input multiplexer 110 remains inoperable. In other words, if a new data value is received during the first phase or the second phase of the retention mode, the input multiplexer 110 cannot provide the newly received data value to the first latch 104 because the local clock signal CPI is invalid. This ensures that even if data values ​​are received during a portion of the retention mode, these data values ​​will not replace the retained data values ​​in the retention latch 108 and will not be provided to the data output terminal Q.

[0047] When the second stage of the retention mode is completed, the retention flip-flop 102 enters the standard mode again. In the standard mode, the local clock signal CPI is restored. This causes the input multiplexer 110 to resume supplying the newly received data input value to the first latch 104. Various other schemes, circuits and components can be used without departing from the scope of the present disclosure.

[0048] Figure 2A is a schematic diagram of a holding latch 102 according to one embodiment. Figure 2A The holding latch 102 is Figure 1 As described in more detail below, Figure 2A The retention latch 102 can effectively and efficiently switch between the standard mode and the retention mode.

[0049] The holding latch 102 includes an input multiplexer 110. The input multiplexer 110 receives a plurality of input signals. One of the input signals is coupled to a data input terminal D of the holding flip-flop 102. The other input signals are not labeled. The input multiplexer 110 receives a local clock signal CPI and a complementary local clock signal CPN. The input multiplexer 110 receives a select signal SL. The select signal SL is a control signal that determines which input is selected for providing to the output of the multiplexer 110. When the local clock signal CPI and the complementary local clock signal CPN transition, the multiplexer 110 provides the value of the selected input to the output. The voltage on the circuit node coupled to the output of the multiplexer 110 is labeled VNM and combines the Figure 3A and is described.

[0050] The holding latch 102 includes a first latch 104. The first latch 104 includes a first inverter 116 and a second inverter 118 that are cross-coupled together. The input of the first inverter 116 corresponds to the input of the first latch 104 and is coupled to the output of the multiplexer 110. The first inverter 116 includes a first PMOS transistor P1 and a first NMOS transistor N1 that are coupled together as an inverter between a main supply voltage VDDP and ground. The gate terminals of P1 and N1 correspond to the input of the first inverter 116. The common drain terminal of the transistors P1 and N1 corresponds to the output of the inverter 116. The voltage at the node corresponding to the output of the first latch 104 is labeled VM, as will be described in conjunction with Figure 3A described.

[0051] The second inverter 118 is a tri-state inverter. The second inverter 118 includes PMOS transistors P2 and P3 and NMOS transistors N2 and N3, which are coupled between the main supply voltage VDDP and the ground. The gate terminals of P2 and N3 correspond to the input of the inverter 118 and are coupled to the output of the inverter 116. The common drain terminal of transistors P3 and N2 corresponds to the output of the inverter 118 and is coupled to the input of the inverter 116. The gate terminals of transistors P3 and N2 receive CPN and CPI respectively. The second inverter 118 is a tri-state inverter because if CPN is high and CPI is low, the inverter 118 can be made inoperable.

[0052] The retention flip-flop 102 includes a transmission gate 120. The transmission gate 120 includes a PMOS transistor P4 and an NMOS transistor N4. The input of the transmission gate 120 is coupled to the output of the latch 104. The gate terminal of P4 receives CPN. The gate terminal of N4 receives CPI. If CPN is high and CPI is low, the transmission gate 120 will not pass the signal.

[0053] The retention flip-flop 102 includes a second transmission gate 121. The second transmission gate 121 includes transistors P8 and N8. The input of the transmission gate 121 is coupled to the output of the transmission gate 120. The gate terminal of N8 receives the complementary retention control signal RETN. The gate terminal of P8 receives the retention control signal RET. If RETN is low and RET is high, the transmission gate 121 will not pass the signal.

[0054] The retention flip-flop 102 includes a second latch 106. The second latch 106 includes a first inverter 122 and a second inverter 124 that are cross-coupled together. The input of the inverter 122 corresponds to the input of the latch 106 and is coupled to the output of the transmission gate 121. Therefore, the input of the latch 106 is coupled to the output of the latch 104 via the transmission gates 120 and 121. The inverter 122 includes a transistor P7 and a transistor N7 coupled between the auxiliary supply voltage VDDS and the ground. The gate terminals of P7 and N7 correspond to the input of the inverter 122. The common drain terminal of P7 and N7 corresponds to the output of the inverter 122.

[0055] Inverter 124 is a tri-state inverter and includes transistors P5, P6, N5 and N6 coupled between a main supply voltage VDDP and ground. The gate terminals of P5 and N6 correspond to the input terminals of inverter 124 and are coupled to the output terminals of inverter 122. The common drain terminal of P6 and N5 corresponds to the output of inverter 124 and is coupled between transmission gate 120 and transmission gate 121. Therefore, via transmission gate 121, the output of inverter 124 is coupled to the input of inverter 122. The gate terminals of P6 and N5 receive CPN and CPI respectively. Therefore, inverter 124 is a tri-state inverter in the sense that inverter 124 can be made inoperable if CPN is high and CPI is low. Other configurations of second latch 106 can be used without departing from the scope of the present disclosure.

[0056] The retention flip-flop 102 includes a retention latch 108. The retention latch 108 shares an inverter 122 with the second latch 106. The retention latch 108 also includes an inverter 126 cross-coupled with the latch 122. The input of the inverter 122 corresponds to the input of the retention latch 108.

[0057] Latch 126 includes transistors P9, P10, N9 and N10 coupled between an auxiliary supply voltage VDDS and ground. The gate terminals of P9 and N10 correspond to the input of inverter 126 and are coupled to the output of inverter 122. The common drain terminal of P10 and N9 corresponds to the output of inverter 126 and is coupled to the input of inverter 122. The gate terminals of P10 and N9 receive RETN and L, respectively. Inverter 126 is a three-state inverter because it can be made inoperable if RETN is high and RET is low.

[0058] The input of the holding inverter latch 108 corresponds to the holding node of the holding flip-flop 102. The voltage of the holding node is denoted as VSR, as shown in FIG. Figure 3A As described above, the inverter 122 and the inverter 126 of the holding latch 102 are both powered by the auxiliary supply voltage VDDS. Therefore, the holding latch 108 is powered by the auxiliary supply voltage VDDS.

[0059] The holding latch 102 includes a tri-state inverter 128 coupled between the holding latch 108 and the input of the first latch 104. The inverter 128 includes transistors P11, P12, N11, and N12 coupled between the main supply voltage VDDP and ground. The gate terminals of P11 and N12 correspond to the input of the inverter 128 and are coupled to the input of the holding latch 108. The common drain terminal of P12 and N11 corresponds to the output of the inverter 128 and is coupled to the input of the first latch 104. The gate terminals of P12 and N11 receive RETN and L, respectively. The inverter 128 is a tri-state inverter because the inverter 128 can be made inoperable if RETN is high and RET is low.

[0060] The retention latch 102 includes a clock generation circuit 112. The clock generation circuit 112 includes transistors P14, P15, and N14 coupled between a main supply voltage VDDP and ground. The gate terminal of transistor P14 receives a retention control signal RET. The gate terminals of P15 and N14 receive a global clock signal CP. The clock generation circuit 112 includes a transistor N15 having: a source terminal coupled to ground; a drain terminal coupled to a common drain terminal of P15 and N14; and a gate terminal receiving the retention control signal RET. The clock generation circuit 112 includes transistors P16 and N16 coupled between a main supply voltage VDDP and ground. The gate terminals of P16 and N16 are coupled to a common drain terminal of P15 and N14.

[0061] The operation of the clock generation circuit 112 will now be described. If the hold control signal RET is low and VDDP is active, transistor P14 is turned on, and transistors P15 and N14 act as inverters that output a complementary local clock signal CPN corresponding to the logical complement of the global clock signal CP (and CPI). If the hold control signal RET is low, transistor N15 is turned off. If VDDP is active, P16 and N16 act as inverters that receive the complementary local clock signal CPN and generate the local clock signal CPI as the logical complement of CPN. Therefore, if the main supply voltage VDDP is active and the hold control signal is low, the clock generation circuit is active.

[0062] However, if the hold control signal RET is high, CPN will be shorted to ground and will remain low without transitioning. If VDDP is valid, CPI will remain high without transitioning. If VDDP is disconnected, CPI may float or may remain high without transitioning. Therefore, the value of the hold control signal RET determines whether the clock generation circuit 112 will generate CPN and CPI as valid clock signals. In response to the hold control signal RET, the clock generation circuit 112 may stop generating CPN and CPI as valid clock signals.

[0063] The retention flip-flop 102 includes an inverter 130. The inverter 130 includes transistors P13 and N13 coupled between an auxiliary supply voltage VDDS and ground. The gate terminals of N13 and P13 receive a complementary retention control signal RETN. The common drain terminal of the transistors P13 and N13 generates a retention control signal RET, which is a logical complement of the complementary retention control signal RETN.

[0064] In one embodiment, the retention flip-flop 102 includes an inverter 131 and an inverter 133 coupled together in series between the input of the transmission gate 121 and the data output terminal Q. The output of the inverter 133 is coupled to the data output terminal Q.

[0065] Figure 2B-2D Corresponding to the retention flip-flop 102 in various modes of operation according to one embodiment. Figure 2B-2D Arrows are used to illustrate the signal flow within retention flip-flop 102 for the various operating modes. Figure 2B-2D A large "X" is used to illustrate the portions of retention flip-flop 102 through which signals for the various operating modes do not flow.

[0066] Figure 2B Figure 1 shows a schematic diagram of a standard mode according to one embodiment. Figure 2AIn the standard mode, the retention control signal RET is low and the complementary retention control signal RETN is high. The main supply voltage VDDP is turned on, and the clock signals CPI and CPN are valid (ie, oscillating).

[0067] Because the clock signals CPI and CPN oscillate, the multiplexer 110 transmits the data value from the data input terminal D to the input of the first latch 104. The inverter 116 of the first latch inverts the input data value and outputs the merged data value. The second inverter 118 is effective, so that the latch 104 operates. The transmission gate 120 is intermittently opened and closed with the transition of the effective clock signals CPI and CPN, thereby transmitting the inverted data value in each clock cycle. Because RET is low and RETN is high, the transmission gate 121 transmits the inverted data value to the input of the second latch 106. The inverted data value is also transmitted to the output terminal Q via the inverters 131 and 133. Therefore, in one embodiment, when being transmitted to the data output terminal, the input data value is inverted. However, in one embodiment, the holding flip-flop 102 can be constructed so that the inverted data value is inverted again before being transmitted to the data output terminal Q.

[0068] The input of latch 106 receives the inverted data value via transmission gates 120 and 121. Inverter 122 is active because it is powered by the auxiliary supply voltage VDDS. Inverter 124 is active because CPN and CPI oscillate and the main supply voltage VDDP is turned on. Holding latch 108 is inactive because tri-state latch 126 is inactive because RETN is high and RET is low. Inverter 128 is likewise inactive because RETN is high and RET is low.

[0069] exist Figure 2C , according to one embodiment, the retention flip-flop 102 has entered the first stage of the retention mode. In the first stage of the retention mode, the retention control signal RET has gone high, and the complementary retention control signal RETN has gone low. In response to the retention control signal RET going high (or in response to the complementary retention control signal RETN going low), the interrupt circuit 114 has interrupted the supply of the main supply voltage VDDP. In the case where RET is high, the clock generation circuit 112 is invalid. CPI is locked to a high value, and CPN is locked to a low value.

[0070] Because CPI and CPN are invalid, multiplexer 110 does not transmit a new data value from data input terminal D. Because the main supply voltage is low, inverters 116, 118, 124 and 128 are invalid. Transmission gate 121 does not transmit a signal because RET is high and RETN is low. Holding latch 108 is valid because the auxiliary supply voltage VDDS is not interrupted and because latch 126 is activated by RETN being low and rising to high. Therefore, the current data output value is latched at the input of holding latch 108. When entering the holding mode, voltage VSR corresponds to the data value present at data output terminal Q.

[0071] exist Figure 2D , according to one embodiment, the retention flip-flop 102 has entered the second stage of the retention mode. The second stage of the retention mode corresponds to a stage in which the retained data value is provided to the data output terminal Q, while the multiplexer 110 is still prevented from transmitting the newly received input data value. In the second stage of the retention mode, the interrupt circuit 114 has restored the supply of the main supply voltage VDDP. However, the local clock signal CPI is still invalid and is locked at a high value, while the complementary local clock signal CPN is locked at a low value.

[0072] In the second phase of the hold mode, multiplexer 110 is inactive because clock signals CPI and CPN do not oscillate. Transmission gate 120 is active. Transmission gate 121 is inactive. Inverter 116 of first latch 104 is active because main supply voltage VDDP is high. Inverter 118 is still active because CPN is high and CPI is low. Inverter 128 is active because main supply voltage is high, RETN is low and RET is high. Hold flip-flop 108 is active because RETN is low and RET is high.

[0073] The retained data value from the latch input of the retention latch 108 is transmitted to the inverter 128 and is inverted. The inverted retained data value is transmitted to the inverter 116 and is inverted back to the retained data value. The retained data value is then transmitted to the transmission gate 120 and continues to be transmitted to the data output terminal Q. In this way, during the second stage of the retention mode, the retained data value is supplied to the data output terminal Q, and the multiplexer 110 is inoperable.

[0074] Figure 3A is a diagram illustrating a method according to an embodiment of the present invention Figures 2A-2D A timing diagram 300 of signals associated with a hold flip-flop is shown. Figure 3A, the value 0 is initially stored at the data output terminal Q and is stored in the holding node VSR. Between time T0 and T1, the flip-flop 102 is in standard mode. The input data value is low and the data output value is low (but in some cases, depending on the configuration of the holding flip-flop, the data output value may be inverted for the data input value). The voltage VSR on the holding node is low. The main supply voltage VDDP is high. The local clock signal CPI oscillates and the voltage VM is low. The voltage VNM is high. The holding control signal RET is low.

[0075] At time T1, as the hold control signal RET goes high, the first stage of the hold mode is entered. This keeps CPI high and stops oscillation. This causes the main supply voltage VDDP to be interrupted (go low). At time T2, the voltage VNM dissipates to a low value. The hold latch latches the voltage VSR at a low value.

[0076] At time T3, the second phase of the hold mode is entered. The main supply voltage VDDP goes high again. This causes CPI to temporarily go low between times T4 and T5. The hold control signal RET remains high. VNM goes high. VSR and VNM remain low. For illustration purposes Figures 2A-2D As a benefit of the circuit, if the input voltage goes high at time T4, the holding voltage VSR and the voltage at the data output terminal Q remain low because the local clock signal does not oscillate, thereby preventing the input multiplexer 110 from outputting any new voltage.

[0077] At time T6, the retention control signal RET goes low, indicating that the retention mode has ended and the standard mode has started again. This causes the CPI to start oscillating again. In the case of CPI oscillation, the multiplexer 110 is effective again. This causes the high voltage value at the data input terminal D to be transmitted to the data output terminal Q and the storage node of the retention latch.

[0078] Figure 3B is a diagram illustrating a method according to an embodiment of the present invention Figures 2A-2D A timing diagram 300 of signals associated with a hold flip-flop. Figure 3B Similar to Figure 3A , except that the value 1 is initially stored at the data output terminal Q and is stored in the holding node VSR. In addition, VNM is not shown in Figure 3B Between time T0 and T1, flip-flop 102 is in standard mode. The input data value is high, and the data output value is high (although in some cases, depending on the configuration of the retention flip-flop, the data output value may be inverted for the data input value). The voltage VSR on the retention node is high. The main supply voltage VDDP is high. The local clock signal CPI oscillates, and the voltage VM is low. The retention control signal RET is low.

[0079] At time T1, as the hold control signal RET goes high, the first stage of the hold mode is entered. This keeps CPI high and stops oscillation. This causes the main supply voltage VDDP to be interrupted (go low). At time T2, the voltage VM dissipates to a low value. The hold latch latches the voltage VSR at a high value.

[0080] At time T3, the second phase of the hold mode is entered. The main supply voltage VDDP goes high again. This causes CPI to temporarily go low between times T4 and T5. The hold control signal RET remains high. VM goes high. VSR remains high. For illustration purposes Figures 2A-2D As a benefit of the circuit, if the input voltage goes low at time T4, the holding voltage VSR and the voltage at the data output terminal Q remain high because the local clock signal does not oscillate, thereby preventing the input multiplexer 110 from outputting any new voltage.

[0081] At time T6, the retention control signal RET goes low, indicating that the retention mode has ended and the standard mode has started again. This causes the CPI to start oscillating again. In the case of CPI oscillation, the multiplexer 110 is again effective. This causes the low voltage value at the data input terminal D to be transmitted to the data output terminal Q and the storage node of the retention latch.

[0082] Figure 4 is a flow chart of a method 400 for operating a hold trigger according to one embodiment. The method 400 can be used in conjunction with Figure 1-3B The method 400 includes: at 402, powering a first latch and a second latch of a retention flip-flop using a main supply voltage. At 404, the method 400 includes: powering a retention latch of the flip-flop using an auxiliary supply voltage. At 406, the method 400 includes: in response to receiving a retention control signal at the retention flip-flop, interrupting the main supply voltage. At 408, the method 400 includes: in response to receiving the retention control signal, latching an output data value of the flip-flop using the retention latch.

[0083] Figure 5 is a flow chart of a method 500 for operating a hold trigger according to one embodiment. The method 500 can be used in conjunction with Figure 1-3BThe method 500 includes: operating a retention flip-flop in a standard mode. At 504, operating in the standard mode includes: supplying a primary supply voltage to a first latch and a second latch of the retention flip-flop. At 506, operating in the standard mode includes: supplying an auxiliary supply voltage to a retention latch of the retention flip-flop. At 508, operating in the standard mode includes: generating a clock signal. At 510, the method includes: in response to receiving a retention control signal, causing the retention flip-flop to transition from the standard mode to a retention mode, the retention mode including interrupting generation of the clock signal in response to receiving the retention control signal.

[0084] An embodiment of the present disclosure provides an integrated circuit, the integrated circuit includes a retention trigger with a single retention control pin, the retention control pin enables the trigger to retain data during the retention mode without the operation of the clock. The retention trigger includes a first latch, a second latch, a retention latch and a clock generation circuit. The main supply voltage is provided to the first latch and the second latch. The auxiliary supply voltage is provided to the retention latch. The retention trigger receives a single retention control signal, which causes the trigger to transition from a standard mode to a retention mode. In the retention mode, the main supply voltage is interrupted. The clock generation circuit is also interrupted so that a clock signal is not generated during the retention phase.

[0085] In one embodiment, the clock generation circuit receives a global clock signal from a source external to the flip-flop. In a standard mode, the clock generation circuit generates a local clock signal from the global clock signal. The local clock signal controls the operation of the flip-flop. The clock generation circuit includes a control terminal for receiving a hold control signal. When the hold control signal indicates entering a hold mode, the clock generation circuit stops generating the local clock signal.

[0086] In one embodiment, the hold mode has a first stage and a second stage. In the first stage, in response to the hold control signal, the main supply voltage and the local clock signal are interrupted. In the first stage, the hold latch is activated in response to the hold control signal and captures the current output value of the trigger. In the second stage, the main supply voltage is restored, and the local clock signal remains interrupted. Because the local clock signal remains interrupted, the data input terminal of the trigger is prevented from providing the data value to the first latch. During the second stage of the hold mode, the data value stored in the hold latch (or the inverted data value of the data value stored in the hold latch) is provided to the input of the first latch. Because the first latch and the second latch are valid during the second stage, the data value stored in the hold latch is provided to the data output terminal of the trigger.

[0087] In one embodiment, when the second phase of the hold mode ends, the local clock signal is restored. This results in the flip-flop resuming its normal mode, in which the data value received at the data input terminal of the flip-flop is transferred to the data output terminal of the flip-flop.

[0088] In one embodiment, a method includes: powering a first latch and a second latch of a retention flip-flop with a main supply voltage; and powering a retention latch of the flip-flop with an auxiliary supply voltage. The method includes: interrupting the main supply voltage in response to receiving a retention control signal at the retention flip-flop; and latching an output data value of the flip-flop with the retention latch in response to receiving the retention control signal.

[0089] In one embodiment, the method includes interrupting a clock signal of the flip-flop in response to receiving a hold control signal.

[0090] In one embodiment, the method includes interrupting operation of the first latch in response to receiving a retention control signal.

[0091] In one embodiment, the first latch comprises a tri-state inverter receiving a clock signal as a control signal.

[0092] In one embodiment, interrupting operation of the first latch includes interrupting the control signal by interrupting the clock signal in response to receiving the retention control signal.

[0093] In one embodiment, the method includes: reactivating a main supply voltage when a hold control signal is present; and in response to reactivating the main supply voltage when the hold control signal is present, activating an inverter coupled between an output of the balloon latch and an input of the first latch.

[0094] In one embodiment, the method includes, after reactivating the main supply voltage and while the clock signal is interrupted, transferring the output data value from the output of the balloon latch to the output of the first latch via the inverter.

[0095] In one embodiment, the method includes reactivating the clock signal by removing the hold control signal.

[0096] In one embodiment, an integrated circuit includes a retention trigger. The retention trigger includes: a first latch configured to receive a main supply voltage; and a second latch configured to receive the main supply voltage. The retention trigger includes: a retention latch configured to receive an auxiliary supply voltage and including a first terminal, the first terminal configured to receive a retention control signal to activate the retention latch; and a clock generation circuit configured to generate a clock signal and including a second terminal, the second terminal configured to receive the retention control signal.

[0097] In one embodiment, a method includes: operating a retention flip-flop in a standard mode, including: supplying a main supply voltage to a first latch and a second latch of the retention flip-flop; supplying an auxiliary supply voltage to the retention latch of the retention flip-flop; generating a clock signal. In one embodiment, the method includes: in response to receiving a retention control signal, causing the retention flip-flop to transition from the standard mode to the retention mode. The retention mode includes interrupting the generation of the clock signal in response to receiving the retention control signal.

[0098] In one embodiment, the retention mode includes: in response to a retention control signal, interrupting the main supply voltage at least during a first phase of the retention mode; and activating a retention trigger in response to receiving the retention control signal.

[0099] In one embodiment, the method comprises: during the second phase of the holding mode, restoring the supply of the main supply voltage.

[0100] In one embodiment, the method includes, during the second phase of the retention mode, activating a tri-state inverter coupled between an output of the retention latch and an input of the first latch.

[0101] The various embodiments described above can be combined to provide additional embodiments. In view of the above detailed description, these and other changes can be made to the embodiments. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents of such claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. An integrated circuit, characterized in that: A holding trigger is included, wherein the holding trigger includes: a first latch configured to receive a main supply voltage; a second latch configured to receive a main supply voltage; a retention latch configured to receive an auxiliary supply voltage and comprising a first terminal configured to receive a retention control signal to activate the retention latch; and The clock generation circuit is configured to generate a clock signal and includes a second terminal configured to receive a retention control signal. 2 . The integrated circuit of claim 1 , wherein the clock generation circuit is configured to interrupt generation of the clock signal in response to receiving a hold control signal.

3. The integrated circuit of claim 1, wherein the retention control signal causes the retention flip-flop to transition from a standard mode to a retention mode. 4 . The integrated circuit of claim 3 , wherein supply of a main supply voltage to the first latch and the second latch is interrupted in response to a hold control signal.

5. The integrated circuit of claim 3, wherein the retention flip-flop comprises a tri-state inverter coupled between an output of the retention latch and an input of the first latch. 6 . The integrated circuit of claim 5 , wherein the tri-state inverter comprises a third terminal configured to receive a hold control signal.

7. The integrated circuit of claim 4, wherein the retention flip-flop comprises a transmission gate coupled between the first latch and the second latch, wherein the transmission gate is configured to transfer a signal from the first latch to the second latch when a retention control signal is present at the second terminal. 8 . The integrated circuit of claim 4 , wherein the first latch comprises a tri-state inverter configured to receive a clock signal as a control signal.

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