Single-chip integrated full bridge
Through the integrated full-bridge technology of a single chip, the diode is integrated on one chip, which solves the problems of complex and low power density of traditional rectified full-bridge packaging, and achieves efficient power density and cost-effectiveness.
Patent Information
- Application Number
- CN202421096645.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2034-05-20
AI Technical Summary
The packaging process of traditional rectifier full bridges is complex and the packaging body is large, resulting in reduced power density and increased cost, making it difficult to meet the high requirements of modern semiconductor devices for power density and cost-effectiveness.
Using single-chip integrated full-bridge technology, four transverse conductive diodes are integrated on one chip, and efficient utilization of chip area is achieved by optimizing the design of doped regions and the structure of the isolation layer.
It effectively reduces the packaging process steps and costs, reduces the chip usage, and has a power density of 4 times that of traditional full-bridge devices.
Smart Images
Figure CN222564255U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a single-chip integrated full bridge. Background Art
[0002] In the field of power electronic device technology, AC to DC conversion has always been an important application field. The current rectification methods include diode rectification, half-bridge rectification and full-bridge rectification.
[0003] Full-bridge rectification is a commonly used rectification method and is often used in power transmission, industrial control and other fields. The traditional full-bridge rectification is to package four diode chips into one device. The packaging process is complicated and the package body is large, resulting in a decrease in device power density and an increase in cost. As power semiconductors have higher and higher requirements for power density and cost-effectiveness, increasing the power density of full-bridge rectification has attracted more and more attention. Utility Model Content
[0004] In view of the above problems, the utility model provides a single-chip integrated full-bridge rectifier which effectively improves the power density of the full-bridge rectifier.
[0005] The technical solution of the utility model is:
[0006] A single chip integrated full bridge comprises a second isolation layer, an epitaxial wafer and a first isolation layer arranged in sequence from bottom to top;
[0007] The epitaxial wafer comprises:
[0008] A first lightly doped N region extends downward from the top surface of the second intrinsic silicon region of the epitaxial wafer; a first heavily doped N region and a first heavily doped P region are provided on the top surface of the first lightly doped N region and extend downward at intervals;
[0009] A second lightly doped N region extends downward from the top surface of the second intrinsic silicon region of the epitaxial wafer, and the lower surface is not lower than the upper surface of the oxide isolation layer; the top surface of the second lightly doped N region is provided with a second heavily doped N region and a second heavily doped P region extending downward at intervals;
[0010] A third lightly doped N region extends upward from the bottom surface of the first intrinsic silicon region of the epitaxial wafer; a third heavily doped N region and a third heavily doped P region are provided on the bottom surface of the third lightly doped N region and extend upward at intervals;
[0011] A fourth lightly doped N region extends upward from the bottom surface of the first intrinsic silicon region of the epitaxial wafer; a fourth heavily doped N region and a fourth heavily doped P region are provided on the bottom surface of the fourth lightly doped N region and extend upward at intervals;
[0012] The top surface of the first isolation layer is provided with:
[0013] a first cathode connected to the first heavily doped N region;
[0014] a first anode connected to the first heavily doped P region;
[0015] a second cathode connected to the second heavily doped N region;
[0016] a second anode connected to the second heavily doped P region;
[0017] The bottom surface of the second isolation layer is provided with:
[0018] a third cathode connected to the third heavily doped N region;
[0019] a third anode connected to the third heavily doped P region;
[0020] a fourth cathode connected to the fourth heavily doped N region;
[0021] A fourth anode is connected to the fourth heavily doped P region.
[0022] Specifically, the epitaxial wafer is an SOI epitaxial wafer, which includes, from bottom to top, a first intrinsic silicon region, an oxide isolation layer, and a second intrinsic silicon region.
[0023] Specifically, the thickness of the first intrinsic silicon region is 50-1000 um.
[0024] Specifically, the second intrinsic silicon region has a thickness of 50-1000 um.
[0025] Specifically, the oxide isolation layer has a thickness of 1-10 um.
[0026] Beneficial effects of the utility model:
[0027] The traditional full-bridge rectifier needs to package four diode chips. The packaging process is complicated and the package body is large, which results in a decrease in the power density of the device and an increase in the cost. In this case, the full-bridge rectifier chip integrates four transversely conductive diodes on one chip. The first anode and the second cathode form a metal interconnection and are connected to one end of the AC power supply. The third cathode and the fourth anode form a metal interconnection and are connected to the other end of the AC power supply. The third anode and the second anode are electrically interconnected through a package or a PCB board and are connected to one end of the load. The first cathode and the fourth cathode are electrically interconnected through a package or a PCB board and are connected to one end of the load. The first anode and the second cathode are connected to a positive voltage on one side. The current flows to the load through the first anode, the first heavily doped P region, the first lightly doped N region, the first heavily doped N region, and the first cathode. The current flows through the load into the third anode, the third heavily doped P region, the third lightly doped N region, the third heavily doped N region, the third cathode, and finally into the other end of the AC power supply. When the third cathode and one side of the fourth anode are connected to a positive voltage, the current flows to the load through the fourth anode, the fourth heavily doped P region, the fourth lightly doped N region, the fourth heavily doped N region, and the fourth cathode, and flows through the load into the second anode, the second heavily doped P region, the second lightly doped N region, the second heavily doped N region, and the second cathode, and finally into the other end of the AC power supply. The full-bridge rectifier chip in this case effectively utilizes the chip area. Using the full-bridge rectifier chip in this case only requires one chip to be packaged, and the packaging process steps and costs are reduced. Using the full-bridge rectifier chip in this case can reduce the chip usage by three quarters, and the power density is 4 times that of traditional full-bridge devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 This is a process flow chart of the utility model.
[0029] Figure 2 This is a schematic diagram of the cross-sectional structure of an SOI epitaxial wafer.
[0030] Figure 3 is a schematic diagram of the cross-sectional structure of the device in step S100,
[0031] Figure 4 is a schematic diagram of the cross-sectional structure of the device in step S200,
[0032] Figure 5 is a schematic diagram of the cross-sectional structure of the device in step S300,
[0033] Figure 6 is a schematic diagram of the cross-sectional structure of the device in step S400,
[0034] Figure 7 is a schematic diagram of the cross-sectional structure of the device in step S500,
[0035] Figure 8 is a schematic diagram of the cross-sectional structure of the device in step S600,
[0036] In the figure, 1 is the SOI epitaxial wafer, 2 is the first lightly doped N region, 3 is the second lightly doped N region, 4 is the first heavily doped N region, 5 is the second heavily doped N region, 6 is the first heavily doped P region, 7 is the second heavily doped P region, 8 is the first isolation layer, 9 is the first cathode, 10 is the second cathode, 11 is the first anode, 12 is the second anode, 13 is the third lightly doped N region, 14 is the fourth lightly doped N region, 15 is the third heavily doped N region, 16 is the fourth heavily doped N region, 17 is the third heavily doped P region, 18 is the fourth heavily doped P region, 19 is the second isolation layer, 20 is the third cathode, 21 is the fourth cathode, 22 is the third anode, 23 is the fourth anode, 24 is the first intrinsic silicon region, 25 is the oxide isolation layer, and 26 is the second intrinsic silicon region. DETAILED DESCRIPTION
[0037] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0038] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0040] The utility model is described below with reference to Figures 1-8;
[0041] A method for preparing a single-chip integrated full bridge comprises the following steps:
[0042] Step S100, in the Figure 2 A first lightly doped N region 2 and a second lightly doped N region 3 are prepared on the epitaxial wafer 1 shown;
[0043] Prepare a first heavily doped N region 4 and a first heavily doped P region 6 inside the first lightly doped N region 2;
[0044] A second heavily doped N region 5 and a second heavily doped P region 7 are prepared inside the second lightly doped N region 3; Figure 3 As shown;
[0045] Step S110, using a mask to protect the outer regions of the first lightly doped N region 2 and the second lightly doped N region 3 through a photolithography process, and forming the first lightly doped N region 2 and the second lightly doped N region 3 through a diffusion or ion implantation process;
[0046] Step S120, using a mask to protect the outer regions of the first heavily doped N region 4 and the second heavily doped N region 5 through a photolithography process, and forming the first heavily doped N region 4 and the second heavily doped N region 5 through a diffusion or ion implantation process;
[0047] Step S130 , using a mask to protect the outer regions of the first heavily doped P region 6 and the second heavily doped P region 7 through a photolithography process, and forming the first heavily doped P region 6 and the second heavily doped P region 7 through a diffusion or ion implantation process.
[0048] Correspondingly, the epitaxial wafer is an SOI epitaxial wafer, and the epitaxial wafer 1 is composed of a first intrinsic silicon region 24, an oxide isolation layer 25, and a second intrinsic silicon region 26 from bottom to top. The thickness of the epitaxial wafer is 101-2010um, the thickness of the first intrinsic silicon region 24 is 50-1000um, the thickness of the second intrinsic silicon region 26 is 50-1000um, the thickness of the oxide isolation layer 25 is 1-10um, the junction depth of the first lightly doped N region 2 is 50-1000um, the first heavily doped N region 4 and the first heavily doped P region 6 are located inside the first lightly doped N region 2, the upper surface is level with the upper surface of the epitaxial wafer 1, and the lower surface is higher than the lower surface of the first lightly doped N region 2, the junction depth is set to 1-100um, and the width is set to 1-100 um, the first heavily doped N region 4 and the first heavily doped P region 6 are not connected, and the distance between them is set to 10-500um, the junction depth of the second lightly doped N region 3 is 50-1000um, the second heavily doped N region 5 and the second heavily doped P region 7 are located inside the second lightly doped N region 3, the upper surface is level with the upper surface of the epitaxial wafer 1, and the lower surface is higher than the lower surface of the second lightly doped N region 3, the junction depth is set to 1-100um, the width is set to 1-100um, the second heavily doped N region 5 and the second heavily doped P region 7 are not connected, and the distance between them is set to 10-500um, the first lightly doped N region 2 and the second lightly doped N region 3 are not connected, and the distance is set to 10-100um, and the doping concentration of all lightly doped regions is 1e 13 .cm -3 To 1e 17 .cm -3, the doping concentration of the heavily doped region is 1e 19 .cm -3 To 1e 21 .cm -3 , the N-type doping element is phosphorus or arsenic, the P-type doping element is boron, and the relevant parameter settings are related to the device electrical design;
[0049] In this embodiment, the thickness of the epitaxial wafer 1 is 405um, the thickness of the first intrinsic silicon region 24 is 200um, the thickness of the second intrinsic silicon region 26 is 200um, the thickness of the oxide isolation layer 25 is 5um, the junction depth of the first lightly doped N region 2 and the second lightly doped N region 3 is 200um, the distance between the two is 30um, the doping element is phosphorus, and the doping concentration is 1e 14. cm -3 The width of the first heavily doped N region 4, the second heavily doped N region 5, the first heavily doped P region 6, and the second heavily doped P region 7 is 30um, the junction depth is 30um, the doping element of the first heavily doped N region 4 and the second heavily doped N region 5 is phosphorus, and the doping concentration is 2e 19 .cm -3 The doping element of the first heavily doped P region 6 and the second heavily doped P region 7 is boron, and the doping concentration is 2e 19 .cm -3 The first heavily doped N region 4 and the first heavily doped P region 6 are not connected, and the distance between them is 70um. The second heavily doped N region 5 and the second heavily doped P region 7 are not connected, and the distance between them is 70um. The first lightly doped N region 2, the second lightly doped N region 3, the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5, and the second heavily doped P region 7 are prepared by diffusion process.
[0050] Step S200, preparing a first isolation layer 8 on the epitaxial wafer 1, and opening windows at the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5, and the second heavily doped P region 7 respectively; Figure 4 As shown;
[0051] Step S210, preparing a first isolation layer 8 by chemical vapor deposition;
[0052] Step S220, through the photolithography process, use a mask to protect the external areas of the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5 and the second heavily doped P region 7, and use an etching process to open windows in the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5 and the second heavily doped P region 7.
[0053] Correspondingly, the first isolation layer 8 plays a protective role, and its material is SiO2 or Si3N4, and its thickness is set to 10-5000nm. ICP dry etching is used for window opening, and the relevant parameter settings are related to the electrical design of the device.
[0054] In this embodiment, Si3N4 is used as the first isolation layer 8, the thickness is set to 200nm, CF4 is used for ICP dry etching, the etching rate is 10nm / min to ensure the accuracy of etching, and the etching time is set to 21min to ensure successful window opening.
[0055] Step S300, preparing the corresponding first cathode 9, first anode 11, second cathode 10 and second anode 12 at the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5 and the second heavily doped P region 7 by a stripping process or an etching process; Figure 5 As shown;
[0056] Correspondingly, the first cathode 9, the first anode 11, the second cathode 10, the second anode 12 are in contact with the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5, and the second heavily doped P region 7 below to form a good ohmic contact, and their upper surfaces are level with the upper surface of the first isolation layer 8, and the first anode 11 and the second cathode 10 form a metal interconnection;
[0057] In this embodiment, a metal stripping process is used to prepare the first cathode 9, the first anode 11, the second cathode 10, and the second anode 12, and four layers of metal Al / Ti / Ni / Ag are used as ohmic contact metals. The first anode 11 and the second cathode 10 form a metal interconnection.
[0058] Step S400, preparing a third lightly doped N region 13 and a fourth lightly doped N region 14 on the epitaxial wafer 1;
[0059] A third heavily doped N region 15 and a third heavily doped P region 17 are formed inside the third lightly doped N region 13;
[0060] A fourth heavily doped N region 16 and a fourth heavily doped P region 18 are prepared inside the fourth lightly doped N region 14; Figure 6 As shown;
[0061] Step S410, using a mask to protect the outer regions of the third lightly doped N region 13 and the fourth lightly doped N region 14 through a photolithography process, and forming the third lightly doped N region 13 and the fourth lightly doped N region 14 through a diffusion or ion implantation process;
[0062] Step S420, using a mask to protect the third heavily doped N region 15 and the fourth heavily doped N region 16 and the external region through a photolithography process, and forming the third heavily doped N region 15 and the fourth heavily doped N region 16 through a diffusion or ion implantation process;
[0063] Step S430: Protect the outer regions of the third heavily doped P region 17 and the fourth heavily doped P region 18 by using a mask through a photolithography process, and form the third heavily doped P region 17 and the fourth heavily doped P region 18 by a diffusion or ion implantation process.
[0064] Correspondingly, the junction depth of the third lightly doped N region 13 is 50-1000um, the third heavily doped N region 15 and the third heavily doped P region 17 are located inside the third lightly doped N region 13, the lower surface is level with the lower surface of the epitaxial wafer 1, and the upper surface is lower than the upper surface of the third lightly doped N region 13, the junction depth is set to 1-100um, the width is set to 1-100um, the third heavily doped N region 15 and the third heavily doped P region 17 are not connected, and the distance between the two is set to 10-500um, the junction depth of the fourth lightly doped N region 14 is 50-1000um, and the fourth heavily doped The doped N region 16 and the fourth heavily doped P region 18 are located inside the fourth lightly doped N region 14, with the lower surface being level with the lower surface of the epitaxial wafer 1, and the upper surface being lower than the upper surface of the fourth lightly doped N region 14, the junction depth is set to 1-100um, the width is set to 1-100um, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 are not connected, and the distance between them is set to 10-500um, the third lightly doped N region 13 and the fourth lightly doped N region 14 are not connected, and the distance between them is set to 10-100um, and the relevant parameter settings are related to the electrical design of the device;
[0065] In this embodiment, the junction depth of the third lightly doped N region 13 and the fourth lightly doped N region 14 is 200 um, the distance between them is 30 um, the doping element is phosphorus, and the doping concentration is 1e 14. cm -3 The width of the third heavily doped N region 15, the fourth heavily doped N region 16, the third heavily doped P region 17, and the fourth heavily doped P region 18 is 30um, the junction depth is 30um, the doping element of the third heavily doped N region 15 and the fourth heavily doped N region 17 is phosphorus, and the doping concentration is 2e 19 .cm -3 The third heavily doped P region 16 and the fourth heavily doped P region 18 are doped with boron, and the doping concentration is 2e 19 .cm -3 The third heavily doped N region 15 and the third heavily doped P region 17 are not connected, and the distance between them is 70um. The fourth heavily doped N region 16 and the fourth heavily doped P region 18 are not connected, and the distance between them is 70um. The third lightly doped N region 13, the fourth lightly doped N region 14, the third heavily doped N region 15, the fourth heavily doped N region 16, the third heavily doped P region 17, and the fourth heavily doped P region 18 are prepared by diffusion process.
[0066] Step S500, preparing a second isolation layer 19 on the epitaxial wafer 1, and opening windows in the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18; Figure 7As shown;
[0067] Step S510, preparing a second isolation layer 19 by chemical vapor deposition;
[0068] In step S520, a mask is used to protect the outer regions of the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 through a photolithography process, and windows are opened in the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 through an etching process.
[0069] Correspondingly, the second isolation layer 19 plays a protective role and is made of SiO2 or Si3N4 with a thickness set to 10-5000nm. ICP dry etching is used for window opening, and the relevant parameter settings are related to the electrical design of the device.
[0070] In this embodiment, Si3N4 is used as the second isolation layer 19, the thickness is set to 200nm, CF4 is used for ICP dry etching, the etching rate is 10nm / min to ensure the accuracy of etching, and the etching time is set to 21min to ensure successful window opening.
[0071] Step S600, preparing corresponding third cathode 20, third anode 22, fourth cathode 21 and fourth anode 23 at the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 by a stripping process or an etching process, as shown in FIG. Figure 8 As shown, the entire device is prepared.
[0072] Accordingly, the third cathode 20, the third anode 22, the fourth cathode 21, and the fourth anode 23 are in contact with the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18 below to form a good ohmic contact, and the lower surface thereof is level with the lower surface of the second isolation layer 19, and the third cathode 20 and the fourth anode 23 form a metal interconnection;
[0073] In this embodiment, the third cathode 20, the third anode 22, the fourth cathode 21, and the fourth anode 23 are prepared by a metal stripping process, and four layers of metal Al / Ti / Ni / Ag are used as ohmic contact metals. The third cathode 20 and the fourth anode 23 form a metal interconnection, and the entire device is prepared.
[0074] A single chip integrated full bridge comprises a second isolation layer 19, an epitaxial wafer 1 and a first isolation layer 8 arranged in sequence from bottom to top;
[0075] The epitaxial wafer 1 comprises:
[0076] A first lightly doped N region 2 extends downward from the top surface of the second intrinsic silicon region 26 of the epitaxial wafer 1, and the lower surface thereof is not lower than the upper surface of the oxide isolation layer 25; a first heavily doped N region 4 and a first heavily doped P region 6 extending downward at intervals are provided on the top surface of the first lightly doped N region 2; the lower surfaces of the first heavily doped N region 4 and the first heavily doped P region 6 are both higher than the lower surface of the first lightly doped N region 2;
[0077] The second lightly doped N region 3 extends downward from the top surface of the second intrinsic silicon region 26 of the epitaxial wafer 1, and the lower surface is not lower than the upper surface of the oxide isolation layer 25; the second lightly doped N region 3 is spaced apart from the first lightly doped N region 2; the second lightly doped N region 3 is spaced apart from the second heavily doped N region 5 and the second heavily doped P region 7 extending downward; the lower surfaces of the second heavily doped N region 5 and the second heavily doped P region 7 are both higher than the lower surface of the second lightly doped N region 3;
[0078] That is, the first cathode 9, the first anode 11, the second cathode 10, and the second anode 12 are in contact with the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5, and the second heavily doped P region 7 below to form a good ohmic contact, and their upper surfaces are level with the upper surface of the first isolation layer 8, and the first anode 11 and the second cathode 10 form a metal interconnection.
[0079] The third lightly doped N region 13 extends upward from the bottom surface of the first intrinsic silicon region 24 of the epitaxial wafer 1, and the upper surface is not higher than the lower surface of the oxide isolation layer 25; the bottom surface of the third lightly doped N region 13 is provided with a third heavily doped N region 15 and a third heavily doped P region 17 extending upward at intervals; the upper surfaces of the third heavily doped N region 15 and the third heavily doped P region 17 are both lower than the upper surface of the third lightly doped N region 13;
[0080] A fourth lightly doped N region 14 extends upward from the bottom surface of the first intrinsic silicon region 24 of the epitaxial wafer 1, and the upper surface thereof is not higher than the lower surface of the oxide isolation layer 25; a fourth heavily doped N region 16 and a fourth heavily doped P region 18 extending upward at intervals are provided on the bottom surface of the fourth lightly doped N region 14; the upper surfaces of the fourth heavily doped N region 16 and the fourth heavily doped P region 18 are both lower than the upper surface of the third lightly doped N region 13;
[0081] The first lightly doped N region 2 and the third lightly doped N region 13 are arranged at intervals; the second lightly doped N region 3 and the fourth lightly doped N region 14 are arranged at intervals.
[0082] The top surface of the first isolation layer 8 is provided with:
[0083] A first cathode 9 connected to the first heavily doped N region 4;
[0084] A first anode 11 connected to the first heavily doped P region 6;
[0085] a second cathode 10 connected to the second heavily doped N region 5;
[0086] A second anode 12 connected to the second heavily doped P region 7;
[0087] The bottom surface of the second isolation layer 19 is provided with:
[0088] A third cathode 20 connected to the third heavily doped N region 15;
[0089] A third anode 22 connected to the third heavily doped P region 17;
[0090] a fourth cathode 21 connected to the fourth heavily doped N region 16;
[0091] The fourth anode 23 is connected to the fourth heavily doped P region 18 .
[0092] That is, the third cathode 20, the third anode 22, the fourth cathode 21, and the fourth anode 23 are in contact with the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18 above, forming a good ohmic contact, and their lower surfaces are level with the lower surface of the second isolation layer 19, and the third cathode 20 and the fourth anode 23 form a metal interconnection.
[0093] The doping concentration of the lightly doped region in this case is 1e 13 .cm -3 To 1e 17 .cm -3 , the doping concentration of the heavily doped region is 1e 19 .cm -3 To 1e 21 .cm -3 The N-type doping element is phosphorus or arsenic, and the P-type doping element is boron.
[0094] It is further defined that the epitaxial wafer 1 is an SOI epitaxial wafer, which includes, from bottom to top, a first intrinsic silicon region 24 , an oxide isolation layer 25 , and a second intrinsic silicon region 26 .
[0095] It is further defined that the thickness of the first intrinsic silicon region 24 is 50-1000 um.
[0096] It is further defined that the thickness of the second intrinsic silicon region 26 is 50-1000 um.
[0097] It is further defined that the oxide isolation layer 25 has a thickness of 1-10 um.
[0098] The utility model has the following advantages:
[0099] The traditional full-bridge rectifier needs to package four diode chips, the packaging process is complicated, and the package body is large, resulting in a decrease in device power density and an increase in cost. In this case, the full-bridge rectifier chip integrates four transversely conductive diodes on one chip, the first anode 11 and the second cathode 10 form a metal interconnection, which is connected to one end of the AC power supply, the third cathode 20 and the fourth anode 23 form a metal interconnection, and are connected to the other end of the AC power supply, the third anode 22 and the second anode 12 are electrically interconnected through packaging or a PCB board, and are connected to one end of the load, the first cathode 9 and the fourth cathode 21 are electrically interconnected through packaging or a PCB board, and are connected to one end of the load, the first anode 11 and the second cathode 10 are connected to a positive voltage on one side, and the current flows to the load through the first anode 11, the first heavily doped P region 6, the first lightly doped N region 2, the first heavily doped N region 4, and the first cathode 9, and passes through the negative The current flows into the third anode 22, the third heavily doped P region 17, the third lightly doped N region 13, the third heavily doped N region 15, the third cathode 20, and finally flows into the other end of the AC power supply. When the third cathode 20 and one side of the fourth anode 23 are connected to a positive voltage, the current flows to the load through the fourth anode 23, the fourth heavily doped P region 18, the fourth lightly doped N region 14, the fourth heavily doped N region 16, and the fourth cathode 21, and flows into the second anode 12, the second heavily doped P region 7, the second lightly doped N region 3, the second heavily doped N region 5, the second cathode 10 through the load, and finally flows into the other end of the AC power supply. The full-bridge rectifier chip in this case effectively utilizes the area of the chip. When using the full-bridge rectifier chip in this case, only one chip needs to be packaged, and the packaging process steps and costs are reduced. Using the full-bridge rectifier chip in this case can reduce the chip usage by three quarters, and the power density is 4 times that of traditional full-bridge devices.
[0100] Regarding the contents disclosed in this case, there are a few points that need to be explained:
[0101] 1. The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case, and other structures can refer to the general design;
[0102] 2. In the absence of conflict, the embodiments and features of the embodiments disclosed in this case can be combined with each other to obtain new embodiments;
[0103] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. Single chip integrated full bridge, characterized in that, It comprises a second isolation layer (19), an epitaxial wafer (1) and a first isolation layer (8) which are arranged in sequence from bottom to top; The epitaxial wafer (1) comprises: A first lightly doped N region (2) extending downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1); a first heavily doped N region (4) and a first heavily doped P region (6) extending downward at intervals are provided on the top surface of the first lightly doped N region (2); A second lightly doped N region (3) extending downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1), the lower surface of which is not lower than the upper surface of the oxide isolation layer (25); a second heavily doped N region (5) and a second heavily doped P region (7) extending downward at intervals are provided on the top surface of the second lightly doped N region (3); A third lightly doped N region (13) extends upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); a third heavily doped N region (15) and a third heavily doped P region (17) extending upward in an interval manner are provided on the bottom surface of the third lightly doped N region (13); A fourth lightly doped N region (14) extending upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); a fourth heavily doped N region (16) and a fourth heavily doped P region (18) extending upward in an interval manner are provided on the bottom surface of the fourth lightly doped N region (14); The top surface of the first isolation layer (8) is provided with: A first cathode (9) connected to the first heavily doped N region (4); A first anode (11), connected to the first heavily doped P region (6); a second cathode (10), connected to the second heavily doped N region (5); a second anode (12), connected to the second heavily doped P region (7); The bottom surface of the second isolation layer (19) is provided with: a third cathode (20), connected to the third heavily doped N region (15); a third anode (22), connected to the third heavily doped P region (17); a fourth cathode (21), connected to the fourth heavily doped N region (16); A fourth anode (23) is connected to the fourth heavily doped P region (18).
2. The single-chip integrated full bridge according to claim 1, characterized in that: The epitaxial wafer (1) is an SOI epitaxial wafer, and comprises, from bottom to top, a first intrinsic silicon region (24), an oxide isolation layer (25), and a second intrinsic silicon region (26).
3. The single-chip integrated full bridge according to claim 2, characterized in that: The first intrinsic silicon region (24) has a thickness of 50-1000 um.
4. The single-chip integrated full bridge according to claim 2, characterized in that: The second intrinsic silicon region (26) has a thickness of 50-1000 um.
5. The single-chip integrated full bridge according to claim 2, characterized in that: The oxide isolation layer (25) has a thickness of 1-10 um.