Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate with a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. Wherein the display pixels can emit light under the driving of signals provided by the signal lines, and each signal line comprises a pull-up power line and a pull-down power line. The light-emitting control circuit can respond to a light-emitting control signal provided by the light-emitting control line and control connection and disconnection between the pull-up power line or the pull-down power line and the display pixels. Thus, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the conduction duration of the pull-up power line or the pull-down power line and the display pixel, and then the light-emitting duration of the display pixel is flexibly controlled. Therefore, in the display panel, the driving flexibility for the display pixels is relatively good.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel generally includes a plurality of pixels, each pixel includes a pixel circuit and a light-emitting unit that are connected to each other, and the pixel circuit can drive the light-emitting unit to emit light, so that the display panel displays a picture.

[0003] In the related art, the pixel circuit generally includes a data writing circuit and a light-emitting driving circuit. The data writing circuit is respectively connected to the gate line, the data line and the light-emitting driving circuit, and is used to control the data line to transmit the data signal to the light-emitting driving circuit in response to the gate driving signal provided by the gate line. The light-emitting driving circuit is also respectively connected to the pull-up power line and the light-emitting unit, and is used to transmit the light-emitting driving signal to the light-emitting unit based on the data signal and the pull-up power signal provided by the pull-up power line. The light-emitting unit is also connected to the pull-down power line, and the light-emitting unit can emit light under the drive of the light-emitting driving signal and the pull-down power signal provided by the pull-down power line.

[0004] However, since both the pull-up power line and the pull-down power line will continuously provide a power signal, the pixel circuit in the related art cannot flexibly control the light-emitting duration of the light-emitting unit, and the driving flexibility is poor. Utility Model Content

[0005] Provided are a display panel and a display device, which can solve the problem in the related art that the pixel circuit cannot flexibly control the light-emitting duration of the light-emitting unit and has poor driving flexibility.

[0006] The technical solution is as follows:

[0007] In one aspect, a display panel is provided, the display panel comprising:

[0008] A substrate having a display area and a peripheral area at least partially surrounding the display area;

[0009] A plurality of display pixels arranged in an array are located in the display area, each of the display pixels comprises: a data writing circuit, a light emitting driving circuit, an external compensation circuit and a light emitting unit, the data writing circuit is respectively connected to a gate line, a data line and an input node, the external compensation circuit is respectively connected to a compensation line, a sensing line and an output node, the light emitting driving circuit is respectively connected to the input node, the output node and a pull-up power line, and the light emitting unit is respectively connected to the output node and the pull-down power line;

[0010] A plurality of groups of light-emitting control circuits are located in the peripheral area, each group of the light-emitting control circuits corresponds to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponds to a different row of display pixels, and each group of the light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction, each of the light-emitting control circuits is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line, and is used to control the on-off of the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line;

[0011] Wherein, the target power line is the pull-down power line or the pull-up power line.

[0012] Optionally, each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

[0013] Optionally, each of the light emitting control circuits comprises: an active layer, a gate metal layer and a source-drain metal layer which are located on one side of the substrate and stacked in sequence;

[0014] Each of the light emitting control circuits is switched with the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light emitting control circuits is switched with two display pixels in the same column of the two adjacent rows of display pixels through the same switching via hole.

[0015] Optionally, the thickness and width of the source and drain metal layer satisfy: I_t / (t*b)≤a;

[0016] Among them, I_t refers to the sum of pixel currents of multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; and a refers to the maximum current density resistance of the portion of the source-drain metal layer located in the transfer via.

[0017] Optionally, each group of the light emitting control circuits includes: one light emitting control circuit located at each of two sides of the at least one row of display pixels in the row direction;

[0018] Furthermore, a light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

[0019] Optionally, the light emitting control circuit comprises: a light emitting control transistor;

[0020] A gate of the light emission control transistor is connected to the light emission control line, a first electrode of the light emission control transistor is connected to the target power supply line, and a second electrode of the light emission control transistor is connected to the at least one row of display pixels.

[0021] Optionally, the light emitting control transistor is an N-type transistor.

[0022] Optionally, the light emission control transistor is a dual-gate transistor.

[0023] Optionally, the data writing circuit includes: a data writing transistor; the external compensation circuit includes: a compensation transistor; the light emitting driving circuit includes: a driving transistor;

[0024] The gate of the data writing transistor is connected to the gate line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the input node;

[0025] The gate of the compensation transistor is connected to the compensation line, the first electrode of the compensation transistor is connected to the sensing line, and the second electrode of the compensation transistor is connected to the output node;

[0026] When the target power line is the pull-up power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the transfer node, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the pull-down power line;

[0027] When the target power line is the pull-down power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the pull-up power line, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the transfer node;

[0028] The light emitting control circuit is connected to the transfer node.

[0029] Optionally, any one of the data writing transistor, the compensation transistor and the driving transistor is an N-type transistor or a P-type transistor.

[0030] Optionally, each of the display pixels further comprises: a storage capacitor;

[0031] When the driving transistor is a P-type transistor, the target power line is the pull-down power line, and the storage capacitor is connected in series between the input node and the pull-up power line;

[0032] When the driving transistor is an N-type transistor, the target power line is the pull-up power line, and the storage capacitor is connected in series between the input node and the output node.

[0033] Optionally, the display panel further includes:

[0034] A plurality of dummy pixels are located in the display area and between the plurality of rows of display pixels and the plurality of groups of light emitting control circuits.

[0035] In another aspect, a display device is provided, the display device comprising: a light emitting control driving circuit, and the display panel as described in the above aspect;

[0036] The light-emitting control driving circuit is connected to a plurality of light-emitting control lines connected to a plurality of light-emitting control circuits in the display panel, and is used to transmit light-emitting control signals to the plurality of light-emitting control lines.

[0037] Optionally, the light emitting control driving circuit is located in a peripheral area of ​​a substrate in the display panel, and the light emitting control driving circuit includes a plurality of cascaded light emitting control driving units, the plurality of light emitting control driving units are connected to the plurality of light emitting control lines in a one-to-one correspondence, and are used to transmit light emitting control signals to the plurality of light emitting control lines in sequence; or,

[0038] The light emitting control driving circuit is independent of the display panel, and the light emitting control driving circuit is used to transmit light emitting control signals to the plurality of light emitting control lines simultaneously.

[0039] In summary, the beneficial effects brought about by the technical solution provided by the present disclosure may at least include:

[0040] A display panel and a display device are provided. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power line and a pull-down power line. The light-emitting control circuit can control the on-off of the pull-up power line or the pull-down power line and the display pixels in response to the light-emitting control signal provided by the light-emitting control line. In this way, the light-emitting control signal can be flexibly set so that the light-emitting control circuit can flexibly control the duration of the conduction between the pull-up power line or the pull-down power line and the display pixels, thereby flexibly controlling the light-emitting duration of the display pixels. It can be seen from this that the display panel has good driving flexibility for the display pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0043] Figure 2 is a structural schematic diagram of a display pixel and a light emitting control circuit provided by an embodiment of the present disclosure;

[0044] Figure 3 is a structural schematic diagram of another display pixel and light emitting control circuit provided by an embodiment of the present disclosure;

[0045] Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0046] Figure 5 is a schematic diagram of a circuit structure in a display panel provided by an embodiment of the present disclosure;

[0047] Figure 6 is a schematic diagram of a circuit structure in another display panel provided by an embodiment of the present disclosure;

[0048] Figure 7 is a schematic diagram of a circuit structure in another display panel provided by an embodiment of the present disclosure;

[0049] Figure 8 is a schematic diagram of a circuit structure in another display panel provided by an embodiment of the present disclosure;

[0050] Fig. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0051] Fig.10 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0052] Fig.11 is a characteristic curve diagram of a light emitting control circuit provided by an embodiment of the present disclosure;

[0053] Fig.12 is a schematic flow chart of a method for driving a display panel provided by an embodiment of the present disclosure;

[0054] Fig.13 is a schematic diagram of a signal timing in a display panel provided by an embodiment of the present disclosure;

[0055] Fig.14 is a schematic diagram of signal timing in another display panel provided by an embodiment of the present disclosure;

[0056] Fig.15 is a schematic diagram of signal timing in another display panel provided by an embodiment of the present disclosure;

[0057] Fig.16 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0058] Fig.17 It is a schematic diagram of the structure of another display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0060] It should be noted that the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain are interchangeable, and the source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the transistors used in the embodiments of the present disclosure may include any one or a combination of P-type transistors and N-type transistors. Among them, the P-type transistor is turned on when the gate is a low voltage and is turned off when the gate is a high voltage, and the N-type transistor is turned on when the gate is a high voltage and is turned off when the gate is a low voltage. In addition, multiple signals in each embodiment correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent that the first potential or the second potential has a specific value.

[0061] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel includes: a substrate 01 having a display area AA and a peripheral area BB at least partially surrounding the display area AA.

[0062] For example, Figure 1 The display area AA shown is rectangular, and the peripheral area BB is located on the left and right sides of the display area AA, partially surrounding the display area AA. Of course, in some other embodiments, the display area AA may also be in other shapes, such as a circle; and the peripheral area BB may be located on each side of the display area AA, that is, surrounding the display area AA.

[0063] It is understandable that the display area AA can display images, while the peripheral area BB cannot display images. The peripheral area BB can also be called a non-display area. Also, the area of ​​the display area AA is generally much larger than the area of ​​the non-display area BB. The attached figure is only a schematic illustration.

[0064] Continue to refer Figure 1 The display panel further includes: a plurality of display pixels 02 arranged in an array, and the plurality of display pixels 02 are located in the display area AA. The array arrangement may refer to an arrangement in rows and columns, that is, the display panel includes a plurality of rows and columns of display pixels 02 .

[0065] exist Figure 1 Based on the reference Figure 2 It can be seen that each display pixel 02 includes: a data writing circuit 021, a light emitting driving circuit 022, an external compensation circuit 023 and a light emitting unit 024. The data writing circuit 021, the light emitting driving circuit 022 and the external compensation circuit 023 can be collectively referred to as a pixel circuit.

[0066] Among them, the data writing circuit 021 is respectively connected to the gate line Gate_A, the data line Data and the input node N1, the external compensation circuit 023 is respectively connected to the compensation line Gate_B, the sensing line SENS and the output node N2, the light-emitting driving circuit 022 is respectively connected to the input node N1, the output node N2 and the pull-up power line VDD, and the light-emitting unit 024 is respectively connected to the output node N2 and the pull-down power line VSS.

[0067] Optionally, the light emitting unit 024 may be an organic light-emitting diode (OLED). Figure 2 , the first electrode (eg, anode) of the light emitting unit 024 may be connected to the output node N2, and the second electrode (eg, cathode) of the light emitting unit 024 may be connected to the pull-down power line VSS.

[0068] The data writing circuit 021 can control the connection between the data line Data and the input node N1 in response to the gate driving signal provided by the gate line Gate_A. For example, the data writing circuit 021 can control the data line Data to be disconnected from the input node N1 when the potential of the gate driving signal is a first potential; and can control the data line Data to be connected to the input node N1 when the potential of the gate driving signal is a second potential, so that the data signal provided by the data line Data can be transmitted to the input node N1.

[0069] The light-emitting driving circuit 022 can transmit a light-emitting driving signal (e.g., pixel current) to the output node N2 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, so that the light-emitting unit 024 can emit light based on the light-emitting driving signal and the pull-down power signal provided by the pull-down power line VSS.

[0070] The external compensation circuit 023 can control the connection between the sensing line SENS and the output node N2 in response to the compensation signal provided by the compensation line Gate_B. Figure 2 It can also be seen that the sensing line SENS can be connected to the external compensation device 10. For example, the external compensation circuit 023 can control the sensing line SENS to be disconnected from the output node N2 when the potential of the compensation signal is the first potential; and can control the sensing line SENS to be connected to the output node N2 when the potential of the compensation signal is the second potential, so that the sensing line SENS transmits the reference signal provided by the external compensation device 10 to the output node N2 to reset the output node N2, or the sensing line SENS collects the potential of the output node N2 and transmits it to the external compensation device 10, so that the external compensation device 10 extracts the threshold voltage Vth of the driving transistor in the light-emitting driving circuit 022 and the pixel current transmitted from the light-emitting driving circuit 022 to the light-emitting unit 024 and other sensing signals, and externally compensates the data signal provided by the data line Data based on the extracted sensing signal to ensure that the light-emitting unit 024 can emit light reliably.

[0071] Continue to refer Figure 1 , the display panel further includes: a plurality of groups of light emitting control circuits 03Z, the plurality of groups of light emitting control circuits 03Z are located in the peripheral area BB, each group of light emitting control circuits 03Z corresponds to at least one row of display pixels 02 among the plurality of rows of display pixels 02, and each group of light emitting control circuits 03Z corresponds to a different row of display pixels 02. And, each group of light emitting control circuits 03Z includes: a light emitting control circuit 03 located at least one side of the corresponding at least one row of display pixels 02 in the row direction X. Each light emitting control circuit 03 is connected between the target power line and at least one row of display pixels 02, and is also connected to the light emitting control line EM, and is used to control the on-off of the target power line and at least one row of display pixels 02 in response to a light emitting control signal provided by the light emitting control line EM.

[0072] For example, each light-emitting control circuit 03 can control the target power line to be disconnected from at least one row of display pixels 02 when the potential of the light-emitting control signal provided by the light-emitting control line EM is a first potential; and can control the target power line to be connected to at least one row of display pixels 02 when the potential of the light-emitting control signal is a second potential, so that the power signal provided by the target power line can be transmitted to the display pixel 02, so as to drive the display pixel 02 to emit light reliably. The target power line is a pull-down power line VSS or a pull-up power line VDD. Figure 1 The target power supply line shown is the pull-up power supply line VDD.

[0073] That is, combined Figure 2 In one implementation, the target power line is the pull-up power line VDD, that is, the light-emitting driving circuit 022 in the display pixel 02 can be indirectly connected to the pull-up power line VDD through the light-emitting control circuit 03, and the connection point is also called the transfer node N3. The light-emitting control circuit 03 can control the on-off of the pull-up power line VDD and the light-emitting driving circuit 022 under the control of the light-emitting control signal provided by the light-emitting control line EM. Combined with the above-mentioned records, when the light-emitting control circuit 03 controls the pull-up power line VDD and the light-emitting driving circuit 022 to be turned on, the light-emitting driving circuit 022 can transmit the light-emitting driving signal to the first pole of the light-emitting unit 024 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, thereby driving the light-emitting unit 024 to emit light.

[0074] Or, combined Figure 3 In another implementation, the target power line may be a pull-down power line VSS, that is, the second pole of the light-emitting unit 024 in the display pixel 02 may be indirectly connected to the pull-down power line VSS through the light-emitting control circuit 03, and the connection point is also referred to as the transfer node N3. The light-emitting control circuit 03 can control the on-off of the pull-down power line VSS and the second pole of the light-emitting unit 024 under the control of the light-emitting control signal provided by the light-emitting control line EM. Combined with the above description, when the light-emitting control circuit 03 controls the pull-down power line VSS and the second pole of the light-emitting unit 024 to be turned on, the light-emitting unit 024 can emit light based on the light-emitting drive signal transmitted by the light-emitting drive circuit 022 and the pull-down power signal provided by the pull-down power line VSS.

[0075] Therefore, by flexibly setting the light control signal, the light control circuit 03 can flexibly control the duration of the pull-up power line VDD or the pull-down power line VSS to transmit the power signal to the display pixel 02, thereby achieving the purpose of flexibly controlling the light-emitting duration ratio (duty) of the light-emitting unit 024. On this basis, the display abnormality of bad smear can be effectively improved to ensure a good display effect of the display panel.

[0076] In addition, in the embodiment of the present disclosure, for the display pixel 02 with an external compensation function, the light-emitting control circuit 03 is located in the peripheral area BB rather than the display area AA, that is, the light-emitting control circuit 03 is an external / external circuit relative to the pixel circuit included in the display pixel 02. Therefore, relative to the embodiment in which the display pixel 02 is set to also include a light-emitting control circuit located in the display area AA, the solution provided by the embodiment of the present disclosure will not increase the size of the display pixel 02 (that is, pixel pitch), and will not cause the PPI of the display area AA to decrease. That is, it can also facilitate the design of a high PPI display panel. Among them, PPI (pixels per inch) refers to the number of pixels that can be set in 1 inch of the display panel, which is used to characterize the resolution.

[0077] Optionally, the first potential may refer to an invalid potential, the second potential may refer to an effective potential, and for the N-type transistors included in each circuit, the invalid potential may be a low potential relative to the effective potential; for the P-type transistors included in each circuit, the invalid potential may be a high potential relative to the effective potential.

[0078] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power line and a pull-down power line. The light-emitting control circuit can control the on-off of the pull-up power line or the pull-down power line and the display pixel in response to the light-emitting control signal provided by the light-emitting control line. In this way, the light-emitting control signal can be flexibly set so that the light-emitting control circuit can flexibly control the duration of the conduction between the pull-up power line or the pull-down power line and the display pixel, thereby flexibly controlling the light-emitting duration of the display pixel. It can be seen from this that in the display panel, the driving flexibility for the display pixel is good.

[0079] Optionally, Figure 4 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present disclosure. Figure 4 As shown, each group of light emitting control circuits 03Z may correspond to every two adjacent rows of display pixels 02 .

[0080] For example, reference Figure 4 , from top to bottom, the adjacent first row of display pixels 02 and second row of display pixels 02 can be connected to each light control circuit 03 included in the same group of light control circuits 03Z. The adjacent third row of display pixels 02 and fourth row of display pixels 02 can be connected to each light control circuit 03 included in the same group of light control circuits 03Z. And so on. In this way, not only can the wiring be facilitated, but also only a small number of light control circuits 03 need to be set, which is conducive to the narrow frame design of the display panel.

[0081] Optionally, refer to Figure 1 and Figure 4 It can also be seen that in the embodiment of the present disclosure, each group of light emitting control circuits 03Z may include: one light emitting control circuit 03 located on both sides of at least one row of display pixels 02 in the row direction X. That is, each group of light emitting control circuits 03Z may include: one light emitting control circuit 03 located on the left side of the display area AA as shown in the figure, and another light emitting control circuit 03 located on the right side of the display area AA as shown in the figure, a total of two light emitting control circuits 03.

[0082] Furthermore, a light emitting control circuit 03 located on one of the two sides can be connected to a part of the display pixels 02 in at least one row of display pixels 02, and another light emitting control circuit 03 located on the other side of the two sides can be connected to another part of the display pixels 02 in at least one row of display pixels 02 except a part of the display pixels 02.

[0083] Thus, in the row direction X, for the display pixels 02 near the left side of the display area AA and near the right side of the display area AA, the light control circuit 03 can timely control the on-off of the target power lines such as the pull-up power line VDD or the pull-down power line VSS and the display pixels 02. In addition, since the longer the line connecting the light control circuit 03 to the display pixel 02, the greater the impedance on it, which easily leads to the worse reliability of the power signal transmitted from the target power line to the display pixel 02, therefore, by arranging a light control circuit 03 on both sides of the row direction X, the length of the line connected to each light control circuit 03 can be reduced, thereby reducing the impedance on the line, and ensuring that the power signal provided by the target power line is reliably transmitted to the display pixel 02. In some embodiments, for scenarios with large impedance, it is also considered to reduce the impedance by increasing the line width, but by adopting the solution of the embodiment of the present disclosure, there is no need to increase the line width, which is conducive to the high PPI design of the display panel.

[0084] Optionally, combined Figure 2 , Figure 5 A schematic diagram of a circuit structure in a display panel is shown. Figure 6 FIG. 2 shows a schematic diagram of a circuit structure in another display panel. Figure 3 , Figure 7 A schematic diagram of a circuit structure in yet another display panel is shown. Figure 8 FIG. 2 shows a schematic diagram of a circuit structure in another display panel. Figures 5 to 8 It can be seen that the light emitting control circuit 03 may include: a light emitting control transistor M0.

[0085] The gate of the light emitting control transistor M0 can be connected to the light emitting control line EM, the first electrode of the light emitting control transistor M0 can be connected to the target power line, and the second electrode of the light emitting control transistor M0 can be connected to at least one row of display pixels 02, that is, connected to the transfer node N3. Figure 5 and Figure 6 The target power line shown in is the pull-up power line VDD; Figure 7 and Figure 8 The target power line shown in is the pull-down power line VSS.

[0086] Alternatively, if Figure 5 As shown, the light emitting control transistor M0 may be an N-type transistor. Of course, in other embodiments, such as Figures 6 to 8 As shown, the light emission control transistor M0 may be a P-type transistor.

[0087] Optionally, in the embodiment of the present disclosure, the light emission control transistor M0 may also be a dual-gate transistor, that is, the light emission control transistor M0 may have two gates.

[0088] Since the leakage current of a P-type transistor is generally large, when the light-emitting control transistor M0 is set as an N-type transistor, the leakage current of the light-emitting control transistor M0 can be reduced, ensuring reliable transmission of the power signal to the display pixel 02. In addition, when the light-emitting control transistor M0 is set as a dual-gate transistor, the threshold voltage Vth of the light-emitting control transistor M0 can be stabilized, further ensuring reliable transmission of the power signal to the display pixel 02.

[0089] Optionally, continue to refer to Figures 5 to 8 It can be seen that the data writing circuit 021 may include: a data writing transistor M1. The external compensation circuit 023 may include: a compensation transistor M2. The light emitting driving circuit 022 may include: a driving transistor M3.

[0090] A gate of the data writing transistor M1 may be connected to the gate line Gate_A, a first electrode of the data writing transistor M1 may be connected to the data line Data, and a second electrode of the data writing transistor M1 may be connected to the input node N1.

[0091] A gate of the compensation transistor M2 may be connected to the compensation line Gate_B, a first electrode of the compensation transistor M2 may be connected to the sensing line SENS, and a second electrode of the compensation transistor M2 may be connected to the output node N2.

[0092] When the target power line is the pull-up power line VDD, such as Figure 5 and Figure 6As shown, the gate of the driving transistor M3 can be connected to the input node N1, the first electrode of the driving transistor M3 can be connected to the transfer node N3, the second electrode of the driving transistor M3 can be connected to the first electrode of the light-emitting unit 024, and the second electrode of the light-emitting unit 024 can be connected to the pull-down power line VSS.

[0093] When the target power line is the pull-down power line VSS, such as Figure 7 and Figure 8 As shown, the gate of the driving transistor M3 can be connected to the input node N1, the first electrode of the driving transistor M3 can be connected to the pull-up power line VDD, the second electrode of the driving transistor M3 can be connected to the first electrode of the light-emitting unit 024, and the second electrode of the light-emitting unit 024 can be connected to the transfer node N3.

[0094] The light emitting control circuit 03 may be connected to the switching node N3. That is, in combination with the above description, the second electrode of the light emitting control transistor M0 may be connected to the display pixel 02 by being connected to the switching node N3.

[0095] Optionally, any one of the data writing transistor M1 , the compensation transistor M2 and the driving transistor M3 may be an N-type transistor or a P-type transistor.

[0096] For example, reference Figure 5 In the circuit structure shown, the data writing transistor M1, the compensation transistor M2 and the driving transistor M3 are all N-type transistors. Figure 6 In the circuit structure shown, the data writing transistor M1 is a P-type transistor, and the compensation transistor M2 and the driving transistor M3 are both N-type transistors. Figure 7 In the circuit structure shown, the data writing transistor M1 and the driving transistor M3 are both P-type transistors, and the compensation transistor M2 is an N-type transistor. Figure 8 In the circuit structure shown, the data writing transistor M1, the compensation transistor M2 and the driving transistor M3 are all P-type transistors.

[0097] Optionally, in the embodiment of the present disclosure, the material of the P-type transistor may be low temperature polysilicon (LTPS). The material of the N-type transistor may be oxide. Figure 5 The circuit structure shown can be called a full N-type oxide architecture pixel circuit. Figure 6 and Figure 7 The circuit structure shown may be referred to as a pixel circuit of a low temperature poly-silicon oxide (LTPO) architecture including both P-type transistors and N-type transistors. Figure 8The circuit structure shown can be called a full P-type LTPS architecture pixel circuit.

[0098] in, Figure 6 and Figure 7 The LTPO architecture shown takes advantage of both the low leakage current of the oxide's N-type transistor and the mobility of the LTPS's P-type transistor, and has better operating reliability.

[0099] Optionally, each transistor described in the embodiments of the present disclosure may be a metal oxide semiconductor (MOS) field effect transistor.

[0100] Optionally, refer to Figure 5 and Figure 8 It can also be seen that each display pixel 02 may further include a storage capacitor Cst. The storage capacitor Cst may be used to store signals.

[0101] When the driving transistor M3 is a P-type transistor, such as Figure 7 and Figure 8 As shown, the target power line can be the pull-down power line VSS, that is, the first electrode of the light-emitting control transistor M0 can be connected to the pull-down power line VSS, and the second electrode of the light-emitting control transistor M0 can be connected to the second electrode of the light-emitting unit 024 to the transfer node N3. And the storage capacitor Cst can be connected in series between the input node N1 and the pull-up power line VDD.

[0102] When the driving transistor M3 is an N-type transistor, such as Figure 5 and Figure 6 As shown, the target power line can be the pull-up power line VDD, that is, the first electrode of the light-emitting control transistor M0 can be connected to the pull-up power line VDD, and the second electrode of the light-emitting control transistor M0 can be connected to the first electrode of the driving transistor M3 to the transfer node N3. And the storage capacitor Cst can be connected in series between the input node N1 and the output node N2.

[0103] For the embodiment in which the driving transistor M3 is a P-type transistor, by setting the target power line as the pull-down power line VSS, that is, setting the light-emitting control transistor M0 to indirectly connect the pull-down power line VSS and the second pole of the light-emitting unit 024, while flexibly controlling the light-emitting duration, the current difference caused by the voltage drop (IR drop) at the source of the driving transistor M3 can also be reduced, ensuring that the driving transistor M3 can reliably transmit the light-emitting drive signal to the light-emitting unit 024, so as to drive the light-emitting unit 024 to reliably emit light.

[0104] Understandably, Figures 5 to 8In the circuit structure shown, the pixel circuit included in the display pixel 02 can be considered as a 3T1C structure circuit including 3 transistors and 1 storage capacitor. Of course, in some other embodiments, it can also be a 2T1C structure circuit.

[0105] Optionally, refer to Figures 5 to 8 It can also be seen that the external compensation device 10 described above can also include: a switch K1 and a switch K2.

[0106] The switch K1 may be connected between the reference signal terminal V_REF and the sensing line SENS and may be connected to the switch control terminal S_REF, and may be used to control the on / off of the reference signal terminal V_REF and the sensing line SENS in response to a switch control signal provided by the switch control terminal S_REF.

[0107] For example, the switch K1 can control the reference signal terminal V_REF and the sensing line SENS to be turned on when the potential of the switch control signal provided by the switch control terminal S_REF is a valid potential, so that the reference signal terminal V_REF transmits the reference signal described above to the output node N2 via the sensing line SENS; and can control the reference signal terminal V_REF and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_REF is an invalid potential.

[0108] The switch K2 may be connected between the test terminal VSENS and the sensing line SENS and may be connected to the switch control terminal S_SAMP, and may be used to control the on / off of the test terminal VSENS and the sensing line SENS in response to a switch control signal provided by the switch control terminal S_SAMP.

[0109] For example, the switch K2 can control the test terminal VSENS and the sensing line SENS to be turned on when the potential of the switch control signal provided by the switch control terminal S_SAMP is a valid potential, so that the test terminal VSENS collects the sensing signal recorded above through the sensing line SENS; and can control the test terminal VSENS and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_SAMP is an invalid potential.

[0110] Alternatively, if Figures 5 to 8 As shown, switch K1 and switch K2 can both be single-pole single-throw switches. For any switch, when the potential of the switch control signal received by it is a valid potential, it can be closed; when the potential of the switch control signal received by it is an invalid potential, it can be opened. Of course, in some other embodiments, switch K1 and / or switch K2 can also be the transistors described above.

[0111] Optionally, combined Figure 4 The structure shown, Fig. 9The structure of a display panel is shown. Fig. 9 It can be seen that each light emitting control circuit 03 (ie, the light emitting control transistor M0 externally mounted in the peripheral area BB) may include: an active (ACT) layer ACT1, a gate metal layer GATE1 and a source & drain (SD) metal layer SD1 located on one side of the substrate 01 and stacked in sequence.

[0112] Each light-emitting control circuit 03 can be connected to at least one row of display pixels 02 through the source-drain metal layer SD1 and the connecting via K0. Moreover, each light-emitting control circuit 03 can be connected to two display pixels 02 located in the same column in two adjacent rows of display pixels 02 through the same connecting via K0. In this way, reliable connection between the light-emitting control circuit 03 and the display pixel 02 can be ensured, and the process can be simplified to reduce the cost.

[0113] For example, for an implementation in which the target power line is the pull-up power line VDD, that is, the light emitting control transistor M0 is connected to the first electrode of the driving transistor M3 in the display pixel 02, as shown in FIG. Fig. 9 As shown, the source-drain metal layer SD1 of the light-emitting control transistor M0 can be switched to the active layer ACT1 of the driving transistor M3. That is, the active layer ACT1 of the driving transistor M3 in the adjacent up and down rows of display pixels can be switched to the source-drain metal layer SD1 of the light-emitting control transistor M0 through the same switching via K0.

[0114] For another example, for an implementation in which the target power line is the pull-down power line VSS, that is, the light-emitting control transistor M0 is connected to the second electrode of the light-emitting unit 024 in the display pixel 02, assuming that the second electrode of the light-emitting unit 024 is a cathode, it can be considered that the source-drain metal layer SD1 of the light-emitting control transistor M0 is switched to the cathode of the light-emitting unit 024. That is, the cathodes of the light-emitting units 024 in the adjacent upper and lower rows of display pixels can be switched to the source-drain metal layer SD1 of the light-emitting control transistor M0 through the same switching via K0.

[0115] In addition, reference Fig. 9 It can also be seen that the light emission control transistor M0 shown therein has two gates, and is a double-gate transistor.

[0116] Optionally, refer to Fig. 9 It can also be seen that the display panel may further include: a plurality of dummy pixels 04, which may be located in the display area AA and between the plurality of rows of display pixels 02 and the plurality of groups of light emitting control circuits 03Z (i.e., external light emitting control transistors M0). In this way, the etching uniformity during the preparation of the display panel may be ensured to be good. Optionally, in Fig. 9 Based on the layout shown, Fig.10 The structure layout including a plurality of rows of display pixels 02 is also schematically shown.

[0117] It is understandable that since the pull-up power line VDD or the pull-down power line VSS is connected to multiple display pixels 02 through a light-emitting control transistor M0 to transmit power signals to multiple display pixels 02, it is known that the on-state current of the light-emitting control transistor M0 needs to be relatively large. It is further known that the width and film thickness of the metal wiring at the switching node N3 (i.e., the wiring formed by the source and drain metal layer SD1 of the light-emitting control transistor M0) need to meet the maximum current density corresponding to the large current to reduce the problem of wiring heating.

[0118] Thus, in the embodiment of the present disclosure, the thickness and width of the source-drain metal layer SD1 of the light emitting control transistor M0 may satisfy: I_t / (t*b)≤a.

[0119] Wherein, I_t may refer to the total pixel current of the plurality of display pixels 02 connected to each light emitting control circuit 03. t may refer to the thickness of the source-drain metal layer SD1. b may refer to the width of the source-drain metal layer SD1. a may refer to the maximum current density of the portion of the source-drain metal layer SD1 located at the transfer via K0 (i.e., the transfer node N3).

[0120] Assume that the unit of I_t is microampere (μA) and the unit of a is milliampere / square micrometer (mA / μm 2 ), the unit of b is μm, and the unit of t is μm. After converting the units, it can be deduced that the wiring width b formed by the source-drain metal layer SD1 can satisfy: b≥I_t / 1000 / (t*a).

[0121] Furthermore, it can be understood that the on-state current of the light emitting control transistor M0 should also be greater than or equal to I_t, that is, the sum of the maximum currents of all display pixels controlled. In some embodiments, the on-state current of the light emitting control transistor M0 can be made larger by increasing the width-to-length ratio W / L of the light emitting control transistor M0 or the source-to-drain current Vds of the light emitting control transistor M0.

[0122] For example, assuming that the pixel current of each display pixel is Id (μA), each light emitting control transistor M0 is connected to n rows of display pixels 02 to control the target power line to transmit a power signal to the n rows of display pixels 02, and each row of display pixels 02 includes m display pixels, then I_t can satisfy: I_t=Id*n*m.

[0123] Wherein, n is an integer greater than or equal to 1 and less than the number of rows of display pixels 02 , and m is an integer greater than 1 and less than the number of columns of display pixels 02 .

[0124] Taking an OLED display product as an example, assuming that its horizontal resolution H=2000, that is, the display panel includes 2000 columns of display pixels 02, Id=150 nanoamperes (nA), a group of light-emitting control circuits 03Z includes a light-emitting control circuit 03 located on the left and right sides, and each light-emitting control circuit 03 is connected to a row of display pixels 02, that is, n=1, n=H / 2=500, then it can be calculated that: I_t=150μA. That is, the on-state current of the light-emitting control transistor M0 in each light-emitting control circuit 03 must be at least equal to 150μA.

[0125] Optionally, Fig.11 The characteristic curve diagram of the light emitting control transistor M0 under different on-state currents (eg, 1, 2.1, 4.1, etc.) is schematically shown, wherein the abscissa refers to the current and the ordinate refers to the voltage.

[0126] It is understandable that the light-emitting control transistor M0 described in the embodiment of the present disclosure is not only applicable to OLED display products in which the light-emitting unit 024 is an OLED, but also to MLED display products in which the light-emitting unit 024 is a micro light-emitting diode (MLED). Compared with OLED, the pixel current required by MLED is at the μA level, which is about 100 times larger than the pixel current required by OLED. Therefore, it can be known that the width-to-length ratio W / L of the light-emitting control transistor M0 set in the MLED display product can be much larger than the width-to-length ratio W / L of the light-emitting control transistor M0 set in the OLED display product, and a larger current needs to be provided.

[0127] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power line and a pull-down power line. The light-emitting control circuit can control the on-off of the pull-up power line or the pull-down power line and the display pixel in response to the light-emitting control signal provided by the light-emitting control line. In this way, the light-emitting control signal can be flexibly set so that the light-emitting control circuit can flexibly control the duration of the conduction between the pull-up power line or the pull-down power line and the display pixel, thereby flexibly controlling the light-emitting duration of the display pixel. It can be seen from this that in the display panel, the driving flexibility for the display pixel is good.

[0128] Fig.12 1 is a flow chart of a method for driving a display panel provided by an embodiment of the present disclosure, and the method is used to drive the display panel as described above. Fig.12 As shown, the method includes:

[0129] Step 1201, writing stage, the potential of the light emitting control signal provided by the light emitting control line is a first potential, and the light emitting control circuit controls the target power line to be disconnected from the display pixel in response to the light emitting control signal of the first potential.

[0130] Step 1202, in the light emitting stage, the potential of the light emitting control signal provided by the light emitting control line is a second potential, and the light emitting control circuit controls the target power line and the display pixel to be turned on in response to the light emitting control signal of the second potential.

[0131] The target power line is a pull-up power line connected to a light-emitting driving circuit in a display pixel, or the target power line is a pull-down power line connected to a light-emitting unit in a display pixel.

[0132] Optionally, for the multiple light control lines connected to the multiple light control circuits, in one implementation, the required light control signals may be provided to the multiple light control lines one by one, or, in another implementation, the required light control signals may be provided to the multiple light control lines uniformly. Figure 5 The structure shown, Fig.13 and Fig.14 The signal sequence diagrams in a display panel are shown respectively. Referring to the timing diagram, it can be seen that a frame period may include a display phase T1 and a sensing phase T2 that are executed in sequence, the display phase T1 may include a writing phase T11 and a light emitting phase T12 that are executed in sequence, and the sensing phase T2 may include a reset phase T21, a compensation phase T22, and an extraction phase T23 that are executed in sequence.

[0133] In the writing phase T11 , the gate line Gate_A may provide a high-potential gate driving signal, the compensation line Gate_B may provide a high-potential compensation signal, and the light-emitting control line EM may provide a low-potential light-emitting control signal. Figure 5 In the structure shown, the high potential is the effective potential, and the low potential is the invalid potential. Accordingly, the data write transistor M1 and the compensation transistor M2 can both be turned on, and the light emission control transistor M0 can be turned off. Furthermore, the data line Data can transmit a data signal to the input node N1 through the turned-on data write transistor M1 to charge the input node N1; and the sensing line SENS can transmit a reference signal to the output node N2 through the turned-on compensation transistor M2 to reset the output node N2. The storage capacitor Cst can store the data signal transmitted to the input node N1.

[0134] In the light-emitting stage T12, the gate line Gate_A can provide a low-potential gate drive signal, the compensation line Gate_B can provide a low-potential compensation signal, and the light-emitting control line EM can provide a high-potential light-emitting control signal. Correspondingly, the data writing transistor M1 and the compensation transistor M2 can both be turned off, and the light-emitting control transistor M0 can be turned on. Furthermore, the pull-up power line VDD can transmit the pull-up power signal to the transfer node N3 through the turned-on light-emitting control transistor M0, so that the light-emitting drive transistor M3 can transmit the light-emitting drive signal to the anode of the light-emitting unit 024 based on the pull-up power signal and the data signal of the input node N1, so that the light-emitting unit 024 can emit light based on the light-emitting drive signal and the pull-down power signal provided by the pull-down power line VSS connected to the cathode. The light-emitting duration is positively correlated with the duration of the high-potential light-emitting control signal. That is, the longer the duration of the high-potential light-emitting control signal, the longer the light-emitting duration of the light-emitting unit 024. Thus, flexible control of the light-emitting duration of the display pixel 02 can be achieved.

[0135] In the reset stage T21 to the extraction stage T23, the gate line Gate_A can provide a high potential gate drive signal, the compensation line Gate_B can provide a high potential compensation signal, and the light control line EM can provide a high potential light control signal. Accordingly, the data writing transistor M1, the compensation transistor M2 and the light control transistor M0 can all be turned on.

[0136] Furthermore, in the reset phase T21, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal of a valid potential (e.g., a low potential), and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal of an invalid potential (e.g., a high potential), so that the switch K1 is turned on and the switch K2 is turned off. Thus, the reference signal terminal V_REF and the sensing line SENS can be turned on, and the reference signal is transmitted to the output node N2 via the sensing line SENS and the turned-on compensation transistor M2, so as to reset the output node N2, that is, the anode of the light-emitting unit 024.

[0137] In the compensation stage T22 , in the external compensation device 10 , the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an invalid potential, and the switch control terminal S_SAMP connected to the switch K2 can also provide a switch control signal with an invalid potential, so that both the switch K1 and the switch K2 are closed.

[0138] In the extraction phase T23, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal of an invalid potential, and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal of a valid potential, so that the switch K1 is turned off and the switch K2 is turned on. In addition, the test terminal VSENS and the sensing line SENS can be connected, and the sensing line SENS can extract the signal of the output node N2 as a sensing signal and transmit it to the test terminal VSENS, so that the external compensation device 10 can perform external compensation on the data signal based on the sensing signal.

[0139] Understandably, reference Fig.14 The multiple gate lines Gate_A connected to the multiple rows of display pixels 02 can provide gate driving signals with effective potentials to the multiple rows of display pixels 02 row by row. Fig.13 In the timing sequence shown, the plurality of switch control lines EM may be switch control signals that provide effective potentials row by row, that is, the light emitting control transistors M0 connected to the display pixels 02 in each row may be turned on row by row. Fig.14 In the timing sequence shown, the multiple switch control lines EM can be a gate drive signal with an effective potential provided by the multiple gate lines Gate_A to all rows of display pixels 02, so that the data signal provided by the data line Data is written to all rows of display pixels 02, and then further uniformly provide a light-emitting control signal with an effective potential, that is, the light-emitting control transistors M0 connected to the display pixels 02 of each row can be turned on at the same time. In addition, the same as the multiple gate lines Gate_A, such as Fig.14 As shown, the multiple compensation lines Gate_B connected to the multiple rows of display pixels 02 can also provide compensation signals with effective potentials row by row to the multiple rows of display pixels 02. In the figure, the display panel including n rows of display pixels 02 is taken as an example for explanation.

[0140] Optionally, Fig.15 Also Figure 8 Taking the structure shown in the figure as an example, a signal sequence diagram in a display panel is shown. Fig.13 and Fig.14 It can be seen that, different from Figure 5 In the structure shown, since the data writing transistor M1, the compensation transistor M2 and the light emitting control transistor M0 are all P-type transistors, the effective potentials of the gate driving signal, the compensation signal and the light emitting control signal all become low potentials, and at the same time, the invalid potentials all become high potentials.

[0141] It can be understood that since the driving method has substantially the same technical effects as those of the aforementioned display panel embodiment, the technical effects of the driving method will not be repeatedly described herein for the purpose of brevity.

[0142] Fig.16 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. Fig.16As shown, the display device includes: a light emitting control driving circuit 20, and a display panel 00 as described above.

[0143] Among them, combined Figure 1 The light emitting control driving circuit 20 is connected to a plurality of light emitting control lines EM connected to a plurality of light emitting control circuits 03 in the display panel 00 , and is used to transmit light emitting control signals to the plurality of light emitting control lines EM.

[0144] Optionally, as an optional implementation, such as Fig.16 As shown, the light emitting control driving circuit 20 and the display panel 00 can be independent of each other, and the light emitting control driving circuit 20 can be used to transmit light emitting control signals to multiple light emitting control lines EM at the same time. That is, the transmission satisfies the following conditions: Fig.14 Lighting control signal with the timing shown.

[0145] For example, the light emitting control driving circuit 20 may be an external integrated circuit (IC).

[0146] Understandably, Fig.16 The display panel schematically shows a display area AA and a 3T1C pixel circuit+light-emitting unit located in the display area AA, a peripheral area BB and a light-emitting control circuit located in the peripheral area BB.

[0147] Alternatively, as another optional implementation, such as Fig.17 As shown, the light-emitting control driving circuit 20 can be located in the peripheral area BB of the substrate 01 in the display panel 00. For example, the light-emitting control driving circuit 20 can be set on the substrate 01 using the gatedriver on array (GOA) technology. Accordingly, the light-emitting control driving circuit 20 can also be called an EMGOA circuit. And the light-emitting control driving circuit 20 can include a plurality of cascaded light-emitting control driving units EM GOA, and the plurality of light-emitting control driving units EM GOA can be connected to a plurality of light-emitting control lines EM in a one-to-one correspondence, and are used to transmit light-emitting control signals to the plurality of light-emitting control lines EM in sequence. That is, the transmission satisfies the following conditions: Fig.13 Lighting control signal with the timing shown.

[0148] Understandably, Fig.17A plurality of rows of display pixels 02 located in the display area AA are also schematically shown, and each light emitting control circuit 03 can be connected to a row of display pixels 02. In addition, a power supply (Power) 30 is also shown, and the power supply 30 is connected to the light emitting control circuit 03 and the display pixel 02, respectively, and is used to supply power to the light emitting control circuit 03 and the display pixel 02. In addition, the display device may further include: a gate drive circuit located in the peripheral area BB, that is, a Gate GOA circuit, for transmitting a gate drive signal to the gate line Gate_A. The provision of the compensation signal is similar, and will not be repeated here.

[0149] Optionally, the display device can be any type of display device such as an OLED display device and an MLED display device. In addition, the display device includes any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, and virtual reality (VR). Among them, since the VR display device will produce a tail-like effect when moving at a fast speed or changing the viewing angle quickly, the two images will be reflected in the human brain at the same time, which will cause a ghosting anomaly and affect the viewing effect. In the embodiment of the present disclosure, by flexibly controlling the light emission duration, the defect of the ghosting anomaly can be effectively improved.

[0150] It should be understood that the terms used in the embodiments of the present disclosure are used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0151] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "connected" may refer to an electrical connection. The term "plurality" refers to two or more, unless otherwise expressly defined. Similarly, similar words such as "one" or "an" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0152] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: A substrate having a display area and a peripheral area at least partially surrounding the display area; A plurality of display pixels arranged in an array are located in the display area, each of the display pixels comprises: a data writing circuit, a light emitting driving circuit, an external compensation circuit and a light emitting unit, the data writing circuit is respectively connected to a gate line, a data line and an input node, the external compensation circuit is respectively connected to a compensation line, a sensing line and an output node, the light emitting driving circuit is respectively connected to the input node, the output node and a pull-up power line, and the light emitting unit is respectively connected to the output node and the pull-down power line; A plurality of groups of light-emitting control circuits are located in the peripheral area, each group of the light-emitting control circuits corresponds to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponds to a different row of display pixels, and each group of the light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction, each of the light-emitting control circuits is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line, and is used to control the on-off of the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line; Wherein, the target power line is the pull-down power line or the pull-up power line.

2. The display panel according to claim 1, characterized in that: Each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

3. The display panel according to claim 2, characterized in that: Each of the light emitting control circuits comprises: an active layer, a gate metal layer and a source-drain metal layer which are located on one side of the substrate and are stacked in sequence; Each of the light emitting control circuits is switched with the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light emitting control circuits is switched with two display pixels in the same column of the two adjacent rows of display pixels through the same switching via hole.

4. The display panel according to claim 3, characterized in that: The thickness and width of the source and drain metal layers satisfy: I_t / (t*b)≤a; Among them, I_t refers to the sum of pixel currents of multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; and a refers to the maximum current density resistance of the portion of the source-drain metal layer located in the transfer via.

5. The display panel according to any one of claims 1 to 4, characterized in that: Each group of the light emitting control circuits comprises: one light emitting control circuit located on each side of the at least one row of display pixels in the row direction; Furthermore, a light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

6. The display panel according to any one of claims 1 to 4, characterized in that: The light emitting control circuit comprises: a light emitting control transistor; A gate of the light emission control transistor is connected to the light emission control line, a first electrode of the light emission control transistor is connected to the target power supply line, and a second electrode of the light emission control transistor is connected to the at least one row of display pixels.

7. The display panel according to claim 6, characterized in that: The light emission control transistor is an N-type transistor.

8. The display panel according to claim 6, characterized in that: The light emission control transistor is a dual-gate transistor.

9. The display panel according to any one of claims 1 to 4, characterized in that: The data writing circuit includes: a data writing transistor; the external compensation circuit includes: a compensation transistor; the light emitting driving circuit includes: a driving transistor; The gate of the data writing transistor is connected to the gate line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the input node; The gate of the compensation transistor is connected to the compensation line, the first electrode of the compensation transistor is connected to the sensing line, and the second electrode of the compensation transistor is connected to the output node; When the target power line is the pull-up power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the transfer node, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the pull-down power line; When the target power line is the pull-down power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the pull-up power line, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the transfer node; The light emitting control circuit is connected to the transfer node.

10. The display panel according to claim 9, characterized in that: Any one of the data writing transistor, the compensation transistor and the driving transistor is an N-type transistor or a P-type transistor.

11. The display panel according to claim 10, characterized in that: Each of the display pixels further includes: a storage capacitor; When the driving transistor is a P-type transistor, the target power line is the pull-down power line, and the storage capacitor is connected in series between the input node and the pull-up power line; When the driving transistor is an N-type transistor, the target power line is the pull-up power line, and the storage capacitor is connected in series between the input node and the output node.

12. The display panel according to any one of claims 1 to 4, characterized in that: The display panel further includes: A plurality of dummy pixels are located in the display area and between the plurality of rows of display pixels and the plurality of groups of light emitting control circuits.

13. A display device, characterized in that: The display device comprises: a light emitting control driving circuit, and a display panel as claimed in any one of claims 1 to 12; The light-emitting control driving circuit is connected to a plurality of light-emitting control lines connected to a plurality of light-emitting control circuits in the display panel, and is used to transmit light-emitting control signals to the plurality of light-emitting control lines.

14. The display device according to claim 13, characterized in that: The light emitting control driving circuit is located in the peripheral area of ​​the substrate in the display panel, and the light emitting control driving circuit includes a plurality of cascaded light emitting control driving units, the plurality of light emitting control driving units are connected to the plurality of light emitting control lines in a one-to-one correspondence, and are used to transmit light emitting control signals to the plurality of light emitting control lines in sequence; or, The light emitting control driving circuit is independent of the display panel, and the light emitting control driving circuit is used to transmit light emitting control signals to the plurality of light emitting control lines simultaneously.

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