Storage chip power consumption testing device

Abstract

The utility model discloses a power consumption testing device for a storage chip. The power consumption testing device comprises a bearing device, a power supply, a power consumption detection device, a main controller and an upper computer, the bearing device bears to-be-tested memory chips and is provided with at least two interfaces which are electrically connected with different types of to-be-tested memory chips respectively. The power supply supplies power to the to-be-tested memory chip borne on the bearing device, and the power consumption detection device is used for detecting the power consumption of the to-be-tested memory chip borne on the bearing device; the main controller is electrically connected with the at least two interfaces and the power consumption detection device, and the upper computer is in communication connection with the main controller and is used for sending a test instruction to the main controller. In the technical scheme of the utility model, the memory chip power consumption testing device can be adapted to at least two different types of memory chips, and the main controller can monitor and obtain the power consumption data of the at least two different types of memory chips through the power consumption detection device, so that the testing requirements of the memory chips with various interfaces are met, and the testing efficiency is also improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, in particular to a storage chip power consumption test device. Background Art

[0002] Memory chips are an important part of digital chips and are used to store programs and various data. With the continuous development of computer applications, the performance requirements for memory chips are getting higher and higher. Among them, power consumption performance is a key indicator that directly affects the energy efficiency and service life of the device. Therefore, it is crucial to accurately and comprehensively test the power consumption performance of memory chips.

[0003] Most of the current memory chip power consumption test devices are composed of a test socket, a main controller, a power consumption detection device, etc., in which one test socket corresponds to a power consumption detection device. The test socket is used to place the memory chip to be tested, and the main controller is electrically connected to the test socket and the power consumption detection device, respectively. In this way, the main controller can perform read and write tests on the memory chip to be tested placed on the test socket, and at the same time can obtain the power consumption of the memory chip through the power consumption detection device.

[0004] However, traditional memory chip power consumption test solutions are usually limited to a single test socket used in conjunction with a specific interface type and a single power consumption detection device. This means that each test socket can only test memory chips with one interface type. If you need to test memory chips with different interface types, you must replace the corresponding test socket, which cannot meet the testing needs of memory chips with multiple interfaces. Utility Model Content

[0005] The main purpose of the utility model is to provide a memory chip power consumption test device, aiming to solve the problem that the existing memory chip power consumption test device cannot meet the test requirements of memory chips with multiple interfaces.

[0006] To achieve the above object, the utility model provides a memory chip power consumption test device, the memory chip power consumption test device comprising:

[0007] A carrying device, the carrying device is used to carry the memory chip to be tested, and the carrying device has at least two interfaces, and the at least two interfaces are respectively used to electrically connect with different types of memory chips to be tested;

[0008] A power supply, the power supply being electrically connected to the carrying device so as to supply power to the memory chip to be tested carried on the carrying device;

[0009] A power consumption detection device, the power consumption detection device is connected between the power supply and the carrying device, and is used to detect the power consumption of the memory chip to be tested carried on the carrying device;

[0010] A main controller, the main controller being electrically connected to the at least two interfaces and the power consumption detection device respectively;

[0011] A host computer is communicatively connected with the main controller to send a test instruction to the main controller.

[0012] In some embodiments, the carrying device includes at least two test sockets, the test sockets are used to carry the memory chip to be tested, and each of the test sockets is correspondingly provided with a type of interface, and the power consumption detection device is electrically connected to the at least two test sockets respectively.

[0013] In some embodiments, the carrier device has at least two of the following interfaces: an SPI communication interface, an ONFI communication interface, an SDIO communication interface, an eMMC communication interface, and a UFS communication interface.

[0014] In some embodiments, the carrier device has all of the following interfaces: SPI communication interface, ONFI communication interface, SDIO communication interface, eMMC communication interface, and UFS communication interface.

[0015] In some embodiments, the memory chip power consumption testing device also includes a switch control circuit, which is connected between the power consumption detection device and the at least two test sockets to control the conduction or disconnection of the circuit between the power consumption detection device and the at least two test sockets.

[0016] In some embodiments, the switch control circuit includes at least two electronically controlled switches, the number of the electronically controlled switches is the same as the number of the test sockets, and each electronically controlled switch is respectively connected between a test socket and the power consumption detection device; and / or,

[0017] The number of the power consumption detection device is one.

[0018] In some embodiments, the memory chip power consumption testing device further includes:

[0019] A heat dissipation device is electrically connected to the main controller and is used for dissipating heat from the memory chip to be tested carried on the carrying device.

[0020] In some embodiments, the carrier device includes at least two test sockets, and the heat dissipation device includes at least two heat dissipation components, each of which is used to dissipate heat for a memory chip to be tested on at least one of the test sockets.

[0021] In some embodiments, the number of the heat dissipation components is the same as the number of the test sockets, and each heat dissipation component is used to dissipate heat for a memory chip to be tested on the test socket; and / or,

[0022] The heat dissipation device is a heat dissipation fan.

[0023] In some embodiments, the main controller is an ARM Cortex-M4 processor.

[0024] In the technical solution of the utility model, a comprehensive storage chip power consumption test device is formed by combining a carrier device, a power supply, a power consumption detection device, a main controller and a host computer; the carrier device has at least two interfaces, so that the storage chip power consumption test device can adapt to at least two different types of storage chips, and at the same time, the main controller can monitor and obtain power consumption data of different types of storage chips through the power consumption detection device, which not only meets the testing requirements of storage chips with multiple interfaces, but also improves the testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a structural schematic diagram of a storage chip power consumption detection device in one embodiment of the utility model;

[0026] Figure 2 This is a structural schematic diagram of a storage chip power consumption detection device in one embodiment of the utility model;

[0027] Figure 3 This is a structural schematic diagram of a storage chip power consumption detection device in another embodiment of the utility model;

[0028] Figure 4 It is a structural schematic diagram of a storage chip power consumption detection device in another embodiment of the utility model.

[0029] Description of Figure Numbers:

[0030] 100, carrying device; 104, test socket; 200, power supply; 300, power consumption detection device; 400, main controller; 500, host computer; 600, switch control circuit; 602, electric control switch; 700, heat dissipation device.

[0031] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the scheme in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0033] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0034] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0035] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0036] See also Figure 1 , Figure 1 It is a structural schematic diagram of a storage chip power consumption detection device in one embodiment of the utility model.

[0037] This embodiment provides a memory chip power consumption detection device, the memory chip power consumption detection device comprising:

[0038] A carrier device 100, the carrier device 100 is used to carry the memory chip to be tested, and the carrier device 100 has at least two interfaces, and the at least two interfaces are respectively used to electrically connect with different types of memory chips to be tested;

[0039] A power supply 200, the power supply 200 is electrically connected to the carrier device 100, and is used to supply power to the memory chip to be tested carried on the carrier device 100;

[0040] A power consumption detection device 300, which is connected between the power supply 200 and the carrier device 100, and is used to detect the power consumption of the memory chip to be tested carried on the carrier device 100;

[0041] A main controller 400, the main controller 400 is electrically connected to at least two interfaces and the power consumption detection device 300;

[0042] The host computer 500 is connected to the main controller 400 for communication so as to send a test instruction to the main controller 400 .

[0043] In this embodiment, the carrying device 100 is used as a device for carrying the memory chip to be tested, and it has at least two interfaces, which are respectively used to electrically connect with different types of memory chips to be tested. For example, one interface can be SPI and the other can be ONFI. Such a design allows to adapt to the interface standards of different memory chips.

[0044] In this embodiment, the power supply 200 is electrically connected to the carrying device 100 to provide power to the carried memory chip to be tested, which ensures that the chip to be tested can operate normally during the power consumption test.

[0045] Generally speaking, the wider the input voltage range of the power supply 200, the stronger the adaptability. Common input voltage ranges include 5V, 12V, 24V, etc. Common output voltages include 3.3V, 5V, 12V, etc. In the process of power consumption monitoring of the memory chip, a sufficiently precise power supply 200 is required; in order to obtain a precise power supply 200, the input voltage accuracy can be adjusted through the power supply 200 management chip. The higher the adjustment accuracy, the more stable the output voltage of the chip, which is conducive to improving the accuracy of the power consumption data of the memory chip.

[0046] The power consumption detection device 300 in this embodiment is connected between the power supply 200 and the carrier 100, and is mainly used to measure the power consumption of the memory chip to be tested on the carrier 100. By monitoring the current and voltage, it can calculate the power consumption of the chip.

[0047] The basic principle of power consumption testing is to estimate the power consumption of a device by measuring the current. According to Ohm's law, the relationship between current (I) and voltage (V) is I = V / R, where R is the resistance. Therefore, if a resistor is placed in the power supply 200 circuit and the voltage difference across it is measured, the current flowing through the resistor can be obtained. By multiplying the current value by the actual voltage value, the instantaneous power consumption can be obtained. In this way, the current can be measured at different time points and the average power consumption of the entire system can be calculated.

[0048] In this embodiment, the power consumption detection device 300 is a multi-channel detection device, which has many types, for example:

[0049] 1. Multi-channel power analyzer:

[0050] This analyzer can measure multiple voltages and currents simultaneously to calculate power. For example, the PA8000 power analyzer can directly measure up to 7 voltages and currents, making it suitable for high-voltage test scenarios.

[0051] 2. Multi-channel synchronous acquisition card:

[0052] For example, a 16-channel acquisition card (DQM-16250) can simultaneously operate at a sampling rate of 200 kS / s and, in conjunction with an oscilloscope recorder, support simultaneous measurement of up to 128 channels.

[0053] 3. Oscilloscope recorder with current test kit:

[0054] This combination can perform waveform splicing for currents with a large dynamic range, thereby achieving current testing with a large dynamic range.

[0055] In summary, the working principle of these devices is based on the real-time measurement of current and voltage. Through multi-channel synchronous acquisition technology, the power consumption data of the memory chip on each test socket 104 can be accurately monitored and recorded. Power consumption tests can be performed on multiple memory chips at the same time, which improves test efficiency and accuracy. In addition, synchronous acquisition technology also allows the analysis of the cause-and-effect relationship between product components, thereby gaining a deeper understanding of the power consumption characteristics of the memory chip.

[0056] The main controller 400, in this embodiment, can use an ARM Cortex-M4 processor. In addition to the Cortex-M4, there are some similar processors, such as the ARM Cortex-M3, which was introduced before the Cortex-M4. The main difference between it and the Cortex-M4 is that it lacks a floating point unit (FPU) and some DSP extension instructions.

[0057] If performance is a concern, the ARM Cortex-M7 processor can be used. The Cortex-M7 is more powerful and has higher performance than the Cortex-M4. It has a higher DMIPS score and is suitable for applications that require higher computing power.

[0058] If you consider security and low power consumption, you can choose ARM Cortex-M23 and Cortex-M33, which are processor cores designed for security and low power consumption. Among them, Cortex-M23 is suitable for resource-constrained applications, while Cortex-M33 has more features, including security extensions, and is suitable for applications with low power consumption and high real-time requirements.

[0059] The host computer 500 is an interface between the user and the memory chip power consumption detection device. The user can send a test instruction through the host computer 500 to obtain power consumption data.

[0060] During the test process of the memory chip power consumption test device in this embodiment, firstly, it is ensured that the power supply 200 is connected to the carrier device 100, and then the entire test system is initialized. After the initialization is completed, the system automatically enters the test state; at this time, the operator can place one or two memory chips to be tested on the carrier device 100. During the placement process, it is necessary to ensure that the memory chip to be tested is correctly placed on the carrier device 100, and it is necessary to pay attention to the correct electrical connection between the pins of the memory chip to be tested and the carrier device 100 to avoid the occurrence of false connection and the like.

[0061] After placement, the main controller 400 is set up, and the main controller 400 is connected to at least two interfaces, which are electrically connected to different types of memory chips to be tested, and are electrically connected to the power consumption detection device 300 to receive power consumption data. The power consumption detection device 300 is then configured to be ready to measure the power consumption of the memory chip to be tested, and to determine the sampling rate, accuracy and measurement range.

[0062] During the read / write test, the host computer 500 communicates with the main controller 400 to transmit test instructions. The host computer 500 sends test instructions to the main controller 400, such as starting the read / write operation of the storage chip, stopping the test, etc.

[0063] In the power consumption test, after receiving the test instruction, the main controller 400 passes it to the power consumption detection device 300. The power consumption detection device 300 starts to measure the power consumption of the memory chip to be tested on the carrier 100, records the power consumption data in real time and transmits it back to the main controller 400. The main controller 400 processes and analyzes the data, removes noise interference, and obtains accurate test results (filtering, average value calculation and other methods can be used to process the data to improve the credibility and accuracy of the test results); then the main controller 400 passes the data to the host computer 500. The host computer 500 analyzes the power consumption data, calculates the average power consumption, peak power consumption, etc., and generates a power consumption test report, including test data, charts, etc. This report can be used to evaluate the power consumption performance of the memory chip. Through this process, the power consumption of the memory chip can be effectively tested to optimize the design and development process.

[0064] In the technical solution of this embodiment, in the technical solution of the utility model, a comprehensive power consumption test is formed by combining the carrier device 100, the power supply 200, the power consumption detection device 300, the main controller 400 and the host computer 500; the carrier device 100 has at least two interfaces, so that the storage chip power consumption test device can adapt to various types of storage chips, and the main controller 400 can monitor and obtain the power consumption data of at least two different types of storage chips through the power consumption detection device 300, which not only meets the testing requirements of storage chips with multiple interfaces, but also improves the testing efficiency.

[0065] See also Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a storage chip power consumption detection device in an embodiment of the utility model. Figure 2 It is a structural schematic diagram of a storage chip power consumption detection device in one embodiment of the utility model.

[0066] In this embodiment, the carrier 100 includes at least two test sockets 104 for carrying the memory chip to be tested, and each test socket 104 is provided with a corresponding type of interface, and the power consumption detection device 300 is electrically connected to the at least two test sockets 104 respectively.

[0067] In this embodiment, the carrier device 100 can correspond to different types of interfaces through a test socket 104. After the storage chip is placed, the system automatically identifies its model and switches to the corresponding interface for subsequent communication. In this way, multiple types of storage chips can be tested through a test socket 104, and there is no need to switch the corresponding model interface. Of course, in this embodiment, preferably, a similar test socket 104 can be added on this basis, which means that the power consumption of the same model or different models of storage chips can be detected at the same time, which greatly improves the test efficiency and is very suitable for batch testing.

[0068] See also Figure 3 , Figure 3 It is a structural schematic diagram of a storage chip power consumption detection device in another embodiment of the utility model.

[0069] In this embodiment, the carrier device 100 has at least two of the following interfaces: an SPI communication interface, an ONFI communication interface, an SDIO communication interface, an eMMC communication interface, and a UFS communication interface.

[0070] In this embodiment, the carrier device 100 only needs to have at least two of the SPI communication interface, ONFI communication interface, SDIO communication interface, eMMC communication interface, and UFS communication interface. For example, it can be an SPI communication interface, an ONFI communication interface, or a combination of an SDIO communication interface, an eMMC communication interface, and the like. There is no special limitation here. In this way, power consumption detection can be performed on at least two storage chips of the same model or different models at the same time, which greatly improves the test efficiency.

[0071] Continue reading Figure 3In this embodiment, the carrier device 100 has all the following interfaces: SPI communication interface, ONFI communication interface, SDIO communication interface, eMMC communication interface, and UFS communication interface. It should be noted that the communication interface in this embodiment may also include NAND Flash, NOR Flash, Serial Flash, MicroSD card, etc.

[0072] In this embodiment, the carrier device 100 may have a test socket 104, and the test socket 104 has an SPI communication interface, an ONFI communication interface, an SDIO communication interface, an eMMC communication interface, and a UFS communication interface. That is, one test socket 104 can test multiple types of storage chips, and the switching of the communication interface can be automatically detected and switched by the system.

[0073] In some embodiments, the number of test sockets 104 of the carrier device 100 may correspond to the communication interface. For example, if the carrier device 100 has all interfaces such as SPI communication interface, ONFI communication interface, SDIO communication interface, eMMC communication interface, and UFS communication interface, then the number of test sockets 104 corresponds to five or more. In this way, each test socket 104 corresponds to a type of interface. In this design, each test socket 104 of the carrier device 100 corresponds to a specific communication interface, which means that each memory chip has a dedicated location and interface for testing. For example, if there is a test socket 104 with an SPI interface, it will be specifically used to test memory chips with SPI interfaces. Similarly, the test sockets 104 of ONFI, SDIO, eMMC, and UFS interfaces will be used to test memory chips with corresponding interfaces, respectively.

[0074] Each memory chip of each interface type has a dedicated test socket 104, which can test multiple types of chips at the same time, thereby improving test efficiency. By providing multiple communication interfaces, the carrier device 100 can be compatible with multiple memory chip standards, reducing the need for additional adapters. The dedicated test socket 104 ensures the accuracy of the interface connection and reduces the possibility of test errors. Testers can quickly select the appropriate test socket 104 according to the interface type of the memory chip, thereby simplifying the test process.

[0075] If new memory chip interface standards emerge in the future, the function of the carrier 100 can be expanded by adding a new test socket 104, providing a flexible, efficient and accurate memory chip power consumption test platform that can adapt to diverse memory chip testing needs and provide support for future technological development.

[0076] See also Figure 3 and Figure 4 , Figure 3This is a schematic diagram of the structure of a storage chip power consumption detection device in another embodiment of the utility model. Figure 4 It is a structural schematic diagram of a storage chip power consumption detection device in another embodiment of the utility model.

[0077] In this embodiment, the memory chip power consumption testing device also includes a switch control circuit 600, which is connected between the power consumption detection device 300 and at least two test sockets 104 to control the conduction or disconnection of the circuit between the power consumption detection device 300 and at least two test sockets 104.

[0078] In this embodiment, the switch control circuit 600 is a component for controlling the conduction or disconnection of the circuit between the power consumption detection device 300 and at least two test sockets 104. It can be set to be controlled simultaneously or individually according to actual test needs; for example, two different types of memory chips may have different test times. When testing memory chips of different models, the test time of each chip may be different. The switch control circuit 600 can control the power supply 200 of each test socket 104 individually, allowing individual power failure. In this way, once the test of a certain memory chip is completed, it can be immediately removed and replaced with another memory chip to be tested without affecting other chips being tested.

[0079] When the memory chips on all the test sockets 104 are of the same type, their test times will be roughly the same. In this case, the switch control circuit 600 can be set to control simultaneously, and the power supplies 200 of all the test sockets 104 can be controlled simultaneously to achieve synchronous on or off. This can simplify the operation process and improve the efficiency of the test process.

[0080] In this embodiment, the switch control circuit 600 is used to turn on and off the power supplies 200 of at least two test sockets 104 simultaneously or individually, and the power supply 200 control can be flexibly adjusted according to the test requirements, reducing the waiting time and improving the efficiency of the overall test process. Among them, through the individual control function, the utilization rate of the test socket 104 can be maximized, and idle time can be avoided, thereby optimizing resource utilization, and multiple types of memory chips can be tested at the same time, providing greater test flexibility and adaptability. This control mechanism provides a basis for further automating the test process, helps to reduce human operation errors, and ensures the accuracy and consistency of the test.

[0081] In summary, the design of the switch control circuit 600 not only improves the flexibility and efficiency of the test process, but also provides the possibility for future automation and optimization, thereby enhancing the overall performance and practical value of the memory chip power consumption test device.

[0082] Continue reading Figure 4In this embodiment, the switch control circuit 600 includes at least two electronically controlled switches 602, the number of the electronically controlled switches 602 is the same as the number of the test sockets 104, and each electronically controlled switch 602 is connected between a test socket 104 and the power consumption detection device 300; and / or,

[0083] The number of the power consumption detection device 300 is one.

[0084] In this embodiment, the switch control circuit 600 implements the principle of individual or simultaneous control, mainly by setting at least two electric control switches 602 to simultaneously or individually control the on and off of the power supplies 200 of at least two test sockets 104. Of course, two electric control switches 602 can also control multiple test sockets 104 respectively. In this embodiment, it is preferred that the number of electric control switches 602 corresponds to the number of test sockets 104, that is, one electric control switch 602 controls the on and off of the power supply 200 of one test socket 104, and can switch between individual control mode or simultaneous control mode to maximize the utilization rate of the test socket 104, avoid idle time, and thus optimize resource utilization.

[0085] Among them, the electronically controlled switch 602 is a device for on-off control, and there are many types, such as relays, crystal optical switches, solid-state relays, etc. Among them, the relay is an electromagnetic switch, and when the input current reaches a certain threshold, it will be closed or disconnected (it should be noted that the relay has normally open and long closed terminals, and the terminals should be connected accordingly when selecting different control strategies). The transistor controls the conduction and disconnection between the collector and the emitter by controlling the base current, and it is mainly suitable for low power consumption and fast switching applications. A solid-state relay is a switch without mechanical moving parts, using photoelectric coupling and semiconductor switching elements. The solid-state relay can provide fast response and high reliability, and is suitable for high-frequency operating environments.

[0086] In summary, when selecting the electronically controlled switch 602, it is necessary to consider the specific requirements of the test device, such as current, voltage, switching speed and reliability, etc. These devices can realize independent or simultaneous control of multiple test sockets 104 through the control circuit, thereby improving the flexibility and efficiency of the test device.

[0087] In this embodiment, a multi-channel power consumption detection device 300 is used to simultaneously monitor the power consumption data of the storage chips on multiple test sockets 104, which reduces the time required to test each chip separately. At the same time, the need to purchase multiple single-channel detection devices is reduced, reducing the equipment cost. In terms of data consistency, since the same device is used for testing, the consistency and comparability of data collection can be ensured.

[0088] Continue reading Figure 4 In this embodiment, the memory chip power consumption test device further includes:

[0089] The heat dissipation device 700 is electrically connected to the main controller 400 to dissipate heat for the memory chip to be tested carried on the carrying device 100 .

[0090] In this embodiment, the heat sink 700 is mainly used to dissipate heat and cool down the memory chip during the test process, wherein the heat sink 700 can be divided into passive heat sinks, active heat sinks and hybrid heat sinks; passive heat sinks rely on natural convection to dissipate heat and do not require an external power supply 200 or a control system, while active heat sinks use power devices such as fans or liquid pumps to enhance the heat dissipation effect. The hybrid heat sink combines the characteristics of passive and active heat sinks and automatically adjusts the cooling capacity according to temperature requirements.

[0091] In this embodiment, the working principle and function of the heat sink in the memory chip power consumption test is to electrically connect the heat sink 700 to the main controller 400, and use the heat dissipation capacity of the heat sink 700 to reduce the heat generated by the memory chip during the test. This is because the chip generates heat when working. If there is too much heat, it will affect the performance and life of the chip. The heat sink transfers heat to the surrounding environment through heat conduction, convection heat transfer and thermal radiation, thereby keeping the operating temperature of the chip within a safe range.

[0092] In this embodiment, the heat sink 700 is used to dissipate heat and cool the memory chip under test, ensuring that the surface temperature of the memory chip is always infinitely close to room temperature during the power consumption measurement of the memory chip, thereby achieving accurate measurement and control of the power consumption of the memory chip.

[0093] Continue reading Figure 4 In this embodiment, the carrier device 100 includes at least two test sockets 104 , and the heat dissipation device 700 includes at least two heat dissipation components, each of which is used to dissipate heat for a memory chip to be tested on at least one test socket 104 .

[0094] In this embodiment, in the memory chip power consumption test device, the main purpose of providing at least two test sockets 104 is to improve the test efficiency. Such a design allows multiple memory chips to be tested at the same time, thereby saving time and improving overall work efficiency. In addition, such a configuration can also collect more data within a test cycle, which helps to identify and solve potential problems more quickly.

[0095] Correspondingly, one heat dissipation component can dissipate heat and cool down two test sockets 104 , which can save costs and control temperature changes during the memory chip testing process.

[0096] Further, the number of heat dissipation components is the same as the number of test sockets 104, and each heat dissipation component is used to dissipate heat for a memory chip to be tested on a test socket 104; and / or,

[0097] The heat dissipation device 700 is a heat dissipation fan.

[0098] In this embodiment, the heat dissipation component is used as a component for dissipating heat from the memory chip to be tested on the test socket 104 , and it may be a heat dissipation fan.

[0099] Of course, in some embodiments, a heat dissipation fan can be used in conjunction with a semiconductor heat dissipation device 700. The semiconductor heat dissipation device 700 is usually composed of an N-type semiconductor and a P-type semiconductor, which are respectively connected to two metal sheets to form a closed loop. This structure utilizes the Peltier effect, that is, when current passes through such a semiconductor loop, heat absorption and heat release phenomena will occur at different joints, thereby achieving the purpose of heat dissipation or cooling.

[0100] The use of a cooling fan in conjunction with the semiconductor cooling device 700 can bring multiple benefits. The cooling fan can provide additional air flow, enhance the cooling effect of the semiconductor cooling device 700, improve the heat dissipation efficiency, and prevent the temperature of the memory chip from being too high during the test process.

[0101] In this embodiment, each test socket 104 is equipped with at least one heat sink 700. Such a design ensures that each memory chip to be tested can be effectively cooled. Since the memory chip may generate a large amount of heat during the test process, proper heat dissipation is necessary to prevent the chip from overheating and ensure the accuracy of the test and the stability of the chip. At the same time, this also helps to simulate the heat dissipation conditions in the actual working environment, thereby obtaining more realistic test results.

[0102] In general, the one-to-one configuration of the test socket 104 and the heat sink 700 can more accurately control the temperature of each memory chip during the test, which is very important for maintaining the test accuracy and the quality of the memory chip. This design can also reduce the risk of memory chip damage caused by overheating, extend the service life of the memory chip, and thus provide users with more reliable products.

[0103] Continue reading Figure 4In this embodiment, the main controller 400 is an ARM Cortex-M4 processor. The ARM Cortex-M4 processor has the characteristics of low power consumption and high performance. Its power consumption is usually less than 200uA / MHz. The Cortex-M4 provides a performance of 3CoreMark / MHz, which means that it can quickly process test data and improve the efficiency of the test process. At the same time, the Cortex-M4 supports up to 240 vector interrupts and 8 to 256 interrupt priorities, and the interrupt waiting time is short, only 12 cycles. This fast response capability is crucial for real-time power consumption testing, which can ensure that power consumption changes are captured immediately when the state of the memory chip changes.

[0104] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A memory chip power consumption test device, characterized in that: include: A carrying device, the carrying device is used to carry the memory chip to be tested, and the carrying device has at least two interfaces, and the at least two interfaces are respectively used to electrically connect with different types of memory chips to be tested; A power supply, the power supply being electrically connected to the carrying device so as to supply power to the memory chip to be tested carried on the carrying device; A power consumption detection device, the power consumption detection device is connected between the power supply and the carrying device, and is used to detect the power consumption of the memory chip to be tested carried on the carrying device; A main controller, the main controller being electrically connected to the at least two interfaces and the power consumption detection device respectively; A host computer is communicatively connected with the main controller to send a test instruction to the main controller.

2. The memory chip power consumption test device according to claim 1, characterized in that: The carrying device comprises at least two test sockets, the test sockets are used to carry the memory chip to be tested, and each of the test sockets is correspondingly provided with a type of interface, and the power consumption detection device is electrically connected to the at least two test sockets respectively.

3. The memory chip power consumption test device according to claim 2, characterized in that: The carrier device has at least two of the following interfaces: an SPI communication interface, an ONFI communication interface, an SDIO communication interface, an eMMC communication interface, and a UFS communication interface.

4. The memory chip power consumption test device according to claim 3, characterized in that: The carrier device has all of the following interfaces: SPI communication interface, ONFI communication interface, SDIO communication interface, eMMC communication interface, and UFS communication interface.

5. The memory chip power consumption test device according to claim 2, characterized in that: The memory chip power consumption testing device also includes a switch control circuit, which is connected between the power consumption detection device and the at least two test sockets to control the conduction or disconnection of the circuit between the power consumption detection device and the at least two test sockets.

6. The memory chip power consumption test device according to claim 5, characterized in that: The switch control circuit includes at least two electronically controlled switches, the number of the electronically controlled switches is the same as the number of the test sockets, and each electronically controlled switch is respectively connected between a test socket and the power consumption detection device; and / or, The number of the power consumption detection device is one.

7. The memory chip power consumption test device according to any one of claims 1 to 6, characterized in that: Also includes: A heat dissipation device is electrically connected to the main controller and is used for dissipating heat from the memory chip to be tested carried on the carrying device.

8. The memory chip power consumption test device according to claim 7, characterized in that: The carrying device includes at least two test sockets, and the heat dissipation device includes at least two heat dissipation components, each of which is used to dissipate heat for a memory chip to be tested on at least one of the test sockets.

9. The memory chip power consumption test device according to claim 8, characterized in that: The number of the heat dissipation components is the same as the number of the test sockets, and each heat dissipation component is used to dissipate heat for a memory chip to be tested on the test socket; and / or, The heat dissipation device is a heat dissipation fan.

10. The memory chip power consumption test device according to any one of claims 1 to 6, characterized in that: The main controller is an ARM Cortex-M4 processor.

Images