Wafer-level chip packaging structure with front protection
By pressing a layer of ABF film on the front of the semiconductor chip and forming an open groove on the surface of the chip, the problem of reliability and risk of rupture in the temperature and humidity sensitive chip during the packaging process is solved, and higher waterproof vapor intrusion ability and chip stability are achieved.
Patent Information
- Application Number
- CN202420816705.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-04-18
AI Technical Summary
Existing semiconductor packaging technologies are difficult to effectively protect temperature-humidity-sensitive chips, resulting in risks such as reliability failure and insulating layer fragmentation.
The packaging structure is adopted with a layer of ABF film pressed on the front of the chip. By forming the ABF film on the front of the product, the resistance to water vapor intrusion is improved, and open grooves are formed on the surface of the chip to relieve stress.
Effectively protect chips, especially temperature- and humidity-sensitive products, reduce the risk of rupture, improve the reliability of the chip, and enhance the resistance to water vapor intrusion.
Smart Images
Figure CN222600963U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a wafer-level chip packaging structure with front protection. Background Art
[0002] In the current semiconductor industry, electronic packaging has become an important aspect of industry development. Decades of development in packaging technology have made high-density, small-size packaging requirements the mainstream direction of packaging. Fan-out wafer-level packaging is an embedded package processed at the wafer level. It is also a major advanced packaging process with a large number of I / Os and good integration flexibility. With the continuous development of advanced packaging technology, the reliability requirements for products are also getting higher and higher.
[0003] In today's packaging field, in order to meet the functional requirements of semiconductor electronic products, there are strict packaging and testing requirements for products. Some chips that are sensitive to temperature and humidity are prone to risks such as reliability failure and insulation layer cracking. In order to enhance chip stability and achieve better performance, it is now a major research and development project for semiconductor manufacturers. Utility Model Content
[0004] In order to solve the above problems, the utility model provides a wafer-level chip packaging structure with front protection, which can effectively protect the chip, especially for products sensitive to temperature and humidity, relieve stress, reduce the risk of cracking, and increase chip reliability.
[0005] According to one aspect of the utility model, a wafer-level chip packaging structure with front protection is provided, including a chip, a welding area is provided on the front of the chip, a passivation layer is covered on the front of the chip, a first PI layer is covered on the passivation layer, an opening is formed on the passivation layer and the first PI layer to expose the welding area, a metal bump is provided on the first PI layer, a seed layer is provided at the bottom of the metal bump and is embedded in the opening to interconnect with the welding area, an ABF film is coated on the front of the chip, the ABF film surrounds the metal bump and exposes the top of the metal bump, and the ABF film is coated on the side of the chip packaging structure to the front of the chip. As a result, the wafer-level chip packaging structure has a layer of ABF film pressed on the front of the product, which can improve the ability to resist water vapor intrusion during operation and protect products that are sensitive to temperature and humidity.
[0006] In some embodiments, the chip packaging structure further includes a redistribution layer, the redistribution layer includes a metal layer and a second PI layer, the metal layer is located on the first PI layer, a seed layer is provided at the bottom of the metal layer and is embedded in the opening of the first PI layer and interconnected with the welding area, the second PI layer covers the first PI layer and covers the metal layer, an opening is formed on the second PI layer to expose the metal layer, the bottom of the metal bump is embedded in the opening on the second PI layer, and the metal bump is interconnected with the metal layer through the seed layer at the bottom, and the ABF film is located on the second PI layer and surrounds the metal bump and exposes the top of the metal bump. Therefore, for a chip packaging structure with a redistribution layer, a layer of ABF film can also be formed on the front of the product to improve the resistance to water vapor intrusion.
[0007] In some embodiments, the metal layer and the second PI layer have the same number of layers, and the metal layer and the second PI layer are provided with multiple layers, the multiple metal layers and the second PI layer are stacked and interconnection lines are formed between the metal layers, the bottom metal layer is interconnected with the welding area through the bottom seed layer, the bottom of the metal bump is embedded in the opening of the top second PI layer, and is interconnected with the top metal layer through the bottom seed layer, and the ABF film is located on the top second PI layer and surrounds the metal bump and exposes the top of the metal bump. Therefore, in practical applications, the redistribution layer can be a simple single-layer metal layer and PI layer structure, or a complex multi-layer metal layer and PI layer structure, both of which can improve the resistance to water vapor intrusion through the ABF film coated on the front of the chip.
[0008] In some embodiments, the chip and each packaging layer packaged on the surface of the chip are provided with an open groove, the bottom of the open groove extends to the inside of the chip and does not penetrate the chip, the center of the open groove is at the same position as the center of the designed scribing road, and the open groove is wider than the scribing road, the bottom of the ABF film is filled into the open groove, and the ABF film in the formed chip packaging structure covers each packaging layer on the front of the chip, and wraps the side of each packaging layer of the chip and the open groove of the chip. Therefore, before the ABF film is formed, the chip and each packaging layer on its surface are first grooved to form an open groove, which can relieve stress, and after the product packaging is completed, the risk of cracking can be reduced and the reliability of the chip can be increased; the bottom of the open groove is opened to the inside of the wafer of the chip, and the open groove is located at the position of the scribing road and is wider than the scribing road. After the ABF film is formed, when it is cut into a single chip, the ABF film filled in the open groove extends to the layer where the chip is located, and the ABF film can completely cover each packaging layer on the front of the chip and wrap around the layer where the chip is located, which can protect the bottom line from external factors, and the ability to resist water vapor intrusion is further improved.
[0009] In some embodiments, each packaging layer on the surface of the chip is provided with an open groove, the bottom of the open groove extends to the surface of the chip, the center of the open groove is at the same position as the center of the designed scribing road, and the open groove is wider than the scribing road, the bottom of the ABF film is filled into the open groove, and the ABF film in the formed chip packaging structure covers each packaging layer on the front of the chip and wraps the side of each packaging layer of the chip. Therefore, before the ABF film is formed, the chip packaging structure is grooved on each packaging layer above the chip to form an open groove, which can relieve stress, reduce the risk of cracking after the product packaging is completed, increase the reliability of the chip, completely cover each packaging layer on the front of the chip and the surroundings of each packaging layer, and improve the ability to resist water vapor intrusion.
[0010] Compared with the prior art, the beneficial effects of the utility model are as follows: the wafer-level chip packaging structure provided by the utility model protects the product by pressing a layer of ABF film on the front of the product, especially plays a good protective role on products that are sensitive to temperature and humidity. The packaging layers and / or chip wafers on the chip are first grooved, and then the ABF film is formed. This process is conducive to relieving stress, reducing the risk of product breakage after packaging, and increasing chip reliability. When the groove depth reaches the layer where the chip wafer is located, the single chip after segmentation, its plastic-sealed ABF film can not only wrap the packaging layers on the front of the chip, but also wrap the surroundings of the packaging layers and the chip, protecting the underlying circuit from external factors, and further improving the ability to resist water vapor intrusion. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 This is a structural schematic diagram of Embodiment 1 of a wafer-level chip packaging structure with front protection according to the utility model;
[0012] Figure 2 yes Figure 1 Schematic diagram of the packaging process of the chip packaging structure before the ABF film is formed;
[0013] Figure 3 yes Figure 1 Schematic diagram of the packaging process of the chip packaging structure after the ABF film is formed;
[0014] Figure 4 It is a structural schematic diagram of Example 2 of a wafer-level chip packaging structure with front protection. DETAILED DESCRIPTION
[0015] The utility model is further described below in conjunction with specific implementation methods.
[0016] Example 1
[0017] like Figure 1As shown, a front-side protected wafer-level chip packaging structure according to one embodiment of the utility model comprises a chip 1, the front side of the chip 1 has a welding area 11, the front side of the chip 1 is covered with a passivation layer 2, the passivation layer 2 is covered with a first PI layer 3, an opening is formed on the passivation layer 2 and the first PI layer 3 to expose the welding area 11, a metal bump 5 is provided on the first PI layer 3, a seed layer 4 is provided at the bottom of the metal bump 5 and is embedded in the opening and interconnected with the welding area 11, and the front side of the chip 1 is coated with an ABF film 6, the ABF film 6 surrounds the metal bump 5 and exposes the top end of the metal bump 5. The chip 1 and each packaging layer packaged on the surface of the chip 1 have an opening groove 12 (such as Figure 2 The bottom of the opening groove 12 extends to the inside of the chip 1 and does not penetrate the chip 1. The center of the opening groove 12 is at the same position as the center of the designed scribing road (not shown), and the opening groove 12 is wider than the scribing road. After the ABF film 6 is formed, the bottom of the ABF film 6 is filled into the opening groove 12. The ABF film 6 covers the packaging layers on the front of the chip and the sides of the packaging layers of the chip, as well as the opening groove 12 of the chip 1, so as to fully wrap the surroundings and the front of the chip.
[0018] The wafer-level chip packaging structure of this embodiment is a 1P1M structure. Figure 2 and 3 , specifically describing the packaging process of the wafer-level chip packaging structure with front protection of this embodiment, the steps are as follows:
[0019] Step 1: First, perform plasma cleaning on the incoming wafer, that is, the chip wafer, to remove incoming contamination and avoid abnormalities in subsequent processes due to incoming contamination.
[0020] Step 2: If Figure 2 As shown in 2A to 2E, the cleaned wafer is subjected to photolithography, sputtering, and electroplating processes to form a passivation layer 2, a first PI layer 3, a seed layer 4, and a metal bump 5. The metal bump 5 is composed of Cu / Ni / SnAg or Cu / Sn. The metal bump 5 forms an interconnection circuit with the welding area 11 on the surface of the chip wafer.
[0021] Step 3: If Figure 2 As shown in Figure 2F, after the metal bump 5 process is completed, pre-cutting (Pre-Cut) is performed to form an open groove 12. The pre-cutting process can achieve a better cutting effect on the wafer with the ABF (Ajinomoto Build-up Film) film, and can also achieve the effect of relieving stress. The product needs to be cut into single grains after packaging, so the dicing path will be preset. In this embodiment, the width of the open groove 12 is greater than the designed width of the dicing path, and the position of the open groove 12 is the same as the designed position of the dicing path. The open groove 12 runs through each packaging layer on the surface of the chip 1, and the bottom of the open groove 12 extends to the inside of the chip 1 and does not penetrate the chip 1.
[0022] Step 4: Use AOI (automatic optical inspection) to check whether there are any dicing anomalies on the pre-cut wafers to determine whether the operation can continue.
[0023] Step 5: Use ABF (Ajinomoto Build-up Film) material to bond the front side of the wafer. Press the ABF (Ajinomoto Build-up Film) material onto the wafer. The ABF (Ajinomoto Build-up Film) covers the front side of the chip and fills the pre-cut opening 12. Figure 2 As shown in 2G.
[0024] Step 6: If Figure 2 As shown in FIG. 2H , the wafer after ABF (Ajinomoto Build-up Film) pressing is subjected to a grinding process until the surface of the metal bump 5 is exposed.
[0025] Step 7: Test, print, and sort until the wafer is cut along the preset dicing path to produce chips with ABF (Ajinomoto Build-up Film) on the front. Figure 2 As shown in 2I and 2J, since the opening groove 12 is wider than the dicing road, the encapsulation layers on the chip wafer of the single chip after cutting are all wrapped with ABF film 6, and the layer where the bottom chip wafer is located is also wrapped with ABF film 6.
[0026] Before the ABF film 6 is formed, the wafer-level chip packaging structure first grooves the chip 1 and each packaging layer on its surface to form an open groove 12, which can relieve stress. After the product packaging is completed, the risk of cracking can be reduced and the reliability of the chip can be increased. A layer of ABF film 6 is pressed on the front of the product, which can improve the ability to resist water vapor intrusion during operation and protect products that are sensitive to temperature and humidity. In particular, in this embodiment, the bottom of the open groove 12 is opened to the inside of the wafer of the chip 1, and the open groove 12 is located at the position of the dicing road and is wider than the dicing road. After the ABF film 6 is formed, when it is cut into a single chip, the ABF film 6 filled in the open groove 12 extends to the layer where the chip 1 is located. The ABF film 6 can completely cover the various packaging layers on the front of the chip 1 and wrap around the layer where the chip 1 is located, which can protect the bottom line from external factors, and the ability to resist water vapor intrusion is further improved.
[0027] Example 2
[0028] like Figure 4As shown, the main difference between this embodiment 2 and embodiment 1 is that the wafer-level chip packaging structure with front protection has a redistribution layer 7 inside. For the chip packaging structure with the redistribution layer 7, a layer of ABF film 6 can also be formed on the front of the product to improve the ability to resist water vapor intrusion.
[0029] The wafer-level chip packaging structure of this embodiment is a 2P2M structure, and the redistribution layer 7 includes a metal layer 71 and a second PI layer 72. The metal layer 71 and the second PI layer 72 have the same number of layers, and the metal layer 71 and the second PI layer 72 are both one layer. The metal layer 71 is located on the first PI layer 3, and the bottom of the metal layer 71 has a seed layer 4 and is embedded in the opening of the first PI layer 3 and interconnected with the welding area 11. The second PI layer 72 covers the first PI layer 3 and covers the metal layer 71. An opening is formed on the second PI layer 72 to expose the metal layer 71. The bottom of the metal bump 5 is embedded in the opening on the second PI layer 72, and the metal bump 5 is interconnected with the metal layer 71 through the seed layer 4 at the bottom. The ABF film 6 is located on the second PI layer 72 and surrounds the metal bump 5, and the top of the metal bump 5 is exposed. The ABF film 6 covers each packaging layer on the front of the chip and wraps the side surfaces of each packaging layer of the chip.
[0030] The wafer-level chip packaging structure of this embodiment is a 2P2M structure. The packaging process of the chip packaging structure of this embodiment is specifically described as follows:
[0031] Step 1: First, perform plasma cleaning on the incoming wafer, that is, the chip wafer, to remove incoming contamination and avoid abnormalities in subsequent processes due to incoming contamination.
[0032] Step 2: The cleaned wafer is subjected to photolithography, sputtering and electroplating processes to form a passivation layer 2, a first PI layer 3, a seed layer 4 at the bottom of the metal layer 71, a metal layer 71, a second PI layer 72, a seed layer 4 at the bottom of the metal bump 5, and a metal bump 5. The metal layer 71 is interconnected with the welding area 11 on the surface of the chip wafer, and the metal bump 5 is interconnected with the metal layer 71.
[0033] Step 3: After completing the metal bump 5 process, pre-cutting is performed to form an open groove. The structure of the open groove is the same as that in Example 1, except that the depth is different. The pre-cutting process. The product needs to be cut into single grains after packaging, so a scribe line will be preset. In this embodiment, the width of the open groove is greater than the designed width of the scribe line, the position of the open groove is the same as the designed position of the scribe line, the open groove passes through each packaging layer on the surface of the chip 1, and the bottom of the open groove extends above the surface of the chip 1.
[0034] Step 4: Use AOI (automatic optical inspection) to check whether there are any dicing anomalies on the pre-cut wafers to determine whether the operation can continue.
[0035] Step 5: Use ABF (Ajinomoto Build-up Film) material to perform bonding process on the front side of the wafer. Press the ABF (Ajinomoto Build-up Film) material onto the wafer. The ABF (Ajinomoto Build-up Film) covers the front side of the chip and fills the pre-cut opening groove 12.
[0036] Step 6: Grinding the wafer after ABF (Ajinomoto Build-up Film) pressing until the surface of the metal bump 5 is exposed.
[0037] Step 7: Test, print, and sort until the wafer is cut along the preset dicing path to produce chips with ABF (Ajinomoto Build-up Film) pressed on the front. After the single chip is cut, each packaging layer on the chip wafer is wrapped with ABF film 6.
[0038] In this chip packaging structure, before the ABF film 6 is formed, grooves are cut in the packaging layers above the chip 1 to form open grooves, which can relieve stress. After the product packaging is completed, the risk of cracking can be reduced, the reliability of the chip 1 can be increased, and the packaging layers on the front of the chip 1 and the surrounding areas of each packaging layer can be completely covered to improve the resistance to water vapor intrusion.
[0039] Example 3
[0040] The main difference between the present embodiment 3 and the embodiment 2 is that in the present embodiment, the metal layer 71 and the second PI layer 72 of the redistribution layer 7 are both provided with a multi-layer structure, which is not shown in the structural diagram.
[0041] The multi-layer metal layer 71 and the second PI layer 72 are stacked, and a multi-layer interconnection structure is formed between each metal layer 71. The bottom metal layer 71 is interconnected with the welding area 11 through the bottom seed layer 4. The bottom of the metal bump 5 is embedded in the opening of the top second PI layer 72, and is interconnected with the top metal layer 71 through the bottom seed layer 4. The ABF film 6 is located on the top second PI layer 72 and surrounds the metal bump 5 and exposes the top of the metal bump 5.
[0042] In the present embodiment, during pre-cutting, the opening grooves penetrate through the packaging layers on the surface of the chip 1 , and the bottoms of the opening grooves extend to above the surface of the chip 1 .
[0043] The wafer-level chip packaging structure provided by the utility model adopts a layer of ABF film 6 pressed on the front of the product to protect the product, especially the products that are sensitive to temperature and humidity. After the packaging layers on the chip 1 are grooved first, or after the packaging layers on the chip 1 and the chip 1 wafer are grooved first, the ABF film 6 is formed. This process is conducive to relieving stress, reducing the risk of product breakage after packaging, and increasing chip reliability. When the groove depth reaches the layer where the chip wafer is located, the plastic-sealed ABF film 6 of the single chip after segmentation can not only wrap the packaging layers on the front of the chip, but also wrap the surroundings of the packaging layers and the chip, protecting the bottom line from external factors, and further improving the ability to resist water vapor intrusion.
[0044] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.
Claims
1. A wafer-level chip packaging structure with front protection, comprising a chip (1), wherein a welding area (11) is provided on the front side of the chip (1), characterized in that: The front side of the chip (1) is covered with a passivation layer (2), the passivation layer (2) is covered with a first PI layer (3), openings are formed on the passivation layer (2) and the first PI layer (3) to expose a welding area (11), a metal bump (5) is provided on the first PI layer (3), a seed layer (4) is provided at the bottom of the metal bump (5) and is embedded in the opening to interconnect with the welding area (11), the front side of the chip is covered with an ABF film (6), the ABF film (6) surrounds the metal bump (5) and exposes the top end of the metal bump (5), and the ABF film (6) is coated to the front side of the chip (1) at the side of the chip packaging structure.
2. The wafer-level chip packaging structure with front protection according to claim 1, characterized in that: The invention also comprises a redistribution layer (7), wherein the redistribution layer (7) comprises a metal layer (71) and a second PI layer (72), wherein the metal layer (71) is located on the first PI layer (3), a seed layer (4) is provided at the bottom of the metal layer (71) and is embedded in an opening of the first PI layer (3) and interconnected with the welding area (11), the second PI layer (72) covers the first PI layer (3) and covers the metal layer (71), an opening is formed on the second PI layer (72) to expose the metal layer (71), the bottom of the metal bump (5) is embedded in the opening on the second PI layer (72), and the metal bump (5) is interconnected with the metal layer (71) through the seed layer (4) at the bottom, and the ABF film (6) is located on the second PI layer (72) and surrounds the metal bump (5) and exposes the top end of the metal bump (5).
3. The wafer-level chip packaging structure with front protection according to claim 2, characterized in that: The metal layer (71) and the second PI layer (72) have the same number of layers, and the metal layer (71) and the second PI layer (72) are provided with multiple layers, the multiple layers of the metal layer (71) and the second PI layer (72) are stacked and interconnection lines are formed between the metal layers (71), the bottom metal layer (71) is interconnected with the welding area (11) through the bottom seed layer (4), the bottom of the metal bump (5) is embedded in the opening of the top second PI layer (72) and is interconnected with the top metal layer (71) through the bottom seed layer (4), and the ABF film (6) is located on the top second PI layer (72) and surrounds the metal bump (5) and exposes the top end of the metal bump (5).
4. The wafer-level chip packaging structure with front protection according to any one of claims 1 to 3, characterized in that: The chip (1) and each packaging layer packaged on the surface of the chip (1) are provided with an open groove (12); the bottom of the open groove (12) extends to the inside of the chip (1) and does not penetrate the chip (1); the center of the open groove (12) is at the same position as the center of the designed scribing road, and the open groove (12) is wider than the scribing road; the bottom of the ABF film (6) is filled into the open groove (12); in the formed chip packaging structure, the ABF film (6) covers each packaging layer on the front side of the chip, and wraps the side surfaces of each packaging layer of the chip and the open groove (12) of the chip (1).
5. The wafer-level chip packaging structure with front protection according to claim 2 or 3, characterized in that: Each packaging layer on the surface of the chip (1) is provided with an open groove (12), the bottom of the open groove (12) extends to the surface of the chip (1), the center of the open groove (12) is at the same position as the center of the designed scribing road, and the open groove (12) is wider than the scribing road, and the bottom of the ABF film (6) is filled into the open groove (12), and in the formed chip packaging structure, the ABF film (6) covers each packaging layer on the front side of the chip and wraps the side surfaces of each packaging layer of the chip.