Multilayer printed circuit board for interconnecting pins and semiconductor die, pins and power module

Abstract

The utility model relates to a multilayer printed circuit board for interconnecting a pin and a semiconductor die, a pin, and a power module. There is provided a multilayer printed circuit board for interconnecting a pin and a semiconductor die, including: a multilayer substrate including a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each of the substrate layers being composed of an insulating material; pin holders embedded in the multilayer substrate, one end of each pin holder being exposed from the top surface of the top substrate layer for inserting a pin in the pin holder; die contacts embedded in the multilayer substrate, one end of each die contact being exposed from a bottom surface of the bottom substrate layer for electrical coupling with a contact of a semiconductor die; and first interconnection structures embedded in the multilayer substrate, each first interconnection structure being connected between a respective pin holder and a respective die contact for electrically coupling the two.

Description

Technical Field

[0001] The present disclosure relates to a power module package, and more particularly, to a multi-layer printed circuit board for interconnecting pins and semiconductor dies in a power module package process and a corresponding interconnection method. Background Art

[0002] Pins are a common interconnection method used to connect semiconductor dies (especially semiconductor dies used in power modules in vehicles) to the main circuit board (usually a printed circuit board). They play a very important interconnection role in the final product, but pins and pin retainers are one of the most fragile components in the final product. Unlike wiring, pins and pin retainers are very easy to damage because they not only have to withstand the force of being pressed / inserted during the interconnection process, but also face various conditions that may occur during the welding process. The welding process of pins and pin retainers is relatively complicated, so various defects often occur, including, for example, solder spatter, pin tilt deformation, retainer deformation, retainer failure, etc.

[0003] In short, pins and pin holders are important and critical components for interconnecting semiconductor dies, and any defects or failures thereof will have adverse effects on the final product. Therefore, it is urgent to propose an interconnection technology solution that can avoid defects and failures of pins and pin holders.

[0004] To this end, the present application proposes a multi-layer printed circuit board for interconnecting pins and semiconductor dies and a corresponding interconnection method that can solve the above-mentioned problems. Summary of the invention

[0005] One of the objects of the present disclosure is to provide an improved multi-layer printed circuit board for interconnecting pins and semiconductor dies and a corresponding interconnection method.

[0006] According to one aspect of the present disclosure, there is provided a multilayer printed circuit board for interconnecting pins and semiconductor dies, comprising: a multilayer substrate, comprising a bottom substrate layer, one or more core substrate layers and a top substrate layer stacked in sequence, each substrate layer being made of an insulating material; a pin holder embedded in the multilayer substrate, one end of each pin holder being exposed from the top surface of the top substrate layer for plugging a pin in the pin holder; a die contact embedded in the multilayer substrate, one end of each die contact being exposed from the bottom surface of the bottom substrate layer for electrically coupling with a contact of the semiconductor die; and a first interconnect structure embedded in the multilayer substrate, each first interconnect structure being connected between a corresponding pin holder and a corresponding die contact for electrically coupling the two.

[0007] According to one or more embodiments of the present disclosure, each pin retaining member includes: a tubular cavity extending in a direction perpendicular to the multi-layer substrate and suitable for inserting a pin therein at one end; and a first flange arranged at one end of the tubular cavity and protruding laterally relative to the tubular cavity, the first flange being arranged above the top surface of the top substrate layer.

[0008] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: auxiliary connectors embedded in the multilayer substrate and extending in a direction perpendicular to the multilayer substrate, one end of each auxiliary connector being electrically coupled to a corresponding pin retainer and the other end being electrically connected to a corresponding die contact, wherein each auxiliary connector includes: a columnar body extending in a direction perpendicular to the multilayer substrate; and a second flange arranged at one end of the columnar body and protruding laterally relative to the columnar body.

[0009] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: flange interconnectors, each flange interconnector being connected between the second flange of the corresponding auxiliary connector and the corresponding pin holder to electrically couple the two.

[0010] According to one or more embodiments of the present disclosure, the auxiliary connector includes a first auxiliary connector, the second flange of the first auxiliary connector and a flange interconnector connected thereto are arranged between the top substrate layer and the adjacent core substrate layer; and wherein the flange interconnector connected to the second flange of the first auxiliary connector is also connected to the tubular cavity of the corresponding pin retainer, thereby electrically coupling the corresponding pin retainer with the first auxiliary connector.

[0011] According to one or more embodiments of the present disclosure, the second flange of the first auxiliary connecting member connected to each other and the corresponding flange interconnecting member are integrally formed by a same layer of metal.

[0012] According to one or more embodiments of the present disclosure, wherein the auxiliary connector includes a second auxiliary connector, a second flange of the second auxiliary connector and a flange interconnect connected thereto are disposed above the top surface of the top substrate layer; and wherein the flange interconnect connected to the second flange of the second auxiliary connector is also connected to the first flange of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector,

[0013] According to one or more embodiments of the present disclosure, the second flange of the second auxiliary connector, the corresponding flange interconnection member, and the first flange of the corresponding pin holder connected to each other are integrally formed by a same layer of metal.

[0014] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: a second interconnect structure embedded in the multilayer substrate, each second interconnect structure connected between at least two die contacts for electrically coupling the at least two die contacts.

[0015] According to one or more embodiments of the present disclosure, at least a portion of the first interconnect structure, the second interconnect structure and / or the die contact is formed by a thick copper damascene process.

[0016] According to one or more embodiments of the present disclosure, the multilayer printed circuit board also includes: buried spacers, each buried spacer extending from the bottom surface of the top substrate layer through the one or more core substrate layers and the bottom substrate layer, and extending beyond the bottom surface of the bottom substrate layer to a first length, wherein the first length depends on the thickness of the semiconductor die.

[0017] According to one or more embodiments of the present disclosure, the first length is equal to the sum of the thickness of the semiconductor die and the thickness of a die attach layer, the die attach layer being used to attach the semiconductor die to the multi-layer printed circuit board.

[0018] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: a negative temperature coefficient contact embedded in the multilayer substrate, the negative temperature coefficient contact being exposed from an opening disposed at a central portion of the bottom substrate layer for coupling to a negative temperature coefficient sensor.

[0019] According to one or more embodiments of the present disclosure, the die contact comprises a thick copper contact and / or a thin copper contact; and wherein the die contact is used as one or more of: a gate-substrate contact, a source-substrate contact, a gate pad contact, and / or a source pad contact.

[0020] According to another aspect of the present disclosure, a pin is provided, comprising: a rod-shaped body, a first end of which is pointed and suitable for being inserted into a pin holder, a second end of which comprises an elastic portion and is suitable for being inserted into a through hole; and a stop portion, which is arranged at a position of the rod-shaped body at a certain distance from the first end and protrudes laterally relative to the rod-shaped body, wherein the pin is suitable for being installed in a pin holder in a multilayer printed circuit board as described above, and wherein, when the first end of the pin is inserted into the pin holder, the stop portion abuts against a first flange of the pin holder.

[0021] According to another aspect of the present disclosure, a power module is provided, comprising: a carrier substrate; a semiconductor die attached to the carrier substrate; a multilayer printed circuit board as described above, attached to the semiconductor die and electrically coupled to the semiconductor die through die contacts of the multilayer printed circuit board; a housing encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board; and pins inserted into pin holders in the multilayer printed circuit board and exposed from one side of the housing.

[0022] According to another aspect of the present disclosure, a method for interconnecting pins and semiconductor die is provided, comprising the steps of: attaching the semiconductor die to a carrier substrate; attaching a multilayer printed circuit board as described above to the semiconductor die; inserting pins into pin holders in the multilayer printed circuit board; and encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board with insulating material to form a housing.

[0023] According to yet another aspect of the present disclosure, a method for interconnecting pins and semiconductor die is provided, comprising the steps of: attaching a multilayer printed circuit board as described above to the semiconductor die; attaching the semiconductor die to a carrier substrate; inserting pins into pin holders in the multilayer printed circuit board; and encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board with insulating material to form a housing.

[0024] According to one or more embodiments of the present disclosure, attaching the multilayer printed circuit board to the semiconductor die includes the following steps: coating an attachment material on contacts of the semiconductor die; placing the multilayer printed circuit board on the semiconductor die so that contacts of a bottom substrate layer of the multilayer printed circuit board and contacts of the semiconductor die are in contact with each other via the attachment material; and performing a sintering, welding and / or curing process to cure the attachment material.

[0025] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0027] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0028] Figure 1A Schematically shows a cross-sectional view of a multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure;

[0029] Figure 1B and Figure 1C They are schematically shown Figure 1A A top view and a bottom view of the multilayer printed circuit board 100 shown in FIG.

[0030] Figure 2A Schematically shows a front view of a pin 10 according to one or more embodiments of the present disclosure, Figure 2B A side view of pin 10 is shown;

[0031] Figure 3 Schematic size comparison between a conventional pin 20 and a pin 10 according to an embodiment of the present disclosure is shown;

[0032] Figure 4 An exemplary flow chart of a method 300 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is shown;

[0033] FIG. 5A to FIG. 5E Schematically shows the Figure 4 A schematic cross-sectional view of a device corresponding to some steps of the method shown;

[0034] Figure 6 An exemplary flow chart showing another method 300' for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure

[0035] Fig. 7A A schematic three-dimensional model of a power module according to an embodiment of the present disclosure is shown;

[0036] Figure 7B Shows Fig. 7A A perspective view of a portion of a multi-layer printed circuit board for interconnecting pins and semiconductor dies in a power module;

[0037] Figure 7C Shows Fig. 7A A bottom view of a multi-layer printed circuit board used to interconnect pins and semiconductor dies in a power module.

[0038] Note that in the embodiments described below, sometimes the same reference numerals are used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In some cases, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the present disclosure is not limited to the position, size, range, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0040] In automotive applications, a pin interconnection process is often used to interconnect a power module containing a semiconductor die and a main circuit board (such as a printed circuit board). For example, first, the semiconductor die is attached to a carrier substrate, and a pin holder is installed on the carrier substrate. Subsequently, pins are inserted into the pin holder on the carrier substrate and soldered by reflow soldering or the like. Finally, the semiconductor die and the carrier substrate are encapsulated with an insulating material such as epoxy resin to obtain a power module with pins, which are used to further attach to the main circuit board. However, the pins and pin holders in the power module obtained by such a manufacturing process often have various defects, such as poor contact between the pins and the pin holders caused by poor welding, damage or excessive tilting of the pin holders, solder overflow, etc. These defects can cause the product performance to deteriorate or even become unusable, and need to be solved urgently.

[0041] To this end, the inventor of the present application has proposed a brand-new technical solution for interconnecting pins and semiconductor die, that is, using a dedicated multi-layer printed circuit board to interconnect pins and semiconductor die. Specifically, the multi-layer printed circuit board for interconnecting pins and semiconductor die proposed in the present disclosure includes a pin holder embedded therein and a contact for coupling to the semiconductor die. When the pins need to be interconnected with the semiconductor die, the multi-layer printed circuit board is first attached to the semiconductor die through its contact, and then the pins are plugged into the pin holder in the multi-layer printed circuit board, thereby realizing the interconnection between the semiconductor die and the pins. In addition, other interconnection structures can also be provided in the multi-layer printed circuit board for interconnecting pins and semiconductor die proposed in the present disclosure, so that the multi-layer printed circuit board can provide other interconnection functions for the semiconductor die.

[0042] The following will describe in detail a more detailed embodiment of the novel technical solution for interconnecting pins and semiconductor dies disclosed in the present invention with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​described in these embodiments do not limit the scope of the present invention.

[0043] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0044] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0045] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0046] Figure 1A A cross-sectional view of a multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is schematically shown.

[0047] like Figure 1A As described in the specification, a multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include a multilayer substrate 102, which is composed of a bottom substrate layer 104, one or more core substrate layers 106, and a top substrate layer 108 stacked in sequence. Each substrate layer includes an insulating material, which may include any material suitable for forming an insulating substrate layer of a printed circuit board, such as polyimide or epoxy resin, etc. In addition, the materials of the various substrate layers of the multilayer substrate 102 may be the same or different from each other.

[0048] In a preferred embodiment, the hardness and mechanical strength of the bottom substrate layer 104 and the top substrate layer 108 may be better than that of the core substrate layer 106 , thereby providing better mechanical support for the entire multi-layer printed circuit board 100 .

[0049] Those skilled in the art will understand that although Figure 1A Schematically showing three core substrate layers 106 and the shape, size and thickness of each substrate layer, but this is not intended to constitute any limitation. The multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include any number of core substrate layers, and the shape, size, thickness and material of each substrate layer may be arbitrarily set as needed.

[0050] Figure 1B and Figure 1CThey are schematically shown Figure 1A , wherein the multilayer printed circuit board 100 is shown in a top view and a bottom view. Figure 1B The top substrate layer 108 is shown in more detail, while Figure 1C Details of the bottom substrate layer 104 are shown in greater detail. Figure 1A The cross-sectional view is along Figure 1B and Figure 1C Intercepted by line AA in .

[0051] Combined with reference Figures 1A to 1C The multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may further include: a pin holder 110 embedded in the multilayer substrate 102. One end of each pin holder 110 may be exposed from the top surface of the top substrate layer 108 for plugging pins in the pin holder. The multilayer printed circuit board 100 according to an embodiment of the present disclosure may further include: a die contact 120 embedded in the multilayer substrate 102, and a first interconnect structure 130 embedded in the multilayer substrate 102. Figure 1C As shown in FIG. 1 , one end of each die contact 120 may be exposed from the bottom surface of the bottom substrate layer 104 for electrical coupling with a contact of the semiconductor die. Each first interconnect structure 130 may be connected between a corresponding pin holder 110 and a corresponding die contact 120 for electrical coupling of the two.

[0052] According to the embodiment of the present disclosure, the multilayer printed circuit board 100 embeds a pin holder 110 for plugging pins and a die contact 120 for coupling semiconductor die in its multilayer substrate 102, and the pin holder 110 and the die contact 120 are interconnected through a first interconnection structure 130. When the multilayer printed circuit board 100 according to the present disclosure is used to interconnect pins and semiconductor die, the interconnection between the pins and the semiconductor die can be achieved by attaching the multilayer printed circuit board 100 and the semiconductor die together through planar contact, and then inserting the pin into the pin holder 110 in the multilayer printed circuit board 100. Such an interconnection scheme can achieve many beneficial technical effects. On the one hand, compared with the prior art in which the pin holder is fixed above the carrier substrate, the scheme of the present disclosure embeds the pin holder 110 in the multilayer substrate 102 so that the pin holder 110 is more stable and not easy to tilt, thereby avoiding the problem of damage to the pin holder that may occur during the process of plugging pins. On the other hand, the multilayer printed circuit board 100 and the semiconductor die are interconnected by planar contact, which can also improve the effect of interconnection.

[0053] In one or more embodiments according to the present disclosure, the pin holder 110 may be electrically coupled to the corresponding die contact 120 via one or more first interconnect structures 130. For example, Figure 1A As shown in the figure, the leftmost pin holder 110 is electrically coupled to the die contact 120 through a first interconnect structure 130, while another adjacent pin holder 110 is electrically coupled to the die contact 120 through two first interconnect structures 130 respectively arranged between different core substrate layers.

[0054] In one or more embodiments according to the present disclosure, the first interconnect structure 130 and the die contact 120 may be formed by various processes known in the art for manufacturing conductive components in a printed circuit board. For example, they may be formed by a thin copper layer disposed between various substrate layers, or by a thick copper block embedded in a substrate layer by a thick copper embedding (also known as copper block embedding, Cu In-lay) process.

[0055] In one or more embodiments according to the present disclosure, the die contact 120 may include a thick copper contact and / or a thin copper contact, wherein the thick copper contact may be used as a source contact that needs to conduct a larger current, and the thin copper contact may be used as a gate contact that only needs to conduct a smaller current. In a preferred embodiment, the die contact 120 may be used as one or more of the following: a gate-substrate contact, a source-substrate contact, a gate pad contact, and / or a source pad contact, etc.

[0056] Those skilled in the art will understand that although Figures 1A to 1C The number, distribution, shape and size of the pin holders 110, the die contacts 120 and the corresponding first interconnect structures 130 are shown in the figure, but this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may include any number, any distribution, any shape and any size of the pin holders 110, the die contacts 120 and / or the first interconnect structures 130. In addition, the die contacts 120 and the first interconnect structures 130 according to the embodiment of the present disclosure are not limited to being composed of copper, but may include any material suitable for forming conductive contacts.

[0057] Continue to refer Figure 1A and Figure 1B In one or more embodiments according to the present disclosure, each pin holder 110 may include a tubular cavity 112 and a first flange 114. The tubular cavity 112 may extend in a direction perpendicular to the multi-layer substrate 102 and is suitable for inserting one end of the pin 10 therein. The first flange 114 may be disposed at one end of the tubular cavity 112 and protrude laterally relative to the tubular cavity 112. Figure 1AAs described in , the first flange 114 is disposed on the top surface of the top substrate layer 108 to serve as one end of the pin holder 110 exposed from the top surface of the top substrate layer 108. In order to be suitable for plugging the pin 10 in the pin holder, the inner diameter of the tubular cavity 112 of the pin holder 110 matches the diameter of the plugging end of the pin 10, and the first flange 114 can be formed into a ring shape with an inner diameter consistent with the inner diameter of the tubular cavity 112 and an outer diameter greater than the inner diameter, as shown in FIG. Figure 1B Clearly shown in.

[0058] In the embodiment according to the present disclosure, by providing a first flange 114 at one end of the tubular cavity 112 of the pin holder 110 , the pin holder 110 can be more firmly supported in the multi-layer substrate 102 by means of the interaction between the first flange 114 and the top substrate layer 108 .

[0059] Figure 2A A front view of a pin 10 according to one or more embodiments of the present disclosure is schematically shown, and the pin 10 is adapted to a pin holder 110 in a multilayer printed circuit board 100 according to an embodiment of the present disclosure. Figure 2B A side view of the pin 10 is shown.

[0060] like Figure 2A and Figure 2B As shown in , the pin 10 according to an embodiment of the present disclosure may include an elongated rod-shaped body 12. The first end of the rod-shaped body 12 is pointed and suitable for being inserted into the pin holder 110, and the second end thereof includes an elastic portion 16 and is suitable for being snapped into a through hole, which, for example, includes a through hole arranged in a total circuit board (e.g., a printed circuit board) to which the pin is to be connected. The pin 10 may also include a stopper 14, which is arranged at a position of the rod-shaped body 12 at a certain distance L1 from the first end and protrudes laterally relative to the rod-shaped body 12. The distance L1 of the stopper 14 from the first end of the rod-shaped body 12 may depend on the height of the pin holder. In a preferred embodiment, the distance L1 of the stopper 14 from the first end of the rod-shaped body 12 may be the same as or slightly less than the height of the pin holder. In a preferred embodiment, the stopper 14 may include two semi-cylindrical protrusions relatively disposed on opposite sides of the rod-shaped body 12. The radius W1 of such a semi-cylindrical protrusion may depend on the size of the flange of the pin holder, for example, it may be equal to or slightly smaller than the width W0 of the annular flange of the pin holder (e.g. Figure 1B ).

[0061] In the embodiment according to the present disclosure, when the first end of the pin 10 is inserted into the pin holder 110, the stopper 14 of the pin 10 can abut against the first flange 114 of the pin holder 110. On the one hand, the mutual abutment between the stopper 14 of the pin 10 and the first flange 114 of the pin holder 110 can provide more mechanical support for the pin 10 (to be discussed in more detail later), making the insertion of the pin 10 more secure. On the other hand, the stopper 14 of the pin 10 can also prevent the pin 10 from being inserted too deeply into the pin holder, ensuring that the insertion depth of the pin 10 is appropriate.

[0062] Figure 3 A schematic size comparison between a conventional pin 20 and a pin 10 according to an embodiment of the present disclosure is shown.

[0063] As described above, the existing pin interconnection technology sets the pin holder on the carrier substrate. However, in the embodiment of the present application, the pin holder is set in the multi-layer printed circuit board attached to the semiconductor die. Therefore, under the premise that the overall thickness of the power module remains unchanged, the existence of the multi-layer printed circuit board according to the embodiment of the present disclosure allows the height of the pin holder to be higher and the pins to be shorter. These changes can also improve the effect of pin interconnection.

[0064] like Figure 3 As shown in , the height H1 of the pin 10 according to the embodiment of the present disclosure can be less than the height H0 of the conventional pin 20. In a preferred embodiment, the height H1 of the pin 10 according to the embodiment of the present disclosure can be about 1.3 mm smaller than the height H0 of the conventional pin 20. This is because the thickness of the bottom substrate layer of the multilayer printed circuit board can be about 1 mm, and the total thickness of the semiconductor die and the die attach layer for attaching the semiconductor die to the multilayer printed circuit board can be about 0.3 mm. Therefore, the height H1 of the pin 10 according to the embodiment of the present disclosure can be reduced by about 1 mm + 0.3 mm = 1.3 mm relative to the conventional pin.

[0065] Continue to refer Figure 3, and schematically shows a conventional pin holder 22 plugged into a conventional pin 20 and a pin holder 110 according to an embodiment of the present disclosure plugged into a pin 10 according to an embodiment of the present disclosure, wherein the height of the pin holder 22 is D0, and the height of the pin holder 110 is D1. When the pin 10 is plugged into the pin holder 110, if the top of the pin 10 is subjected to a lateral force F1, the portion of the pin 10 plugged into the pin holder 110 will be subjected to a corresponding force f1. It is desirable that the force f1 is as small as possible to avoid damage to the pin. The force f1 to which the portion of the pin 10 plugged into the pin holder 110 is subjected satisfies the formula: F1*(H1-D1)=f1*D1, wherein H1 is the height of the pin 10, and D1 is the height of the pin holder 110. From this formula, it can be seen that the smaller the height of the pin and the larger the height of the pin holder, when the top of the pin is subjected to a lateral force, the smaller the corresponding force f1 to which the portion of the pin plugged into the pin holder is subjected. For example, the height H0 of the conventional pin 20 is 14.8 mm, and the corresponding height D0 of the pin holder 22 is 2.8 mm. Then, the force f0 to which the plugged portion of the pin 20 is subjected is F0*(H0-D0) / D0=F0*(14.8-2.8) / 2.8≈4.29F0. In contrast, according to the present disclosure, the height H1 of the pin 10 is 13.5 mm, and the corresponding height D0 of the pin holder 110 is 4.5 mm. Based on the above formula, the force f1 to which the plugged portion of the pin 10 is subjected is F1*(13.5-4.5) / 4.5≈2.22F1, which is reduced by about 51.7% relative to the conventional pin.

[0066] Back to Figures 1A to 1C The multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may further include auxiliary connectors 140A / 140B embedded in the multilayer substrate 102 and extending in a direction perpendicular to the multilayer substrate 102. One end of each auxiliary connector is electrically coupled to the corresponding pin holder 110, and the other end thereof is electrically connected to the corresponding die contact 120.

[0067] In one or more embodiments according to the present disclosure, Figure 1A As shown in FIG. 1 , each auxiliary connector 140A / 140B may include a columnar body 144 and a second flange 142 disposed at one end of the columnar body 144. The columnar body 144 may extend in a direction perpendicular to the multilayer substrate 102 to connect to the die contact 120. The second flange 142 protrudes laterally relative to the columnar body 144.

[0068] like Figure 1A and Figure 1BAs shown in , the multilayer printed circuit board 100 according to an embodiment of the present disclosure may also include flange interconnects 146, each of which may be connected between the second flange 142 of the corresponding auxiliary connector 140A / 140B and the corresponding pin holder 110, thereby electrically coupling the corresponding auxiliary connector 140A / 140B with the corresponding pin holder 110.

[0069] In one or more embodiments according to the present disclosure, the auxiliary connector may include a first auxiliary connector 140A, the second flange 142 of the first auxiliary connector 140A and a flange interconnect 146 connected thereto are disposed between the top substrate layer 108 and the adjacent core substrate layer 106. The flange interconnect 146 connected to the second flange 142 of the first auxiliary connector 140A may also be connected to the tubular cavity 112 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the first auxiliary connector 140A.

[0070] Since the flange interconnector 146 connected to the second flange 142 of the first auxiliary connector 140A is disposed below the top substrate layer 108, Figure 1B The flange interconnect is not visible in the top view of the top substrate layer 108 shown, but is shown in FIG. Figure 1B The flange interconnect 146 is shown in a perspective state in dotted lines in the top view of FIG.

[0071] In a preferred embodiment, the second flange 142 of the first auxiliary connection member 140A and the corresponding flange interconnection member 146 connected to each other may be integrally formed by the same layer of metal.

[0072] In one or more embodiments according to the present disclosure, the auxiliary connector may include a second auxiliary connector 140B, the second flange 142 of the second auxiliary connector 140B and the flange interconnection 146 connected thereto are disposed above the top surface of the top substrate layer 108. The flange interconnection 146 connected to the second flange 142 of the second auxiliary connector 140B may also be connected to the first flange 114 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the second auxiliary connector 140B.

[0073] In a preferred embodiment, the second flange 142 of the second auxiliary connector 140B, the corresponding flange interconnection member 146 and the corresponding first flange 114 of the pin holder 110 connected to each other are integrally formed by the same layer of metal.

[0074] In one or more embodiments according to the present disclosure, the first flange of a pin holder can be connected to the plurality of second flanges of the plurality of auxiliary connectors respectively through a plurality of flange interconnectors. Figure 1B As described in the figure, the first flange 114' of the pin holder is respectively connected to the two second flanges 142' of the two auxiliary connectors 140B' through two flange interconnectors 146' extending in opposite directions, so that the pin holder can be electrically connected to at least two auxiliary connectors 140B' and further electrically coupled to at least two tube core contacts.

[0075] Those skilled in the art will understand that although Figures 1A to 1C The first auxiliary connector 140A and the second auxiliary connector 140B are shown in the figure, but this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may include only the first auxiliary connector 140A, only the second auxiliary connector 140B, or both the first auxiliary connector 140A and the second auxiliary connector 140B.

[0076] In one or more embodiments according to the present disclosure, the pin retainer 110 can be electrically coupled to the die contact through the first interconnection structure, and can also be electrically coupled to the die contact via the flange interconnection and the auxiliary connector, which provides great flexibility for the interconnection design of the multi-layer printed circuit board, so that various different interconnection structures can be flexibly arranged in the multi-layer printed circuit board according to application needs, making full use of area and space and reducing hardware consumption.

[0077] Continue to refer Figure 1A and Figure 1B In one or more embodiments according to the present disclosure, the multilayer printed circuit board 100 may further include a second interconnect structure 150 embedded in the multilayer substrate 102. Each second interconnect structure 150 may be connected between at least two die contacts 120 for electrically coupling the die contacts together. The second interconnect structure 150 may be formed by various processes known in the art for manufacturing conductive components in printed circuit boards, for example, it may be formed by a thin copper layer disposed between the various substrate layers, or may be formed by a thick copper block embedded in the substrate layer by a thick copper embedding (also referred to as copper block embedding, CuIn-lay) process.

[0078] In a preferred embodiment, at least a portion of the first interconnect structure 130 , the second interconnect structure 150 , and / or the die contact 120 according to embodiments of the present disclosure are formed by a thick copper damascene process.

[0079] In the multilayer printed circuit board 100 according to the embodiment of the present disclosure, in addition to the connection structure (such as the first interconnection structure 130, the auxiliary connectors 140A / 140B, the flange connector 146, etc.) for connecting the pin holder 110 and the die contact 120, an interconnection structure (such as the second interconnection structure 150) for realizing the connection between the various die contacts 120 may also be included. The second interconnection structure 150 enables the various contacts of the semiconductor die to be attached to be interconnected without pins through the multilayer printed circuit board 100, which makes it possible to add a possible connection method between the various contacts of the semiconductor die, thereby bringing more possibilities for the design of the entire power module.

[0080] Those skilled in the art will understand that although Figures 1A to 1C The number, distribution, shape and size of the auxiliary connectors 140A / 140B, the flange interconnection 146 and the second interconnection structure 150 are shown in FIG, but this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may include any number, any distribution, any shape and any size of auxiliary connectors 140A / 140B, flange interconnection 146 and / or second interconnection structure 150, etc. In addition, the flange interconnection 146 and the second interconnection structure 150 according to the embodiment of the present disclosure are not limited to being composed of copper, but may include any material suitable for forming a conductive component.

[0081] Continue to refer Figures 1A to 1C According to the embodiment of the present disclosure, the multilayer printed circuit board 100 may also optionally include a buried spacer 160, which is disposed in an idle position in the multilayer substrate 102 where no other conductive components are disposed, and is made of an insulating material with a certain mechanical strength, so as to enhance the mechanical support for the multilayer printed circuit board 100. Figure 1A As shown in , each buried spacer 160 extends from the bottom surface of the top substrate layer 108, through the core substrate layer 106 and the bottom substrate layer 104, and extends beyond the bottom surface of the bottom substrate layer 104 to a first length, which first length may depend on the thickness of the semiconductor die to which the multilayer printed circuit board 100 is to be attached.

[0082] In a preferred embodiment, when the multi-layer printed circuit board 100 is attached to the semiconductor die, one end of the buried spacer 160 extending beyond the bottom substrate layer 104 abuts against a support structure for supporting the semiconductor die to enhance mechanical support for the multi-layer printed circuit board 100. Therefore, a first length of the buried spacer 160 extending beyond the bottom substrate layer 104 may be equal to or slightly greater than the sum of the thickness of the semiconductor die and the thickness of the die attach layer, which refers to a material layer for attaching the semiconductor die to the multi-layer printed circuit board.

[0083] Continue to refer Figures 1A to 1C The multilayer printed circuit board 100 according to an embodiment of the present disclosure may also optionally include a negative temperature coefficient (NTC) contact 170 embedded in the multilayer substrate 102. The negative temperature coefficient contact 170 may be exposed from an opening 180 disposed at the center of the bottom substrate layer 104 for coupling to a negative temperature coefficient sensor. A temperature sensor may be disposed in the opening 180 for detecting the temperature of the power module.

[0084] Those skilled in the art will understand that although Figures 1A to 1C The number, distribution, shape and size of the buried spacers 160 and the negative temperature coefficient contacts 170, etc. are shown in FIG. 1 , but this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may include buried spacers 160 and negative temperature coefficient contacts 170, etc., of any number, any distribution, any shape and any size.

[0085] Those skilled in the art will understand that although Figures 1A to 1C The multilayer printed circuit board 100 shown in the figure includes various components, but this is only for the purpose of showing the various components as comprehensively as possible in the same set of drawings, and is not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may only include Figures 1A to 1C Some of the various components shown in FIG. Figures 1A to 1C The number, distribution, shape and size of the various components shown in the figure are also only used as examples and are not intended to constitute any limitation. The multilayer printed circuit board 100 according to the embodiment of the present disclosure may include the above-mentioned components in any number, distribution, shape and size.

[0086] It should also be understood by those skilled in the art that although Figure 1A The various components are shown in the same cross-sectional view, but this is only for the purpose of showing the various components as comprehensively as possible in the same figure, and is not intended to constitute any limitation. The various components of the multilayer printed circuit board 100 according to the embodiment of the present disclosure may not appear in the same cross-sectional view, so the cross-sectional view of the multilayer printed circuit board 100 may only include Figure 1A A portion of the components shown in FIG.

[0087] Combine the following Figure 4 as well as FIG. 5A to FIG. 5E A method for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is described. Figure 4 An exemplary flow chart of a method for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is shown, and FIG. 5A to FIG. 5E Schematically shows the Figure 4A schematic cross-sectional view of a device corresponding to some steps of the method shown. A person skilled in the art will understand that Figure 4 as well as FIG. 5A to FIG. 5E The described method for interconnecting pins and semiconductor dies employs a multilayer printed circuit board according to an embodiment of the present disclosure for interconnection, and thus the corresponding descriptions of the multilayer printed circuit board mentioned above also apply hereto.

[0088] like Figure 4 As shown, the method 300 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include step S310 , step S320 , step S330 , and step S340 .

[0089] At step S310, Figure 5A As shown, the semiconductor die 200 is attached to a carrier substrate 30. In an embodiment according to the present disclosure, the carrier substrate 30 may be a ceramic substrate covered with copper, such as a direct bonded copper (DBC) ceramic substrate or an active metal brazing (AMB) ceramic substrate, or any other type of carrier substrate.

[0090] In one or more embodiments according to the present disclosure, the semiconductor die 200 may include a plurality of contacts 202 and 204. In a preferred embodiment, the smaller contact 204 may include a gate contact, and the larger contact 202 may include a source contact.

[0091] Those skilled in the art will appreciate that, although FIG2 schematically illustrates the number, distribution, shape, and size of the contacts of the semiconductor die 200, this is not intended to constitute any limitation. The semiconductor die 200 according to an embodiment of the present disclosure may include any number, distribution, shape, and size of contacts.

[0092] At step S320 , the multilayer printed circuit board 100 according to an embodiment of the present disclosure is attached to the semiconductor die 200 .

[0093] In one or more embodiments according to the present disclosure, attaching the multilayer printed circuit board 100 to the semiconductor die 200 may be implemented by steps S322 , S324 , and S326 described below.

[0094] At step S322, Figure 5B As shown in FIG. 1 , an attachment material 206 is applied on the contacts 202 and 204 of the semiconductor die 200. The attachment material 206 may include, for example, sintering material, solder, gel, etc.

[0095] At step S324, Figure 5CAs shown in , the multilayer printed circuit board 100 is placed on the semiconductor die 200 so that the contacts 120 of the multilayer printed circuit board 100 exposed from the bottom substrate layer 104 and the contacts 202 and 204 of the semiconductor die 200 contact each other via the attaching material 206 .

[0096] In a preferred embodiment, the negative temperature coefficient contact 170 may be coupled to a negative temperature coefficient sensor 208 .

[0097] In a preferred embodiment, one end of the buried spacer 160 of the multi-layer printed circuit board 100 protruding from the bottom substrate layer 104 abuts against the carrier substrate 30 below the semiconductor die 200 , thereby providing better mechanical support for the multi-layer printed circuit board 100 .

[0098] At step S326, a sintering, welding and / or curing process is performed to cure the attachment material 206, thereby fixedly attaching the multilayer printed circuit board 100 and the semiconductor die 200 together. Figure 5C As shown in FIG. 4 , a sintering tool 40 may be used to press the printed circuit board 200 against the semiconductor die 200 , thereby improving the strength of the attachment.

[0099] Continue to refer Figure 4 At step S330, the pin 10 is inserted into the pin holder 110 of the multi-layer printed circuit 100, as shown in FIG. Figure 5D shown.

[0100] At step S340, Figure 5E As shown, the carrier substrate 30, the semiconductor die 200 and the multi-layer printed circuit board 100 are molded or potted with epoxy resin to form a housing 50, thereby obtaining a packaged power module.

[0101] Figure 4 The execution order of steps S310 and S320 of the method 300 for interconnecting pins and semiconductor dies shown in FIG. 3 is interchangeable. Figure 6 Another method 300' for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is shown. The method 300' is Figure 4 A variant embodiment of the method 300 for interconnecting pins and semiconductor dies is shown in FIG. Figure 4 Method 300 in Figure 6 The main difference of the method 300' shown is that step S320 is performed first, and then step S310 is performed. Figure 4 The contents described in method 300 can be applied to Figure 6 Corresponding features of method 300' are shown.

[0102] like Figure 6 As shown in , the method 300 ′ for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include step S320 , step S310 , step S330 , and step S340 .

[0103] At step S320 , the multilayer printed circuit board 100 according to an embodiment of the present disclosure is attached to the semiconductor die 200 .

[0104] At step S310 , the semiconductor die 200 is attached to the carrier substrate 30 .

[0105] At step S330 , the pins 10 are inserted into the pin holders 110 of the multi-layer printed circuit 100 .

[0106] At step S340, the carrier substrate 30, the semiconductor die 200 and the multi-layer printed circuit board 100 are molded or potted with epoxy resin to form a housing 50, thereby obtaining a packaged power module.

[0107] Figure 5E The power module according to one or more embodiments of the present disclosure is schematically shown. The power module can be, for example, Figure 4 The interconnect pins and the semiconductor die are fabricated by a method 300, or by Figure 6 A method 300 ′ of manufacturing interconnect pins and a semiconductor die is shown.

[0108] like Figure 5E As shown, the power module may include: a carrier substrate 30; a semiconductor die 200, which is arranged on the carrier substrate 30; a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure, which is arranged on the semiconductor die 200 and electrically coupled to the semiconductor die 200 through its die contacts; a housing 40, which encapsulates the carrier substrate 30, the semiconductor die 200 and the multilayer printed circuit board 100; and pins 10, which are inserted into pin holders in the multilayer printed circuit board 100 and exposed from one side of the housing 50.

[0109] Fig. 7A FIG. 1 shows a schematic three-dimensional model of a power module according to an embodiment of the present disclosure. Fig. 7A , shows a packaged power module, wherein the pins 10 are exposed from one side of the housing 50 for further coupling to the main circuit board.

[0110] Figure 7B Shows Fig. 7A A perspective view of a portion of a multilayer printed circuit board used to interconnect pins and semiconductor die in a power module. Figure 7B, showing the pin 10, the pin holder 110, the auxiliary connection 140 and the flange interconnection 146, and also showing the gate contact 120a and the source contact 120b used as the die contact.

[0111] Figure 7C Shows Fig. 7A A bottom view of a multi-layer printed circuit board used to interconnect pins and semiconductor dies in a power module. Figure 7C As shown in the figure, the multilayer printed circuit board according to an embodiment of the present disclosure includes a source-substrate contact 120c, a gate-substrate contact 120d, a source pad contact 120e and a gate pad contact 120f exposed from its bottom substrate layer and serving as a die contact, and a negative temperature coefficient contact 170 exposed from an opening of the bottom substrate layer.

[0112] Those skilled in the art will understand that the above 7A to 7C The modeling model shown is only for facilitating those skilled in the art to better understand the technical concept of the present invention, and is not intended to constitute any limitation.

[0113] The words "front", "rear", "top", "bottom", "above", "below", etc., if present, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0114] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0115] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0116] In addition, the foregoing description may have referred to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically or otherwise. Similarly, unless otherwise expressly stated, "coupling" means that one element / node / feature can be mechanically, electrically, logically or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly connected. In other words, "coupling" is intended to include direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0117] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0118] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0119] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0120] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0121] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multilayer printed circuit board for interconnecting pins and semiconductor dies, characterized in that: include: A multi-layer substrate, comprising a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each substrate layer being composed of an insulating material; Pin holders embedded in the multi-layer substrate, one end of each pin holder exposed from the top surface of the top substrate layer for plugging a pin in the pin holder; die contacts embedded in the multi-layer substrate, one end of each die contact exposed from the bottom surface of the bottom substrate layer for electrical coupling with a contact of a semiconductor die; as well as The first interconnect structures are embedded in the multi-layer substrate, and each of the first interconnect structures is connected between a corresponding pin holder and a corresponding die contact to electrically couple the two.

2. The multilayer printed circuit board according to claim 1, characterized in that: Each pin holder includes: a tubular cavity extending in a direction perpendicular to the multi-layer substrate and adapted to receive one end of a pin therein; and A first flange is disposed at one end of the tubular cavity and protrudes laterally relative to the tubular cavity, and the first flange is disposed on a top surface of the top substrate layer.

3. The multilayer printed circuit board according to claim 2, characterized in that: Also includes: auxiliary connectors embedded in the multi-layer substrate and extending in a direction perpendicular to the multi-layer substrate, one end of each auxiliary connector being electrically coupled to a corresponding pin holder and the other end being electrically connected to a corresponding die contact, Wherein, each auxiliary connecting piece comprises: a columnar body extending in a direction perpendicular to the multi-layer substrate; and The second flange is arranged at one end of the columnar body and protrudes laterally relative to the columnar body.

4. The multilayer printed circuit board according to claim 3, characterized in that: Also includes: The flange interconnecting members are each connected between the second flange of the corresponding auxiliary connecting member and the corresponding pin holder to electrically couple the two.

5. The multilayer printed circuit board according to claim 4, characterized in that: in, The auxiliary connector comprises a first auxiliary connector, a second flange of the first auxiliary connector and a flange interconnector connected thereto are arranged between the top substrate layer and an adjacent core substrate layer; and The flange interconnector connected to the second flange of the first auxiliary connector is also connected to the tubular cavity of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the first auxiliary connector.

6. The multilayer printed circuit board according to claim 5, characterized in that: in, The second flange of the first auxiliary connecting member and the corresponding flange interconnecting member connected to each other are integrally formed by the same layer of metal.

7. The multilayer printed circuit board according to claim 4, It is characterized in that wherein the auxiliary connector comprises a second auxiliary connector, a second flange of the second auxiliary connector and a flange interconnector connected thereto are arranged on the top surface of the top substrate layer; and The flange interconnector connected to the second flange of the second auxiliary connector is also connected to the first flange of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector.

8. The multilayer printed circuit board according to claim 7, characterized in that: in, The second flange of the second auxiliary connecting member, the corresponding flange interconnecting member, and the first flange of the corresponding pin holder, which are connected to each other, are integrally formed by the same layer of metal.

9. The multilayer printed circuit board according to claim 1, characterized in that: Also includes: Second interconnect structures are embedded in the multi-layer substrate, each of the second interconnect structures is connected between at least two die contacts to electrically couple the at least two die contacts.

10. The multilayer printed circuit board according to claim 9, characterized in that: in, At least a portion of the first interconnect structure, the second interconnect structure and / or the die contacts are formed by a thick copper damascene process.

11. The multilayer printed circuit board according to claim 1, characterized in that: Also includes: buried spacers, each buried spacer extending from a bottom surface of the top substrate layer, through the one or more core substrate layers and the bottom substrate layer, and extending beyond the bottom surface of the bottom substrate layer by a first length, The first length depends on the thickness of the semiconductor die.

12. The multilayer printed circuit board according to claim 11, characterized in that: in, The first length is equal to the sum of the thickness of the semiconductor die and the thickness of a die attach layer, the die attach layer being used to attach the semiconductor die to the multi-layer printed circuit board.

13. The multilayer printed circuit board according to claim 1, characterized in that: Also includes: A negative temperature coefficient contact is embedded in the multi-layer substrate, the negative temperature coefficient contact being exposed from an opening disposed at a central portion of the bottom substrate layer for coupling to a negative temperature coefficient sensor.

14. The multilayer printed circuit board according to any one of claims 1 to 13, characterized in that: in, The die contacts include thick copper contacts and / or thin copper contacts; and Wherein, the die contact is used as one or more of the following: a gate-substrate contact, a source-substrate contact, a gate pad contact, and / or a source pad contact.

15. A pin, characterized in that: include: A rod-shaped body, the first end of which is pointed and is suitable for being inserted into the pin holder, and the second end of which includes an elastic portion and is suitable for being inserted into the through hole; as well as a stopper, which is arranged at a position of the rod-shaped body at a certain distance from the first end and protrudes laterally relative to the rod-shaped body, wherein the pin is adapted to be mounted in a pin holder in a multilayer printed circuit board as claimed in any one of claims 2 to 14, and When the first end of the pin is inserted into the pin holder, the stopper abuts against the first flange of the pin holder.

16. A power module, characterized in that: include: A carrier substrate; a semiconductor die attached to the carrier substrate; The multilayer printed circuit board according to any one of claims 1 to 14, attached to the semiconductor die and electrically coupled to the semiconductor die through die contacts of the multilayer printed circuit board; A housing encapsulating the carrier substrate, the semiconductor die and the multi-layer printed circuit board; as well as The pins are inserted into the pin holders in the multilayer printed circuit board and exposed from one side of the housing.

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