Memory cell and integrated device

Abstract

The utility model relates to a memory unit and an integrated device. The memory unit comprises a channel layer which is arranged on a substrate and extends along the vertical direction. A floating gate is disposed over the substrate and separated from the channel layer along a first lateral direction by a gate dielectric. The control gate is disposed on one side of the floating gate and the channel layer along a first lateral direction, and is separated from the floating gate by a tunneling dielectric. The source / drain terminal pair is arranged on the other side, opposite to the control gate, of the channel layer and the floating gate.

Description

Technical Field

[0001] The embodiments of the utility model relate to a memory unit and an integrated device. Background Art

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be either volatile or non-volatile. Non-volatile memory retains its stored data when power is removed, whereas volatile memory loses its stored data when power is removed. Flash memory is a type of non-volatile memory that uses electrons tunneling in and out of a floating gate to change the threshold voltage of a memory cell. The tunneling of electrons is induced by applying a programming voltage or an erase voltage to the control gate. Utility Model Content

[0003] One aspect of the utility model provides a memory cell. The memory cell includes: a channel layer, a floating gate, a control gate, and a source / drain terminal pair. The channel layer is arranged on a substrate and extends along a vertical direction perpendicular to the surface of the substrate. The floating gate is arranged on the substrate and is separated from the channel layer by a gate dielectric along a first lateral direction perpendicular to the vertical direction. The control gate is arranged on one side of the floating gate and the channel layer along the first lateral direction and is separated from the floating gate by a tunneling dielectric. The source / drain terminal pair is arranged on the other side of the channel layer and the floating gate opposite to the control gate.

[0004] Another aspect of the utility model provides an integrated device. The integrated device includes: a channel layer, a gate dielectric, a first floating gate, a first control gate, a second floating gate and a second control gate. The channel layer is arranged on a substrate and extends along a vertical direction perpendicular to the surface of the substrate. The gate dielectric is arranged on one side of the channel layer and extends along a first sidewall of the channel layer. The first floating gate is arranged in a first memory cell region adjacent to the gate dielectric and is separated from the channel layer by the gate dielectric. The first control gate is arranged on a side of the first floating gate opposite to the channel layer and is separated from the first floating gate by a first tunneling dielectric. The second floating gate is stacked on the first floating gate, is also arranged adjacent to the gate dielectric and is separated from the channel layer by the gate dielectric. The second control gate is arranged on a side of the second floating gate opposite to the channel layer and is separated from the second floating gate by a second tunneling dielectric.

[0005] Another aspect of the present invention provides a method for forming an integrated device. The method includes: forming a first source / drain precursor layer, a gate precursor layer, and a second source / drain precursor layer stacked one on top of another and separated by an interlayer dielectric (ILD) layer on a substrate; forming a vertical trench that separates the first source / drain precursor layer, the gate precursor layer, and the second source / drain precursor layer into a first side and a second side in a lateral direction; forming a floating gate, a gate dielectric, and a channel layer in the vertical trench; and patterning the first source / drain precursor layer, the gate precursor layer, and the second source / drain precursor layer to form a first dummy source / drain terminal, a control gate, and a second dummy source / drain terminal on a first side, and forming a first source / drain terminal, a dummy control gate, and a second source / drain terminal on a second side.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 3D views of some embodiments of memory devices having stackable memory cells.

[0008] Figures 2 to 7 A series of cross-sectional views of some embodiments of methods of forming a memory device having stackable memory cells.

[0009] Figure 8 Flowcharts of some embodiments of methods of forming a memory device having stackable memory cells.

[0010] Fig. 9 3D views of some further embodiments of memory devices having stacked memory cells.

[0011] Fig.10 3D views of some additional embodiments of memory devices having stacked memory cells.

[0012] Figures 11 to 23 A series of 3D views of some further embodiments of methods of forming a memory device having stackable memory cells.

[0013] Figures 24 to 33 A series of 3D views of some further embodiments of methods of forming a memory device having stackable memory cells. DETAILED DESCRIPTION

[0014] The present invention provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed by itself.

[0015] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Flash memory consists of memory cells with floating gate transistors, each of which includes a control gate configured to control the flow of current in a channel layer between a source terminal and a drain terminal, and a floating gate disposed between the control gate and the channel layer. Each memory cell stores one or more bits of information as a charge in the floating gate. The floating gate is isolated from the rest of the circuit by an insulating layer, and the floating gate is programmed by applying a programming voltage to the control gate, which causes electrons to tunnel through the insulating layer and become trapped in the floating gate. Erasing flash memory involves removing the charge from the floating gate. An erase voltage can be applied to the control gate, which causes electrons to tunnel back through the insulating layer back to the source. To read the data stored in the memory cell, a read voltage is applied to the control gate, and the resulting current is measured. Whether the current is high or low depends on a larger or smaller threshold voltage based on whether the floating gate is charged, thus representing a 1 bit or a 0 bit, respectively. As the size of flash memory decreases, smaller and denser memory cells are needed. Furthermore, as different logic architectures are developed, such as fin field effect transistors (FinFETs) and gate-all-around field effect transistors (GAA-FETs), it becomes increasingly difficult to use the same processes used to manufacture logic devices to manufacture memory cells.

[0017] In summary, the utility model provides a technology for forming a flash memory with stackable memory cells and a related manufacturing method. The flash memory is integrated in the back-end of line (BEOL) process. Compared with the traditional memory device that integrates the memory cell and the logic component in the front-end of line (FEOL) process on the same substrate, embedding the memory cell in the BEOL process will reduce the chip size, greatly improve the component density per chip area, and also provide process flexibility for other FEOL components. In some embodiments, the flash memory includes a memory cell, and the memory cell includes a channel layer and a floating gate disposed on a substrate separated by a gate dielectric and extending in a vertical direction perpendicular to the surface of the substrate. The control gate is disposed on one side of the floating gate and the channel layer, and is separated from the floating gate by a tunneling dielectric. The source / drain terminal pair is disposed on the other side of the channel layer and the floating gate opposite to the control gate. By arranging the channel layer along the vertical direction and arranging the control gate and the source / drain terminal pair on opposite sides of the floating gate and the channel layer along the first lateral direction, additional memory cells can be stacked along the vertical direction while sharing the channel layer, thereby realizing a compact memory cell array with a greater cell density. The following description, in association with the accompanying drawings, provides more detailed embodiments and examples of the structure and manufacturing method of a memory device including memory cells that can be stacked in the vertical direction.

[0018] Figure 1 3D views of some embodiments of memory devices having stackable memory cells. Figure 1 As shown, the memory cell 104 is disposed in a plurality of interlayer dielectric (ILD) layers 106 on a substrate 102. The substrate 102 may be any type of substrate (e.g., including a semiconductor body) and / or an epitaxial layer (e.g., silicon, silicon germanium (SiGe), silicon on insulator (SOI), or the like). The ILD layer 106 may be a dielectric material or may be composed of a dielectric material, such as silicon dioxide (SiO 2 ) or the like. In some embodiments, FEOL components (e.g., logic components), plugs, and one or more lower interconnects (e.g., conductive contacts, interconnect vias, and / or interconnects connected to the logic components) may be disposed between substrate 102 and memory cell 104. The logic components may be or include metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), nanosheet field effect transistors, the like, or any combination of the foregoing. Using BEOL processes to form memory devices creates a more flexible integrated circuit design that can take advantage of continued advances in transistor technology.

[0019] In some embodiments, the memory cell 104 includes a channel layer 116 extending along a vertical direction 216. In some embodiments, the vertical direction 216 is defined as a direction perpendicular to the upper surface of the substrate 102, and other FEOL components (e.g., logic components coupled to the memory cell) are disposed on the substrate 102 along the upper surface of the substrate 102. In some embodiments, the channel layer 116 is or includes an oxide semiconductor (OS) material, such as indium gallium zinc oxide (InGaZnO), indium oxide (InO), indium tin oxide (InSnO), indium zinc oxide (InZnO), indium tungsten oxide (InWO), etc. The floating gate 112 is disposed on the substrate 102 and separated from the channel layer 116 by the gate dielectric 114 along a first lateral direction 212. The first lateral direction 212 is perpendicular to the vertical direction 216 and is in the plane of the upper surface of the substrate 102. The floating gate 112 is, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum alloy (TiAl), heavily doped polysilicon, a combination of the foregoing, or the like, or the floating gate 112 is composed of, for example, TiN, TaN, TiAl, heavily doped polysilicon, a combination of the foregoing, or the like.

[0020] The control gate 108 is disposed on one side of the floating gate 112 and the channel layer 116. For example, the control gate 108 can be disposed at a first side 126, such as a left side of the channel layer 116 and the floating gate 112 along a first lateral direction 212. The control gate 108 can be separated from the floating gate 112 by a tunnel dielectric 110. In some embodiments, the floating gate 112 has a first sidewall and a second sidewall separated in the first lateral direction 212. The tunnel dielectric 110 and the control gate 108 are closer to the first sidewall than the second sidewall. The gate dielectric 114 can directly contact the second sidewall. In some embodiments, the tunnel dielectric 110 is or includes, for example, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a combination of the foregoing, or one of the like.

[0021] A pair of source / drain terminals 118a, 118b are disposed on the other side of the channel layer 116 and the floating gate 112 opposite to the control gate 108. For example, the pair of source / drain terminals 118a, 118b can be disposed on the second side 128, such as the right side of the channel layer 116 and the floating gate 112 along the first side direction 212. In some embodiments, the source / drain terminal 118 or the control gate 108 is, for example, titanium nitride (TiN), tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel silicide (NiSi), a combination thereof, or the like, or the source / drain terminal 118 or the control gate 108 is composed of, for example, titanium nitride (TiN), tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel silicide (NiSi), a combination thereof, or the like.

[0022] In some embodiments, the gate contact 138 is disposed on an upper surface of the control gate 108 at the first side 126. The first source / drain contact 140a is disposed on an upper surface of a first source / drain terminal 118a of a pair of source / drain terminals, and the second source / drain contact 140b is disposed on an upper surface of a second source / drain terminal 118b of the pair of source / drain terminals. The gate contact 138, the first source / drain contact 140a, and the second source / drain contact 140b are laterally offset from each other and extend upward along the vertical direction 216. In some embodiments, the gate contact 138, the first source / drain contact 140a, and the second source / drain contact 140b are offset in a first lateral direction, in a second lateral direction, or in both a first lateral direction and a second lateral direction. In some embodiments, the gate contact 138, the first source / drain contact 140a, and the second source / drain contact 140b can extend and couple to an interconnection machine of a single metal layer. In other embodiments, one or more of the gate contact 138 , the first source / drain contact 140 a , and the second source / drain contact 140 b may be extended and coupled to interconnects at different metal layers to obtain more flexible routing.

[0023] The control gate 108, tunneling dielectric 110, and floating gate 112 may function as a metal-insulator-metal (MIM) capacitor to provide charge storage. The transfer of electrons between the control gate 108 and the floating gate 112 through the tunneling dielectric 110 produces a memory cell 104 with a more flexible design than a memory cell that transfers electrons between a channel layer and a floating gate. For example, by reducing the size of the control gate 108 and the tunneling dielectric 110, the memory cell 104 may have a lower programming voltage because the capacitance of the MIM capacitor is thereby reduced. In addition, in some embodiments, the gate dielectric 114 may be or consist of a ferroelectric material, which may be used to store polarization of an electric field. The stored polarization helps retain charge in the floating gate 112, thereby improving the preservation of the memory cell 104.

[0024] In some embodiments, a dummy control gate 108' is disposed on the second side 128 and vertically between the pair of source / drain terminals 118a, 118b. In addition, a pair of dummy source / drain terminals 118'a, 118'b may be disposed on the first side 126 and vertically separated by the control gate 108. For example, the dummy control gate 108' and the dummy tunneling dielectric 110' may be disposed on the other side of the channel layer 116 opposite the floating gate 112, the tunneling dielectric 110, and the control gate 108. The pair of dummy source / drain terminals 118'a, 118'b are disposed on the other side of the floating gate 112 opposite the channel layer 116 and the pair of source / drain terminals 118a, 118b.

[0025] In some embodiments, the dummy control gate 108' and the pair of dummy source / drain terminals 118'a and 118'b are made of different conductive materials. For example, the dummy control gate 108' may be made of the same conductive material as the control gate 108, such as nickel (Ni). The pair of dummy source / drain terminals 118'a, 118'b may be made of the same conductive material as the pair of source / drain terminals 118a, 118b, such as titanium nitride (TiN). In some other embodiments, the dummy control gate 108' and the pair of dummy source / drain terminals 118'a, 118'b are made of different semiconductor materials. For example, the dummy control gate 108' may be silicon germanium or consist of silicon germanium, and the pair of dummy source / drain terminals 118'a, 118'b may be silicon or consist of silicon, or vice versa.

[0026] During operation, when a programming or erasing voltage is applied to the MIM capacitor, charge can be stored in or removed from the floating gate 112, and 1 bit of information is represented by being in a "0" state or a "1" state. Providing a programming voltage (e.g., in a "programming" operation) or an erasing voltage (e.g., in an "erase" operation) at the control gate 108 can change the state of the memory cell from a "0" state to a "1" state or from a "1" state to a "0" state, respectively. The charge stored in the floating gate 112 is changed by electrons tunneling in and out of the floating gate 112 through the tunneling dielectric 110.

[0027] The charge changes the threshold voltage of the memory cell, thereby changing whether current is detected through the channel layer 116 during a "read" operation. For example, when a programming voltage is applied to the control gate 108, electrons are drawn from the floating gate 112, causing the floating gate 112 to be positively charged, thereby setting the memory cell to a first threshold value. When an erase voltage is applied to the control gate 108, electrons are pushed into the floating gate 112, causing the floating gate 112 to be negatively charged, thereby raising the voltage threshold of the memory cell 104 to a second threshold value that is higher than the first threshold value. The read voltage is set between the first threshold value and the second threshold value. When the read voltage is applied to the control gate 108 during a "read" operation, if the memory cell 104 is in a first state having a first threshold value, current flows through the channel layer 116, indicating that the memory cell is in the first state (e.g., "1"). If the memory cell 104 is in the second state with the second threshold, no current or a small current flows through the channel layer 116, indicating that the memory cell is in the second state (e.g., "0"). The read voltage can be less than the programming voltage to not write to the memory cell 104, but greater than the voltage threshold to turn on the channel layer 116.

[0028] Figures 2 to 7 A series of cross-sectional views of some embodiments of methods of forming a memory device having stackable memory cells. Figures 2 to 7 Described as a series of actions, it should be understood that these actions are not restrictive, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0029] like Figure 2As shown, in some embodiments, a stack of source / drain precursor layers 132 (e.g., 132-1, 132-2) and a gate precursor layer 134 is formed in an ILD layer 106 on a substrate 102. The substrate 102 may be any type of substrate (e.g., including a semiconductor body) and / or an epitaxial layer (e.g., silicon, SiGe, silicon on insulator (SOI) or the like). In some embodiments, a FEOL component (e.g., a logic component), a plug, and one or more lower interconnects (e.g., a conductive contact, an interconnect via, and / or an interconnect connected to a logic component) may be formed on the substrate 102 before forming the stack of source / drain precursor layers 132 (e.g., 132-1, 132-2) and a gate precursor layer 134. The stack of source / drain precursor layers 132 (e.g., 132-1, 132-2) and gate precursor layer 134 may be formed by a series of deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. Multiple dielectric material depositions may be performed between forming source / drain precursor layers 132 (e.g., 132-1, 132-2) and gate precursor layer 134 to form the ILD layer 106. The source / drain precursor layers 132 (e.g., 132-1, 132-2) and gate precursor layer 134 are made of different metals or other conductive materials. For example, the source / drain precursor layer 132 (e.g., 132-1, 132-2) can be a first metal material (e.g., titanium nitride (TiN)) or composed of a first metal material (e.g., TiN), and the gate precursor layer 134 can be a second metal material (e.g., nickel (Ni)) or composed of a second metal material (e.g., Ni). Other candidate materials for the source / drain precursor layer 132 (e.g., 132-1, 132-2) or the gate precursor layer 134 can include, for example, one of tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), heavily doped silicon, a combination of the foregoing, or the like. The first metal material and the second metal material can be selected so that the etching selectivity is high (e.g., 10:1 or higher), so that during a subsequent process of recessing the gate precursor layer 134, one metal is etched preferentially over the other metal. As another option, the source / drain precursor layer 132 (e.g., 132-1, 132-2) and the gate precursor layer 134 are semiconductor or non-conductive or have a high etching selectivity, so that the gate precursor layer 134 can be selectively recessed to form a gate dielectric, a floating gate and / or other structures. For example, the gate precursor layer 134 can be formed of silicon germanium, and the source / drain precursor layer 132 can be formed of silicon, or vice versa.

[0030] like Figure 3As shown, in some embodiments, a vertical trench 130 is formed through the ILD layer 106, and the vertical trench 130 laterally separates the stack of source / drain precursor layers 132 (e.g., 132-1, 132-2) and gate precursor layers 134 to form a control gate 108 and a pair of dummy source / drain terminals 118'a, 118'b on the first side 126, and a dummy control gate 108' and a pair of source / drain terminals 118a, 118b on the second side 128. The vertical trench 130 can be performed by a series of etching processes with the mask 129 in place. Although not shown in the figure, an etch stop layer can be formed over the FEOL component or one or more lower interconnects so that the series of etching processes can stop on the etch stop layer.

[0031] like Figure 4 As shown, in some embodiments, the tunneling dielectric 110 is formed on a first side 126 in contact with the control gate 108. In some embodiments, a dummy tunneling dielectric 110' is also formed on a second side 128 in contact with the dummy control gate 108'. The tunneling dielectric 110 and the dummy tunneling dielectric 110' can be formed, for example, of silicon nitride or other suitable dielectric materials. The tunneling dielectric 110 and the dummy tunneling dielectric 110' can be formed by first performing an etch to form a recess on the control gate 108, forming a tunneling dielectric precursor, and performing an etch to remove excess portions of the tunneling dielectric precursor and leaving the tunneling dielectric 110 and the dummy tunneling dielectric 110' in place.

[0032] like Figure 5 As shown, in some embodiments, a floating gate 112, a gate dielectric 114, and a channel layer 116 are formed in the vertical trench. The floating gate 112, the gate dielectric 114, and the channel layer 116 can be formed by a series of deposition processes to fill the vertical trench 130 and then a vertical etching process to remove part of the vertical trench 130.

[0033] like Figure 6 As shown, in some embodiments, a "staircase" structure is formed to prepare for forming gate contacts and source / drain contacts. As an example, at the first side 126, the upper dummy source / drain terminal 118'b can be etched to shorten so that the upper surface of the control gate 108 can be exposed to the contact trench. Similarly, at the second side 128, the upper source / drain terminal 118b and the dummy control gate 108' can be etched to shorten so that the upper surface of the lower source / drain terminal 118a can be exposed to the contact trench.

[0034] like Figure 7As shown, in some embodiments, a gate contact 138 is formed through the ILD layer 106 to reach the upper surface of the control gate 108. Source / drain contacts 140a, 140b are formed through the ILD layer 106 and reach the upper surfaces of the lower source / drain terminal 118a and the upper source / drain terminal 118b, respectively.

[0035] Figure 8 A method 800 of forming a BEOL memory cell according to some embodiments is illustrated. Although this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it should be understood that the present invention is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0036] At act 802 , in some embodiments, a stack of source / drain precursor layers and a gate precursor layer is formed over a substrate. Figure 2 An example of forming a stack of source / drain precursor layers and gate precursor layers is provided. Fig.11 and Fig.24 Additional examples of forming a stack of source / drain precursor layers and gate precursor layers to form a stacked memory cell with a separate floating gate and a shared channel layer are also provided.

[0037] At act 804 , in some embodiments, a vertical trench is formed through the ILD layer, and the vertical trench laterally separates the stack of source / drain precursor layers and gate precursor layers into a first side and a second side. Figure 3 An example of forming a vertical groove is provided. In addition, the following Fig.12 and Fig.25 Additional examples of forming vertical trenches to separate stacks of source / drain precursor layers and gate precursor layers for stacked memory cells with separate floating gates and a shared channel layer are also provided.

[0038] At act 806, in some embodiments, a tunneling dielectric is formed on the first side in contact with the gate precursor layer. In some embodiments, a dummy tunneling dielectric is also formed on the second side in contact with the gate precursor layer. Figure 4 An example of forming a tunneling dielectric is provided. In addition, the following Figures 13 to 16 and Figure 26 to Figure 28 Additional examples of forming a tunneling dielectric for stacked memory cells having separate floating gates and a shared channel layer are also provided.

[0039] At act 808, in some embodiments, a floating gate, a gate dielectric, and a channel layer are formed within the vertical trench. Figure 5 Examples of forming a floating gate, a gate dielectric, and a channel layer in a vertical trench are provided. In addition, the following Figures 17 to 21 and Figure 28 to Figure 32 Additional examples of forming separate floating gates and a shared channel layer for stacked memory cells are also provided.

[0040] In some embodiments, contacts and interconnects are formed for the control gate and source / drain terminals at act 810. A "staircase" structure may be formed for the control gate, source / drain terminals, and / or corresponding dummy structures so that a gate contact may be formed to the control gate, and a source / drain contact may be formed to the source / drain terminals. Figure 6 to Figure 7 Examples of exposing the upper surfaces of the control gate and source / drain terminals and forming contacts on these upper surfaces are provided, respectively. Figure 22 to Figure 23 and Fig.33 Additional examples of forming contacts for the control gates and source / drain terminals of stacked memory cells are also provided.

[0041] Fig. 9 and Fig.10 3D views of some further embodiments of memory devices with stacked memory cells are shown. Figures 1 to 7 The memory cells 104 described may be stacked one after another on the substrate 102. In some embodiments, the stacked memory cells may each have a control gate and source / drain terminals disposed on opposite sides of a shared channel layer, and may have a floating gate separated from the shared channel layer by a shared gate dielectric. As described in more detail below, in some embodiments, the floating gates each extend from a recess of the control gate and are separated from the control gate by a tunnel dielectric. For simplicity, in Fig. 9 and Fig.10 The first memory cell 104a and the second memory cell 104b are shown in other subsequent figures, however, more similar memory cells may be stacked to realize a memory device with a higher cell density and reduced size.

[0042] like Fig. 9 As shown, in some embodiments, the channel layer 116 extends along the vertical direction 216. The gate dielectric 114 is disposed on one side of the channel layer 116 and extends along the first sidewall of the channel layer 116. In some embodiments, the gate dielectric 114 may also extend to the bottom surface of the channel layer 116. Fig. 9As shown, the gate dielectric 114 can cover a portion of the bottom surface of the channel layer 116. As another option, the gate dielectric 114 can cover the entire bottom surface of the channel layer 116. The gate dielectric 114 can be a conformal liner. For example, the gate dielectric 114 can be silicon oxide or consist of silicon oxide.

[0043] In some embodiments, the first floating gate 112a of the first memory cell 104a and the second floating gate 112b of the second memory cell 104b are disposed adjacent to the gate dielectric 114 and separated from the channel layer 116 by the gate dielectric 114. The second floating gate 112b may be stacked on the first floating gate 112a and spaced apart from the first floating gate 112a. In some embodiments, the first floating gate 112a and the second floating gate 112b are or consist of a bump-shaped conductive member having a convex sidewall contacting the gate dielectric 114, respectively. In some embodiments, the gate dielectric 114 includes a first portion and a second portion, the first portion and the second portion lining and contacting the convex sidewalls of the first floating gate 112a and the second floating gate 112b, respectively, and connected by an intermediate portion disposed between the first floating gate 112a and the second floating gate 112b. The middle portion may be a first sidewall vertically aligned with the first sidewalls of the first floating gate 112 a and the second floating gate 112 b, or the middle portion may consist of a first sidewall vertically aligned with the first sidewalls of the first floating gate 112 a and the second floating gate 112 b. The first sidewalls of the first floating gate 112 a and the second floating gate 112 b may be a planar portion directly contacting the vertical sidewalls of the ILD layer 106, or the first sidewalls of the first floating gate 112 a and the second floating gate 112 b may consist of a planar portion directly contacting the vertical sidewalls of the ILD layer 106.

[0044] In some embodiments, the first control gate 108a is disposed on a side (e.g., the first side 126) of the first floating gate 112a opposite to the channel layer 116, and is separated from the first floating gate 112 by the first tunnel dielectric 110a. The second control gate 108b is disposed on a side (e.g., the first side 126) of the second floating gate 112b opposite to the channel layer 116, and is separated from the second floating gate 112b by the second tunnel dielectric 110b. The first floating gate 112a and the second floating gate 112b may include straight sidewalls contacting the first tunnel dielectric 110a and the second tunnel dielectric 110b, respectively. In some embodiments, the first floating gate 112a and the second floating gate 112b include protrusions extending from the first sidewall toward the first tunnel dielectric 110a and the second tunnel dielectric 110b, respectively. The protrusion of the first floating gate 112a, the first tunnel dielectric 110a, and the first control gate 108a may have coplanar upper and bottom surfaces and coplanar sidewall surfaces along the first lateral direction 212. The protrusion of the first floating gate 112a, the first tunnel dielectric 110a, and the first control gate 108a may also have equal sizes along the second lateral direction 214 and the vertical direction 216. Similarly, the protrusion of the second floating gate 112b, the second tunnel dielectric 110b, and the second control gate 108b may have coplanar upper and bottom surfaces and coplanar sidewall surfaces along the first lateral direction 212, and may also have equal sizes along the second lateral direction 214 and the vertical direction 216.

[0045] In some embodiments, the first pair of source / drain terminals 118a, 118b are disposed on the other side (e.g., the second side 128) of the channel layer 116 opposite to the first floating gate 112a. The second pair of source / drain terminals 118c, 118d are disposed on the other side (e.g., the second side 128) of the channel layer 116 opposite to the second floating gate 112b. In some embodiments, the first dummy control gate 108'a and the second dummy control gate 108'b may be disposed on the second side 128 between the first pair of source / drain terminals 118a, 118b and between the second pair of source / drain terminals 118c, 118d, respectively. The first dummy tunnel dielectric 110'a may be disposed on the second side 128 between the first dummy control gate 108'a and the channel layer 116. Similarly, the second dummy tunneling dielectric 110'b can be disposed on the second side 128 between the second dummy control gate 108'b and the channel layer 116. In some further embodiments, the floating gate residue 142 can be located between the channel layer 116 and the dummy tunneling dielectrics 110'a, 110'b. The floating gate residue 142, the dummy tunneling dielectrics 110'a, 110'b, and the dummy control gates 108'a, 108'b can respectively have coplanar top and bottom surfaces and coplanar sidewall surfaces along the first lateral direction 212, and can also have equal dimensions along the second lateral direction 214 and the vertical direction 216.

[0046] In some embodiments, a first gate contact 138a is disposed on an upper surface of a first control gate 108a at a first side 126. A first pair of source / drain contacts 140a, 140b are disposed on an upper surface of a first pair of source / drain terminals 118a, 118b at a second side 128. Similarly, a second gate contact 138b is disposed on an upper surface of a second control gate 108b at a first side 126. A second pair of source / drain contacts 140c, 140d are disposed on an upper surface of a second pair of source / drain terminals 118c, 118d at a second side 128. The gate contacts 138a, 138b and the source / drain contacts 140a-140d are laterally offset from one another and extend upwardly along a vertical direction 216. In some embodiments, the gate contacts 138a, 138b and the source / drain contacts 140a-140d are staggered in the first lateral direction 212, the second lateral direction 214, or both the first lateral direction 212 and the second lateral direction 214. In some embodiments, the gate contacts 138a, 138b and the source / drain contacts 140a-140d can extend and couple to interconnects of a single metal layer. In other embodiments, one or more of the gate contacts 138a, 138b and the source / drain contacts 140a-140d can extend and couple to interconnects of different metal layers for more flexible routing.

[0047] In some embodiments, a first dummy control gate 108'a may be disposed on the second side 128 and vertically disposed between the first pair of source / drain terminals 118a, 118b. A second dummy control gate 108'b may be disposed on the second side 128 and vertically disposed between the second pair of source / drain terminals 118c, 118d. The first pair of dummy source / drain terminals 118'a, 118'b may be disposed on the first side 126 and vertically separated by the first control gate 108a. In some embodiments, an additional dummy source / drain terminal 118'c may be disposed on the first side 126 below the second control gate 108b, while another dummy source / drain terminal may or may not be present above the second control gate 108b, so that the second gate contact 138b may be more flexibly arranged to reach the second control gate 108b.

[0048] In some embodiments, the dummy control gates 108'a, 108'b and the pair of dummy source / drain terminals 118'a-118'c are made of different materials. For example, the pair of dummy source / drain terminals 118'a-118'c can be or consist of the first set of semiconductor layers 122-1, 122-2, 122-3, and the semiconductor layers 122-1, 122-2, 122-3 are made of a first semiconductor material (e.g., silicon). The dummy control gates 108'a-108'b can be or consist of the second set of semiconductor layers 124-1, 124-2, and the second set of semiconductor layers 124-1, 124-2 are made of a second semiconductor material (e.g., silicon germanium), or vice versa.

[0049] like Fig.10 As shown, in some embodiments, in addition to the association Fig. 9In addition to the features described above, the pair of dummy source / drain terminals 118'a-118'c can be or consist of a set of source / drain precursor layers 132-1, 132-2, 132-3, which are made of the same first conductive material as the source / drain terminals 118a-118d, such as titanium nitride (TiN). The dummy control gates 108'a, 108'b can be or consist of a set of gate precursor layers 134-1, 134-2, which are made of the same second conductive material as the control gate 108, such as nickel (Ni). In some embodiments, the floating gates 112a and 112b may include three continuous bumps, respectively, and the middle bumps contact the tunnel dielectrics 110a and 110b. Some of the bumps may contact the source / drain precursor layers 132-1, 132-2, and 132-3. By forming the floating gates 112a and 112b that vertically extend beyond the tunnel dielectric 110 and even beyond the source / drain precursor layers 132-1, 132-2, and 132-3 (that is, the virtual source / drain terminals 118'a and 118'b to be formed), the volume of the floating gates 112a and 112b is enlarged, and more carriers can be stored in the floating gates 112a and 112b.

[0050] Figures 11 to 23 A series of 3D views of some further embodiments of methods of forming a memory device having stacked memory cells 104a, 104b. Figures 11 to 23 is described as corresponding to the formation and Fig. 9 However, it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0051] like Fig.11As shown, in some embodiments, a first set of semiconductor layers 122 (e.g., 122-1, 122-2, 122-3, 122-4) and a second set of semiconductor layers 124 (e.g., 124-1, 124-2)) are formed in an ILD layer 106 on a substrate 102. The substrate 102 may be any type of substrate (e.g., including a semiconductor body) and / or an epitaxial layer (e.g., silicon, SiGe, SOI, or the like). In some embodiments, FEOL components (e.g., logic components), plugs, and one or more lower interconnects (e.g., conductive contacts, interconnect vias, and / or interconnects connected to logic components) may be formed on the substrate 102 before forming the first set of semiconductor layers 122 and the second set of semiconductor layers 124. The semiconductor layers 122 and 124 may be formed by a series of deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. Multiple dielectric material depositions may be performed between forming the semiconductor layers 122, 124 to form the ILD layer 106. In some embodiments, the first set of semiconductor layers 122 and the second set of semiconductor layers 124 are different semiconductor materials with high etch selectivity, so that the second set of semiconductor layers 124 can be selectively recessed for subsequent formation of gate dielectrics, floating gates, and / or other structures. For example, the second set of semiconductor layers 124 can be formed of silicon germanium, while the first set of semiconductor layers 122 can be formed of silicon, or vice versa. In some embodiments, one or more mask layers may be formed to cover the semiconductor layers 122, 124 for patterning. For example, a first mask layer 144 made of metal and a second mask layer 146 made of dielectric may then be deposited. The first mask layer 144 may be, for example, TiN or composed of TiN. The second mask layer 146 may be, for example, SiN or composed of SiN.

[0052] like Fig.12 As shown, in some embodiments, a vertical trench 130 is formed through the ILD layer 106, and the vertical trench 130 laterally separates the semiconductor layers 122 and 124 on the first side 126 and the second side 128. The vertical trench 130 can be performed by a series of mask-in-place etching processes. An etch stop layer can be formed over the FEOL component or one or more lower interconnects, so that the series of etching processes can stop on the etch stop layer. The etching process can include, for example, a dry etching technique, which includes using tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ) or the like. The etching process may be performed using carbon tetrachloride (CCl 4 ), boron trichloride (BCl 3 ) for metal etching, or the etching process can be performed by using carbon tetrachloride (CCl4 ), boron trichloride (BCl 3 ) and other additional plasma etching for metal etching.

[0053] like Figures 13 to 16 As shown, in some embodiments, the tunnel dielectric 110 is formed on the first side 126 and contacts the second semiconductor layer 124, and the dummy tunnel dielectric 110' is formed on the second side 128 and contacts the second semiconductor layer 124. The tunnel dielectric 110 and the dummy tunnel dielectric 110' may be formed of, for example, silicon nitride or other suitable dielectric materials. Fig.13 As shown, in some embodiments, the tunnel dielectric 110 and the dummy tunnel dielectric 110' may be formed by first performing etching to form recesses 120a, 120b on the set of semiconductor layers 124. Then, as shown in FIG. Fig.14 As shown, in some embodiments, a tunneling dielectric precursor 111 is deposited to fill the recesses 120a, 120b. The tunneling dielectric precursor 111 may be formed by conformally depositing silicon nitride on the exposed surface of the workpiece. The tunneling dielectric precursor 111 may be performed, for example, by low pressure chemical vapor deposition (LPCVD). Fig.15 As shown, in some embodiments, a vertical etch may then be performed to remove the exposed portion of the tunneling dielectric precursor 111, leaving the portion of the tunneling dielectric precursor 111 in the recess 120a at the first side 126 as the tunneling dielectric 110, and leaving the portion of the tunneling dielectric precursor 111 in the recess 120b at the second side 128 as the dummy tunneling dielectric 110'. Fig.16 As shown, in some embodiments, the tunnel dielectric 110 and the dummy tunnel dielectric 110' are then recessed, leaving space for forming a floating gate.

[0054] like Figures 17 to 21 As shown, in some embodiments, a floating gate 112, a gate dielectric 114, and a channel layer 116 are formed in the vertical trench 130. The floating gate 112, the gate dielectric 114, and the channel layer 116 can be formed by a series of deposition processes for filling the vertical trench 130 and then a vertical etching process for partially removing the vertical trench 130.

[0055] For example, Fig.17 As shown, first, a floating gate precursor 113 is formed in the recesses of the tunnel dielectric 110 and the dummy tunnel dielectric 110'. The floating gate precursor 113 can be formed by conformally depositing a metal (e.g., TiN) on the exposed surface of the workpiece and then vertically etching to remove the exposed portion and the portion remaining in the recesses of the tunnel dielectric 110 and the dummy tunnel dielectric 110' as the floating gate precursor 113. Fig.18As shown, in some embodiments, selective metal deposition can be performed to further extend the floating gate precursor 113 as a separate component of the plurality of memory cells 104a, 104b. The floating gate precursor 113 can be formed with, for example, a curved convex surface within the trench 130, while the sidewall surface in contact with the sidewall of the vertical trench 130 can be a straight plane. The metal material for the floating gate precursor 113 can also be deposited on other structures (e.g., the first mask layer 144). As shown in FIG. Fig.19 As shown, a first filling structure 150 is formed in the trench 130, and then patterned to remove half of the floating gate precursor 113 close to the second side 128, and to form floating gates 112a, 112b spaced apart from each other. A first mask layer stack 148 may be used to expose half of the floating gate precursor 113 for a series of etching processes. As an example, the first mask layer stack 148 may include one or more of an organic material, a dielectric material, and a metal material. In some embodiments, the floating gate residue 142 may remain in the recess of the dummy tunnel dielectric 110' and / or the recess of the second set of semiconductor layers 124.

[0056] After forming the floating gates 112a and 112b, as shown in FIG. Fig. 20 As shown, a gate dielectric 114 is formed along the surface of the floating gates 112a and 112b. In some embodiments, the gate dielectric 114 may extend continuously over the surface of the floating gates 112a and 112b. The gate dielectric 114 may be a high-k dielectric material or may be composed of a high-k dielectric material, such as hafnium oxide (HFO). 2 ), aluminum oxide (Al 2 O 3 ), hafnium zirconium oxide (HfZrO), or the like. For example, in some embodiments, the gate dielectric 114 is conformally deposited on the exposed surface of the workpiece to line the sidewalls and bottom surface of the vertical trench 130. A second filling structure 154 is then formed in the remaining space of the vertical trench 130, and then a vertical etching is performed using the second mask layer stack 152 in place to remove the exposed portion of the gate dielectric 114. The second mask layer stack 152 may include one or more of an organic material, a dielectric material, and a metal material. Fig.21 As shown, the second mask layer stack 152 is removed. A channel layer 116 is formed in the remaining space of the trench 130. A planarization process (eg, a chemical mechanical planarization (CMP) process) is then performed.

[0057] like Fig. 22As shown, in some embodiments, a "staircase" structure is formed to prepare for forming gate contacts and source / drain contacts. As an example, on the first side 126, etching can be performed to remove or shorten the upper dummy source / drain terminals 118'b, 118'd, so that the upper surfaces of the semiconductor layers 124-1, 124-2 can be exposed to the contact trenches to be formed vertically. Similarly, on the second side 128, the semiconductor layers 122-2, 122-3, 122-4 and the dummy control gates 108'a, 108'b can be etched to shorten so that the upper surfaces of the semiconductor layers 122-1, 122-2, 122-3 can be exposed to the contact trenches to be formed vertically.

[0058] like Fig.23 As shown, in some embodiments, the control gates 108a, 108b and the source / drain terminals 118a, 118c can be formed by forming contact trenches, removing the semiconductor layers 124-1, 124-2, and filling with conductive materials. Gate contacts 138a, 138b are formed in the contact trenches through the ILD layer 106 and reach the upper surfaces of the control gates 108a, 108b. Source / drain contacts 140a-140d are formed in the contact trenches through the ILD layer 106 and reach the upper surfaces of the lower source / drain terminals 118a, 118c and the upper source / drain terminals 118b, 118d, respectively. The contacts 138a-138b and 140a-140d can extend and couple to interconnects of a single metal layer or to interconnects of different metal layers for more flexible wiring.

[0059] Figures 24 to 33 A series of 3D views of some further embodiments of methods of forming a memory device having stackable memory cells 104a, 104b. Figures 24 to 33 is described as corresponding to the formation and Fig.10 However, it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0060] like Fig.24As shown, in some embodiments, a stack of source / drain precursor layers 132 (e.g., 132-1, 132-2, 132-3, 132-4, 132-5...) and gate precursor layers 134 (e.g., 134-1, 134-2) is formed in the ILD layer 106 on the substrate 102. The stack of source / drain precursor layers 132 and gate precursor layers 134 can be formed by a series of deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable deposition processes. Multiple dielectric material depositions can be performed between forming the source / drain precursor layers 132 and the gate precursor layers 134 to form the ILD layer 106. The source / drain precursor layers 132 and the gate precursor layers 134 are made of different metals or other conductive materials. For example, the source / drain precursor layer 132 (e.g., 132-1, 132-2) can be a first metal material (e.g., TiN) or composed of a first metal material (e.g., TiN), and the gate precursor layer 134 can be a second metal material (e.g., Ni) or composed of a second metal material (e.g., Ni). Other candidate materials for the source / drain precursor layer 132 or the gate precursor layer 134 can include, for example, tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), heavily doped silicon, a combination of the foregoing, or one of the like. The first metal material and the second metal material can be selected so that the etching selectivity is high (e.g., 10:1 or higher), so that during the subsequent process of recessing the gate precursor layer 134, one metal is etched preferentially over the other metal.

[0061] like Fig.25 As shown, in some embodiments, a vertical trench 130 is formed through the ILD layer 106, and the vertical trench 130 laterally separates the source / drain precursor layer 132 and the gate precursor layer 134 on the first side 126 and the second side 128. The vertical trench 130 can be performed by a series of etching processes with a mask in place. An etch stop layer can be formed over the FEOL component or one or more lower interconnects, so that the series of etching processes can stop on the etch stop layer.

[0062] like Figure 26 to Figure 28 As shown, in some embodiments, the tunnel dielectric 110 is formed on the first side 126 in contact with the gate precursor layer 134, and the dummy tunnel dielectric 110' is formed on the second side 128 in contact with the gate precursor layer 134. Fig.26 As shown, in some embodiments, selective oxidation may be performed to form an oxide film on the source / drain precursor layer 132. Fig. 27As shown, in some embodiments, etching or a series of etching processes are performed to form recesses 120a, 120b on the gate precursor layer 134. By forming an oxide film before forming the recess, the source / drain precursor layer 132 is protected from being changed during the process of forming the recess. The oxide film can be removed by etching later.

[0063] Then, if Fig.28 As shown, a tunneling dielectric precursor is deposited to fill the recesses 120a, 120b, and then vertical etching is performed to remove the exposed portion of the tunneling dielectric precursor, leaving the portion of the tunneling dielectric precursor in the recess 120a on the first side 126 as the tunneling dielectric 110, and leaving the portion of the tunneling dielectric precursor in the recess 120b on the second side 128 as the dummy tunneling dielectric 110'. The tunneling dielectric 110 and the dummy tunneling dielectric 110' can be formed of, for example, silicon nitride or other suitable dielectric materials. In some embodiments, the tunneling dielectric 110 and the dummy tunneling dielectric 110' are then recessed, leaving space for forming a floating gate. Still as Fig.28 As shown, a floating gate precursor 113 is then formed in the recesses of the tunnel dielectric 110 and the dummy tunnel dielectric 110'. The floating gate precursor 113 can be formed by conformally depositing a metal (e.g., TiN) on an exposed surface of the workpiece, and then performing vertical etching to remove the exposed portion and the portion remaining in the recesses of the tunnel dielectric 110 and the dummy tunnel dielectric 110' as the floating gate precursor 113.

[0064] like Figure 29 to Figure 32 As shown, in some embodiments, a floating gate 112, a gate dielectric 114, and a channel layer 116 are formed in the vertical trench 130. The floating gate 112, the gate dielectric 114, and the channel layer 116 can be formed by a series of deposition processes for filling the vertical trench 130 and then a vertical etching process for partially removing the vertical trench 130. For example, Fig.29As shown, in some embodiments, the floating gate precursor 113 is extended by selective metal deposition from the floating gate precursor 113 and is also deposited on the source / drain precursor layer 132 (e.g., 132-1, 132-2, 132-3, 132-4, and 132-5). In this way, a plurality of conductive bumps are formed that contact the tunneling dielectric 110, the dummy tunneling dielectric 110', and the source / drain precursor layer 132, respectively. In some embodiments, a set of continuous conductive bumps (e.g., three conductive bumps extending from the lower and upper source / drain precursor layers 132 (e.g., 132-1 and 132-2 or 132-3 and 132-4) and the tunneling dielectric 110 therebetween) form the floating gate 112a or the floating gate 112b. By forming the floating gates 112a, 112b that vertically extend beyond the tunnel dielectric 110 and even beyond the respective lower and upper source / drain precursor layers 132 (i.e., the dummy source / drain terminals 118'a, 118'b to be formed), the volume of the floating gates 112a, 112b is enlarged and more carriers can be stored in the floating gates.

[0065] like Fig.30 As shown, a first filling structure 150 is formed in the trench 130 and then patterned to protect the floating gates 112a, 112b when removing half of the conductive bump near the second side 128, and to form the floating gates 112a, 112b spaced apart from each other. The first mask layer stack 148 can be used to expose half of the floating gate precursor 113 for a series of etching processes. As an example, the first mask layer stack 148 can include one or more of an organic material, a dielectric material, and a metal material.

[0066] like Fig.31 As shown, a gate dielectric 114 is formed along the surface of the floating gates 112a and 112b. In some embodiments, the gate dielectric 114 may extend continuously over the surface of the floating gates 112a and 112b. The gate dielectric 114 may be a high-k dielectric material or may be composed of a high-k dielectric material, such as hafnium oxide (HFO). 2 ), aluminum oxide (Al 2 O 3 ), hafnium zirconium oxide (HfZrO), or the like. For example, in some embodiments, the gate dielectric 114 is conformally deposited on the exposed surface of the workpiece to line the sidewalls and bottom surface of the vertical trench 130. A second filling structure 154 is then formed in the remaining space of the vertical trench 130, and then a vertical etching is performed using the second mask layer stack 152 in place to remove the exposed portion of the gate dielectric 114. The second mask layer stack 152 may include one or more of an organic material, a dielectric material, and a metal material. The second mask layer stack 152 is then removed. Fig.32As shown, a channel layer 116 is formed in the remaining space of the trench 130. A planarization process (eg, a chemical mechanical planarization (CMP) process) is then performed.

[0067] like Fig.33 As shown, in some embodiments, a "staircase" structure is formed to prepare for forming gate contacts and source / drain contacts. As an example, on the first side 126, etching can be performed to remove or shorten the dummy source / drain terminals 118'b-118'd so that the vertically formed first gate contact 138a can reach the upper surface of the first control gate 108a. Similarly, on the second side 128, the first dummy control gate 108'a and the source / drain terminal 118b can be etched to shorten them by a first distance so that the vertically formed first source / drain contact 140a can reach the upper surface of the source / drain terminal 118a. The source / drain terminal 118c can be etched to shorten them by a second distance so that the vertically formed second source / drain contact 140b can reach the upper surface of the source / drain terminal 118b. The second dummy control gate 108'b and the source / drain terminal 118d may be etched to shorten the third distance so that the third source / drain contact 140c formed vertically may reach the upper surface of the source / drain terminal 118c. The contacts 138a-138b and 140a-140d may extend and be coupled to interconnects of a single metal layer or to interconnects of different metal layers for more flexible wiring.

[0068] Therefore, the present invention relates to a BEOL flash memory structure including a stackable memory cell, the memory cell including a control gate and a source / drain terminal pair, the source / drain terminal pair being arranged on opposite sides of a channel layer extending in a vertical direction. By arranging the channel layer in a vertical direction, the memory cells can be easily stacked one after another, thereby achieving more compact integration to achieve a higher memory cell density. Examples of more specific details have been discussed in various embodiments of the present invention.

[0069] In some embodiments, the utility model relates to a memory cell. A channel layer is disposed on a substrate and extends along a vertical direction perpendicular to a surface of the substrate. A floating gate is disposed on the substrate and is separated from the channel layer by a gate dielectric along a first lateral direction perpendicular to the vertical direction. A control gate is disposed on one side of the floating gate and the channel layer along the first lateral direction and is separated from the floating gate by a tunnel dielectric. A source / drain terminal pair is disposed on the other side of the channel layer and the floating gate opposite to the control gate.

[0070] In some embodiments, the memory cell further comprises a dummy control gate and a dummy tunneling dielectric disposed on the other side of the channel layer opposite to the floating gate, the tunneling dielectric and the control gate. In some embodiments, the memory cell further comprises a pair of dummy source / drain terminals disposed on the other side of the floating gate opposite to the channel layer and the source / drain terminal pair. In some embodiments, the dummy control gate and the dummy source / drain terminal pair are made of different semiconductor materials. In some embodiments, the floating gate comprises three continuous bumps contacting the tunneling dielectric and the dummy source / drain terminal pair, respectively. In some embodiments, the memory cell further comprises: a first source / drain contact disposed on the upper surface of the first source / drain terminal of the source / drain terminal pair; and a second source / drain contact disposed on the upper surface of the second source / drain terminal of the source / drain terminal pair, wherein the first source / drain contact and the second source / drain contact are laterally offset from each other and extend upward in a vertical direction. In some embodiments, the control gate and the source / drain terminals extend along a first lateral direction parallel to the surface of the substrate and are separated from the substrate by an interlayer dielectric (ILD) layer. In some embodiments, the floating gate has a first sidewall and a second sidewall separated in a first lateral direction, the tunneling dielectric and the control gate are closer to the first sidewall than the second sidewall, the gate dielectric contacts the second sidewall; and the first sidewall is straight and the second sidewall is convex. In some embodiments, the gate dielectric comprises a ferroelectric material.

[0071] In some other embodiments, the utility model relates to an integrated device. A channel layer is disposed on a substrate and extends in a vertical direction perpendicular to a surface of the substrate. A gate dielectric is disposed on one side of the channel layer and extends in a vertical direction. A first floating gate is disposed in a first memory cell region adjacent to the gate dielectric and is separated from the channel layer by the gate dielectric. A first control gate is disposed on a side of the first floating gate opposite to the channel layer and is separated from the first floating gate by a first tunneling dielectric. A second floating gate is stacked on the first floating gate and is also disposed adjacent to the gate dielectric and is separated from the channel layer by the gate dielectric. A second control gate is disposed on a side of the second floating gate opposite to the channel layer and is separated from the second floating gate by a second tunneling dielectric.

[0072] In some embodiments, the first floating gate and the second floating gate each include a bump-shaped metal feature having a convex sidewall contacting the gate dielectric. In some embodiments, the gate dielectric includes a first portion and a second portion, the first portion and the second portion respectively lining and contacting the convex sidewalls of the first floating gate and the second floating gate, and connected through an intermediate portion between the first floating gate and the second floating gate; and the intermediate portion includes a first sidewall vertically aligned with the first sidewall of the first floating gate and the second floating gate. In some embodiments, the first floating gate and the second floating gate each include a straight sidewall contacting the first tunneling dielectric and the second tunneling dielectric. In some embodiments, the above-mentioned integrated device further includes: a first source / drain terminal pair disposed on the other side of the channel layer opposite to the first floating gate; and a second source / drain terminal pair disposed on the other side of the channel layer opposite to the second floating gate, wherein the first source / drain terminal pair and the second source / drain terminal pair contact the second sidewall of the channel layer opposite to the first sidewall. In some embodiments, the integrated device further includes first and second dummy control gates and first and second dummy tunneling dielectrics correspondingly disposed on the other side of the channel layer opposite to the first and second floating gates and the first and second control gates.

[0073] In some other embodiments, the utility model relates to a method for forming an integrated device. The method includes forming a first source / drain precursor layer, a gate precursor layer, and a second source / drain precursor layer stacked one on top of another separated by an interlayer dielectric (ILD) layer on a substrate. The method also includes forming a vertical trench that separates the first source / drain precursor layer, the gate precursor layer, and the second source / drain precursor layer into a first side and a second side in a lateral direction, and forming a floating gate, a gate dielectric, and a channel layer in the vertical trench. The method also includes patterning the first source / drain precursor layer, the gate precursor layer, and the second source / drain precursor layer to form a first dummy source / drain terminal, a control gate, and a second dummy source / drain terminal on a first side, and forming a first source / drain terminal, a dummy control gate, and a second source / drain terminal on a second side.

[0074] In some embodiments, the method further comprises forming a tunneling dielectric contacting the gate precursor layer on the first side and forming a dummy tunneling dielectric contacting the gate precursor layer on the second side after forming the vertical trench. In some embodiments, the floating gate is formed by forming a floating gate precursor in a recess of the tunneling dielectric, selectively depositing a metal material on the floating gate precursor, and patterning the metal material to form the floating gate. In some embodiments, the metal material is also deposited on the first source / drain precursor layer and the second source / drain precursor layer to form three continuous bumps as the floating gate. In some embodiments, the method further comprises: forming a control gate contact reaching the control gate through the ILD layer and a first source / drain contact and a second source / drain contact reaching the first source / drain terminal and the second source / drain terminal respectively; and the control gate, the first source / drain contact and the second source / drain contact are formed by replacing the patterned first source / drain precursor layer, the gate precursor layer and the second source / drain precursor layer with a conductive material.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A memory cell, characterized in that: include: A channel layer is disposed on the substrate and extends along a vertical direction perpendicular to the surface of the substrate; A floating gate is disposed on the substrate and is separated from the channel layer by a gate dielectric along a first lateral direction perpendicular to the vertical direction; a control gate, disposed on one side of the floating gate and the channel layer along the first lateral direction and separated from the floating gate by a tunnel dielectric; and A source / drain terminal pair is disposed on the other side of the channel layer and the floating gate opposite to the control gate.

2. The memory unit according to claim 1, characterized in that The invention also comprises a dummy control gate and a dummy tunnel dielectric, which are arranged on the other side of the channel layer opposite to the floating gate, the tunnel dielectric and the control gate.

3. The memory unit according to claim 2, characterized in that A pair of dummy source / drain terminals is also included, which are arranged on the other side of the floating gate opposite to the channel layer and the pair of source / drain terminals.

4. The memory unit according to claim 3, characterized in that The dummy control gate and the dummy source / drain terminal pair are made of different semiconductor materials.

5. The memory unit according to claim 3, characterized in that The floating gate includes three continuous bumps contacting the tunneling dielectric and the dummy source / drain terminal pair, respectively.

6. The memory cell according to claim 1, characterized in that Also includes: a first source / drain contact disposed on an upper surface of a first source / drain terminal of the source / drain terminal pair; as well as A second source / drain contact is disposed on an upper surface of a second source / drain terminal of the source / drain terminal pair, The first source / drain contact and the second source / drain contact are laterally staggered and extend upward along the vertical direction.

7. An integrated device, characterized in that: include: A channel layer is disposed on the substrate and extends along a vertical direction perpendicular to the surface of the substrate; A gate dielectric is disposed on one side of the channel layer and extends along a first sidewall of the channel layer; a first floating gate disposed in a first memory cell region adjacent to the gate dielectric and separated from the channel layer by the gate dielectric; a first control gate disposed on a side of the first floating gate opposite to the channel layer and separated from the first floating gate by a first tunneling dielectric; A second floating gate, stacked on the first floating gate, also disposed adjacent to the gate dielectric and separated from the channel layer by the gate dielectric; as well as The second control gate is disposed on a side of the second floating gate opposite to the channel layer and is separated from the second floating gate by a second tunnel dielectric.

8. The integrated device according to claim 7, characterized in that: The first floating gate and the second floating gate each include a bump-shaped metal feature having a convex sidewall contacting the gate dielectric.

9. The integrated device according to claim 8, characterized in that The gate dielectric includes a first portion and a second portion, the first portion and the second portion respectively lining and contacting the convex sidewalls of the first floating gate and the second floating gate and connected through a middle portion between the first floating gate and the second floating gate; and The middle portion includes a first sidewall vertically aligned with first sidewalls of the first floating gate and the second floating gate.

10. The integrated device according to claim 8, characterized in that The first floating gate and the second floating gate include straight sidewalls contacting the first tunneling dielectric and the second tunneling dielectric, respectively.

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