Image sensor

Abstract

The utility model provides an image sensor, which comprises a plurality of pixel units arranged in an array, each pixel unit comprises a photosensitive module, a floating diffusion node, a gain module, an overflow module, a reset module and a read-out module, and the photosensitive module, the gain module and the read-out module are respectively connected to the floating diffusion node. The reset module is connected to the floating diffusion node through the overflow module; the photosensitive module converts the optical signal into a charge signal, and the charge signal comprises a first charge signal, a second charge signal and a third charge signal; the photosensitive module at least stores the first charge signal; the gain module performs switching of different conversion gains; the overflow module at least stores the second charge signal; the reset module resets the photosensitive module, the floating diffusion node, the gain module and the overflow module and discharges the third charge signal; the read-out module at least reads out the first charge signal. According to the utility model, the problem that the existing image sensor has a potential noise risk is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor. Background Art

[0002] In the pixel unit of the existing image sensor, the reset transistor, the gain transistor, the overflow transistor and the overflow capacitor are connected in series between the power supply potential and the ground potential, wherein the gain transistor and the overflow transistor are connected via a floating diffusion node. When the above circuit structure is working normally, the reset control signal of the reset transistor has the following requirements: in the exposure stage, it is expected that the reset control signal controls the reset transistor to be partially closed to discharge the over-exposure charge; in the readout stage, it is expected that the reset control signal controls the reset transistor to be completely closed, and there is no leakage to affect the quantized readout. When implementing the above two stages, compared with the traditional 4T image sensor, various new types of noise may be introduced, and there is a potential noise risk. Therefore, how to reduce the potential noise risk is a technical problem that technicians in this field are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an image sensor for solving the problem of potential noise risk in the prior art image sensors.

[0005] In order to achieve the above-mentioned object and other related objects, the utility model provides an image sensor, the image sensor comprising:

[0006] A plurality of pixel units arranged in an array, wherein the pixel units include a photosensitive module, a floating diffusion node, a gain module, an overflow module, a reset module and a readout module, wherein the photosensitive module, the gain module and the readout module are respectively connected to the floating diffusion node, and the reset module is connected to the floating diffusion node via the overflow module;

[0007] The photosensitive module is used to convert the light signal into a charge signal, wherein the charge signal includes a first charge signal, a second charge signal and a third charge signal;

[0008] The photosensitive module is also used to store at least the first charge signal; the gain module is used to switch different conversion gains; the overflow module is used to store at least the second charge signal; the reset module is used to reset at least one of the photosensitive module, the floating diffusion node, the gain module and the overflow module and discharge the third charge signal; the readout module is used to read out at least the first charge signal.

[0009] Optionally, the gain module comprises a gain transistor and a gain capacitor, a control end of the gain transistor is connected to a gain control signal, a first end is connected to the floating diffusion node, and a second end is connected to a first potential via the gain capacitor;

[0010] And / or, the overflow module comprises an overflow transistor and an overflow capacitor, the control end of the overflow transistor is connected to the overflow control signal, the first end is connected to the reset module and connected to the second potential via the overflow capacitor, and the second end is connected to the floating diffusion node;

[0011] And / or, the reset module includes a reset transistor, a control end of which is connected to a reset control signal, a first end of which is connected to a third potential, and a second end of which is connected to the overflow module.

[0012] Optionally, when the gain module includes a gain capacitor, the gain capacitor includes an equivalent capacitor or a device capacitor; when the overflow module includes an overflow capacitor, the overflow capacitor includes a device capacitor.

[0013] Optionally, the photosensitive module includes at least one transmission transistor and at least one photosensitive element, the control end of the transmission transistor is connected to the transmission control signal, the first end is connected to the floating diffusion node, and the second end is connected to the fourth potential via the photosensitive element;

[0014] And / or, the readout module is further used to read out at least the second charge signal;

[0015] And / or, the read-out module includes a source follower transistor and a selection transistor, the control end of the source follower transistor is connected to the floating diffusion node, the first end is connected to the fifth potential, the second end is connected to the first end of the selection transistor, the control end of the selection transistor is connected to the selection control signal, and the second end is connected to the column line.

[0016] Optionally, in the pixel array of the image sensor, at least two different pixel units share gain capacitors in each other's gain modules.

[0017] Optionally, the pixel unit in the Nth row and the pixel unit in the (N+1)th row in any pixel column share gain capacitors in each other's gain modules, where N is an integer greater than or equal to 1; and / or different pixel units share gain capacitors in each other's gain modules through a metal connection structure.

[0018] Optionally, the structure formed by different pixel units that share the gain capacitors in each other's gain modules is recorded as a shared structure, and the image sensor also includes a gain reset tube, which corresponds one-to-one to the shared structure; wherein the control end of the gain reset tube is connected to the gain reset signal, the first end is connected to the sixth potential, and the second end is electrically connected to the metal connection structure.

[0019] Optionally, in any two adjacent pixel columns, the pixel units in the Mth row of the pixel column in the previous column and the pixel units in the (M+1)th row share gain capacitors in each other's gain modules, and the pixel units in the (M+1)th row of the pixel column in the latter column and the pixel units in the (M+2)th row share gain capacitors in each other's gain modules, where M is an integer greater than or equal to 1.

[0020] As described above, the image sensor of the present invention, through a new pixel structure design, realizes that the over-exposure charge in the exposure stage is discharged by the reset module without affecting other pixels, and the leakage demand under the first conversion gain in the readout stage is controlled by the overflow module, so that the reset module does not need to be completely shut down, which simplifies the shutdown requirement of the reset module, avoids the introduction of various new noises, and reduces the potential noise risk. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a structural schematic diagram of an image sensor according to the first embodiment.

[0022] Figure 2 Shown is a timing diagram corresponding to any pixel unit in the image sensor of the first embodiment.

[0023] Figure 3 Shown is a schematic structural diagram of the image sensor of the second embodiment.

[0024] Figure 4 Shown is a schematic diagram of the reset state corresponding to the Bayer color array in the image sensor of the second embodiment.

[0025] Figure 5 Shown is a schematic structural diagram of the image sensor of Example 3.

[0026] Figure 6 Shown is a schematic diagram of the reset state corresponding to the Bayer color array in the image sensor of the third embodiment.

[0027] Figure 7 Shown is a schematic structural diagram of an image sensor according to a fourth embodiment.

[0028] Figure 8 Shown is a schematic diagram of the reset state corresponding to the Bayer color array in the image sensor of the fourth embodiment.

[0029] Fig. 9 Shown is a schematic structural diagram of an image sensor according to a fifth embodiment.

[0030] Fig.10 Shown is a schematic diagram of the reset state corresponding to the Bayer color array in the image sensor of the fifth embodiment.

[0031] Component number description

[0032] 100 Image Sensor

[0033] 110 pixel unit

[0034] 111 Photosensitive module

[0035] 112 Gain Block

[0036] 113 Overflow Module

[0037] 114 Reset module

[0038] 115 Readout module DETAILED DESCRIPTION

[0039] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0041] Embodiment 1

[0042] like Figure 1 As shown, this embodiment provides an image sensor 100, including a plurality of pixel units 110 arranged in an array; wherein the pixel unit 110 includes a photosensitive module 111, a floating diffusion node FD, a gain module 112, an overflow module 113, a reset module 114 and a readout module 115.

[0043] The photosensitive module 111 is connected to the floating diffusion node FD, and is used to convert the light signal into a charge signal, wherein the charge signal includes a first charge signal, a second charge signal and a third charge signal; of course, the photosensitive module 111 is also used to store at least the first charge signal.

[0044] In combination with actual application scenarios, the first charge signal refers to the charge signal corresponding to the potential well part, the second charge signal refers to the charge signal corresponding to the overflow part after exceeding the potential well part, and the third charge signal refers to the charge signal exceeding the overflow part; in some applications, the first charge signal is also defined as a potential well charge signal, the second charge signal is also defined as an overflow charge signal, and the third charge signal is also defined as an overexposed charge signal.

[0045] When the amount of charge sensed by the photosensitive module 111 has not reached an overflow state, the converted charge signal only includes the first charge signal, and the second charge signal and the third charge signal can be considered to be zero at this time; when the amount of charge sensed by the photosensitive module 111 has reached an overflow state but has not reached an overexposure state, the converted charge signal includes the first charge signal and the second charge signal, and the third charge signal can be considered to be zero at this time; when the amount of charge sensed by the photosensitive module 111 has reached an overexposure state, the converted charge signal includes the first charge signal, the second charge signal and the third charge signal.

[0046] As an example, the photosensitive module 111 includes at least one transfer transistor M1 and at least one photosensitive element PD; the control end of the transfer transistor M1 is connected to the transmission control signal TX, the first end is connected to the floating diffusion node FD, and the second end is connected to the fourth potential via the photosensitive element PD.

[0047] In one implementation, the transmission transistor M1 includes an NMOS tube, and the photosensitive element PD includes a photodiode; the gate of the transmission transistor M1 is connected to the transmission control signal TX, the drain is connected to the floating diffusion node FD, the source is connected to the first end of the photosensitive element PD (such as the N-type ion doping region), and the second end of the photosensitive element PD (such as the P-type ion doping region) is connected to the fourth potential; wherein the fourth potential includes the ground potential or the negative potential. Of course, in other implementations, it is also feasible that the transmission transistor M1 includes a PMOS tube, and the photosensitive element PD includes a grating or a photoconductor.

[0048] It should be noted that the photosensitive module 111 shown in the figure includes a transfer transistor M1 and a photosensitive element PD. In fact, the number of transfer transistors M1 and photosensitive elements PD is determined by specific needs. For example, the transfer transistors M1 and photosensitive elements PD are set in a one-to-one correspondence, and this embodiment does not impose any restrictions on this.

[0049] The floating diffusion node FD is at least used to receive a first charge signal.

[0050] The gain module 112 is connected to the floating diffusion node FD, and is used to switch different conversion gains, such as switching between a first conversion gain and a second conversion gain; as an optional scheme, the first conversion gain includes a low conversion gain (LCG), and the second conversion gain includes a high conversion gain (HCG) whose conversion gain is greater than the low conversion gain (LCG).

[0051] By switching different conversion gains, the potential well capacity of the floating diffusion node FD can be adjusted; specifically as follows: under the first conversion gain, the potential well capacity of the floating diffusion node FD is the sum of its own storage capacity and the storage capacity of the gain module 112; under the second conversion gain, the potential well capacity of the floating diffusion node FD is its own storage capacity.

[0052] As an example, the gain module 112 includes a gain transistor M2 and a gain capacitor C1; the control end of the gain transistor M2 is connected to the gain control signal DCG, the first end is connected to the floating diffusion node FD, and the second end is connected to the first potential via the gain capacitor C1; wherein the capacity of the gain capacitor C1 is the storage capacity of the gain module 112.

[0053] In one implementation, the gain transistor M2 includes an NMOS tube, and the gain capacitor C1 includes an equivalent capacitor or a device capacitor; the gate of the gain transistor M2 is connected to the gain control signal DCG, the drain is connected to the floating diffusion node FD, the source is connected to the first end of the gain capacitor C1, and the second end of the gain capacitor C1 is connected to the first potential; wherein the first potential includes a ground potential or a variable potential. Of course, in other implementations, it is also feasible for the gain transistor M2 to include a PMOS tube. In fact, the gain capacitor C1 is usually implemented using an equivalent capacitor, in which case the equivalent capacitor of the source of the gain transistor is used as the gain capacitor C1.

[0054] The overflow module 113 is connected to the floating diffusion node FD and is used to store at least the second charge signal.

[0055] As an example, the overflow module 113 includes an overflow transistor M3 and an overflow capacitor C2; the control end of the overflow transistor M3 is connected to the overflow control signal OF, the first end is connected to the reset module 114 and connected to the second potential via the overflow capacitor C2, and the second end is connected to the floating diffusion node FD.

[0056] In one implementation, the overflow transistor M3 includes an NMOS tube, and the overflow capacitor C2 includes a device capacitor; the gate of the overflow transistor M3 is connected to the overflow control signal OF, the drain is connected to the reset module 114 and connected to the second potential via the overflow capacitor C2, and the source is connected to the floating diffusion node FD; wherein the second potential includes a ground potential or a variable potential. Of course, in other implementations, it is also feasible for the overflow transistor M3 to include a PMOS tube. In fact, due to the large capacitance, the overflow capacitor C2 is usually implemented using a device capacitor rather than an equivalent capacitor, wherein the device capacitor can be a MIM capacitor or a MOS capacitor.

[0057] The reset module 114 is connected to the floating diffusion node FD via the overflow module 113 , and is used to reset the photosensitive module 111 , the floating diffusion node FD, the gain module 112 and the overflow module 113 and discharge the third charge signal.

[0058] As an example, the reset module 114 includes a reset transistor M4 , a control terminal of which is connected to the reset control signal RST, a first terminal of which is connected to the third potential, and a second terminal of which is connected to the overflow module 113 and connected to the floating diffusion node FD via the overflow module 113 .

[0059] In one implementation, the reset transistor M4 includes an NMOS tube, the gate is connected to the reset control signal RST, the drain is connected to the third potential, and the source is connected to the overflow module 113, such as the drain of the overflow transistor M2; wherein the third potential includes the power supply potential. Of course, in other implementations, it is also feasible for the reset transistor M4 to include a PMOS tube.

[0060] The readout module 115 is connected to the floating diffusion node FD, and is used to read out at least the first charge signal; further, it is also used to read out at least the second charge signal. In this embodiment, the readout module 115 performs correlated double sampling on the first charge signal at different conversion gains, and performs non-true correlated double sampling on the second charge signal at the first conversion gain.

[0061] As an example, the readout module 115 includes a source follower transistor M5 and a selection transistor M6; the control end of the source follower transistor M5 is connected to the floating diffusion node FD, the first end is connected to the fifth potential, and the second end is connected to the first end of the selection transistor M6; the control end of the selection transistor M6 is connected to the selection control signal SEL, and the second end is connected to the column line.

[0062] In one implementation, the source follower transistor M5 includes an NMOS transistor, and the selection transistor M6 includes an NMOS transistor; the gate of the source follower transistor M5 is connected to the floating diffusion node FD, the drain is connected to the fifth potential, and the source is connected to the drain of the selection transistor M6; the gate of the selection transistor M6 is connected to the selection control signal SEL, and the source is connected to the column line; wherein the fifth potential includes the power supply potential. Of course, in other implementations, it is also feasible that the source follower transistor M5 includes a PMOS transistor and the selection transistor M6 includes a PMOS transistor.

[0063] like Figure 2 As shown, this embodiment also provides a control method for an image sensor 100, which controls the pixel units 110 of each pixel row to achieve quantitative readout, including a reset phase, an exposure phase and a readout phase; wherein the image sensor involved in the control method is implemented using the structure described above.

[0064] In the reset stage, the photosensitive module 111, the floating diffusion node FD, the gain module 112 and the overflow module 113 are reset. In this embodiment, the photosensitive module 111, the floating diffusion node FD, the gain module 112 and the overflow module 113 are reset by the reset module 114.

[0065] The details are as follows: turn on the transfer transistor M1 in the photosensitive module 111, the gain transistor M2 in the gain module 112 and the overflow transistor M3 in the overflow module 113, and clear the charge of the photosensitive element PD in the photosensitive module 111, the floating diffusion node FD, the gain capacitor C1 in the gain module 112 and the overflow capacitor C2 in the overflow module 113 by turning on the reset transistor M4 in the reset module 114 to achieve signal reset and complete the reset operation; thereafter, turn off the transfer transistor M1 in the photosensitive module 111, the gain transistor M2 in the gain module 112 and the reset transistor M4 in the reset module 114.

[0066] In fact, after the reset operation is completed, when the transfer transistor M1 is turned off, it is not completely turned off but partially turned off to facilitate the transfer of the charge signal, but when the gain transistor M2 is turned off, it is completely turned off to prevent the charge signal from affecting the gain module 112; in addition, for the reset transistor M4, after the reset operation is completed, it is controlled to be partially turned off to facilitate the discharge of the charge signal exceeding the overflow part, that is, to discharge the overexposed charge signal relative to the overflow module 113.

[0067] During the exposure phase, the gain module 112 is turned off and the overflow module 113 is turned on, the first charge signal is stored in the corresponding photosensitive module 111, for example, in the photoelectric conversion element PD, and the second charge signal is transferred to the overflow module 113 for storage, and the third charge signal is discharged through the reset module 114.

[0068] Since the gain transistor M2 in the gain module 112 is turned off and the overflow transistor M3 in the overflow module 113 is not turned off after the reset operation is completed, that is, after the reset phase ends and before the exposure phase begins, the gain module 112 has been turned off and the overflow module 113 has been turned on, there is no need to perform additional control on the gain module 112 and the overflow module 113 during the exposure phase.

[0069] As described above for the charge signal, at this stage, different pixel units 110 in the pixel array may have different charge signal generation states, so when the charge signal is transferred and discharged:

[0070] When the charge amount sensed by the photosensitive module 111 does not reach the overflow state, its charge signal only includes the first charge signal, and the second charge signal and the third charge signal are considered to be zero, wherein the first charge signal is stored in the photosensitive module 111, no second charge signal is stored in the overflow capacitor C2 of the overflow module 113, and no third charge signal is discharged through the reset module 114;

[0071] When the charge amount sensed by the photosensitive module 111 reaches an overflow state but does not reach an overexposure state, the converted charge signal includes a first charge signal and a second charge signal, and the third charge signal is considered to be zero, wherein the first charge signal is stored in the photosensitive module 111, and the second charge signal is stored in the overflow capacitor C2 of the overflow module 113 via the floating diffusion node FD, and no third charge signal is discharged through the reset module 114;

[0072] When the amount of charge sensed by the photosensitive module 111 reaches an overexposure state, the converted charge signal includes a first charge signal, a second charge signal and a third charge signal, wherein the first charge signal is stored in the photosensitive module 111, the second charge signal is stored in the overflow capacitor C2 of the overflow module 113 via the floating diffusion node FD, and the third charge signal is discharged through the reset module 114.

[0073] In the readout stage, the overflow module 113 is turned off, and the first charge signal or the first charge signal and the first reset signal corresponding to the first charge signal are quantized and read out at different conversion gains by turning on and off the gain module 112; wherein the state of the reset module 114 in this process is consistent with the state of the reset module 114 in the exposure stage, and both are in a partially closed state. In this embodiment, the first charge signal and the first reset signal are quantized and read out at different conversion gains, that is, correlated double sampling is performed on the first charge signal at different conversion gains.

[0074] When correlated double sampling is performed on the first charge signal under different conversion gains, the overflow module 113 is turned off to cut off the leakage path from the floating diffusion node FD and the gain module 112 to the reset module 114, thereby avoiding the influence of leakage on the quantization readout. At this time, whether the reset module 114 is completely turned off or not does not affect the signal quantization readout, so the reset transistor M4 in the reset module 114 can continue to maintain a partially turned-off state without switching to a fully turned-off state, thereby simplifying signal control.

[0075] Specifically, the selection transistor M6 in the readout module 115 is turned on, the overflow transistor M3 in the overflow module 113 is turned off, the gain transistor M2 in the gain module 112 is turned on to enter the first conversion gain, and the first reset signal under the first conversion gain is quantized and read out, and then the gain transistor M2 in the gain module 112 is turned off to enter the second conversion gain, and the first reset signal under the second conversion gain is quantized and read out;

[0076] The transfer transistor M1 in the photosensitive module 111 is turned on, and the first charge signal is transferred at the second conversion gain, and then the transfer transistor M1 in the photosensitive module 111 is turned off, and the first charge signal at the second conversion gain is quantized and read out; in an optional example, the transfer transistor M1 in the photosensitive module 111 may be turned off and then the selection transistor M6 in the readout module 115 is turned on, and the first charge signal is transferred at the second conversion gain, and then the transfer transistor M1 in the photosensitive module 111 is turned off and then the selection transistor M6 in the readout module 115 is turned on, and the first charge signal at the second conversion gain is quantized and read out;

[0077] The gain transistor M2 in the gain module 112 is turned on to enter the first conversion gain mode, and the transfer transistor M1 in the photosensitive module 111 is turned on and off again to transfer the first charge signal under the first conversion gain and to quantize and read out the first charge signal under the first conversion gain after the transfer; in an optional example, the gain transistor M2 in the gain module 112 may be turned on to enter the first conversion gain mode, and the selection transistor M6 in the readout module 115 may be turned off and then the transfer transistor M1 in the photosensitive module 111 may be turned on to transfer the first charge signal under the first conversion gain, and then the transfer transistor M1 in the photosensitive module 111 may be turned off and then the selection transistor M6 in the readout module 115 may be turned on to quantize and read out the first charge signal under the first conversion gain.

[0078] When the first charge signal is correlated double sampled through the above operation, the closing action of the overflow transistor M3 in the overflow module 113 is performed after the first opening action of the selection transistor M6 in the readout module 115 and before the first opening action of the gain transistor M2 in the gain module 112.

[0079] Furthermore, after the first charge signal is quantized and read out, the readout stage further includes: opening the overflow module 113, and quantizing and reading out the second charge signal or the second charge signal and the second reset signal corresponding to the second charge signal at the first conversion gain; wherein the state of the reset module 114 in this process is consistent with the state of the reset module 114 in the exposure stage, and both are in a partially closed state. Of course, it is also feasible for the reset module 114 to be in a completely closed state during this process, but for the purpose of simplifying signal control, the reset module 114 is usually selected to be in a partially closed state. In this embodiment, the second charge signal and the second reset signal are quantized and read out at the first conversion gain, that is, non-true correlated double sampling is performed on the second charge signal at the first conversion gain.

[0080] Specifically, the overflow transistor M3 in the overflow module 113 is turned on, the transfer transistor M1 in the photosensitive module 111 is turned on, the second charge signal is transferred at the first conversion gain, and the second charge signal at the first conversion gain is quantized and read out through the selection transistor M6 in the readout module 115 that is turned on; in an optional example, the overflow transistor M3 in the overflow module 113 may be turned on, the selection transistor M6 in the readout module 115 may be turned off, and the transfer transistor M1 in the photosensitive module 111 may be turned on, the second charge signal is transferred at the first conversion gain, and then the transfer transistor M1 in the photosensitive module 111 may be turned off and the selection transistor M6 in the readout module 115 may be turned on, and the second charge signal at the first conversion gain may be quantized and read out;

[0081] Next, the reset transistor M4 in the reset module 114 is turned on and then closed to complete the reset operation of the overflow capacitor C2 in the overflow module 113 (actually, the floating diffusion node FD, the gain capacitor C1 in the gain module 112 and the overflow capacitor C2 in the overflow module 113 are reset), and then the second reset signal under the first conversion gain is quantized and read out; in an optional example, the selection transistor M6 in the readout module 115 can also be turned off, and the reset transistor M4 in the reset module 114 is turned on and then closed to complete the reset operation of the overflow capacitor C2 in the overflow module 113, and then the selection transistor M6 in the readout module 115 is turned on to read out the second reset signal under the first conversion gain.

[0082] In fact, after the reset operation of the overflow capacitor C2 is completed, when the reset transistor M4 in the reset module 114 is closed, it is not completely closed but partially closed; in this embodiment, the reset transistor M4 in the reset module 114 has only two states during the whole process, namely, the open state and the partially closed state, which can not only greatly simplify the signal control, but also avoid introducing various new noises and reduce the potential noise risk. In addition, during the quantitative readout process of the second reset signal, the closing action of the selection transistor M6 in the readout module 115 is after the opening action of the reset transistor M4 in the reset module 114 and before the closing action, and the opening action of the selection transistor M6 in the readout module 115 is after the closing action of the reset transistor M4 in the reset module 114.

[0083] It should be noted that the first conversion gain refers to the capacitance corresponding to each node when the gain transistor M2 in the gain module 112 of the readout row is turned on, and the second conversion gain refers to the capacitance corresponding to each node when the gain transistor M2 is turned off; wherein, the capacitance under the first conversion gain and the second conversion gain corresponding to the first charge signal mainly depends on the size of the capacitance of different nodes in the gain module 112. For the second charge signal, in addition to the gain transistor M2 in the gain module 112 being turned on, the first conversion gain also includes the capacitance corresponding to the node after the overflow transistor M3 in the overflow module 113 is turned on.

[0084] Embodiment 2

[0085] like Figure 3 As shown, this embodiment provides an image sensor 100, which is different from the first embodiment in that: in the pixel array, at least two different pixel units 100 share the gain capacitor C1 in each other's gain module 112; in an optional example, different pixel units 110 in any pixel column may share the gain capacitor C1 in each other's gain module 112, for example, two different pixel units 110 in any pixel column share the gain capacitor C1 in each other's gain module 112.

[0086] In a specific example, the pixel unit 110 in the Nth row and the pixel unit 110 in the (N+1)th row in any pixel column share the gain capacitor C1 in each other's gain module 112, where N is an integer greater than or equal to 1. In fact, for the pixel array of the image sensor 100, each pixel row is divided into a group of two from top to bottom, and the two pixel units 110 located in the same pixel column in each group share the gain capacitor C1 in each other's gain module 112. In one implementation, the two pixel units 110 share the gain capacitor C1 in each other's gain module 110 through a metal connection structure; wherein the metal connection structure at least includes a metal connection line, and of course, it is also feasible to set a switch on the metal connection line. By sharing the gain capacitor C1, the FWC (full well capacity) upper limit of the image sensor 100 of this embodiment at the first conversion gain can be increased.

[0087] It should be noted that, in the case of shared gain capacitance, for the readout row, the first charge signal and its corresponding first reset signal have two conversion gains (i.e., the first conversion gain and the second conversion gain), and the second charge signal and its corresponding second reset signal have one conversion gain (i.e., the first conversion gain); wherein, under the first conversion gain, the gain transistor of the gain module of the readout row itself is turned on, and the gain transistor of the shared gain module of the non-readout row is turned off, and sharing is achieved based on the gain capacitance of the non-readout row, and under the second conversion gain, the gain transistor of the gain module of the readout row itself is turned off.

[0088] When the Nth row and the (N+1)th row of pixel units 110 in the image sensor 100 of this embodiment are quantized and read out, the control method is the same as that in the first embodiment, wherein the reset state of the gain module 112 in the Nth row of pixel units 110 under the first conversion gain begins when the gain transistor M2 of the row is turned off in the reset phase, and the reset state of the gain module 112 in the (N+1)th row of pixel units 110 under the first conversion gain begins after the last charge signal (e.g., the second charge signal) of the Nth row of pixel units 110 is quantized, such as when the reset transistor in the reset module is turned off during the quantization process of the second reset signal corresponding to the second charge signal, therefore, the first reset signals of the Nth row and the (N+1)th row of pixel units 110 under the first conversion gain are inconsistent. Of course, in the case where the pixel rows in the image sensor 100 are divided into a group in pairs from top to bottom, the upper row (the row read out first) in each group can be regarded as the Nth row and the lower row (the row read out later) can be regarded as the (N+1)th row.

[0089] Due to the existence of factors such as dark current, the time difference of the reset state will cause the potential of the first reset signal under the first conversion gain corresponding to the Nth row and the (N+1)th row of pixel units 110 to be different, which will cause mismatch between the two green pixels in the Bayer color array in the arrangement of the Bayer color array, affecting color reproduction; Figure 4 As shown, the square green G represents the reset state corresponding to the green pixels in the Nth row, and the circular green G represents the reset state corresponding to the green pixels in the (N+1)th row. In actual applications, the pixel units 110 in different rows are read out row by row in a quantitative manner, and the reset states of the pixel units 110 in each row are kept consistent based on algorithm compensation.

[0090] Embodiment 3

[0091] like Figure 5 As shown, the image sensor 100 provided in this embodiment is the same as that in the second embodiment, but in the image sensor 100 of this embodiment, the row-by-row quantization readout of the pixel units 110 in different rows is adjusted to a single-row partial quantization readout, and the simultaneous quantization readout of the selected pixel units in different rows is realized by the single-row partial quantization readout. In an optional example, the row-by-row quantization readout of the pixel units 110 in different rows is adjusted to a half-row quantization readout, wherein the four groups of pixel units 110 sharing the gain capacitor C1 in the gain module 112 correspond to a color array, and the synchronous quantization readout of the corresponding signals of the diagonal pixels in the color array is realized by the half-row quantization readout, so that the reset state of the diagonal pixels is consistent; for example, the row-by-row quantization readout of the pixel units 110 in the Nth row and the (N+1)th row is adjusted to a half-row quantization readout, wherein the four pixel units 110 in two adjacent pixel columns correspond to a color array, and the synchronous quantization readout of the corresponding signals of the diagonal pixels (such as the first charge signal, the first reset signal, the second charge signal and the second reset signal) is realized by the half-row quantization readout. It should be noted that the control method of half-row quantization readout can be implemented by a control circuit, such as Figure 5 As shown, taking the control of the gain transistor M2 in the gain module 112 as an example, the gate control of the gain transistor M2 has two states, 0 and 1 (off and on), and the synchronous quantization operation of the corresponding pixel unit can be implemented based on the corresponding state selection, such as the on state in which the diagonal pixels are all selected to be 1.

[0092] In one implementation, the color array includes a Bayer color array, that is, an RGGB color array; at this time, when performing half-row quantization readout, the corresponding signals of the two green pixels are first synchronously quantized and readout, and then the corresponding signals of the other two pixels (that is, the blue pixel and the red pixel) are synchronously quantized and readout. At this time, the reset states of the two green pixels in the Bayer color array are as follows: Figure 6Of course, in other examples, the corresponding signals of the other two pixels (ie, the blue pixel and the red pixel) may be synchronously quantized and read out first, and then the corresponding signals of the two green pixels may be synchronously quantized and read out.

[0093] Embodiment 4

[0094] like Figure 7 As shown, this embodiment provides an image sensor 100, which is different from the second embodiment in that: a gain reset tube M7 is added; the structure formed by different pixel units 110 sharing the gain capacitor C1 in each other's gain module 112 is recorded as a shared structure, and the gain reset tube M7 is set in a one-to-one correspondence with the shared structure. Among them, the control end of the gain reset tube M7 is connected to the gain reset signal RST', the first end is connected to the sixth potential, and the second end is electrically connected to the metal connection structure.

[0095] In one implementation, the gain reset tube M7 includes an NMOS tube, the gate is connected to the gain reset signal RST', the drain is connected to the sixth potential, and the source is connected to the metal connection structure; wherein the sixth potential includes the power supply potential. Of course, in other implementations, it is also feasible that the gain reset tube M7 includes a PMOS tube.

[0096] When the image sensor 100 of this embodiment is quantized and read out, the control method differs from that of the second embodiment in that: different pixel units 110 in the shared structure are quantized and read out row by row, and during the operation of the readout row, a step is added in which the gain modules 112 in the pixel units 110 in other rows behind the readout row are reset through the gain reset tube M7.

[0097] Among them, when the previous row of pixel units 110 in the shared structure are quantized and read out, there is a first time interval between the reset operation performed by the gain reset tube M7 and the quantized readout of the first reset signal under the first conversion gain of the previous row of pixel units 110, and when the next row of pixels 110 in the shared structure are quantized and read out, there is a second time interval between the reset operation performed by the reset module 114 on the own row gain module 112 of the previous row of pixel units 110 when the second reset signal is quantized and read out and the quantized readout of the first reset signal under the first conversion gain of the next row of pixel units 110, and the first time interval is equal to the second time interval.

[0098] The step of resetting the gain module 112 in the non-readout row pixel unit 110 by the gain reset tube M7 is correspondingly set in the reset phase or exposure phase of the readout row operation process. Of course, it is also feasible to set it in the readout phase of the readout row operation process, but it needs to be set before the first reset signal is quantized and read out under the first conversion gain, such as performing the reset operation of the gain reset tube before the first reset signal is quantized and read out under the first conversion gain.

[0099] In an optional example, a reset operation of the gain reset tube is performed before the quantitative readout of the first reset signal under the first conversion gain, and the gain module 112 of the gain reset tube itself and the gain modules 112 of other shared rows are reset at the same time, that is, the reset operation is performed through the gain reset tube for the operation of each row. It can be understood that the reset operation of the gain reset tube is also performed after the last row of readout is affected, that is, there is a third time interval between the reset operation corresponding to the second reset signal readout of the second-to-last readout row (such as the Nth row when two rows are shared) and the quantitative readout of the first reset signal under the first conversion gain of the first-to-last readout row (such as the N+1th row when two rows are shared), and the time interval between the additional reset added for each row operation and the quantitative readout of the first reset signal under the first conversion gain of its own row is the same as the third time interval, or, the additional reset added for each row operation is moved close to the side of the quantitative readout of the first reset signal under the first conversion gain of its own row, so that the time interval between the two is less than the third time interval.

[0100] In an optional example, the opening time interval of the gain reset tube corresponds to the opening time interval of the reset transistor when the penultimate readout row performs the second reset signal quantization. Taking two rows as an example, for the operation row, taking the Nth row as an example, the first reset signal quantization readout under the first conversion gain of the Nth row as the operation row can be used as the reference time, and there is an additional reset conduction time point between the additional reset operation of the gain reset tube and the reference point, and an additional reset conduction time period is formed corresponding to this point. At the same time, there is a shared reset conduction time point between the reset operation of the reset transistor when the Nth row performs the second reset signal quantization and the first reset signal quantization readout under the first conversion gain of the N+1th row, and a shared reset conduction time period is formed corresponding to this point. Correspondingly, the reset conduction time period covers the shared reset conduction time period.

[0101] Specifically, the Nth row of pixel units 110 and the (N+1)th row of pixel units 110 in any pixel column share the gain capacitor C1 in each other's gain module 112, and the Nth row and the (N+1)th row of pixel units 110 are quantized and read out row by row, and during the operation of the Nth row of pixel units 110, a step is added to reset the gain module 112 in the (N+1)th row of pixel units 110 through the gain reset tube M7.

[0102] It should be noted that, for the solution of this embodiment, in some implementations, since the metal wiring structure in the shared structure remains conductive, in fact, when a gain reset tube M7 is added to reset the gain module 112 in the (N+1)th row of pixel units 110 during the operation of the Nth row of pixel units 110, the gain module 112 in the Nth row is also reset at the same time, which does not affect the operation execution data readout, which can be known by those skilled in the art based on the solution.

[0103] For the Nth row of pixel units 110, during the operation thereof, the photosensitive module 111, the floating diffusion node FD, the gain module 112 and the overflow module 113 in the Nth row of pixel units 110 are reset through the reset module 114 in the Nth row of pixel units 110, and the gain module 112 in the (N+1)th row of pixel units 110 is reset through the gain reset tube M7, so that the reset state of the first charge signal corresponding to the Nth row of pixel units corresponds to: the node state in which the gain module 112 in the Nth row of pixel units 110 is reset through the reset module 114 in the Nth row of pixel units 110 and the gain module 112 in the (N+1)th row of pixel units 110 is reset through the gain reset tube M7; in one example, the reset operation performed by the gain reset tube M7 occurs after the reset operation performed by the reset module 114.

[0104] For the (N+1)th row of pixel units 110, during the operation thereof, the photosensitive module 111, the floating diffusion node FD, the gain module 112 and the overflow module 113 in the (N+1)th row of pixel units 110 are reset by the reset module 114 in the (N+1)th row of pixel units 110; since the gain module 112 in the Nth row of pixel units 110 has been reset after the second charge signal is quantized and read out, it is no longer necessary to reset it by the gain reset tube M7, so that the reset state of the first charge signal corresponding to the (N+1)th row of pixel units corresponds to: the gain module 112 in the (N+1)th row of pixel units 110 is reset by the reset module 114 in the (N+1)th row of pixel units 110, and the node state in which the gain module 112 is reset by the reset module 114 in the Nth row of pixel units 110 when the second reset signal is read out.

[0105] Due to the existence of the shared structure, during the quantization readout process of the second charge signal of the Nth row pixel unit 110, it is necessary to perform a reset operation on the node corresponding to the first conversion gain, that is, the reset transistor of the reset module 114 is turned on and then closed to perform the operation of reading out the second reset signal corresponding to the second charge signal. At this time, the opening of the reset transistor in the reset module 114 simultaneously performs a reset operation on the gain module 112 (gain capacitor C1) of the (N+1)th row pixel unit 110, thereby destroying the reset state of the (N+1)th row pixel unit 110 after the global reset. In this embodiment, during the reset stage or exposure stage of the Nth row pixel unit 110, the gain reset tube M7 is used to add a reset operation to the gain module 112 (gain capacitor C1) in the (N+1)th row pixel unit 110, so that it is consistent with the reset state of the (N+1)th row pixel unit 110.

[0106] In a specific implementation, it can be considered that, for the Nth row of pixel units 110, there is a first time interval between the reset operation of the gain module 112 (gain capacitor C1) in the (N+1)th row of pixel units 110 added by the gain reset tube M7 and the quantized readout of the first reset signal in the first gain mode of the first charge signal of the Nth row of pixel units 110, and for the (N+1)th row of pixels, there is a second time interval between the reset operation of the gain module 112 (gain capacitor C1) in the (N+1)th row of pixel units 110 performed by the reset module 114 when the second reset signal corresponding to the second charge signal of the Nth row is quantized and readout and the quantized readout of the first reset signal in the first gain mode of the first charge signal of the (N+1)th row of pixels, and the first time interval is equal to the second time interval.

[0107] Thus, when the Nth row and the (N+1)th row of pixel units 110 are read out row by row, the reset states of the gain modules 112 of the two non-readout row pixel units 110 in the shared structure can be made consistent to avoid mismatch. At this time, the reset states of the two green pixels in the Bayer color array are as follows: Figure 8 shown.

[0108] Of course, for the purpose of simplifying signal control, a step of resetting the gain module 112 in the Nth row of pixel units 110 through the gain reset tube M7 can also be added in the reset stage of the (N+1)th row of pixel units 110; at this time, the reset stage is to reset the photosensitive module 111, the floating diffusion node FD, the gain module 112 and the overflow module 113 in the readout row pixel unit 110 through the reset module 114 in the readout row pixel unit 110, and reset the gain module 112 in the non-readout row pixel unit 110 through the gain reset tube M7.

[0109] Embodiment 5

[0110] like Fig. 9 As shown, this embodiment provides an image sensor 100, which is different from the first embodiment in that: in the pixel array, at least two different pixel units 100 share the gain capacitor C1 in each other's gain module 112; in a specific example, in any two adjacent pixel columns, the Mth row pixel unit 110 and the (M+1)th row pixel unit 110 of the previous pixel column share the gain capacitor C1 in each other's gain module 112, and the (M+1)th row pixel unit 110 and the (M+2)th row pixel unit 110 of the next pixel column share the gain capacitor C1 in each other's gain module 112, where M is an integer greater than or equal to 1. In one implementation, the two pixel units 110 share the gain capacitor C1 in each other's gain module 112 through a metal connection structure; wherein the metal connection structure at least includes a metal connection line, and of course, it is also feasible to set a switch on the metal connection line. By sharing the gain capacitor C1, the FWC (full well capacity) upper limit of the image sensor 100 of this embodiment at the first conversion gain can be increased.

[0111] The control method of the image sensor 100 of this embodiment is the same as that of the first embodiment. However, since the pixel units in two adjacent pixel columns are staggered and share the gain capacitor C1 in each other's gain module 112, when the pixel units 110 of each pixel row are read out row by row, the two green pixels in the Bayer color array are both in the upper row of their respective shared structures, so the reset states are consistent, and mismatch can be avoided. At this time, the reset states of the two green pixels in the Bayer color array are as follows: Fig.10 shown.

[0112] In summary, the image sensor of the utility model realizes that the overexposure charge in the exposure stage is discharged by the reset module without affecting other pixels through a new pixel structure design, and the leakage demand under the first conversion gain in the readout stage is controlled by the overflow module so that the reset module does not need to be completely turned off, which simplifies the shutdown demand of the reset module, avoids the introduction of various new noises, and reduces the potential noise risk. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: The image sensor comprises: A plurality of pixel units arranged in an array, wherein the pixel units include a photosensitive module, a floating diffusion node, a gain module, an overflow module, a reset module and a readout module, wherein the photosensitive module, the gain module and the readout module are respectively connected to the floating diffusion node, and the reset module is connected to the floating diffusion node via the overflow module; The photosensitive module is used to convert the light signal into a charge signal, wherein the charge signal includes a first charge signal, a second charge signal and a third charge signal; The photosensitive module is also used to store at least the first charge signal; the gain module is used to switch different conversion gains; the overflow module is used to store at least the second charge signal; the reset module is used to reset at least one of the photosensitive module, the floating diffusion node, the gain module and the overflow module and discharge the third charge signal; the readout module is used to read out at least the first charge signal.

2. The image sensor according to claim 1, characterized in that The gain module comprises a gain transistor and a gain capacitor, wherein the control end of the gain transistor is connected to a gain control signal, the first end is connected to the floating diffusion node, and the second end is connected to a first potential via the gain capacitor; And / or, the overflow module comprises an overflow transistor and an overflow capacitor, the control end of the overflow transistor is connected to the overflow control signal, the first end is connected to the reset module and connected to the second potential via the overflow capacitor, and the second end is connected to the floating diffusion node; And / or, the reset module comprises a reset transistor, a control end of which is connected to a reset control signal, a first end of which is connected to a third potential, and a second end of which is connected to the overflow module; And / or, when the gain module includes a gain capacitor, the gain capacitor includes an equivalent capacitor or a device capacitor; when the overflow module includes an overflow capacitor, the overflow capacitor includes a device capacitor.

3. The image sensor according to claim 1, characterized in that The photosensitive module includes at least one transmission transistor and at least one photosensitive element, wherein the control end of the transmission transistor is connected to the transmission control signal, the first end is connected to the floating diffusion node, and the second end is connected to the fourth potential via the photosensitive element; And / or, the readout module is further used to read out at least the second charge signal; And / or, the read-out module includes a source follower transistor and a selection transistor, the control end of the source follower transistor is connected to the floating diffusion node, the first end is connected to the fifth potential, the second end is connected to the first end of the selection transistor, the control end of the selection transistor is connected to the selection control signal, and the second end is connected to the column line.

4. The image sensor according to any one of claims 1 to 3, characterized in that: In the pixel array of the image sensor, at least two different pixel units share gain capacitors in each other's gain modules.

5. The image sensor according to claim 4, characterized in that: The pixel unit in the Nth row and the pixel unit in the (N+1)th row in any pixel column share the gain capacitor in each other's gain module, where N is an integer greater than or equal to 1; and / or different pixel units share the gain capacitor in each other's gain module through a metal connection structure.

6. The image sensor according to claim 5, characterized in that The structure formed by the different pixel units that share the gain capacitors in each other's gain modules is recorded as a shared structure, and the image sensor also includes a gain reset tube, which corresponds one to one to the shared structure; wherein the control end of the gain reset tube is connected to the gain reset signal, the first end is connected to the sixth potential, and the second end is electrically connected to the metal connection structure.

7. The image sensor according to claim 4, characterized in that: In any two adjacent pixel columns, the pixel units in the Mth row of the pixel column in the previous column and the pixel units in the (M+1)th row share gain capacitors in each other's gain modules, and the pixel units in the (M+1)th row of the pixel column in the latter column and the pixel units in the (M+2)th row share gain capacitors in each other's gain modules, where M is an integer greater than or equal to 1.

Images