LED time-sharing circuit based on single control signal port

Abstract

The utility model provides an LED time-sharing circuit based on a single control signal port, and the circuit comprises a control signal end which receives a control signal of which the logic level alternately changes between a first logic level and a second logic level in a normal working mode; the anti-reverse module is connected with the control signal end; the energy storage capacitor C1 is connected with the anti-reverse module; the first voltage output module comprises a control end A, a power supply input end VCC and a first voltage output end HVIO1; the second voltage output module comprises a control end B, a power supply input end VCC and a second voltage output end HVIO2; and the logic control module is connected with the energy storage capacitor C1. Compared with the prior art, the time-sharing output of the power supply can be controlled through a single control signal port, so that the number of driving RGB is doubled, and the problem of large quiescent current in a sleep mode can be solved.

Description

[Technical field]

[0001] The utility model relates to the technical field of LED dimming, in particular to an LED time-sharing circuit based on a single control signal port. [Background technology]

[0002] With the continuous development of vehicle interior lighting, the number of RGB (Red Green Blue, i.e. multi-color LED) is also gradually increasing, which means that more constant current sources are needed, which increases the cost of the solution.

[0003] To solve this problem, a time-sharing circuit is added to double the number of RGBs driven by the LED Driver.

[0004] 1) Most of the existing technical solutions for time-sharing applications are integrated inside the LED Driver. Such LED Drivers have a large number of internal constant current sources and are costly. If the number of RGB is small, the price of such drivers is not cost-effective.

[0005] 2) The existing external time-sharing solution has requirements for the GPIO and VIN input voltages. The difference between the two needs to be less than the conduction voltage drop of the transistor Vbe. For some vehicle manufacturers, the existing solution has a major problem, which is that it cannot solve the problem of high static current in sleep mode. Please refer to Figure 1 As shown, it is a circuit diagram of an existing LED time-sharing circuit, which adopts an external time-sharing scheme. In the sleep mode, no matter what the state of the GPIO port is, there will be a loop input to the ground, such as Figure 1 As shown, the current will pass through the BE diode of the PNP transistor Q1, and then through the resistor R5, the diode D2 and the resistor R1 to the ground.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Contents of the utility model]

[0007] One of the purposes of the utility model is to provide an LED time-sharing circuit based on a single control signal port, which can not only control the power time-sharing output through a single control signal port, thereby doubling the number of driven RGB, but also solve the problem of large static current in sleep mode.

[0008] According to one aspect of the utility model, the utility model provides an LED time-sharing circuit based on a single control signal port, which includes: a control signal end, which receives a control signal whose logic level alternates between a first logic level and a second logic level in a normal working mode; an anti-reverse module, which is connected to the control signal end; an energy storage capacitor C1, which is connected to the anti-reverse module, and when the control signal received at the control signal end is a first logic level, the control signal end charges the energy storage capacitor C1 through the anti-reverse module; a first voltage output module, which includes a control end A, a power input end VCC and a first voltage output end HVIO1, when the control end A is a first logic level, the first voltage output module connects the power input end VCC and the first voltage output end HVIO1, and when the control end A is a second logic level, the first voltage output module disconnects the connection between the power input end VCC and the first voltage output end HVIO1, wherein the control end A of the first voltage output module connected to the control signal terminal; a second voltage output module, which includes a control terminal B, a power input terminal VCC and a second voltage output terminal HVIO2. When the control terminal B is at a first logic level, the second voltage output module connects the power input terminal VCC and the second voltage output terminal HVIO2. When the control terminal B is at a second logic level, the second voltage output module disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; a logic control module, which is connected to the energy storage capacitor C1, and the output end of the logic control module is connected to the control terminal B of the second voltage output module. In a normal working mode, when the control signal received at the control signal terminal is a first logic level, the second logic level is output to the control terminal B of the second voltage output module. When the control signal received at the control signal terminal is a second logic level, the charged energy storage capacitor C1 causes the logic control module to output the first logic level to the control terminal B of the second voltage output module.

[0009] Furthermore, in the sleep mode, the control signal terminal receives a control signal that is continuously at the second logic level, and the logic control module outputs the second logic level to the control terminal of the second voltage output module.

[0010] Further, the anti-reverse module includes a diode D1 and a diode D2; the first voltage output module includes a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch Q5 and a switch Q6; the second voltage output module includes a resistor R1, a resistor R2, a resistor R4, a resistor R6, a switch Q1 and a switch Q3; the logic control module includes a resistor R3, a resistor R5, a resistor R7, a resistor R8, a resistor R13, a switch Q2 and a switch Q4, the positive electrode of the diode D1 is connected to the control signal end, and the negative electrode thereof is connected to the first connection end of the switch Q4 via the resistor R3; the second connection end of the switch Q4 The first connection terminal of the switch Q2 is connected to the cathode of the diode D2, the second connection terminal of the switch Q2 is connected to the cathode of the diode D1, and the control terminal of the switch Q2 is connected to the connection node between the resistor R13 and the resistor R7 through the resistor R5; the first connection terminal of the switch Q4 is connected to the connection node between the resistor R13 and the resistor R7 through the resistor R5; the first connection terminal of the switch Q4 is connected to the connection node between the resistor R3 and the resistor R4; the control terminal of the switch Q2 is connected to the connection node between the resistor R13 and the resistor R7 through the resistor R5; the control ...4; the control terminal of the switch Q2 is connected to the connection node between the resistor R13 and the resistor R7 through the resistor R5; the control terminal of the switch Q4 is connected to the connection node between the resistor R3 and the resistor R4; the control terminal of the switch Q2 is connected to the connection node between the resistor R1 The point is called the output end of the logic control module, the first connection end of the switch Q5 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the switch Q6 via the resistor R10; the control end of the switch Q6 is connected to the control end A of the first voltage output module via the resistor R11, and the second connection end thereof is grounded; one end of the resistor R12 is connected to the control end of the switch Q6, and the other end thereof is connected to the second connection end of the switch Q6; one end of the resistor R9 is connected to the control end of the switch Q5, and the other end thereof is connected to the switch Q 5; the first connection end of the switch Q1 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the switch Q3 via the resistor R2; the control end of the switch Q3 is connected to the control end B of the second voltage output module via the resistor R4, and the second connection end thereof is grounded; one end of the resistor R6 is connected to the control end of the switch Q3, and the other end thereof is connected to the second connection end of the switch Q3; one end of the resistor R1 is connected to the control end of the switch Q1, and the other end thereof is connected to the first connection end of the switch Q1.

[0011] Further, in the normal working mode, when the control signal received by the control signal end is at the first logic level, the switches Q1, Q2 and Q3 are turned off, and the switches Q4, Q5 and Q6 are turned on. At this time, the voltage of the power input end VCC is provided to the first voltage output end HVIO1 via the switch Q5; in the normal working mode, when the control signal received by the control signal end is at the second logic level, the switches Q1, Q2 and Q3 are turned on, and the switches Q4, Q5 and Q6 are turned off. At this time, the voltage of the power input end VCC is provided to the second voltage output end HVIO2 via the switch Q1; in the sleep mode, the control signal end receives the control signal continuously at the second logic level, and at this time, the switches Q4 and Q6 are both turned off.

[0012] Further, the switch Q1 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch Q1 are respectively the emitter, the collector and the base of the PNP transistor; the switch Q2 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch Q2 are respectively the emitter, the collector and the base of the PNP transistor; the switch Q3 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch Q3 are respectively the collector, the emitter and the base of the NPN transistor. base; the switch Q4 is an NPN type transistor, and the first connection end, the second connection end and the control end of the switch Q4 are respectively the collector, the emitter and the base of the NPN type transistor; the switch Q5 is a PNP type transistor, and the first connection end, the second connection end and the control end of the switch Q5 are respectively the emitter, the collector and the base of the PNP type transistor; the switch Q6 is an NPN type transistor, and the first connection end, the second connection end and the control end of the switch Q6 are respectively the collector, the emitter and the base of the NPN type transistor.

[0013] Furthermore, the capacitance of the energy storage capacitor C1 satisfies: in a normal working mode, when the control signal terminal is at a second logic level, the switch Q3 is always turned on.

[0014] Furthermore, the LED is two multi-color LEDs, namely a first multi-color LED and a second multi-color LED, the anode of the first multi-color LED is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module; the anode of the second multi-color LED is connected to the second voltage output terminal HVIO2, and the cathode thereof is connected to the constant current source module.

[0015] Compared with the prior art, the utility model can not only control the time-sharing output of power through a single control signal port, thereby doubling the number of driven RGB, but also solve the problem of large static current in sleep mode.

Brief Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0017] Figure 1 It is a circuit diagram of an LED time-sharing circuit in the prior art;

[0018] Figure 2 This is a circuit diagram of an LED time-sharing circuit based on a single control signal port in one embodiment of the utility model;

[0019] Figure 3 FIG. 4 is a circuit diagram of an LED driving system in one embodiment of the present invention. [Specific implementation method]

[0020] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0021] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the utility model. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "coupled", "connected", "connected" and "connected" in this document that indicate electrical connection all mean direct or indirect connection. For example, A is connected to B, which includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.

[0022] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0023] Please refer to Figure 2 As shown, it is a circuit diagram of an LED time-sharing circuit based on a single control signal port in one embodiment of the utility model. Figure 2The LED time-sharing circuit based on a single control signal port shown includes a control signal terminal gpio, an anti-reverse module 210 , an energy storage capacitor C1 , a first voltage output module 220 , a second voltage output module 230 and a logic control module 240 .

[0024] Wherein, when the control signal terminal gpio is in normal working mode, it receives a control signal whose logic level alternates between a first logic level and a second logic level; the anti-reverse module 210 is connected to the control signal terminal gpio; the energy storage capacitor C1 is connected to the anti-reverse module 210, and when the control signal received by the control signal terminal gpio is at the first logic level, the control signal terminal gpio charges the energy storage capacitor C1 through the anti-reverse module 210; the first voltage output module 220 includes a control terminal A, a power input terminal VCC and a first voltage output terminal HVIO1, when its control terminal A is at the first logic level, the first voltage output module 220 connects the power input terminal VCC and the first voltage output terminal HVIO1, when its control terminal A is at the second logic level, the first voltage output module 220 disconnects the connection between the power input terminal VCC and the first voltage output terminal HVIO1, wherein the control terminal A of the first voltage output module 220 is connected to the control signal terminal gpio; the second voltage output Module 230 includes a control terminal B, a power input terminal VCC and a second voltage output terminal HVIO2. When its control terminal B is at a first logic level, the second voltage output module 230 connects the power input terminal VCC and the second voltage output terminal HVIO2. When its control terminal B is at a second logic level, the second voltage output module 230 disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2. The logic control module 240 is connected to the energy storage capacitor C1, and the output end of the logic control module 240 is connected to the control terminal B of the second voltage output module 230. In the normal working mode, when the control signal received by the control signal terminal gpio is a first logic level, the second logic level is output to the control terminal B of the second voltage output module 230. When the control signal received by the control signal terminal gpio is a second logic level, the charged energy storage capacitor C1 causes the logic control module 240 to output the first logic level to the control terminal B of the second voltage output module 230.

[0025] In the sleep mode, the control signal terminal gpio receives a control signal that is continuously at the second logic level, and the logic control module 240 outputs the second logic level to the control terminal B of the second voltage output module 230 .

[0026] exist Figure 2In the specific embodiment shown, the anti-reverse module 210 includes a diode D1 and a diode D2; the first voltage output module 220 includes a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch Q5, and a switch Q6; the second voltage output module 230 includes a resistor R1, a resistor R2, a resistor R4, a resistor R6, a switch Q1, and a switch Q3; the logic control module 240 includes a resistor R3, a resistor R5, a resistor R7, a resistor R8, a resistor R13, a switch Q2, and a switch Q4.

[0027] Among them, the power input terminal VCC is connected to the power supply; the positive electrode of the diode D1 is connected to the control signal terminal gpio, and the negative electrode thereof is connected to the first connection terminal of the switch Q4 through the resistor R3; the second connection terminal of the switch Q4 is grounded, and the control terminal thereof is connected to the control signal terminal gpio through the resistor R7 and the resistor R13 in sequence; one end of the resistor R8 is connected to the control terminal of the switch Q4, and the other end thereof is connected to the second connection terminal of the switch Q4; the positive electrode of the diode D2 is connected to the control signal terminal gpio, and the negative electrode thereof is grounded through the energy storage capacitor C1; the first connection terminal of the switch Q2 is connected to the negative electrode of the diode D2, the second connection terminal thereof is connected to the negative electrode of the diode D1, and the control terminal thereof is connected to the connection node between the resistor R13 and the resistor R7 through the resistor R5; the connection node B between the first connection terminal of the switch Q4 and the resistor R3 can be called the output terminal of the logic control module 240.

[0028] The first connection end of the switch Q5 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the switch Q6 via the resistor R10; the control end of the switch Q6 is connected to the control end A of the first voltage output module 220 via the resistor R11, and the second connection end thereof is grounded; one end of the resistor R12 is connected to the control end of the switch Q6, and the other end thereof is connected to the second connection end of the switch Q6; one end of the resistor R9 is connected to the control end of the switch Q5, and the other end thereof is connected to the first connection end of the switch Q5.

[0029] The first connection end of the switch Q1 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the switch Q3 via the resistor R2; the control end of the switch Q3 is connected to the control end B of the second voltage output module 230 (or the connection node B between the first connection end of the switch Q4 and the resistor R3) via the resistor R4, and the second connection end thereof is grounded; one end of the resistor R6 is connected to the control end of the switch Q3, and the other end thereof is connected to the second connection end of the switch Q3; one end of the resistor R1 is connected to the control end of the switch Q1, and the other end thereof is connected to the first connection end of the switch Q1.

[0030] exist Figure 2In the specific embodiment shown, switch Q1, switch Q2, switch Q3, switch Q4, switch Q5, and switch Q6 are all triodes; the control signal terminal gpio is an I / O port. Among them, switch Q1 is a PNP triode, and the first connection terminal, the second connection terminal, and the control terminal of switch Q1 are respectively the emitter, the collector, and the base of the PNP triode; switch Q2 is a PNP triode, and the first connection terminal, the second connection terminal, and the control terminal of switch Q2 are respectively the emitter, the collector, and the base of the PNP triode; switch Q3 is an NPN triode, and the first connection terminal, the second connection terminal, and the control terminal of switch Q3 are respectively the collector, the emitter, and the base of the NPN triode. The switch Q4 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the switch Q4 are respectively the collector, the emitter and the base of the NPN transistor; the switch Q5 is a PNP transistor, and the first connection terminal, the second connection terminal and the control terminal of the switch Q5 are respectively the emitter, the collector and the base of the PNP transistor; the switch Q6 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the switch Q6 are respectively the collector, the emitter and the base of the NPN transistor.

[0031] The following is a detailed introduction Figure 2 The working principle of the LED time-sharing circuit based on a single control signal port is shown.

[0032] In the normal working mode, when the control signal received by the control signal terminal gpio is at a high level (which can be called the first logic level of the control signal), the high level of the control signal terminal gpio reaches the base of the NPN transistor Q6 through the resistor R11. At this time, the NPN transistor Q6 is turned on, and the base of the PNP transistor Q5 is pulled down to the ground through the resistor R10 and the NPN transistor Q6, so that the PNP transistor Q5 is also turned on, and the power input terminal VCC reaches the first voltage output terminal HVIO1 through the PNP transistor Q5 to supply power to the subsequent stage; the control signal terminal gp The high level of io reaches the base of the NPN transistor Q4 through the resistor R13 and the resistor R7. At this time, the NPN transistor Q4 is turned on, the emitter voltage of the NPN transistor Q4 is pulled down, and the connection node B between the first connection end of the switch Q4 and the resistor R3 outputs a low level (that is, the logic control module 240 outputs the second logic level), causing the NPN transistor Q3 to be cut off (or turned off), and then the PNP transistor Q1 is also cut off (or turned off), and the power input terminal VCC cannot reach the second voltage output terminal HVIO2 through the PNP transistor Q1 to supply power to the subsequent stage. Note that when the control signal received by the control signal terminal gpio is at a high level, the high level of the control signal terminal gpio reaches the base of the PNP transistor Q2 through the resistor R13 and the resistor R5. At this time, the PNP transistor Q2 is cut off (or turned off), which is equivalent to the control signal terminal gpio charging the energy storage capacitor C1 through the diode D2. This step is very critical and plays an important role when the control signal received by the control signal terminal gpio is at a low level.

[0033] In normal working mode, when the control signal received by the control signal terminal gpio is at a low level (which can be called the second logic level of the control signal), the low level of the control signal terminal gpio reaches the base of the NPN transistor Q6 through the resistor R11. At this time, the NPN transistor Q6 is cut off (or turned off), and then the PNP transistor Q5 is also cut off (or turned off), and the power input terminal VCC cannot reach the first voltage output terminal HVIO1 through the PNP transistor Q5 to supply power to the subsequent stage; the low level of the control signal terminal gpio reaches the base of the NPN transistor Q4 through the resistor R13 and the resistor R7. At this time, the NPN transistor Q4 is cut off (or turned off); because the capacitor C1 is charged when the control signal received by the control signal terminal gpio is at a high level, and due to the presence of the diode D2, Here, the voltage of the emitter of the PNP transistor Q2 is the voltage of the capacitor C1 (which is a high level); the low level of the control signal terminal gpio reaches the base of the PNP transistor Q2 through the resistor R13 and the resistor R5. At this time, the PNP transistor Q2 is turned on, and the voltage (or high level) of the capacitor C1 reaches the node B through the PNP transistor Q2 and the resistor R3, that is, the connection node B between the first connection end of the switch Q4 and the resistor R3 outputs a high level (that is, the logic control module 240 outputs the first logic level), so that the NPN transistor Q3 is turned on, and the base of the PNP transistor Q1 is pulled down to the ground through the resistor R2 and the NPN transistor Q3, so that the PNP transistor Q1 is also turned on, and the power input terminal VCC reaches the second voltage output terminal HVIO2 through the PNP transistor Q1 to supply power to the next stage.

[0034] In sleep mode, the control signal terminal gpio is set to be continuously at a low level (or the control signal terminal gpio receives a control signal that is continuously at a second logic level). Since the energy storage capacitor C1 cannot be continuously at a high level, the output end of the logic control module 240 (i.e., the connection node B between the first connection end of the switch Q4 and the resistor R3) outputs a low level (or the second logic level). At this time, the NPN transistor Q4 and the NPN transistor Q6 are both in a cut-off (or turned-off) state, and the power input terminal VCC cannot flow to the ground terminal GND through the NPN transistor Q4 and the NPN transistor Q6, thereby making the static current less than 100uA.

[0035] It can also be said that in the normal working mode, when the control signal received by the control signal terminal gpio is at a high level (which can be called the first logic level of the control signal), the switches Q1, Q2 and Q3 are turned off, and the switches Q4, Q5 and Q6 are turned on. At this time, the voltage of the power input terminal VCC is provided to the first voltage output terminal HVIO1 through the switch Q5; in the normal working mode, when the control signal received by the control signal terminal gpio is at a low level (which can be called the second logic level of the control signal), the switches Q1, Q2 and Q3 are turned on, and the switches Q4, Q5 and Q6 are turned off. At this time, the voltage of the power input terminal VCC is provided to the second voltage output terminal HVIO2 through the switch Q1; in the sleep mode, the control signal terminal gpio receives a control signal that is continuously at a low level (or continuously at the second logic level). At this time, the switches Q4 and Q6 are both in a cut-off (or turned-off) state, and the power input terminal VCC cannot flow to the ground terminal GND through the NPN transistors Q4 and Q6.

[0036] It should be noted that the capacitance of the capacitor C1 needs to satisfy the following requirements: in the normal working mode, when the control signal terminal gpio is at a low level (which can be referred to as the second logic level of the control signal), the switch Q3 is always turned on.

[0037] Please refer to Figure 3 As shown, it is a circuit diagram of an LED driving system in one embodiment of the utility model. Figure 3 The LED driving system shown includes the following Figure 2 The LED time-sharing circuit 310 based on a single control signal port, two multi-color LEDs and a constant current source module 320 are shown. The two multi-color LEDs (i.e., two RGB) are respectively a first multi-color LED1 and a second multi-color LED2, wherein the anode of the first multi-color LED1 is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module 320; the anode of the second multi-color LED2 is connected to the second voltage output terminal HVIO2, and the cathode thereof is connected to the same constant current source module 320.

[0038] In summary, the LED time-sharing circuit based on a single control signal port provided by the utility model is an RGB external time-sharing driving circuit, which can double the number of RGB drivers; the MCU (Microcontroller Unit) provides a gpio as a control signal, and the voltage of the power input terminal VIN is divided into two paths for use. When the gpio state is constantly switched, the first voltage output terminal HVIO1 and the second voltage output terminal HVIO2 are alternately turned on to play a time-sharing role. In addition, in the sleep state, the control signal terminal gpio is set to be continuously low (or the control signal terminal gpio receives a control signal that is continuously at the second logic level), so that the NPN transistor Q4 and the NPN transistor Q6 are both in the cut-off (or turned off) state, so that the power input terminal VCC cannot flow to the ground terminal GND through the NPN transistor Q4 and the NPN transistor Q6, so as to solve the problem of large static current in the sleep mode.

[0039] Based on the above analysis, the beneficial effects of the LED time-sharing circuit based on a single control signal port provided by the utility model are:

[0040] 1) In the case of limited resources, only one control signal end gpio is used to control RGB two-time division;

[0041] 2) Solved the problem of excessive static current in sleep mode;

[0042] 3) The capacitance of capacitor C1 needs to satisfy the following requirements: In normal working mode, when the control signal terminal gpio is at a low level (which can be referred to as the second logic level of the control signal), switch Q3 is always turned on.

[0043] It should be noted that any changes made by those skilled in the art to the specific implementation of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the aforementioned specific implementation.

Claims

1. An LED time-sharing circuit based on a single control signal port, characterized in that: It includes: A control signal terminal, which receives a control signal whose logic level alternately changes between a first logic level and a second logic level in a normal working mode; An anti-reverse module connected to the control signal terminal; An energy storage capacitor C1 is connected to the anti-reverse module. When the control signal received by the control signal end is at a first logic level, the control signal end charges the energy storage capacitor C1 through the anti-reverse module. A first voltage output module, comprising a control terminal A, a power input terminal VCC and a first voltage output terminal HVIO1, wherein when the control terminal A is at a first logic level, the first voltage output module connects the power input terminal VCC and the first voltage output terminal HVIO1, and when the control terminal A is at a second logic level, the first voltage output module disconnects the power input terminal VCC and the first voltage output terminal HVIO1, wherein the control terminal A of the first voltage output module is connected to the control signal terminal; A second voltage output module, comprising a control terminal B, a power input terminal VCC and a second voltage output terminal HVIO2, wherein when the control terminal B is at a first logic level, the second voltage output module connects the power input terminal VCC and the second voltage output terminal HVIO2, and when the control terminal B is at a second logic level, the second voltage output module disconnects the power input terminal VCC and the second voltage output terminal HVIO2; A logic control module is connected to the energy storage capacitor C1, and the output end of the logic control module is connected to the control end B of the second voltage output module. In a normal working mode, when the control signal received at the control signal end is a first logic level, the second logic level is output to the control end B of the second voltage output module. When the control signal received at the control signal end is a second logic level, the charged energy storage capacitor C1 causes the logic control module to output the first logic level to the control end B of the second voltage output module.

2. The LED time-sharing circuit based on a single control signal port according to claim 1, characterized in that: In the sleep mode, the control signal terminal receives a control signal which is continuously at the second logic level, and the logic control module outputs the second logic level to the control terminal of the second voltage output module.

3. The LED time-sharing circuit based on a single control signal port according to any one of claims 1-2, characterized in that: The anti-reverse module includes a diode D1 and a diode D2; the first voltage output module includes a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch Q5 and a switch Q6; the second voltage output module includes a resistor R1, a resistor R2, a resistor R4, a resistor R6, a switch Q1 and a switch Q3; the logic control module includes a resistor R3, a resistor R5, a resistor R7, a resistor R8, a resistor R13, a switch Q2 and a switch Q4, The anode of the diode D1 is connected to the control signal terminal, and the cathode of the diode D1 is connected to the first connection terminal of the switch Q4 via the resistor R3; the second connection terminal of the switch Q4 is grounded, and the control terminal of the switch Q4 is connected to the control signal terminal via the resistor R7 and the resistor R13 in sequence; one end of the resistor R8 is connected to the control terminal of the switch Q4, and the other end of the resistor R8 is connected to the second connection terminal of the switch Q4; the anode of the diode D2 is connected to the control signal terminal, and the cathode of the diode D2 is grounded via the energy storage capacitor C1; the first connection terminal of the switch Q2 is connected to the cathode of the diode D2, the second connection terminal of the switch Q2 is connected to the cathode of the diode D1, and the control terminal of the switch Q2 is connected to the connection node between the resistor R13 and the resistor R7 via the resistor R5; the connection node between the first connection terminal of the switch Q4 and the resistor R3 is called the output terminal of the logic control module, The first connection end of the switch Q5 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the switch Q6 via the resistor R10; the control end of the switch Q6 is connected to the control end A of the first voltage output module via the resistor R11, and the second connection end thereof is grounded; one end of the resistor R12 is connected to the control end of the switch Q6, and the other end thereof is connected to the second connection end of the switch Q6; one end of the resistor R9 is connected to the control end of the switch Q5, and the other end thereof is connected to the first connection end of the switch Q5; The first connection end of the switch Q1 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the switch Q3 via the resistor R2; the control end of the switch Q3 is connected to the control end B of the second voltage output module via the resistor R4, and the second connection end thereof is grounded; one end of the resistor R6 is connected to the control end of the switch Q3, and the other end thereof is connected to the second connection end of the switch Q3; one end of the resistor R1 is connected to the control end of the switch Q1, and the other end thereof is connected to the first connection end of the switch Q1.

4. The LED time-sharing circuit based on a single control signal port according to claim 3, characterized in that: In the normal working mode, when the control signal received by the control signal terminal is at the first logic level, the switches Q1, Q2 and Q3 are turned off, and the switches Q4, Q5 and Q6 are turned on. At this time, the voltage of the power input terminal VCC is provided to the first voltage output terminal HVIO1 via the switch Q5; In the normal working mode, when the control signal received by the control signal terminal is at the second logic level, the switches Q1, Q2 and Q3 are turned on, and the switches Q4, Q5 and Q6 are turned off. At this time, the voltage of the power input terminal VCC is provided to the second voltage output terminal HVIO2 via the switch Q1; In the sleep mode, the control signal terminal receives a control signal that is continuously at the second logic level, and at this time, the switch Q4 and the switch Q6 are both turned off.

5. The LED time-sharing circuit based on a single control signal port according to claim 4, characterized in that: The switch Q1 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch Q1 are respectively the emitter, the collector and the base of the PNP transistor; The switch Q2 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch Q2 are respectively the emitter, the collector and the base of the PNP transistor; The switch Q3 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch Q3 are respectively the collector, the emitter and the base of the NPN transistor; The switch Q4 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch Q4 are respectively the collector, the emitter and the base of the NPN transistor; The switch Q5 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch Q5 are respectively the emitter, the collector and the base of the PNP transistor; The switch Q6 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch Q6 are respectively the collector, the emitter and the base of the NPN transistor.

6. The LED time-sharing circuit based on a single control signal port according to claim 5, characterized in that: The capacitance of the energy storage capacitor C1 satisfies: in a normal working mode, when the control signal terminal is at a second logic level, the switch Q3 is always turned on.

7. The LED time-sharing circuit based on a single control signal port according to claim 1, characterized in that: The LEDs are two multi-color LEDs, namely a first multi-color LED and a second multi-color LED. The anode of the first multi-color LED is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module; The anode of the second multi-color LED is connected to the second voltage output terminal HVIO2, and the cathode of the second multi-color LED is connected to the constant current source module.

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