Semiconductor device
By designing a gate structure including the first silicon layer, the interlayer oxide layer, the second silicon layer and the conductive layer in the semiconductor device, and adding side wall coverage, the collapse problem caused by improper thickness of the gate silicon layer is solved, and the reliability of the device is improved.
Patent Information
- Application Number
- CN202421306602.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-06-07
AI Technical Summary
In semiconductor devices, improper mass and thickness of the gate silicon layer may cause the gate structure to collapse, affecting the reliability of the device.
A semiconductor device is designed, with a gate structure including a first silicon layer, an interlayer oxide layer, a second silicon layer and a conductive layer sequentially stacked from bottom to top, and covers the sides of the gate structure through a side wall to prevent collapse.
By using a two-layer silicon layer structure and side wall covering, the collapse of the gate structure is effectively prevented and the reliability of semiconductor devices is improved.
Smart Images
Figure CN222621487U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art
[0002] In semiconductor devices, the preparation of gate structures is a common preparation process. The gate structure includes a gate silicon layer. In order to meet the electrical performance requirements of semiconductor devices, the quality and thickness of the gate silicon layer are required when preparing the gate silicon layer. If there is a problem with the quality of the gate silicon layer or the thickness of the gate silicon layer is too thick, not only the gate silicon layer is at risk of collapse, but the process layer above the gate silicon layer is also at risk of collapse, thereby affecting the reliability of the semiconductor device. Utility Model Content
[0003] The utility model aims to provide a semiconductor device, which can effectively prevent the possibility of gate structure collapse and improve the reliability of the semiconductor device.
[0004] In order to achieve the above object, the utility model provides a semiconductor device, comprising:
[0005] substrate;
[0006] A gate structure, located on the substrate, the gate structure comprising a first silicon layer, an interlayer oxide layer, a second silicon layer and a conductive layer stacked in sequence from bottom to top;
[0007] The sidewalls cover the side surfaces of the gate structure.
[0008] Optionally, side surfaces of the first silicon layer, the interlayer oxide layer and the second silicon layer are aligned in a vertical direction.
[0009] Optionally, the sides of the first silicon layer, the interlayer oxide layer and the second silicon layer have notches, the notches are located at the junctions of the first silicon layer, the interlayer oxide layer and the second silicon layer, and the sidewalls extend into the notches.
[0010] Optionally, the interlayer oxide layer also extends to cover the surface of the notch.
[0011] Optionally, the conductive layer includes a first conductive layer and a second conductive layer stacked in sequence from bottom to top, and a maximum width of the second conductive layer in a horizontal direction is greater than a width of the first conductive layer.
[0012] Optionally, the side surface of the conductive layer is curved.
[0013] Optionally, the side surface of the gate structure is curved.
[0014] Optionally, there is a gap between the side surface of the first silicon layer and the side surface of the second silicon layer.
[0015] Optionally, the first silicon layer and the second silicon layer have different widths in a horizontal direction.
[0016] Optionally, the gate structure further includes a gate oxide layer, wherein the gate oxide layer is located between the substrate and the first silicon layer, and the gate oxide layer has different thicknesses.
[0017] Optionally, the thickness of the gate oxide layer located below the center of the first silicon layer is smaller than the thickness of the gate oxide layer located below the edge of the first silicon layer.
[0018] Optionally, it further includes a first covering layer and a second covering layer, wherein the first covering layer covers the top of the gate structure, the sidewall spacer extends to cover the side of the first covering layer, and the second covering layer covers the first covering layer and the sidewall spacer.
[0019] The semiconductor device provided by the utility model includes: a substrate, a gate structure and a sidewall, wherein the gate structure is located on the substrate, the gate structure includes a first silicon layer, an interlayer oxide layer, a second silicon layer and a conductive layer stacked in sequence from bottom to top, and the sidewall covers the side of the gate structure. The utility model sets the gate structure to include a first silicon layer and a second silicon layer, and the two silicon layers can effectively prevent the possibility of collapse of the gate structure, thereby improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 1 of the present utility model.
[0021] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 2 of the present utility model.
[0022] Figure 3 This is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in the second embodiment of the present utility model.
[0023] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 3 of the present utility model.
[0024] Figure 5 This is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in the third embodiment of the present utility model.
[0025] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 4 of the present utility model.
[0026] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 5 of the present utility model.
[0027] Figure 8This is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in the fifth embodiment of the present utility model.
[0028] Fig. 9 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 6 of the present utility model.
[0029] Fig.10 This is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in the sixth embodiment of the present utility model.
[0030] Fig.11 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 7 of the present utility model.
[0031] Fig.12 This is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in the seventh embodiment of the present utility model.
[0032] Wherein, the accompanying drawings are marked as follows:
[0033] 10-substrate; 12-trench isolation structure; 21-first silicon layer; 22-interlayer oxide layer; 23-second silicon layer; 24-conductive layer; 241-first conductive layer; 242-second conductive layer; 25-gate oxide layer; 30-buffer oxide layer; 40-sidewall; 51-first covering layer; 50-second covering layer; 60-gap. DETAILED DESCRIPTION
[0034] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0035] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0036] Embodiment 1
[0037] Figure 1This is a cross-sectional schematic diagram of a semiconductor device provided in this embodiment. This embodiment provides a semiconductor device, please refer to Figure 1 , including: a substrate 10, a gate structure and a sidewall 40; wherein the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon substrate on an insulating layer, but is not limited thereto; and a plurality of trench isolation structures 12 are formed in the substrate 10, the trench isolation structure 12 separates the substrate 10 into a plurality of active areas, and the preparation of the trench isolation structure 12 is to form an isolation trench in the substrate 10, and then fill the isolation trench with an isolation material to form the trench isolation structure 12.
[0038] The gate structure is located on the substrate 10. Specifically, the gate structure is located on the substrate 10 between two adjacent trench isolation structures 12. The gate structure includes a first silicon layer 21, an interlayer oxide layer 22, a second silicon layer 23 and a conductive layer 24 stacked in sequence from bottom to top along the vertical direction (D1 direction); the material of the first silicon layer 21 and the second silicon layer 23 can be amorphous silicon, the material of the interlayer oxide layer 22 can be silicon oxide, and the material of the conductive layer 24 can be a conductive metal material, such as tungsten, titanium, titanium nitride, but not limited to the above materials. In this embodiment, the side surfaces of the first silicon layer 21, the interlayer oxide layer 22, the second silicon layer 23 and the conductive layer 24 are aligned in the vertical direction (D1 direction). By forming an interlayer oxide layer 22 between the first silicon layer 21 and the second silicon layer 23, the first silicon layer 21 and the second silicon layer 23 with smaller grains can be prepared, thereby avoiding the generation of gaps in the first silicon layer 21 and the second silicon layer 23, thereby obtaining a gate structure with more stable performance.
[0039] Furthermore, the gate structure also includes a gate oxide layer 25, which is located between the substrate 10 and the first silicon layer 21. The thickness of the gate oxide layer 25 at different positions is the same. For example, the thickness of the gate oxide layer 25 located below the center of the first silicon layer 21 is the same as the thickness of the gate oxide layer 25 located below the edge of the first silicon layer 21. The material of the gate oxide layer 25 can be silicon oxide; and a buffer oxide layer 30 is also formed on the substrate 10, the buffer oxide layer 30 covers the trench isolation structure 12 and part of the substrate 10 (that is, covers the area outside the gate structure), and the buffer oxide layer 30 is connected to the gate oxide layer 25. The buffer oxide layer 30 and the gate oxide layer 25 can be formed at the same time (same material), the buffer oxide layer 30 can not only protect the substrate 10, but also reduce the stress generated by the process layer on the substrate 10 or the buffer oxide layer 30. The material of the buffer oxide layer 30 can be silicon oxide.
[0040] Furthermore, a first covering layer 51 is formed on the gate structure, and the first covering layer 51 covers the top of the gate structure (the top of the conductive layer 24). The side of the first covering layer 51 is aligned with the side of the gate structure in the vertical direction (D1 direction). The material of the first covering layer 51 can be silicon nitride, but is not limited to this.
[0041] The side wall 40 covers the side of the gate structure. Specifically, the side wall 40 is located on the buffer oxide layer 30 and covers the side of the first silicon layer 21, the interlayer oxide layer 22, the second silicon layer 23 and the conductive layer 24. The side wall 40 also extends to cover the side of the first covering layer 51. The material of the side wall 40 can be silicon nitride, but is not limited to this.
[0042] Furthermore, a second covering layer 52 is included. The second covering layer 52 covers the surface of the first covering layer 51 and the sidewall 40 and is located on the buffer oxide layer 30. The material of the second covering layer 52 can be silicon oxide, but is not limited thereto.
[0043] In this embodiment, by setting the gate structure to include a first silicon layer and a second silicon layer, compared with a thicker silicon layer, which is prone to collapse during preparation, two silicon layers can effectively prevent the possibility of gate structure collapse, thereby improving the reliability of the semiconductor device.
[0044] Embodiment 2
[0045] Figure 2 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 3 A partially enlarged schematic diagram of a cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 3 for Figure 2 Please refer to the enlarged diagram of the dotted box in the middle. Figure 2 and Figure 3 The difference between this embodiment and the first embodiment is that the side surfaces of the first silicon layer 21, the interlayer oxide layer 22 and the second silicon layer 23 have a notch 60, the notch 60 is located at the junction of the first silicon layer 21, the interlayer oxide layer 22 and the second silicon layer 23, the notch 60 is preferably in a sharp angle shape, the sharp angle of the notch 60 faces the interlayer oxide layer 22, and the sidewall 40 extends into the notch 60. In this embodiment, by providing the side surfaces of the first silicon layer 21, the interlayer oxide layer 22 and the second silicon layer 23 with a notch 60, and the sidewall 40 extends into the notch 60, the possibility of collapse of the gate structure can be effectively prevented, thereby improving the reliability of the semiconductor device.
[0046] Embodiment 3
[0047] Figure 4 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 5 A partially enlarged schematic diagram of a cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 5 for Figure 4 Please refer to the enlarged diagram of the dotted box in the middle. Figure 4 and Figure 5The difference between this embodiment and the second embodiment is that the interlayer oxide layer 22 also extends to cover the surface of the notch 60. Specifically, the sides of the first silicon layer 21, the interlayer oxide layer 22 and the second silicon layer 23 have the notch 60, and the interlayer oxide layer 22 also extends to cover the first silicon layer 21 and the second silicon layer 23 in the notch 60. In this embodiment, the interlayer oxide layer 22 also extends to cover the surface of the notch 60, which can also effectively prevent the possibility of collapse of the gate structure, thereby improving the reliability of the semiconductor device.
[0048] Embodiment 4
[0049] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device provided in this embodiment. Figure 6 The difference between this embodiment and the first embodiment is that there is a gap between the side surface of the first silicon layer 21 and the side surface of the second silicon layer 23, and the widths of the first silicon layer 21 and the second silicon layer 23 are different in the horizontal direction (direction D2). Specifically, the width of the first silicon layer 21 in the horizontal direction (direction D2) is greater than the width of the second silicon layer 23, and the projection of the second silicon layer 23 on the substrate 10 is within the projection range of the first silicon layer 21 on the substrate 10. The width of the interlayer oxide layer 22 can be the same as the width of the first silicon layer 21, the width of the conductive layer 24 and the first covering layer 51 can be the same as the width of the second silicon layer 23, the second silicon layer 23 exposes part of the top surface of the interlayer oxide layer 22, and the sidewall 40 covers the side surfaces of the first silicon layer 21, the interlayer oxide layer 22, the second silicon layer 23, the conductive layer 24 and the first covering layer 51, and covers part of the top surface of the interlayer oxide layer 22. In this embodiment, by setting a gap between the side surfaces of the first silicon layer 21 and the side surfaces of the second silicon layer 23, the width of the first silicon layer 21 is greater than the width of the second silicon layer 23, which can prevent the process layer on the first silicon layer 21 from collapsing, and can also effectively prevent the possibility of the gate structure collapsing, thereby improving the reliability of the semiconductor device.
[0050] Embodiment 5
[0051] Figure 7 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 8 The schematic diagram is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in this embodiment, wherein Figure 8 for Figure 7 Please refer to the enlarged diagram of the dotted box. Figure 7 and Figure 8, the difference between this embodiment and the first to fourth embodiments is that the conductive layer in the vertical direction (D1 direction) includes a first conductive layer 241 and a second conductive layer 242 stacked in sequence from bottom to top, and the maximum width of the second conductive layer 242 in the horizontal direction (D2 direction) is greater than the width of the first conductive layer 241; the side of the conductive layer is in the shape of a curved surface, and the side of the first conductive layer 241 and the second conductive layer 242 are both in the shape of a curved surface; the materials of the first conductive layer 241 and the second conductive layer 242 can be the same or different, for example, the materials of the first conductive layer 241 and the second conductive layer 242 are both titanium nitride, or the material of the first conductive layer 241 is titanium nitride, and the material of the second conductive layer 242 is tungsten. In this embodiment, by setting the conductive layer to include the first conductive layer 241 and the second conductive layer 242 stacked in sequence from bottom to top, the possibility of collapse of the gate structure can also be effectively prevented, thereby improving the reliability of the semiconductor device.
[0052] Embodiment 6
[0053] Fig. 9 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Fig.10 The schematic diagram is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in this embodiment, wherein Fig.10 for Fig. 9 Please refer to the enlarged diagram of the dotted box. Fig. 9 and Fig.10 The difference between this embodiment and the first to fourth embodiments is that the side surface of the gate structure is curved. Specifically, the side surfaces of the first silicon layer 21, the interlayer oxide layer 22, the second silicon layer 23 and the conductive layer are curved. In the first to fourth embodiments, the side surface of the gate structure is vertical. Fig. 9 and Fig.10 The first conductive layer 241 and the second conductive layer 242 are schematically shown, and in fact, there may be only one conductive layer in the first to fourth embodiments. The difference between this embodiment and the fifth embodiment is that the side surfaces of the first silicon layer 21, the interlayer oxide layer 22, and the second silicon layer 23 are also curved. In this embodiment, the side surface of the first covering layer 51 may also be curved, and the side surface of the gate structure is curved. The side wall 40 covers the side surface of the gate structure, which can increase the bonding ability between the side wall 40 and the gate structure, and can also effectively prevent the possibility of collapse of the gate structure, thereby improving the reliability of the semiconductor device.
[0054] Embodiment 7
[0055] Fig.11 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Fig.12 The schematic diagram is a partially enlarged schematic diagram of the cross-sectional schematic diagram of the semiconductor device provided in this embodiment, wherein Fig.12 for Fig.11 Please refer to the enlarged diagram of the dotted box. Fig.11 and Fig.12 The difference between this embodiment and the first to sixth embodiments is that the gate oxide layer 25 has different thicknesses. Specifically, the thickness of the gate oxide layer 25 located below the center of the first silicon layer 21 (S1 region) is less than the thickness of the gate oxide layer 25 located below the edge of the first silicon layer 21 (S2 region). In this embodiment, the thickness of the gate oxide layer 25 located below the center of the first silicon layer 21 is less than the thickness of the gate oxide layer 25 located below the edge of the first silicon layer 21, so that the center of the first silicon layer 21 is embedded in the gate oxide layer 25, the bonding ability between the first silicon layer 21 and the gate oxide layer 25 is increased, and the possibility of collapse of the gate structure can also be effectively prevented, thereby improving the reliability of the semiconductor device.
[0056] In summary, the semiconductor device provided by the present invention includes: a substrate, a gate structure and a sidewall, wherein the gate structure is located on the substrate, the gate structure includes a first silicon layer, an interlayer oxide layer, a second silicon layer and a conductive layer stacked in sequence from bottom to top, and the sidewall covers the side of the gate structure. The present invention sets the gate structure to include a first silicon layer and a second silicon layer. Compared with a thicker silicon layer, which is prone to collapse during preparation, the two silicon layers can effectively prevent the possibility of collapse of the gate structure, thereby improving the reliability of the semiconductor device.
[0057] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A semiconductor device, characterized in that: include: substrate; A gate structure, located on the substrate, the gate structure comprising a first silicon layer, an interlayer oxide layer, a second silicon layer and a conductive layer stacked in sequence from bottom to top; The sidewalls cover the side surfaces of the gate structure.
2. The semiconductor device according to claim 1, wherein Side surfaces of the first silicon layer, the interlayer oxide layer, and the second silicon layer are aligned in a vertical direction.
3. The semiconductor device according to claim 1, wherein The side surfaces of the first silicon layer, the interlayer oxide layer and the second silicon layer have notches, the notches are located at the junctions of the first silicon layer, the interlayer oxide layer and the second silicon layer, and the sidewalls extend into the notches.
4. The semiconductor device according to claim 3, wherein: The interlayer oxide layer also extends to cover the surface of the notch.
5. The semiconductor device according to claim 1, 3 or 4, characterized in that: The conductive layer includes a first conductive layer and a second conductive layer stacked in sequence from bottom to top, and a maximum width of the second conductive layer in a horizontal direction is greater than a width of the first conductive layer.
6. The semiconductor device according to claim 5, characterized in that The side surface of the conductive layer is curved.
7. The semiconductor device according to claim 5, characterized in that The side surface of the gate structure is curved.
8. The semiconductor device according to claim 1, wherein A side surface of the first silicon layer and a side surface of the second silicon layer have a gap therebetween.
9. The semiconductor device according to claim 8, characterized in that The first silicon layer and the second silicon layer have different widths in a horizontal direction.
10. The semiconductor device according to any one of claims 1 to 9, wherein: The gate structure further includes a gate oxide layer, wherein the gate oxide layer is located between the substrate and the first silicon layer, and the gate oxide layer has different thicknesses.
11. The semiconductor device according to claim 10, wherein: The thickness of the gate oxide layer located under the center of the first silicon layer is smaller than the thickness of the gate oxide layer located under the edge of the first silicon layer.
12. The semiconductor device according to claim 1, wherein It also includes a first covering layer and a second covering layer, wherein the first covering layer covers the top of the gate structure, the sidewall spacer extends to cover the side of the first covering layer, and the second covering layer covers the first covering layer and the sidewall spacer.