Data acquisition circuit board for TTE network analyzer

Abstract

The utility model provides a data acquisition circuit board for a TTE (Time-Triggered Ethernet) network analyzer. The circuit board comprises a power management module, a clock management module, an FPGA module, an LVDS switch, a JTAG interface, a DDR3 memory interface module, an SFP interface module, a PCIe interface module, an indicating lamp module and a key module. The TTE network analyzer integrates various high-speed interfaces such as an FPGA (field programmable gate array), a DDR3 (double data rate 3) memory, a PCIe (peripheral component interconnect express), an SFP (small pluggable optical module) and an LVDS (low voltage differential signal), aims to improve the performance of the TTE network analyzer, and is suitable for application scenes needing high-speed data processing and network analysis, such as a data center, a communication base station and high-performance computing equipment.

Description

Technical Field

[0001] The utility model relates to the field of electronic circuits and data processing, and in particular to a multi-interface data acquisition circuit board for a TTE network analyzer. The circuit board integrates multiple high-speed interfaces such as FPGA, DDR3 memory, PCIe, SFP, LVDS, etc., and is intended to improve the performance of the TTE network analyzer, and is suitable for application scenarios such as data centers, communication base stations, and high-performance computing equipment that require high-speed data processing and network analysis. Background Art

[0002] With the rapid development of information technology, data centers, communication base stations and high-performance computing equipment have an increasing demand for high-speed data processing and network analysis. As a new Ethernet technology, TTE (Time-Triggered Ethernet) can realize time-triggered precise data transmission and processing in the network, and is widely used in high-reliability and high-real-time network communication systems. However, existing TTE network analyzers still have many problems in high-speed data acquisition, processing, communication interface integration, signal integrity assurance, clock synchronization and power management, making it difficult to meet the high-performance requirements of complex application scenarios.

[0003] The following problems exist in the traditional TTE network analyzer circuit board design:

[0004] Existing TTE network analyzer circuit boards usually only support limited high-speed interfaces, such as a single PCIe or LVDS interface, which is difficult to adapt to the needs of various application scenarios. With the increase in data volume and the increase in transmission rate, the design of a single interface can no longer meet the requirements of practical applications.

[0005] High-speed signal transmission is easily interfered, resulting in reduced signal integrity. Especially in long-distance transmission and high-speed data exchange, signal attenuation and reflection problems are serious, affecting the stability and performance of the system.

[0006] The clock signals of various parts of the system are not synchronized, which will cause delays and errors in the data processing process, reducing the overall performance of the system. Traditional circuit boards lack high-precision, low-jitter clock management solutions and cannot ensure the synchronous operation of TTE network analyzers.

[0007] High-performance systems require multiple power supplies with different voltages. Existing circuit board power management solutions often cannot meet multiple voltage requirements at the same time, and lack overvoltage and undervoltage protection functions, resulting in unstable system operation.

[0008] Traditional TTE network analyzer circuit boards lack intuitive system status indication and user input control, making it difficult for users to monitor and adjust system status in real time, affecting system operability and maintainability.

[0009] In response to the above problems, the present invention provides an innovative circuit board design, which is specially developed for the TTE network analyzer project, integrating multiple high-speed interfaces and optimized power management and clock management solutions, significantly improving the performance, stability and scalability of the TTE network analyzer. By using FPGA as the core processing unit, combined with DDR3 memory, PCIe, SFP, LVDS and other interfaces, high-efficiency performance and precise clock synchronization in network data acquisition, processing and communication are achieved, comprehensively improving the applicability and reliability of the TTE network analyzer in high-performance application scenarios. Utility Model Content

[0010] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes a

[0011] In order to achieve the above-mentioned purpose of the utility model, the purpose of the utility model is to provide a high-performance multi-interface data acquisition, processing and communication circuit board for a TTE network analyzer, which significantly improves the performance, stability and scalability of the TTE network analyzer by integrating multiple high-speed interfaces and optimized power management and clock management solutions.

[0012] To achieve the above object, the utility model provides a data acquisition circuit board for a TTE network analyzer, comprising:

[0013] Power management module, providing multiple voltage outputs such as 1.5V, 1.8V, 3.3V, etc.

[0014] Clock management module, generating and distributing low-jitter, high-precision clock signals;

[0015] FPGA module, manages various interface signals such as LVDS, PCIe, and JTAG;

[0016] DDR3 memory interface module to achieve high-speed data access;

[0017] SFP interface module to achieve high-speed optical fiber communication;

[0018] PCIe interface module, to achieve high-speed data communication with the host system;

[0019] Indicator module and button module provide system status indication and user input control;

[0020] The power management module is connected to the processor D4 and the FPGA module, the clock management module is connected to the FPGA module, the FPGA module is connected to the DDR3 memory, the FPGA module is connected to the VPX connector through the PCIE X4 interface, the FPGA module is connected to the VPX connector through three sets of LVDS X3 switches, the FPGA module is connected to the lamp holder through the GPIO interface, the FPGA module is connected through the JTAG interface, the FPGA module is connected to the SFP interface module through the LVDS X4 switch, and the SFP X4 interface is connected to the external network.

[0021] Power management module: This module uses LTM4644EY#PBF power module, which provides multiple voltage outputs such as 1.5V, 1.8V, 3.3V, etc. Filtering and voltage stabilization are performed through the resistor-capacitor network to ensure the normal operation of each part.

[0022] The voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the resistor R146 The first end of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the step-down voltage regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the step-down voltage regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the power good indication terminal PGOOD4 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the step-down voltage regulator chip D12;

[0023] The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0024] The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of the buck regulator chip D12, the ground pin GND_11 of the buck regulator chip D12, the ground pin GND_12 of the buck regulator chip D12, the ground pin GND_13 of the buck regulator chip D12, the ground pin GND_14 of the buck regulator chip D12, the ground pin GND_15 of the buck regulator chip D12, the ground pin GND_16 of the buck regulator chip D12, the ground pin GND_17 of the buck regulator chip D12, the ground pin GND_18 of the buck regulator chip D12, the ground pin GND_19 of the buck regulator chip D12, and the ground pin GND_20 of the buck regulator chip D12 are all grounded. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1V_ for output through the buck regulator chip D12.

[0025] The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12;

[0026] The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0027] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0028] The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0029] The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0030] The internal power pin INTVCC1 of the buck regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck regulator chip D12, and the internal power pin INTVCC2 of the buck regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck regulator chip D12. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1.8V and VCC1.5V for output through the buck regulator chip D12.

[0031] Power management module, providing multiple voltage outputs such as 1.5V, 1.8V, 3.3V, etc.

[0032] In a preferred implementation manner of the present utility model, the model of the buck regulator chip D12 is LTM4644EY#PBF.

[0033] The clock management module includes a clock generator U1, a filter inductor, a filter capacitor, a voltage divider resistor, and a resistor-capacitor coupling network for impedance matching, and distributes the clock to the FPGA module through the clock generator U1;

[0034] The clock management module includes: an enable pin OE of the clock generator U1 is connected to the first end of the resistor R114, the second end of the resistor R114 is connected to the input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 is connected to the first end of the capacitor C244 and the second end of the inductor L5, the second end of the capacitor C244 is grounded, the first end of the inductor L5 is connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 is connected to the FPGA module and the first end of the capacitor C255, the second end of the capacitor C255 is connected to the first end of the resistor R126, the first end of the resistor R127, the first end of the inductor L5, the second end of the inductor L5 is connected to the input voltage VCC3.3V, The first end of resistor R171 is connected to the FPGA module, the second end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

[0035] The above FPGA module uses the processor D4 of the XC7K325T-2FFG900I model to manage various interface signals such as LVDS, PCIe, JTAG, etc. The LVDS interface is used for high-speed data transmission, the PCIe interface realizes high-speed data communication with the host system, and the JTAG interface is used for programming and debugging.

[0036] The DDR3 memory interface module includes a DDR3 memory chip and related decoupling capacitors and terminal resistors to achieve high-speed data access. The DDR3 memory chip U1 is connected to the processor D4 and performs data exchange through a data bus.

[0037] SFP interface module: including an SFP module interface connected to the LVD X4 switch through an Ethernet transmission line, and the LVD X4 switch is connected to the FPGA module.

[0038] PCIe interface module: connected to the VPX connector through the PCIe connector J1, and exchanges data with the data processing circuit board through the VPX connector to achieve high-speed data communication with the host system. The PCIe interface supports multi-channel parallel transmission.

[0039] In a preferred implementation of the present invention, the PCIe connector J1 is connected to the VPX connector, data is interacted with the data processing circuit board through the VPX connector, and the data is transmitted to the host computer system.

[0040] Indicator module and button module: including LED indicator lights D1-D4 and buttons S1-S4, which enhance the system operability and user experience by displaying system status and user input control.

[0041] Each module is connected through data bus, control signal and power line to form a complete high-performance multi-interface data acquisition, processing and communication system.

[0042] Through the combination of the above modules, the circuit board of the utility model realizes the integration of multiple high-speed interfaces, has a sufficiently high transmission bandwidth, efficient power management and precise clock synchronization to ensure higher signal integrity and transmission speed, as well as a user-friendly operation interface, which significantly improves the overall performance and applicability of the TTE network analyzer.

[0043] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0045] Figure 1 It is an overall block diagram of the utility model.

[0046] Figure 2 This is the circuit connection diagram of the power management module.

[0047] Figure 3 This is the circuit connection diagram of the clock management module.

[0048] Figure 4 This is a partial circuit connection diagram of the FPGA module.

[0049] Figure 5 This is a schematic diagram of an SFP interface module.

[0050] Figure 6 This is a circuit connection diagram of the PCIe interface module.

[0051] Figure 7 This is the key module circuit connection diagram.

[0052] Figure 8 This is the circuit connection diagram of the indicator light module. DETAILED DESCRIPTION

[0053] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0054] Figure 1 This is a structural block diagram of the circuit board of the utility model. As shown in the figure, the circuit board includes the following modules:

[0055] Power management module, providing multiple voltage outputs such as 1.5V, 1.8V, 3.3V, etc.

[0056] Clock management module, generating and distributing low-jitter, high-precision clock signals;

[0057] FPGA module, manages various interface signals such as LVDS, PCIe, and JTAG;

[0058] DDR3 memory interface module to achieve high-speed data access;

[0059] SFP interface module to achieve high-speed optical fiber communication;

[0060] PCIe interface module, to achieve high-speed data communication with the host system;

[0061] Indicator module and button module provide system status indication and user input control;

[0062] Power management module: This module uses LTM4644EY#PBF power module, which provides multiple voltage outputs such as 1.5V, 1.8V, 3.3V, etc. Capacitors C1, C2 and resistors R1, R2 are used for filtering and voltage stabilization to ensure the normal operation of each part.

[0063] In the above solution, the power management module includes:

[0064] The voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the resistor R146 The first end of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the step-down voltage regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the step-down voltage regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the power good indication terminal PGOOD4 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the step-down voltage regulator chip D12;

[0065] The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0066] The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of the buck regulator chip D12, the ground pin GND_11 of the buck regulator chip D12, the ground pin GND_12 of the buck regulator chip D12, the ground pin GND_13 of the buck regulator chip D12, the ground pin GND_14 of the buck regulator chip D12, the ground pin GND_15 of the buck regulator chip D12, the ground pin GND_16 of the buck regulator chip D12, the ground pin GND_17 of the buck regulator chip D12, the ground pin GND_18 of the buck regulator chip D12, the ground pin GND_19 of the buck regulator chip D12, and the ground pin GND_20 of the buck regulator chip D12 are all grounded. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1V_ for output through the buck regulator chip D12.

[0067] The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12;

[0068] The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0069] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0070] The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0071] The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0072] The internal power pin INTVCC1 of the buck regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck regulator chip D12, and the internal power pin INTVCC2 of the buck regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck regulator chip D12. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1.8V and VCC1.5V for output through the buck regulator chip D12.

[0073] In a preferred embodiment of the utility model, the power management module includes capacitors C272, C273, C274 and C275, each of which has a capacitance of 22uF, capacitors C276, C277 and C278, each of which has a capacitance of 0.1uF, and capacitors C279, C280, C281, C282, C283 and C284, each of which has a capacitance of 47uF.

[0074] In a preferred embodiment of the present utility model, the power management module includes resistors R139, R140, R141 and R142, each having a resistance value of 10 kΩ, resistors R143 and R146 having a resistance value of 90.9 kΩ, resistor R145 having a resistance value of 40.2 kΩ, and resistor R144 having a resistance value of 30.1 kΩ.

[0075] Clock management module: includes clock generator U1, filter inductor, filter capacitor, voltage divider resistor and resistor-capacitor coupling network for impedance matching. The clock is distributed to the FPGA module through clock generator U1.

[0076] The clock management module includes: an enable pin OE of the clock generator U1 is connected to the first end of the resistor R114, the second end of the resistor R114 is connected to the input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 is connected to the first end of the capacitor C244 and the second end of the inductor L5, the second end of the capacitor C244 is grounded, the first end of the inductor L5 is connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 is connected to the FPGA module and the first end of the capacitor C255, the second end of the capacitor C255 is connected to the first end of the resistor R126, the first end of the resistor R127, the first end of the inductor L5, the second end of the inductor L5 is connected to the input voltage VCC3.3V, The first end of resistor R171 is connected to the FPGA module, the second end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

[0077] In a preferred embodiment of the present invention, the clock management module includes: the resistance of resistor R114 is 1KΩ, the capacitance of capacitor 244 is 0.1uF, the resistance of resistors R126, R127, R130 and R155 are 10kΩ, and the resistance of resistor R171 is 100Ω.

[0078] The FPGA module includes a processor D4, which is connected to the SFP module via an LVDS switch, the processor D4 is connected to the VPX connector via the LVDS switch, the processor D4 is connected to three other data acquisition circuit boards via the VPX connector, the processor D4 is connected to the VPX connector via a PCIE interface, and the processor D4 is connected to the debugging serial port via a JTAG interface.

[0079] DDR3 memory interface module: high-speed data access is achieved through DDR3 memory chip and related decoupling capacitors and terminal resistors. DDR3 memory chip U1 is connected to processor D4 and data is exchanged through the data bus.

[0080] SFP interface module: including an SFP module interface connected to the LVD X4 switch through an Ethernet transmission line, and the LVD X4 switch is connected to the FPGA module.

[0081] PCIe interface module: connected to the VPX connector through the PCIe connector J1, and exchanges data with the data processing circuit board through the VPX connector to achieve high-speed data communication with the host system. The PCIe interface supports multi-channel parallel transmission.

[0082] It is connected to the VPX connector through the PCIe connector J1, and exchanges data with the data processing circuit board through the VPX connector, thereby transmitting the data to the host computer system.

[0083] Indicator module and button module: including LED indicator lights and buttons, which enhance the system operability and user experience by displaying system status and user input control.

[0084] Each module is connected through data bus, control signal and power line to form a complete high-performance multi-interface data acquisition, processing and communication system.

[0085] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A data acquisition circuit board for a TTE network analyzer, characterized in that: The circuit board comprises: Power management module, clock management module, FPGA module, LVDS switch, JTAG interface, DDR3 memory interface module, SFP interface module, PCIe interface module, indicator module and button module; The power management module is connected to the FPGA module, the clock management module is connected to the FPGA module, the FPGA module is connected to the DDR3 memory, the FPGA module is connected to the VPX connector through the PCIE X4 interface, the FPGA module is connected to the VPX connector through three sets of LVDS X3 switches, wherein the PCIE X4 interface interacts with the data processing circuit board, the LVDS X3 is connected to another three data acquisition circuit boards, the FPGA module is connected to the indicator module and the button module through the GPIO interface, the FPGA module is connected to the JTAG interface, the FPGA module is connected to the SFP interface module through the LVDS X4 switch, and the SFP X4 interface is connected to the external network.

2. A data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The power management module includes a step-down voltage regulator chip D12, and a plurality of capacitors and resistors for filtering and voltage stabilization; The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12; The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12; The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12; The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12; The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded; The internal power supply pin INTVCC1 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D12, and the internal power supply pin INTVCC2 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D12; The voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the resistor R146 The first end of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the step-down voltage regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the step-down voltage regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the power good indication terminal PGOOD4 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the step-down voltage regulator chip D12; The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12; The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of buck voltage regulator chip D12, the ground pin GND_11 of buck voltage regulator chip D12, the ground pin GND_12 of buck voltage regulator chip D12, the ground pin GND_13 of buck voltage regulator chip D12, the ground pin GND_14 of buck voltage regulator chip D12, the ground pin GND_15 of buck voltage regulator chip D12, the ground pin GND_16 of buck voltage regulator chip D12, the ground pin GND_17 of buck voltage regulator chip D12, the ground pin GND_18 of buck voltage regulator chip D12, the ground pin GND_19 of buck voltage regulator chip D12, and the ground pin GND_20 of buck voltage regulator chip D12 are all grounded.

3. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The clock management module includes an enable pin OE of the clock generator U1 connected to the first end of the resistor R114, the second end of the resistor R114 connected to the input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 connected to the first end of the capacitor C244 and the second end of the inductor L5, the second end of the capacitor C244 is grounded, the first end of the inductor L5 is connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 is connected to the FPGA module and the first end of the capacitor C255, the second end of the capacitor C255 is connected to the first end of the resistor R126, the first end of the resistor R127, the resistor R The first end of resistor R171 is connected to the FPGA module, the second end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

4. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The FPGA module includes a processor D4, which is connected to the SFP module via an LVDS switch, the processor D4 is connected to the VPX connector via the LVDS switch, the processor D4 is connected to three other data acquisition circuit boards via the VPX connector, the processor D4 is connected to the VPX connector via a PCIE interface, and the processor D4 is connected to the debugging serial port via a JTAG interface.

5. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The SFP module interface is connected to the LVD X4 switch through an Ethernet transmission line, the LVD X4 switch is connected to the FPGA module, and the SFP module is connected to an external network.

6. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: It is connected to the VPX connector through the PCIe connector J1, and exchanges data with the data processing circuit board through the VPX connector, thereby transmitting the data to the host computer system.

7. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The indicator light module and the key module are connected to the FPGA module through the GPIO interface, wherein the indicator light module and the key module include LED indicator lights and keys to display system status and user input control.

8. The data acquisition circuit board for a TTE network analyzer according to claim 1, characterized in that: The model of the clock generator U1 of the clock management module is SI534BC002369DG.

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