Memory access control chip, data memory access method and data memory access system

Abstract

The invention provides a memory access control chip, a data memory access method and a data memory access system, and relates to the technical field of computers, in particular to the technical field of chips. The memory access control chip comprises m first controllers and k second controllers, the m first controllers and the k second controllers are connected through an interconnection bus, and m and k are respectively positive integers; wherein the first controller is used for converting a received data access request into an access request conforming to a double data rate (DDR) interface protocol, and sending the access request to a connected DDR through a first interface; and the second controller is used for receiving a data access request sent by the CXL chip through the second interface, determining a target controller according to the configuration information and a target access address in the data access request, and sending the data access request to the target controller through the interconnection bus. The data access method can be realized through an access control chip, and the data access system comprises the access control chip.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular to the field of technologies such as chips, and specifically relates to a memory access control chip, a data memory access method, and a data memory access system. Background Art

[0002] Compute Express Link (CXL) is an open standard high-speed interconnection protocol aimed at solving the interconnection problem between computing devices and memory, and is a core technology for realizing the separation of storage and computing. The CXL pooling function can realize the sharing of memory among multiple Central Processing Units (CPUs), which is of great significance for improving system performance and optimizing memory resource utilization.

[0003] Since many computing tasks on the CPU are sensitive to memory access latency, and the computing tasks run on the CXL pooled memory, the performance is greatly reduced compared with running on the local memory, and in many cases, the requirements of users cannot be met. Therefore, there is an urgent need for a solution to reduce the latency of accessing the pooled memory. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.

[0005] To this end, the purpose of the present disclosure is to provide a memory access control chip, a data memory access method, and a data memory access system. By designing a Double Data Rate (DDR) memory and a CXL controller on one chip, the data access to the pooled memory is realized, which can effectively reduce the read / write latency of the CXL memory pool and improve the performance of computing tasks running on the pooled memory.

[0006] According to a first aspect of the present disclosure, there is provided a memory access control chip, including: m first controllers and k second controllers, where the m first controllers and the k second controllers are connected through an interconnection bus, and m and k are positive integers respectively;

[0007] Among them, the first controller is configured to convert the received data memory access request into a data memory access request that conforms to the Double Data Rate (DDR) interface protocol, and send it to the connected DDR through a first interface;

[0008] The second controller is configured to receive a data memory access request sent by a CXL chip through a second interface, determine a target controller according to the configuration information and the target memory access address in the data memory access request, and send the data memory access request to the target controller through the interconnection bus.

[0009] According to a second aspect of the present disclosure, there is provided a data memory access method, including:

[0010] Receive a data access request sent by the CXL chip, where the data access request includes a target access address;

[0011] Determine a target controller according to the configuration information and the target access address;

[0012] Send the data access request to the target controller, so that the target controller converts the data access request into a data access request that conforms to the double data rate DDR interface protocol and then sends it to the target DDR.

[0013] According to a third aspect of the present disclosure, there is provided a data access system, including a memory access control chip as described in the first aspect of the present disclosure, m DDR chips respectively connected to the first interface of the memory access control chip, and k CXL chips respectively connected to the second interface of the memory access control chip.

[0014] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause the computer to execute the data access method as described in the second aspect.

[0015] According to a fifth aspect of the present disclosure, there is provided a computer program product, including a computer program, and the computer program implements the data access method as described in the second aspect when executed by a processor.

[0016] The memory access control chip, data access method, and data access system provided by the present disclosure have the following beneficial effects:

[0017] By integrating multiple controllers connected to the DDR memory and multiple controllers connected to the CXL chip on one chip and connecting them using an interconnection bus, it is possible to obtain the requested data from the DDR memory or the CPU chip according to the access address in the data access request, so that while realizing CXL pooling and multi-CPU shared memory, the delay of the CPU accessing the pooled memory can be reduced, the performance of the computing tasks running on the pooled memory can be improved, and the data access experience can be optimized.

[0018] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present disclosure will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings. The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure, where:

[0020] Figure 1It is a schematic structural diagram of a memory access control chip proposed according to an embodiment of the present disclosure;

[0021] Figure 2 It is a schematic system diagram of a data memory access implemented using a CXL memory card according to an embodiment of the present disclosure;

[0022] Figure 3 It is a schematic flowchart of a data memory access method proposed according to an embodiment of the present disclosure;

[0023] Figure 4 It is a schematic structural diagram of a data memory access system proposed according to an embodiment of the present disclosure. Detailed implementation manners

[0024] The following makes an explanation of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings. Among them, various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted below.

[0025] The embodiments of the present disclosure relate to technical fields such as chips.

[0026] A chip, also known as a microcircuit, microchip or integrated circuit, is the core component of modern electronic devices. It is a microelectronic circuit that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) on a tiny semiconductor material. Its working principle is based on the physical properties of semiconductor materials. By doping and other processes, its electrical properties are changed, and then semiconductor devices with different functions are manufactured. These devices are then combined into a complex circuit system to achieve specific electronic functions.

[0027] The chips involved in the present disclosure include memory access control chips and CXL chips.

[0028] A memory access control chip is a chip proposed in the present disclosure that has a Compute Express Link (CXL) switch function and supports the CXL pooling function through control logic including Double Data Rate (DDR) memory. The memory access control chip can provide a low-latency, high-bandwidth connection path between multiple devices (such as a Central Processing Unit (CPU)) that support the CXL protocol, and can use DDR memory to build a CXL memory pool to reduce read and write latency.

[0029] A CXL chip refers to a master device that supports the CXL protocol, such as a CPU chip. The CPU chip can be built with a CXL controller to support high-speed communication with other devices.

[0030] In the present disclosure, the memory access control chip and the CXL chip have different functions. The memory access control chip can be connected to the CXL chip, receive data memory access requests sent by the CXL chip, and can access the memory of the connected CXL chip according to the requests.

[0031] In the technical solution of the present disclosure, the processing of the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0032] The following describes the memory access control chip, data memory access method, and data memory access system according to the embodiments of the present disclosure with reference to the accompanying drawings.

[0033] Figure 1 It is a schematic structural diagram of a memory access control chip according to an embodiment of the present disclosure.

[0034] As Figure 1 shown, the memory access control chip includes m first controllers and k second controllers. The m first controllers and the k second controllers are connected through an interconnection bus, where m and k are positive integers respectively. The memory access control chip can also be referred to as a Compute Express Link (CXL) controller chip.

[0035] Among them, the first controller refers to a Double Data Rate (DDR) controller, which contains the master logic of the DDR memory.

[0036] In the embodiments of the present application, the first controller can be used to convert the received data memory access request into a memory access request that conforms to the Double Data Rate DDR interface protocol and send it to the connected DDR through the first interface.

[0037] As Figure 1 shown, each first controller can be connected to the second controller through the interconnection bus. The interconnection bus provides a fully connected data path, so the first controller can receive the data memory access requests sent by the second controller through the interconnection bus. Then, the first controller can convert the received data access requests so that they conform to the DDR interface protocol, and thus the converted access requests can be sent to the connected DDR through the first interface connected to the DDR memory to obtain the data in the DDR memory, ensuring the consistency and standardization of the request format and helping to reduce errors and exceptions caused by inconsistent formats.

[0038] Among them, the second controller is a Compute Express Link (CXL) device controller, which may include CXL upstream port control logic.

[0039] In the embodiments of the present application, the second controller can be used to receive a data access request sent by a CXL chip through a second interface, and then determine a target controller according to the configuration information and the target access address in the data access request, and send the data access request to the target controller through an interconnection bus.

[0040] It should be noted that the second interface is the interface on the second controller connected to the CXL chip. The CXL chip is a Central Processing Unit (CPU) chip based on CXL technology, which may include one or more CXL master controllers.

[0041] In the embodiments of the present application, the configuration information includes the correspondence between addresses and controllers. After the second controller receives a data access request sent by the CXL chip, the CXL upstream port control logic of the second controller can search for the target controller corresponding to the target access address in the data access request in the configuration information, and thus can send the data access request to the target controller according to the interconnection bus.

[0042] It should be noted that Figure 1 In the memory access control chip shown, the target access address in the memory access request can be a DDR memory or other CXL chips, so the target controller may be the first controller or the second controller.

[0043] In the embodiments of the present application, when the target controller is the first controller and the first controller sends the memory access request to the connected DDR through the first interface, the first controller can read data from the connected DDR memory and send the data to the CXL chip that issues the memory access request through the interconnection bus, the upstream port control logic (i.e., the second controller), and the second interface.

[0044] It should be noted that Figure 1 The numbers of the first controller and the second controller are only for illustration, and can be increased or decreased according to needs in an actual memory access control chip, and the present disclosure does not limit this.

[0045] In this embodiment, by integrating multiple controllers connected to the DDR memory and multiple controllers connected to the CXL chips on one chip and connecting them using an interconnect bus, it is possible to obtain the target accessed data from the DDR memory or the CXL chips according to the memory access address in the data memory access request. Thus, while realizing CXL pooling and multi-CPU shared memory, it is possible to reduce the latency of CPU access to the pooled memory, improve the performance of computing tasks running on the pooled memory, and optimize the data memory access experience.

[0046] Optionally, in the Figure 1 shown chip, it may further include a buffer area connected to the interconnect bus and n control logic units, where n is a positive integer.

[0047] Among them, the buffer area is the Figure 1 system cache (Cache) in. The buffer area can be used to cache the frequently used data in the CXL chips to reduce the latency of accessing the CXL chips.

[0048] Among them, the control logic unit, that is, the Figure 1 cache (Cache) coherence control logic unit in, is used to record the cache situation and cache status of the data in the buffer area, the DDR memory, or the CXL chips.

[0049] It should be noted that the memory access control chip proposed in this disclosure can be connected to multiple CXL chips at the same time. Therefore, there may be operations where multiple CPU cores read and write to the same memory address, and if the Cache data is inconsistent, it may cause system errors or crashes. So the control logic unit should conform to Cache coherence.

[0050] In the embodiment of this disclosure, each control logic unit can be used to store the first data information stored in the buffer area and the second data information stored in the associated DDR and CXL chips.

[0051] Among them, the first data information is the cache situation and cache status of the data in the buffer area, which may include the data content and its corresponding memory access address. The second data information is the storage situation and status of the data in the DDR and CXL chips associated with this control logic unit. By analyzing the first data information and the second data information, it is possible to determine whether the latest data requested for memory access is in the buffer area, the DDR memory, or the CXL chips.

[0052] In the embodiments of the present disclosure, the entire memory address space can be partitioned. Each partition of the memory address space is a DDR memory, and the memory access control chip can be connected to multiple CXL chips. To improve the memory access efficiency of the DDR and CXL chips, multiple control logic units can be set in the memory access control chip, and each control logic unit is associated with one or more DDR and CXL chips to respectively record the data information stored therein. Also, there can be multiple buffer areas associated with the control logic units, such as Figure 1 System Cache0 and System Cache1 in

[0053] In the embodiments of the present disclosure, by setting a buffer area in the memory access control chip to store frequently used data, the data access speed can be increased, the access latency can be reduced, and by setting multiple control logic units in the memory access control chip to perform partition management on the memory address space, the memory access efficiency can be further improved.

[0054] Optionally, since Figure 1 the chip shown contains n control logic units, the second controller can also be used to send a data memory access request to the target control logic unit associated with the target controller through an interconnection bus. Then, the target control logic unit can be used to determine the response mode of the data memory access request based on the first data information and / or the second data information.

[0055] In the embodiments of the present disclosure, each control logic unit is associated with one or more DDR and CXL chips, and each DDR or CXL chip is connected to a controller through an interface, so the control logic unit is associated with the controller. After the second controller receives a data memory access request and determines the target controller according to the target memory access address in the data memory access request, in order to determine whether the latest data is in the buffer area, the DDR memory, or the CXL chip, the data memory access request can first be sent to the target control logic unit associated with the target controller. The target control logic unit can judge the location of the earliest data based on the first data information and / or the second data information, and determine the response mode of the data memory access request according to the location.

[0056] In the embodiments of the present disclosure, the response mode can include: in the case where the latest data is in another CXL chip, sending a snooping command to notify the CXL chip to write back the latest data; in the case where the latest data is in the system cache, obtaining the latest data in the system cache and sending it to the CXL chip that issued the memory access request through the interconnection bus and the upstream port control logic; or in the case where the latest data is in the DDR memory, sending the memory access request to the DDR memory through the interconnection bus and the first controller of the DDR, and then sending the read data to the CXL chip that issued the memory access request through the interconnection bus and the upstream port control logic.

[0057] In the embodiments of the present disclosure, the second controller sends a data memory access request to the target control logic unit associated with the target controller. The target control logic unit determines the location of the latest data to be accessed based on the stored data information, and then determines the response mode of the data memory access request, which can further improve the efficiency of data memory access.

[0058] Optionally, when the data memory access request is a data read request, the target control logic unit can be used to determine the storage location of the target data corresponding to the target memory access address based on the first data information and the second data information.

[0059] In the embodiments of the present disclosure, the target data corresponding to the target memory access address is the latest data. The first data information and the second data information may include the time of data storage, so the storage location of the target data corresponding to the target memory access address, whether it is other CXL chips, DDR memory or buffer, can be determined based on the first data information and the second data information.

[0060] Then, when the storage location of the target data is other CXL chips, the target control logic unit can send a data read request to the second controller associated with the other CXL chips.

[0061] In the embodiments of the present application, the target control logic unit needs to send a snooping command to other CXL chips through the interconnect bus and the second controller associated with the other CXL chips. The snooping command includes the target memory access address.

[0062] After that, when receiving the target data returned by the associated second controller, the target control logic unit can send the target data to the CXL chip that initiated the data read request.

[0063] In the embodiments of the present disclosure, the other CXL chips that receive the snooping command can send the target data to the target control logic unit via the upstream port control logic of the second controller and the interconnect bus. Thus, the target control logic unit can send the target data to the CXL chip that initiated the data read request via the interconnect bus and the upstream port control logic associated with the CXL chip that initiated the data read request.

[0064] In the embodiments of the present disclosure, the memory access control chip can read data using the controller connected to the other CXL chips when the storage location of the target data is other CXL chips, realizing memory sharing between multiple CPUs and optimizing resource utilization.

[0065] Optionally, after obtaining the target data, the target control logic unit can write the target data into the buffer and update the first data information based on the target data and the target memory access address.

[0066] In the embodiments of the present disclosure, the obtained target data may need to be frequently accessed. Since the access speed of the cache is generally much faster than that of the main memory or the disk, the target data obtained from the CXL chip is written into the buffer area, i.e., the system cache. Subsequently, when reading the target data again, there is no need to access the CXL chip, thereby effectively reducing the read and write latency of the CXL memory pool. Moreover, when writing the target data into the buffer area, the first data information can be updated by using the target data and the target memory access address.

[0067] It should be noted that when writing the target data into the buffer area but the buffer area is full, the target data and the target memory access address can be used to replace the data with the lowest access frequency and its corresponding memory access address in the current buffer area, completing the update of the first data information. Thereby, the resource utilization rate of the buffer area can be improved, and the accuracy of the control logic unit to determine the response mode based on the stored data information can be ensured.

[0068] Alternatively, when the storage location of the target data is any DDR, the target control logic unit can send a data read request to the first controller associated with any DDR, and then, when receiving the target data returned by the associated first controller, send the target data to the CXL chip that initiated the data read request.

[0069] In the embodiments of the present disclosure, the target control logic unit can send the data read request through the interconnection bus to the first controller associated with the any DDR. The first controller can read the target data from the connected DDR memory, and then send the target data through the interconnection bus and the upstream port control logic associated with the CXL chip that initiated the data read request to the CXL chip that initiated the data read request.

[0070] In the embodiments of the present disclosure, the memory access control chip can read data by using the controller connected to the DDR when the storage location of the target data is DDR, thereby realizing the access to the DDR memory during CXL pooling, optimizing the data transmission speed, and greatly improving the performance of the computing tasks running on the pooled memory.

[0071] Alternatively, when the storage location of the target data is the buffer area, the target control logic unit can obtain the target data from the buffer area, and then send the target data to the CXL chip that initiated the data read request.

[0072] In the embodiments of the present disclosure, the target control logic unit can obtain the target data from the buffer area, and then send the target data through the interconnection bus and the upstream port control logic associated with the CXL chip that initiated the data read request to the CXL chip that initiated the data read request.

[0073] In the embodiments of the present disclosure, when the storage location of the target data is the buffer, the memory access control chip can directly read the data in the buffer, thereby improving the efficiency of data memory access and further enhancing the performance of the computing tasks running on the pooled memory.

[0074] Optionally, when the data memory access request is a data write request, the target control logic unit can also be used to send a data write request to other control logic units through the interconnection bus when the amount of data to be written is greater than the threshold.

[0075] Among them, the threshold can be set according to experience, and the present disclosure does not limit this.

[0076] In the embodiments of the present disclosure, when the data memory access request is a data write request, the controller corresponding to the memory address where the data is to be written is determined by the target memory access address in the data memory access request, and then the data write request can be sent to the target control logic unit associated with the controller. The target control logic unit can determine whether to write the data into a single DDR or multiple DDRs according to the size of the amount of data to be written in the data write request. Since a larger bandwidth is required when the amount of data to be written is greater than the threshold, the target control logic unit can send a data write request to other control logic units through the interconnection bus to determine multiple DDRs that can write data currently.

[0077] Then, when receiving the response message returned by other control logic units, control the data to be written to be interleaved and written into the target DDR associated with the target control logic unit and other DDRs associated with other control logic units.

[0078] In the embodiments of the present disclosure, after other control logic units receive the data write request and determine that data can be written into the associated DDR, these other control logic units can return a response message to the target control logic unit. After receiving the response message, the target control logic unit can control the data to be written to be interleaved and written into the target DDR associated with the target control logic unit and other DDRs associated with other control logic units to increase the effective bandwidth of memory access.

[0079] In Figure 1 The memory access control chip shown may further include a CXL chip system management logic unit, which is connected to the interconnection bus and can manage the startup, initial configuration, power consumption, clock, etc. of the chip.

[0080] It should be noted that when the requirement for data access latency is not high, data memory access can also be implemented by using CXL extended memory.

[0081] Optionally, the memory access control chip may further include j third controllers connected to the interconnection bus, where j is a positive integer.

[0082] Among them, the third controller includes CXL downlink port control logic, and each third controller can be connected to a CXL memory card with pooling function.

[0083] In the embodiments of the present disclosure, each third controller can be used to send the received data memory access request to the connected CXL memory card through the third interface. Thus, CXL pooling can also be implemented through memory expansion, so that the data memory access task is not limited by the memory capacity or memory bandwidth.

[0084] The following Figure 2 illustrates how to implement data memory access control when the memory access control chip includes a third controller. Figure 2 That is, it is a schematic diagram of a system for implementing data memory access using a CXL memory card provided by the embodiments of the present disclosure.

[0085] In Figure 2 , since the CXL Switch function can be implemented in the memory access control chip, it can also be called a CXL Switch chip, which can include multiple CXL uplink port control logics (i.e., the second controller) and multiple CXL downlink port control logics (i.e., the third controller). Each second controller is connected to a CPU chip, and the CPU chip can also be connected to the local memory. Each third controller is connected to a CXL memory card with pooling function. And, in Figure 2 the shown chip, an FM management logic unit can also be included to manage and configure the binding relationship between the uplink port and the downlink port inside the CXL Switch chip.

[0086] In the embodiments of the present disclosure, Figure 2 for the CXL memory pooling system implemented by the shown CXL Switch chip and the memory card supporting the CXL pooling function, taking the memory read process as an example, the CPU chip can first send a memory read request to the CXL Switch chip. According to the memory access address included in the received memory read request, the CXL uplink port control logic of the CXL Switch chip can determine the CXL downlink port to be accessed according to the system configuration, and then the CXL downlink port control logic sends the memory access request to the CXL memory card with pooling function. The CXL memory card can determine whether the latest data corresponding to the memory access address exists in the CXL memory card or in other CPU chips.

[0087] If the latest data is in the CXL memory card, the CXL memory card can send the read data to the CPU chip that issues the memory access request through the downlink port control logic, the interconnection bus, and the uplink port control logic of the CXL Switch chip.

[0088] If the latest data is in other CPU chips, the CXL memory card needs to first send a listen command to notify the CPU chip to write the latest data back to the CXL memory card, and then the CXL memory card delivers it to the CPU chip that issues the memory access request. The listen command sent by the CXL memory card will reach the CPU chip through the downstream port control logic, the interconnect bus, and the upstream port control logic of the CXL Switch chip. The CPU chip that receives the listen command can deliver the latest data to the CXL memory card through the upstream port control logic, the interconnect bus, and the downstream port control logic of the CXL Switch chip.

[0089] It should be noted that because the system structure when using the CXL memory card to implement data memory access is mainly described in Figure 2 , and since there is no need to access the DDR memory at this time, the controller for connecting the DDR memory and the like are not marked in the control chip of Figure 2 . In the specific implementation process, if the memory access control chip needs to access the DDR memory and also needs to access the CXL memory card, the chip structures shown in Figure 1 and Figure 2 can be combined, and the present disclosure does not limit the combination method.

[0090] For the memory access control chip described in the above embodiments, the present disclosure also proposes a data memory access method to implement data reading, writing, etc. using the memory access control chip.

[0091] Figure 3 is a schematic flowchart of the data memory access method proposed in an embodiment of the present disclosure.

[0092] As Figure 3 shown, the data memory access method includes:

[0093] S301: Receive a data memory access request sent by the CXL chip.

[0094] Among them, the memory access request includes the target memory access address.

[0095] In the embodiments of the present disclosure, the second controller in the memory access control chip can be connected to the CXL chip, and the memory access control chip can receive the data memory access request sent by the CXL chip through the second interface connected to the CXL chip by the second controller.

[0096] S302: Determine the target controller according to the configuration information and the target memory access address.

[0097] Among them, the target controller is any controller in the memory access control chip that is connected to the DDR memory.

[0098] In an embodiment of the present disclosure, the configuration information includes the correspondence between addresses and controllers. After receiving a data memory access request, the memory access control chip can, according to the target memory access address included in the data memory access request, look up the target controller corresponding to the target memory access address in the configuration information, and the target controller can obtain the target data corresponding to the memory access address from the connected memory.

[0099] S303: Send the data memory access request to the target controller so that the target controller converts the data memory access request into a data memory access request conforming to the double data rate DDR interface protocol and then sends it to the target DDR.

[0100] Among them, the target DDR is the memory connected to the target controller and containing the target data corresponding to the target memory access address.

[0101] In an embodiment of the present disclosure, after determining the target controller, the memory access control chip can have the target controller convert the memory access request into a memory access request conforming to the double data rate DDR interface protocol and then send it to the target DDR through the interface connected to the DDE.

[0102] In an embodiment of the present disclosure, since the data memory access method can be implemented by using the memory access control chip, for a detailed description of the data memory access method, reference can be made to the description of the memory access control chip in the above embodiments of the present disclosure, and details are not described herein again.

[0103] In this embodiment, by determining the controller corresponding to the memory access address according to the memory access address in the data memory access request, and then having the controller obtain the target accessed data from the connected DDR memory, it is possible to implement CXL pooling by using a double data rate memory, reduce the latency of accessing the pooled memory, improve the performance of the computing tasks running on the pooled memory, and optimize the data memory access experience.

[0104] Optionally, for this data memory access method, when the data memory access request is a read request, the target data read from other CXL chips can be stored in the buffer area, and then based on the target data and the target address, the first data information stored in the buffer area can be updated. Thus, the efficiency of data memory access can be improved, and the performance of the computing tasks running on the pooled memory can be further improved.

[0105] The present disclosure also proposes a data memory access system. Figure 4 It is a schematic structural diagram of the data memory access system.

[0106] As Figure 4 shown, the data memory access system may include the memory access control chip in the above embodiment, m DDR chips respectively connected to the first interface of the memory access control chip, and k CXL chips respectively connected to the second interface of the memory access control chip.

[0107] It should be noted that in the present disclosure, the data memory access system may include multiple memory access control chips. For example, it may include 2 memory access control chips, which are respectively marked as memory access control chip 0 and memory access control chip 1 in Figure 4 . The structures in memory access control chip 0 and memory access control chip 1 are as described above Figure 1 shown in Figure 4 . In order to simplify the schematic diagram in

[0108] In Figure 4 , the CXL chip connected to the second interface of the memory access control chip is the CPU chip containing the CXL main controller. The number of CXL main controllers in the CPU chip determines the number of memory access control chips it can be connected to. Therefore, when there are k second controllers in the memory access control chip, there are k second interfaces, which are marked as second interface 0, 1, 2, 3 in Figure 4 . The data memory access system may include k CXL chips, which are respectively marked as CXL chip 0, 1, 2, 3 in Figure 4 and are connected to the memory access control chip.

[0109] It should be noted that the connection relationship between the CXL main controller and the first interfaces in each memory access control chip in Figure 4 is only schematic. In some embodiments, multiple CXL main controllers in one CXL chip may also be respectively connected to multiple first interfaces in the same memory access control chip.

[0110] In the embodiments of the present disclosure, when there are m first controllers in the memory access control chip (marked as DDR controller 0, 1, 2, 3 in Figure 4 ), there are m first interfaces, and each first interface can be connected to a DDR chip providing DDR memory. Then the data memory access system may include m DDR chips.

[0111] In the embodiments of the present disclosure, by providing a data memory access system including a memory access control chip, m DDR chips, and k CXL chips, high-speed CXL pooled memory access can be achieved, the read / write latency of the CXL memory pool can be effectively reduced, and the CXL memory pooling system can have higher performance in computing tasks.

[0112] According to an embodiment of the present disclosure, the present disclosure also provides a readable storage medium and a computer program product.

[0113] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field-programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems-on-a-chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0114] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0115] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0116] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0117] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), the Internet, and blockchain network.

[0118] A computer system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The relationship between the client and the server is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services ("Virtual Private Server", or simply "VPS"). The server can also be a server of a distributed system, or a server combined with blockchain.

[0119] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0120] Furthermore, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, the words "if" and "when" may be interpreted as "when", "while", "in response to determining", or "in the case of".

[0121] The above specific embodiments do not limit the scope of protection of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A memory access control chip, comprising: m first controllers and k second controllers, the m first controllers and the k second controllers are connected via an interconnection bus, and m and k are positive integers respectively; Wherein, the first controller is used to convert the received data memory access request into a data memory access request that complies with the double data rate DDR interface protocol, and send it to the connected DDR through the first interface; The second controller is used to receive a data access request sent by the CXL chip through the second interface, determine a target controller according to configuration information and a target access address in the data access request, and send the data access request to the target controller through the interconnection bus.

2. The memory access control chip according to claim 1, wherein: The memory access control chip also includes a cache area connected to the interconnect bus and n control logic units, where n is a positive integer; Each of the control logic units is used to store the first data information stored in the buffer area and the second data information stored in the associated DDR and CXL chips.

3. The memory access control chip according to claim 2, wherein: The second controller is further configured to send the data access request to a target control logic unit associated with the target controller via the interconnection bus; The target control logic unit is used to determine a response mode of the data access request based on the first data information and / or the second data information.

4. The memory access control chip according to claim 3, wherein: The data memory access request is a data read request; The target control logic unit is used to determine the storage location of the target data corresponding to the target memory access address based on the first data information and the second data information; When the storage location of the target data is another CXL chip, sending the data read request to a second controller associated with the other CXL chip; When receiving the target data returned by the associated second controller, the target data is sent to the CXL chip that initiated the data read request.

5. The memory access control chip according to claim 4, wherein: The target control logic unit is further used for: In a case where the storage location of the target data is any DDR, sending the data read request to a first controller associated with any DDR; In case of receiving the target data returned by the associated first controller, the target data is sent to the CXL chip that initiated the data read request.

6. The memory access control chip as claimed in claim 4, wherein: The target control logic unit is further used for: Writing the target data into the buffer area; Based on the target data and the target memory access address, the first data information is updated.

7. The memory access control chip according to claim 4, wherein: The target control logic unit is further used for: In a case where the storage location of the target data is a cache area, acquiring the target data from the cache area; The target data is sent to the CXL chip that initiates the data read request.

8. The memory access control chip as claimed in claim 3, wherein: The data memory access request is a data write request; The target control logic unit is further configured to send a data write request to other control logic units via the interconnection bus when the amount of data to be written is greater than a threshold value; When a response message returned by the other control logic unit is received, the data to be written is controlled to be interleaved and written into the target DDR associated with the target control logic unit and other DDRs associated with the other control logic units.

9. The memory access control chip according to any one of claims 1 to 8, wherein: The memory access control chip further includes j third controllers connected to the interconnection bus, where j is a positive integer; Each of the third controllers is used to send the received data access request to the connected CXL memory card through the third interface.

10. A data access method, comprising: Receiving a data memory access request sent by the CXL chip, wherein the data memory access request includes a target memory access address; Determine a target controller according to the configuration information and the target memory access address; The data memory access request is sent to the target controller, so that the target controller converts the memory access request into a data memory access request that complies with a double data rate DDR interface protocol and then sends the request to a target DDR.

11. The method of claim 10, wherein: Also includes: In the case where the data access request is a read request, storing the target data read from the other CXL chip into a cache area; Based on the target data and the target address, the first data information stored in the buffer is updated.

12. A data memory access system, comprising the memory access control chip according to any one of claims 1 to 9, m DDR chips respectively connected to a first interface of the memory access control chip, and k CXL chips respectively connected to a second interface of the memory access control chip.

13. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to claim 10 or 11.

14. A computer program product comprising a computer program, which, when executed by a processor, implements the steps of the method of claim 10 or 11.

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