Instruction sequence verification method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to an instruction sequence verification method and device, electronic equipment and a storage medium, and the method comprises the steps: generating an instruction sequence, and inputting the instruction sequence into tested equipment; acquiring an actual response result output by a double data rate (DDR) memory controller of the tested equipment; the actual response result is compared with a prediction result, the execution correctness of the instruction sequence is verified, and the prediction result is obtained through prediction based on the instruction sequence. According to the embodiment of the invention, the verification platform can independently run on the logic layer of the DDR controller, a verification module does not need to be coupled, and the environmental complexity is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a method, apparatus, electronic device, storage medium, and computer program product for verifying an instruction sequence. Background Art

[0002] In the field of integrated circuit design, as a key module connecting a processor and memory chips, the performance and reliability of a Double Data Rate (DDR) memory controller directly affect the overall energy efficiency of a chip. With the increasing complexity of chips, instruction sequence technology is widely adopted in DDR controllers. By pre-writing multiple instructions into hardware registers and automatically executing them by the hardware, the interaction frequency between software and hardware is significantly reduced, and the task execution efficiency is improved. However, the method for verifying instruction sequences faces severe challenges.

[0003] In related technologies, the verification of instruction sequences often relies on the feedback of a complete execution link, that is, the final execution result is obtained through the complete path of DDR controller → Physical Layer Interface (PHY) → memory chips. For the entire execution sequence, the verification of the instruction sequence only focuses on whether the sequence is executed completely. When verifying the result at the chip end, it will be verified through a Verification Intellectual Property (VIP), and the execution of the instruction sequence is judged correct or not depending on the read and write results of the memory chips, resulting in a long verification cycle, low efficiency, and interference may be introduced due to physical layer delay or protocol conversion error in the feedback at the chip end. Summary of the Invention

[0004] In view of this, the present disclosure proposes a technical solution for verifying an instruction sequence.

[0005] According to one aspect of the present disclosure, there is provided a method for verifying an instruction sequence, including:

[0006] Generating an instruction sequence and inputting the instruction sequence into a device under test;

[0007] Obtaining an actual response result output by a Double Data Rate (DDR) memory controller of the device under test;

[0008] Comparing the actual response result with a predicted result to verify the correctness of the execution of the instruction sequence, where the predicted result is obtained by predicting based on the instruction sequence.

[0009] In a possible implementation, the generating the instruction sequence includes:

[0010] Obtain an enumeration class, which is encapsulated by a predefined instruction type library, and each instruction type corresponds to an instruction in a scenario;

[0011] Perform dynamic randomization on the enumeration class to generate an instruction sequence containing N instructions, where N≥1, and the type of each instruction is independently randomized.

[0012] In a possible implementation manner, the obtaining of the actual response result output by the double data rate memory DDR controller of the device under test includes:

[0013] Collect the DFI protocol signals output by the memory front-end interface DFI of the DDR controller;

[0014] Parse the DFI protocol signals into the form of DFI instructions to obtain the actual response result.

[0015] In a possible implementation manner, after generating the instruction sequence, the method further includes:

[0016] For each instruction in the instruction sequence, generate a corresponding predicted instruction based on the DFI protocol specification to obtain the prediction result.

[0017] In a possible implementation manner, the comparing the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence includes:

[0018] When the DDR controller finishes executing an instruction in the instruction sequence, obtain the predicted instruction from the prediction queue and compare it with the actual response result;

[0019] After the comparison is completed, delete the predicted instruction that has been compared in the prediction queue;

[0020] After detecting that the DDR controller has finished executing the instruction sequence, detect whether there are remaining predicted instructions in the prediction queue;

[0021] If there are no remaining predicted instructions, determine that the instruction sequence has been successfully executed.

[0022] In a possible implementation manner, the method further includes:

[0023] Detect the read and write operations of the verification module of the target language on the registers of the device under test, and the read and write operations include the read and write operations on the register address and data that trigger the execution of the instruction sequence;

[0024] According to the content of the read and write operations, dynamically update the register model in the verification platform to make the register model consistent with the register state of the device under test;

[0025] Obtaining the actual response result output by the double data rate (DDR) controller of the device under test includes:

[0026] Obtaining the actual response result output by the DDR controller based on the register model.

[0027] In a possible implementation, the method further includes:

[0028] Obtaining the target instruction sequence written to the DDR controller by the verification module according to the read / write operation;

[0029] Predicting the target instruction sequence to obtain a target prediction result;

[0030] Comparing the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence includes:

[0031] Comparing the target prediction result with the actual response result to verify the correctness of the execution of the target instruction sequence triggered by the verification module.

[0032] According to another aspect of the present disclosure, there is provided a verification device for an instruction sequence, including:

[0033] An instruction generation module, configured to generate an instruction sequence and input the instruction sequence into the device under test;

[0034] A result acquisition module, configured to obtain the actual response result output by the double data rate (DDR) controller of the device under test;

[0035] A verification module, configured to compare the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence, where the prediction result is obtained by predicting based on the instruction sequence.

[0036] In a possible implementation, the instruction generation module is configured to:

[0037] Obtain an enumeration class, which is encapsulated by a predefined instruction type library, and each instruction type corresponds to an instruction in a scenario;

[0038] Perform dynamic randomization on the enumeration class to generate an instruction sequence including N instructions, where N≥1, and the type of each instruction is independently randomized.

[0039] In a possible implementation, the result acquisition module is configured to:

[0040] Collect the DFI protocol signals output by the memory front-end interface (DFI) of the DDR controller;

[0041] Parse the DFI protocol signal into the form of DFI instructions to obtain the actual response result.

[0042] In a possible implementation, the device further includes:

[0043] A prediction result acquisition module, configured to generate corresponding prediction instructions for each instruction in the instruction sequence based on the DFI protocol specification to obtain the prediction result.

[0044] In a possible implementation, the verification module is configured to:

[0045] When the DDR controller finishes executing an instruction in the instruction sequence, obtain the prediction instruction from the prediction queue and compare it with the actual response result;

[0046] After the comparison is completed, delete the prediction instruction that has been compared in the prediction queue;

[0047] After detecting that the DDR controller has finished executing the instruction sequence, detect whether there are remaining prediction instructions in the prediction queue;

[0048] If there are no remaining prediction instructions, determine that the instruction sequence has been successfully executed.

[0049] In a possible implementation, the device further includes:

[0050] A read / write operation detection module, configured to detect the read / write operations of the verification module of the target language on the registers of the device under test, where the read / write operations include the read / write operations on the register address and data that trigger the execution of the instruction sequence;

[0051] A dynamic update module, configured to dynamically update the register model in the verification platform according to the content of the read / write operation, so that the register model is consistent with the register state of the device under test;

[0052] The result acquisition module is configured to obtain the actual response result output by the DDR controller based on the register model.

[0053] In a possible implementation, the device further includes:

[0054] A target instruction sequence acquisition module, configured to obtain the target instruction sequence written by the verification module to the DDR controller according to the read / write operation;

[0055] A prediction module, configured to perform prediction on the target instruction sequence to obtain a target prediction result;

[0056] The verification module is used to compare the target prediction result with the actual response result to verify the correctness of the execution of the target instruction sequence triggered by the verification module.

[0057] According to another aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the above method.

[0058] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0059] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0060] In the embodiments of the present disclosure, the verification is only for the actual response result and the prediction result of the DDR controller. Since the verification process does not depend on the signal conversion ability of the PHY or the feedback of the memory die, the verification platform does not need to integrate the PHY model or the die model, and only needs to focus on the logic function of the controller itself. For example, in a simulation environment, the PHY and the die are implemented by complex physical models; while this method can only simulate the DFI interface signals by splitting the dependencies, making the verification environment completely independent of the physical layer implementation. Thus, the verification platform can run independently on the logic layer of the DDR controller, without coupling the verification modules of the PHY or the die, reducing the environmental complexity.

[0061] In addition, the DFI protocol is a general industry interface standard between the DDR controller and the PHY (such as defined by JEDEC). Since the verification is based on the comparison of DFI protocol instructions, and the DFI protocol is standardized, any DDR controller that conforms to the DFI protocol can reuse the same verification process. For example, when a project upgrades from a DDR4 to a DDR5 controller, only the DFI protocol mapping rules (such as command encoding, timing parameters) need to be updated, without reconstructing the entire verification platform. Thus, the verification method provided by the present disclosure can quickly adapt to different DDR standards (such as DDR4 / 5) or controller designs of different manufacturers, only by adjusting the protocol prediction rules.

[0062] Moreover, the overall process of the present disclosure is an operation at the logical layer and does not involve physical implementation details, decoupling the verification process from the physical layer implementation (such as the circuit design of the PHY and the electrical characteristics of the die), and is applicable to any controller scenario that complies with the DFI protocol. For example, the same verification platform can be used to verify the LPDDR5 controller in an automotive chip and the DDR5 controller in a server chip, and only the DFI protocol parameters need to be adjusted. Thus, the verification method provided by the present disclosure is not bound to a specific physical implementation and can be applicable to the verification requirements of DDR controllers in multiple scenarios and multiple standards.

[0063] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings included in and constituting a part of this specification, together with the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0065] Figure 1 FIG. shows a flowchart of a verification method for an instruction sequence according to an embodiment of the present disclosure.

[0066] Figure 2 FIG. shows a block diagram of a verification apparatus for an instruction sequence according to an embodiment of the present disclosure.

[0067] Figure 3 FIG. shows a block diagram of a verification apparatus for an instruction sequence according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0069] As used herein, the terms "comprising," "including," "having," or variations thereof are open-ended and include one or more stated features, wholes, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, wholes, elements, steps, components, functions, or groups thereof.

[0070] When an element is referred to as being "connected," "coupled," "responsive," or variations thereof to another element, it can be directly connected, coupled, or responsive to the other element, or there can be intervening elements.

[0071] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments without departing from the teachings of the inventive concept.

[0072] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or better than other embodiments.

[0073] In addition, for a better illustration of the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art should understand that the present disclosure may be practiced without some of these specific details. In some instances, well-known methods, means, elements, and circuits have not been described in detail so as to highlight the gist of the present disclosure.

[0074] As the complexity of integrated circuits continues to increase, it becomes crucial to efficiently and accurately verify the instruction sequences therein. Based on this, the present disclosure provides a method for verifying an instruction sequence. The execution subject of this method may be a verification platform, which is mainly applied in the field of integrated circuit design, especially in the development and verification process of dynamic random access memory (DRAM)-related systems. This method is applicable to various scenarios that require verification of instruction sequences, such as the design and test phases of microprocessors, memory controllers, embedded systems, etc.

[0075] The verification platform may be a simulation environment built based on a hardware description language (such as System Verilog) for functional verification of a device under test (DUT). It checks whether the functions of the DUT meet the design requirements by generating various stimulus signals and test cases to simulate the behavior of the DUT in the actual working environment.

[0076] The DUT may be written in the Verilog hardware description language. Verilog is a widely used hardware description language for designing and verifying digital circuits. The DUT written in Verilog can precisely describe its functions and behaviors, facilitating simulation and testing in the verification platform. The verification platform interacts with the DUT through an interface, applies stimuli, and collects responses to complete a comprehensive verification of the DUT.

[0077] After the register-transfer level (RTL) code (written in Verilog) of the DDR controller is developed, the verification method provided by this disclosure is used to verify whether the instruction sequence execution function complies with the design specifications.

[0078] Figure 1 The flowchart showing the verification method of the instruction sequence according to an embodiment of this disclosure is as follows. Figure 1 As shown, the method includes:

[0079] In step S11, an instruction sequence is generated and input into the device under test.

[0080] An instruction sequence is a set of predefined instructions arranged in a specific order, used to instruct the DDR controller to perform specific tasks. That is to say, the instruction sequence is a set of commands input into hardware modules such as the DDR controller. In one example, the operation type (such as read, write), address, data, etc. of the memory access can be defined in the instruction; in another example, the instruction can also include instructions such as low-power mode switching.

[0081] The device under test is an integrated circuit module or system whose function is to be verified, specifically, it can be a DDR controller or a chip module containing a DDR controller. For example, the memory controller in a system on chip (SoC).

[0082] When generating the instruction sequence, the instruction sequence can be generated by randomization or preset rules (such as read-write combination). For specific possible implementation manners, refer to the implementation manners provided by this disclosure, which will not be elaborated here.

[0083] After generating the instruction sequence, it can be written into the instruction register of the DDR controller, and then the DDR controller is triggered to execute this instruction sequence.

[0084] In step S12, the actual response result output by the double data rate memory DDR controller of the device under test is obtained.

[0085] When the instruction sequence is input into the device under test, the device under test performs corresponding operations according to these instructions. Specifically, the instruction sequence is first sent to the DDR controller, and the DDR controller converts the instructions into instructions of the DFI protocol. These instructions are sent to the PHY layer through the dynamic random access memory front interface (DRAM Front Interface, DFI) interface; the PHY layer receives the DFI instructions from the DDR controller and converts them into signals suitable for transmission on the physical medium; the converted signals are transmitted to the memory die through a physical connection (such as a memory bus); after receiving these signals, the memory die performs corresponding operations.

[0086] The DDR controller is a hardware module used to manage DDR memory access. It communicates with the physical layer interface (PHY) using the DFI protocol and outputs command signals that comply with the protocol specifications. When verifying the successful execution of a command sequence, you can independently verify that the DDR controller correctly converts the command sequence into the signals defined by the DFI protocol.

[0087] The actual response output by the DDR controller can then be obtained and verified for correctness. This actual response is the result of the DUT's DDR controller executing the instruction sequence. Specifically, the DFI protocol output signals of the DDR controller (such as timing waveforms, data content, and protocol status) can be captured and decoded into readable DFI protocol instructions.

[0088] In step S13, the actual response result is compared with the predicted result to verify the correctness of the execution of the instruction sequence, wherein the predicted result is obtained by prediction based on the instruction sequence.

[0089] The prediction result is based on the theoretical expected output of the instruction sequence, which can be the expected DFI protocol instruction generated for each instruction in the instruction sequence according to the DFI protocol specification. It can be implemented by calling a pre-written function. For details, please refer to the possible implementation methods provided in this disclosure, which will not be elaborated here.

[0090] Since the instruction sequence contains multiple instructions, the corresponding actual response result will also correspond to multiple DFI instructions, and the prediction result may also contain multiple DFI instructions. The DFI instructions will include command type, address mapping and timing requirements.

[0091] When comparing the actual response result with the expected result, the command type, address, and timing of the actual DFI protocol instruction and the predicted instruction can be compared one by one. If there is any inconsistency, the instruction sequence is marked as defective; if there is consistency, it indicates that the verification of the instruction sequence has passed.

[0092] In the disclosed embodiments, verification focuses solely on the actual and predicted responses of the DDR controller. Because the verification process doesn't rely on the signal conversion capabilities of the PHY or feedback from the memory chip, the verification platform doesn't need to integrate PHY or chip models, focusing solely on the logical functionality of the controller itself. For example, in a simulation environment, the PHY and chips are implemented using complex physical models; however, this method, by separating these dependencies, only simulates the DFI interface signals, making the verification environment completely independent of the physical layer implementation. This allows the verification platform to operate independently of the DDR controller's logic layer, eliminating the need for coupled PHY or chip verification modules, reducing environmental complexity.

[0093] In addition, the DFI protocol is an interface standard (such as defined by JEDEC) between industry - common DDR controllers and PHYs. Since the verification is based on the comparison of DFI - protocol instructions and the DFI protocol is standardized, any DDR controller that complies with the DFI protocol can reuse the same verification process. For example, when a project upgrades from a DDR4 to a DDR5 controller, only the DFI - protocol mapping rules (such as command encoding, timing parameters) need to be updated, without the need to reconstruct the entire verification platform. Thus, the verification method provided by this disclosure can quickly adapt to different DDR standards (such as DDR4 / 5) or controller designs from different manufacturers, only by adjusting the protocol prediction rules.

[0094] Moreover, the overall process of this disclosure is an operation at the logic layer and does not involve physical implementation details, decoupling the verification process from the physical - layer implementation (such as the circuit design of the PHY and the electrical characteristics of the die). It is applicable to any controller scenario that complies with the DFI protocol. For example, the same verification platform can be used to verify the LPDDR5 controller in automotive chips and the DDR5 controller in server chips, only by adjusting the DFI - protocol parameters. Thus, the verification method provided by this disclosure is not bound to a specific physical implementation and can meet the verification requirements of DDR controllers in multiple scenarios and multiple standards.

[0095] In a possible implementation manner, the generating the instruction sequence includes: obtaining an enumeration class, which is encapsulated from a predefined instruction - type library, and each instruction type corresponds to an instruction in one scenario; performing dynamic randomization on the enumeration class to generate an instruction sequence containing N instructions (N≥1, N is a positive integer), where the type of each instruction is independently randomized.

[0096] An enumeration class is a special class type used to enumerate a set of fixed constant values. An enumeration class can clearly define a set of related constants, and each constant represents a specific state or value. An enumeration class is usually encapsulated from a predefined instruction - type library. In this process, an enumeration class containing various instruction types can be defined first, and each enumeration constant corresponds to a specific instruction type; then, by encapsulating these enumeration constants in a class, it is convenient to manage and use these instruction types.

[0097] Each instruction type corresponds to an instruction in one scenario. Here, the scenario can be, for example, a data - writing / reading instruction, an entering / exiting low - power - mode instruction, etc. Different application scenarios correspond to different types of instructions. By using an enumeration class, these instruction types can be clearly defined and distinguished.

[0098] Dynamically randomizing an enumeration class can generate diverse instruction sequences to cover more test scenarios and situations. Specifically, constants in the enumeration class can be randomly selected by calling a random number generator to generate random instruction types. Additionally, some constraint conditions and weight settings can be combined to make the randomization process more in line with specific requirements and scenarios. For example, in some test scenarios, certain instruction types may need to have a higher probability of occurrence, and in this case, biased randomization can be achieved by setting weights for these enumeration constants.

[0099] When performing randomization, the length N of the instruction sequence can be randomized, that is, an instruction sequence containing N instructions is generated, where N can be any integer greater than or equal to 1. By setting different N values, instruction sequences of different lengths can be generated to meet the requirements of different test scenarios for the length of the instruction sequence. Longer instruction sequences can be used to test the long-term stability and complex logic processing capabilities of the system, while shorter instruction sequences are suitable for rapid functional verification and unit testing.

[0100] In addition, the type of each instruction can be obtained through independent randomization. That is, when generating an instruction sequence, the instruction at each position is randomly selected independently and is not affected by other instructions. This independent randomization method ensures the diversity and unpredictability of the instruction sequence, enabling the generated instruction sequence to cover a wider range of test scenarios.

[0101] In the embodiments of the present disclosure, generating a sequence containing multiple instruction types through dynamic randomization can cover more test scenarios and situations. Since the type of each instruction is obtained through independent randomization, a variety of different instruction combinations and orders can be generated, greatly increasing the diversity of test stimuli. This comprehensive coverage method helps to discover potential defects hidden in various complex scenarios, reduces the possibility of missing problems, and thus improves the comprehensiveness and quality of verification.

[0102] The independent randomization of each instruction ensures the unpredictability of the test, making the verification process more realistic and reliable. Since the test cases are randomly generated, it is difficult for developers and testers to predict the specific test content and order in advance, thus avoiding artificial subjective biases and targeted design of test cases. This objective test method helps to discover marginal problems and abnormal situations that are easily overlooked in conventional tests, and improves the credibility and reliability of verification results.

[0103] In a possible implementation manner, obtaining the actual response result output by the double data rate memory DDR controller of the device under test includes: collecting the DFI protocol signals output by the memory front-end interface DFI of the DDR controller; parsing the DFI protocol signals into the form of DFI instructions to obtain the actual response result.

[0104] DFI is a standardized interface protocol between the DDR controller and the physical layer (PHY), mainly used to transmit information such as commands, addresses, and data. By collecting signals at the DFI interface, the original protocol signals output by the DDR controller during the execution of the instruction sequence can be obtained. These signals exist in the form of electrical signals, containing the direct response information of the DDR controller to the instruction sequence, reflecting the operations and state changes of the controller at each moment.

[0105] The collected DFI protocol signals need to be parsed and processed to convert them into the form of DFI instructions with clear semantics and formats. Through parsing, the original signals can be converted into an instruction set that is easy to understand and process, such as read commands, write commands, refresh commands, etc. These parsed DFI instructions constitute the actual response results, which can intuitively display the specific behaviors and operation sequences of the DDR controller during the execution of the instruction sequence.

[0106] In the embodiments of the present disclosure, by directly collecting and parsing DFI protocol signals, the most original and real response information of the DDR controller can be obtained, avoiding the interference or errors that may be introduced due to relying on the PHY or memory chips, so as to more accurately verify the execution effect of the instruction sequence; since the verification process only focuses on the signals and instructions at the DFI interface level and has nothing to do with the specific implementation details of the PHY and memory chips, the verification can be carried out independently of these hardware components. This independence enables the verification platform to effectively test and verify the instruction sequence of the DDR controller without relying on a complete hardware link; as a standardized interface protocol, DFI is widely used in various DDR storage systems. Therefore, the verification method based on the DFI interface can be easily transplanted to different hardware platforms and design environments, applicable to various types of DDR controller verification projects, greatly improving the versatility and flexibility of the verification environment.

[0107] In a possible implementation manner, after generating the instruction sequence, the method further includes: for each instruction in the instruction sequence, generating a corresponding predicted instruction based on the DFI protocol specification to obtain the prediction result.

[0108] The DFI protocol is a standardized interface protocol that defines the communication method between the DDR controller and the physical layer (PHY). It stipulates the transmission formats and timing requirements of information such as commands, addresses, and data. Familiarity with the DFI protocol specification is the basis for generating accurate predicted instructions.

[0109] Then, when generating prediction instructions, the instruction sequence can be analyzed in detail first to determine the type, parameters, and execution order of each instruction. For example, the instruction sequence can include different types of instructions such as read instructions, write instructions, refresh instructions, etc. Then, according to the DFI protocol specification, corresponding prediction instructions are generated for each instruction. The prediction instruction is a description of the DFI protocol signals expected to be output by the device under test (DUT) when executing the corresponding instruction. For example, for a read instruction, the prediction instruction should conform to the DFI protocol specification and include information such as the command for the read operation, the target address, and the expected data format to be read.

[0110] Then, the generated prediction instructions are organized according to the execution order of the instruction sequence to form a complete prediction result set. For example, the prediction instructions can be put into a queue to form a prediction queue. Each prediction instruction corresponds to a specific instruction in the original instruction sequence, and the order of the prediction instructions in the prediction result set is the same as the order of the instructions in the original instruction sequence.

[0111] In the embodiments of the present disclosure, the prediction instructions generated based on the DFI protocol specification can accurately describe the expected behavior of the DUT when executing each instruction. By comparing in detail with the actual response results, any deviation or error of the DUT can be accurately detected, thereby improving the accuracy of verification.

[0112] In a possible implementation manner, the comparing the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence includes: when the DDR controller finishes executing an instruction in the instruction sequence, obtaining the prediction instruction from the prediction queue and comparing it with the actual response result; after the comparison is completed, deleting the prediction instruction that has been compared in the prediction queue; when it is detected that the DDR controller finishes executing the instruction sequence, detecting whether there are remaining prediction instructions in the prediction queue; in the case that there are no remaining prediction instructions, determining that the instruction sequence has been successfully executed.

[0113] As mentioned above, before the verification starts, a prediction queue is created based on the generated instruction sequence according to the DFI protocol specification. This queue contains prediction instructions corresponding to each instruction in the instruction sequence, and the order of the prediction instructions in the queue is exactly the same as the execution order of the instructions in the instruction sequence. The prediction instruction details information such as the format, content, and timing of the DFI protocol signals expected to be output by the DDR controller when executing the corresponding instruction.

[0114] During the process of the DDR controller executing an instruction sequence, by collecting the DFI protocol signals output from the DFI interface and parsing them into the form of DFI instructions, the actual response results are obtained. Whenever the DDR controller finishes executing an instruction in the instruction sequence, the corresponding predicted instruction can be taken out from the prediction queue. Compare this predicted instruction with the actual response results. For example, if a read instruction is executed, it is necessary to compare whether the memory address read, the data value read, and the timing of the read operation are consistent with the predicted instruction.

[0115] To maintain the accuracy and timeliness of the prediction queue, after each comparison is completed, the predicted instructions that have been compared can be immediately deleted from the queue. This can avoid confusion or incorrect matching in subsequent comparison processes and ensure that only the predicted instructions that have not been compared are included in the queue.

[0116] The management of the prediction queue follows the first-in, first-out (FIFO) principle. Whenever a predicted instruction is taken out for comparison and deleted, the subsequent predicted instructions in the queue automatically move forward to fill the vacancy. This can ensure that the order of the predicted instructions always matches the execution order of the instruction sequence and guarantee the accuracy of the comparison.

[0117] After detecting that the DDR controller has finished executing the instruction sequence, check whether there are any remaining predicted instructions in the prediction queue. If there are remaining predicted instructions, it means that during the execution of the instruction sequence, some predicted instructions did not receive the corresponding actual response results, and there may be problems such as instructions not being executed or incorrect execution order.

[0118] When it is detected that the DDR controller has finished executing the instruction sequence and there are no remaining predicted instructions in the prediction queue, it can be determined that each instruction in the instruction sequence has been correctly executed, indicating that the actual response results are completely consistent with the predicted results and the verification passes.

[0119] After determining that the instruction sequence has been successfully executed, the verification platform can generate a corresponding verification report. The report records the status of successful verification and may include some additional information, such as the time taken for verification, resource consumption, etc., for subsequent analysis and evaluation.

[0120] In the embodiments of the present disclosure, by performing comparison immediately after each instruction is executed, errors during the execution process can be detected in a timely manner, avoiding difficulties in problem location caused by the accumulation of errors. At the same time, the method of comparing one by one ensures precise inspection of the execution status of each instruction, improving the accuracy of verification. Detecting the remaining instructions in the prediction queue after the execution of the instruction sequence ensures that all predicted instructions are compared with the actual response results, avoiding omission of the verification of any instruction and guaranteeing the integrity of verification. If there are remaining predicted instructions, it indicates problems such as unexecuted instructions or incorrect execution order, improving the efficiency of the verification work.

[0121] In a possible implementation manner, the method further includes: detecting the read and write operations of the verification module of the target language on the registers of the device under test, where the read and write operations include the read and write operations on the register addresses and data for triggering the execution of the instruction sequence; dynamically updating the register model in the verification platform according to the content of the read and write operations, so that the register model is consistent with the register status of the device under test; the obtaining of the actual response result output by the double data rate memory (DDR) controller of the device under test includes: obtaining the actual response result output by the DDR controller based on the register model.

[0122] In integrated circuit verification, multiple programming languages and verification tools are usually used, such as System Verilog, C language, etc. The verification module of the target language refers to a module written in a specific language for verifying the functions of the device under test (DUT). These modules can include functions such as test case generation, excitation signal sending, response result collection, etc. The target language is a language different from the programming language of the execution entity of this method. In an example, when the execution entity of this method is a module written in SystemVerilog language, the target language is C language; when the execution entity of this method is a module written in C language, the target language is System Verilog language.

[0123] To verify the test of the DUT by the verification module of the target language, the read and write operations of the verification module of the target language on the DUT registers can be monitored. For example, the read and write operations on the register addresses and data for triggering the execution of the instruction sequence, because these operations directly affect the behavior of the DUT and the execution flow of the instruction sequence.

[0124] The registers inside the DUT are used to control and configure its various functions. The read and write operations on the register addresses can change the working mode of the DUT, trigger specific operations, or obtain the current status information. For example, writing to a certain register address can start the execution of an instruction sequence, and reading that address can return the execution status of the instruction sequence.

[0125] When reading and writing registers, the data transfer is crucial. The written data determines the specific behavioral parameters of the DUT, such as memory addresses, operation types, etc.; the read data reflects the current state or operation result of the DUT, which is crucial for verifying the correctness of the instruction sequence.

[0126] In the verification platform, a register model corresponding to the internal register structure of the DUT will be constructed. This model contains information such as the addresses, bit widths, initial values, and access permissions of all registers, and is used to simulate the behavior and state of the DUT registers.

[0127] Whenever a read or write operation of the DUT register is detected by the target language verification module, the corresponding register state in the register model can be updated in a timely manner according to the content of the operation (such as register address, read / write type, data value, etc.). For example, if a write operation is detected, the written data is updated to the corresponding address in the register model; if a read operation is detected, the data at the corresponding address is obtained from the register model.

[0128] Since the register model is consistent with the register state of the DUT, the actual response result output by the DDR controller can be obtained by querying the register model. For example, the values of some registers in the model directly reflect the output state of the DDR controller, such as information about commands, addresses, data, etc. Then, according to the data in the register model, the actual response result can be parsed according to the DFI protocol specification or other relevant standards.

[0129] Then, the actual response result obtained based on the register model is compared with the predicted result to verify whether the execution of the instruction sequence is correct. If the two are consistent, it means that the behavior of the DUT meets the expectations; otherwise, the reason for the difference needs to be further analyzed.

[0130] In the embodiments of the present disclosure, in a multi-language verification environment, through a unified register model, verification modules written in different languages can work better together, which helps to integrate various verification resources, verify the results of the verification processes triggered by verification modules written in different languages, form a more complete and powerful verification system, and improve the overall quality and efficiency of verification.

[0131] In a possible implementation manner, the method further includes: obtaining a target instruction sequence written by the verification module to the DDR controller according to the read / write operation; predicting the target instruction sequence to obtain a target prediction result; and the comparing the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence includes: comparing the target prediction result with the actual response result to verify the correctness of the execution of the target instruction sequence triggered by the verification module.

[0132] As described above, the communication between the verification module of the target language and the DDR controller can be monitored. By analyzing the content of the read and write operations of the verification module, the instruction sequence written by the verification module to the DDR controller can be extracted. For the sake of convenience of description, this instruction sequence is referred to as the target instruction sequence herein. Specifically, the extracted instructions can be arranged in the execution order to construct a complete target instruction sequence.

[0133] Then, based on the DFI protocol specification, the response result that the DDR controller should generate when executing the target instruction sequence is predicted. As the prediction result, for the sake of convenience of description, this prediction result is referred to as the target prediction result herein. For the specific implementation of generating the prediction instruction provided by the present disclosure, reference can be made thereto, and details are not described herein.

[0134] Then, the target prediction result is compared with the actual response result to verify the correctness of the execution of the instruction sequence triggered by the verification module of the target language. For the specific verification process, reference can be made to the implementation of comparing the actual response result with the prediction result provided by the present disclosure, and details are not described herein.

[0135] In the embodiment of the present disclosure, by monitoring the read and write operations of the verification module of the target language on the registers of the device under test, the target instruction sequence written by the verification module to the DDR controller is directly obtained, ensuring the accuracy and authenticity of the obtained instruction sequence. Then, based on this target instruction sequence, a target prediction result is predicted and compared with the actual response result, so as to accurately verify the correctness of the execution of the instruction sequence triggered by the verification module of the target language. The direct verification of the instruction sequence triggered by the verification module of the target language is realized, avoiding the errors and uncertainties that may be brought by indirect verification, improving the accuracy and reliability of verification, and at the same time helping to timely discover and locate problems in the verification process, and improving the efficiency and quality of the entire verification process.

[0136] According to another aspect of the present disclosure, a verification device for an instruction sequence is provided. Figure 2 The block diagram of the verification device for an instruction sequence according to an embodiment of the present disclosure is shown. The verification device 20 for an instruction sequence includes:

[0137] An instruction generation module 21, configured to generate an instruction sequence and input the instruction sequence into the device under test;

[0138] A result acquisition module 22, configured to acquire the actual response result output by the double data rate memory DDR controller of the device under test;

[0139] A verification module 23, configured to compare the actual response result with the prediction result to verify the correctness of the execution of the instruction sequence, where the prediction result is obtained by predicting based on the instruction sequence.

[0140] In a possible implementation, the instruction generation module is configured to:

[0141] Obtain an enumeration class, which is encapsulated by a predefined instruction type library, and each instruction type corresponds to an instruction in a scenario;

[0142] Perform dynamic randomization on the enumeration class to generate an instruction sequence containing N instructions, where N ≥ 1, and the type of each instruction is independently randomized.

[0143] In a possible implementation, the result acquisition module is configured to:

[0144] Collect DFI protocol signals output by the memory front-end interface DFI of the DDR controller;

[0145] Parse the DFI protocol signals into the form of DFI instructions to obtain the actual response result.

[0146] In a possible implementation, the device further includes:

[0147] A prediction result acquisition module, configured to generate a corresponding prediction instruction for each instruction in the instruction sequence based on the DFI protocol specification to obtain the prediction result.

[0148] In a possible implementation, the verification module is configured to:

[0149] When the DDR controller finishes executing an instruction in the instruction sequence, obtain the prediction instruction from the prediction queue and compare it with the actual response result;

[0150] After the comparison is completed, delete the prediction instruction that has been compared in the prediction queue;

[0151] After detecting that the DDR controller has finished executing the instruction sequence, detect whether there are remaining prediction instructions in the prediction queue;

[0152] If there are no remaining prediction instructions, determine that the instruction sequence has been successfully executed.

[0153] In a possible implementation, the device further includes:

[0154] A read / write operation detection module, configured to detect the read / write operations of the verification module of the target language on the registers of the device under test, and the read / write operations include the read / write operations on the register address and data that trigger the execution of the instruction sequence;

[0155] A dynamic update module, configured to dynamically update a register model in a verification platform according to the content of the read / write operation, so that the register model is consistent with the register state of the device under test;

[0156] The result acquisition module is configured to obtain an actual response result output by the DDR controller based on the register model.

[0157] In a possible implementation manner, the device further includes:

[0158] A target instruction sequence acquisition module, configured to obtain a target instruction sequence written by the verification module to the DDR controller according to the read / write operation;

[0159] A prediction module, configured to perform a prediction on the target instruction sequence to obtain a target prediction result;

[0160] The verification module is configured to compare the target prediction result with the actual response result to verify the correctness of the execution of the target instruction sequence triggered by the verification module.

[0161] In some embodiments, the functions or modules included in the device provided in the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0162] The embodiments of the present disclosure further provide an electronic device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the above method.

[0163] The embodiments of the present disclosure further provide a non-volatile computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0164] The embodiments of the present disclosure further provide a computer program product, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program. When the computer program is executed by a processor, the steps of the above method are implemented.

[0165] Figure 3 A block diagram of an instruction sequence verification device according to an embodiment of the present disclosure is shown. For example, device 1900 can be provided as a server or a terminal device. Refer to Figure 3, Device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above-described method.

[0166] Device 1900 may also include a power component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0167] In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as the memory 1932 including computer program instructions, and the computer program instructions can be executed by the processing component 1922 of the device 1900 to complete the above-described method.

[0168] A computer-readable storage medium can be a tangible device that can hold and store programs / instructions used by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium used herein is not construed as an instantaneous signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through an optical fiber cable), or electrical signals transmitted through wires.

[0169] The computer programs (or computer-readable program instructions) described herein can be downloaded to various computing / processing devices from a computer-readable storage medium or downloaded to an external computer or an external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0170] The computer programs (or computer program instructions) for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0171] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0172] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions for implementing various aspects of the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0173] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0174] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, and the module, segment of code, or portion of an instruction may include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the boxes may occur out of the order noted in the figures. For example, two consecutive boxes may, in fact, be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, can be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or by combinations of special-purpose hardware and computer instructions.

[0175] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A method for verifying an instruction sequence, characterized in that including: generating an instruction sequence and inputting the instruction sequence into the device under test; obtaining an actual response result output by a double data rate memory DDR controller of the device under test; comparing the actual response result with a predicted result to verify the correctness of the execution of the instruction sequence, where the predicted result is obtained by predicting based on the instruction sequence.

2. The method according to claim 1, wherein The generating the instruction sequence includes: obtaining an enumeration class, which is encapsulated by a predefined instruction type library, and each instruction type corresponds to an instruction in a scenario; dynamically randomizing the enumeration class to generate an instruction sequence including N instructions, where N≥1, and the type of each instruction is independently randomized.

3. The method according to claim 1, wherein The obtaining the actual response result output by the double data rate memory DDR controller of the device under test includes: collecting DFI protocol signals output by a memory front-end interface DFI of the DDR controller; parsing the DFI protocol signals into DFI instruction forms to obtain the actual response result.

4. The method according to claim 1, wherein After generating the instruction sequence, the method further includes: for each instruction in the instruction sequence, generating a corresponding predicted instruction based on the DFI protocol specification to obtain the predicted result.

5. The method according to claim 1, wherein The comparing the actual response result with the predicted result to verify the correctness of the execution of the instruction sequence includes: when the DDR controller finishes executing an instruction in the instruction sequence, obtaining a predicted instruction from a prediction queue and comparing it with the actual response result; after the comparison is completed, deleting the predicted instruction that has been compared in the prediction queue; when it is detected that the DDR controller finishes executing the instruction sequence, detecting whether there are remaining predicted instructions in the prediction queue; when there are no remaining predicted instructions, determining that the instruction sequence is successfully executed.

6. The method according to claim 1, wherein The method further includes: detecting read and write operations of a verification module of a target language on registers of the device under test, where the read and write operations include read and write operations on register addresses and data for triggering the execution of the instruction sequence; dynamically updating a register model in a verification platform according to the content of the read and write operations, so that the register model is consistent with the register state of the device under test; The obtaining the actual response result output by the double data rate memory DDR controller of the device under test includes: obtaining the actual response result output by the DDR controller based on the register model.

7. The method according to claim 6, characterized in that, The method further includes: obtaining a target instruction sequence written by the verification module to the DDR controller according to the read and write operations; predicting the target instruction sequence to obtain a target predicted result; The comparing the actual response result with the predicted result to verify the correctness of the execution of the instruction sequence includes: comparing the target predicted result with the actual response result to verify the correctness of the execution of the target instruction sequence triggered by the verification module.

8. A verification device for an instruction sequence, characterized in that, including: an instruction generation module for generating an instruction sequence and inputting the instruction sequence into the device under test; a result acquisition module for obtaining an actual response result output by a double data rate memory DDR controller of the device under test; A verification module, configured to compare the actual response result with the predicted result to verify the correctness of the execution of the instruction sequence, where the predicted result is obtained by predicting based on the instruction sequence.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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